SN74LVC3G06DCTR [TI]
TRIPLE INVERTER BUFFER/DRIVER WITH OPEN DRAIN OUTPUTS; TRIPLE逆变器缓冲/驱动器,具有漏极开路输出型号: | SN74LVC3G06DCTR |
厂家: | TEXAS INSTRUMENTS |
描述: | TRIPLE INVERTER BUFFER/DRIVER WITH OPEN DRAIN OUTPUTS |
文件: | 总12页 (文件大小:318K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ
ꢋ ꢌꢍꢎ ꢄꢏ ꢍꢁ ꢅꢏꢌ ꢋꢏ ꢌ ꢐꢑꢒ ꢒ ꢏ ꢌꢓ ꢔꢌ ꢍ ꢅꢏ ꢌ
ꢕ ꢍꢋ ꢖ ꢗ ꢎꢏꢁ ꢘꢔꢌꢙꢍ ꢁ ꢗ ꢑꢋ ꢎꢑ ꢋꢀ
SCES364G− AUGUST 2001 − REVISED AUGUST 2003
DCT OR DCU PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
Supports 5-V V
Operation
CC
1A
3Y
2A
V
CC
1
2
3
4
8
7
6
5
D
Input and Open-Drain Output Accepts
Voltages Up To 5.5 V
1Y
3A
2Y
GND
D
D
D
D
D
D
D
D
Max t of 3.4 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
CC
24-mA Output Drive at 3.3 V
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
OLP
CC
A
4 5
3 6
2 7
1 8
GND
2A
3Y
2Y
3A
1Y
V
Typical V
(Output V
= 3.3 V, T = 25°C
Undershoot)
OHV
OH
>2 V at V
CC
A
1A
I
Supports Partial-Power-Down Mode
CC
off
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This triple inverter buffer/driver is designed for 1.65-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC3G06YEAR
SN74LVC3G06YZAR
SN74LVC3G06YEPR
SN74LVC3G06YZPR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
_ _ _CT_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SSOP − DCT
Reel of 3000
Reel of 3000
SN74LVC3G06DCTR
SN74LVC3G06DCUR
C06_ _ _
C06_
VSSOP − DCU
Reel of 250
SN74LVC3G06DCUT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢊ
ꢋ ꢌꢍ ꢎ ꢄ ꢏ ꢍ ꢁ ꢅꢏꢌ ꢋ ꢏ ꢌ ꢐꢑ ꢒꢒ ꢏꢌ ꢓꢔ ꢌꢍ ꢅ ꢏꢌ
ꢕꢍ ꢋ ꢖ ꢗꢎꢏ ꢁꢘ ꢔꢌꢙ ꢍ ꢁ ꢗ ꢑꢋꢎ ꢑꢋ ꢀ
SCES364G− AUGUST 2001 − REVISED AUGUST 2003
description/ordering information (continued)
The output of the SN74LVC3G06 is open drain and can be connected to other open-drain outputs to implement
active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
1
3
6
7
5
2
1A
2A
3A
1Y
2Y
3Y
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ
ꢋ ꢌꢍꢎ ꢄꢏ ꢍꢁ ꢅꢏꢌ ꢋꢏ ꢌ ꢐꢑꢒ ꢒ ꢏ ꢌꢓ ꢔꢌ ꢍ ꢅꢏ ꢌ
ꢕ ꢍꢋ ꢖ ꢗ ꢎꢏꢁ ꢘꢔꢌꢙꢍ ꢁ ꢗ ꢑꢋ ꢎ ꢑꢋꢀ
SCES364G− AUGUST 2001 − REVISED AUGUST 2003
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
Operating
5.5
V
Supply voltage
V
CC
IH
Data retention only
1.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.7 × V
CC
0.35 × V
0.7
0.8
0.3 × V
5.5
5.5
4
CC
V
IL
Low-level input voltage
= 4.5 V to 5.5 V
CC
V
V
Input voltage
0
0
V
V
I
Output voltage
O
V
V
= 1.65 V
= 2.3 V
CC
8
CC
16
I
Low-level output current
mA
OL
V
CC
= 3 V
24
V
CC
V
CC
V
CC
V
CC
= 4.5 V
32
= 1.8 V 0.15 V, 2.5 V 0.2 V
= 3.3 V 0.3 V
20
10
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
= 5 V 0.5 V
5
T
A
−40
85
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
V
MIN
MAX
0.1
UNIT
CC
I
I
I
I
I
= 100 mA
= 4 mA
1.65 V to 5.5 V
1.65 V
OL
OL
OL
OL
OL
0.45
0.3
= 8 mA
2.3 V
V
V
OL
= 16 mA
= 24 mA
0.4
3 V
0.55
4.5 V
0 to 5.5 V
0
0.55
5
I
= 32 mA
OL
I
I
I
A inputs
V = 5.5 V or GND
mA
mA
mA
mA
pF
I
I
V or V = 5.5 V
10
off
I
O
V = 5.5 V or GND,
I = 0
O
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
10
CC
I
∆I
CC
One input at V
CC
− 0.6 V, Other inputs at V
CC
or GND
500
C
V = V
or GND
3.5
i
I
CC
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
3
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ꢕꢍ ꢋ ꢖ ꢗꢎꢏ ꢁꢘ ꢔꢌꢙ ꢍ ꢁ ꢗ ꢑꢋꢎ ꢑꢋ ꢀ
SCES364G− AUGUST 2001 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.8
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.9
t
pd
A
7.2
1
3.9
1
3.4
1
ns
Y
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V
CC
= 3.3 V
V
= 5 V
CC
TYP
CC
TYP
PARAMETER
TEST CONDITIONS
f = 10 MHz
UNIT
TYP
TYP
C
Power dissipation capacitance
2
2
3
4
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢕ ꢍꢋ ꢖ ꢗ ꢎꢏꢁ ꢘꢔꢌꢙꢍ ꢁ ꢗ ꢑꢋ ꢎ ꢑꢋꢀ
SCES364G− AUGUST 2001 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
(see Notes E and F)
(see Notes E and G)
V
V
V
PZL
LOAD
LOAD
LOAD
C
L
t
R
PLZ
L
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
M
V
C
V
R
V
CC
LOAD
L
∆
L
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
V
V
/2
/2
2 × V
2 × V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
2 × V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
V
/2
/2
LOAD
V
V
OH
V
V
V
V
V
M
S1 at V
(see Note B)
M
Output
M
LOAD
V
V
OL
∆
OL
OL
t
t
t
PHZ
PLH
PZH
Output
Waveform 2
V
∆
V
V
LOAD
OH
− V
LOAD/2
S1 at V
(see Note B)
V
M
M
M
LOAD
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
and t
PZL
are the same as t .
pd
PLZ
F.
G.
t
t
is measured at V
.
M
PZL
PLZ
is measured at V
+ V .
OL
∆
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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