TLC320AD535PM_技术文档

Data Manual

2000

Mixed Signal Products

SLAS202B

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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Contents

Section

Title

Page

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Voice Channel Codec Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Data Channel Codec Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

2

3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.1

2.2

2.3

2.4

2.5

Device Requirements and System Overview . . . . . . . . . . . . . . . . . . . . 2–1

Codec Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Hybrid Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Voice Channel Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Miscellaneous Logic and Other Circuitry . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Codec Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Analog and Digital Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Software Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.10 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.11 Test Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4

5

4.1

Primary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.1.1

4.1.2

FS High Mode Primary Communication Timing . . . . . . . . . 4–2

FS Low Mode Primary Communication Timing . . . . . . . . . . 4–2

4.2

Secondary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

4.2.1

4.2.2

FS High Mode Secondary Communication Timing . . . . . . . 4–4

FS Low Mode Secondary Communication Timing . . . . . . . 4–4

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.1

Absolute Maximum Ratings Over Operating Free-Air

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.2

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

iii

5.3

Electrical Characteristics Over Operating Free-Air Temperature

Range, DV = 5 V/3.3 V, xAV = 5 V/3.3 V,

DD

MV

= 5 V/3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

DD

5.3.1

Digital Inputs and Outputs, f = 8 kHz,

s

Outputs Not Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.3.2

5.3.3

ADC Channel, f = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

s

ADC Dynamic Performance, f = 8 kHz . . . . . . . . . . . . . . . . 5–2

s

5.3.3.1

5.3.3.2

5.3.3.3

ADC Signal-to-Noise . . . . . . . . . . . . . . . . . . . . . 5–2

ADC Signal-to-Distortion . . . . . . . . . . . . . . . . . . 5–2

ADC Signal-to-Distortion + Noise . . . . . . . . . . 5–2

5.3.4

5.3.5

5.3.6

ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

DAC Channel, f = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

s

DAC Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

5.3.6.1

5.3.6.2

5.3.6.3

DAC Signal-to-Noise . . . . . . . . . . . . . . . . . . . . . 5–3

DAC Signal-to-Distortion . . . . . . . . . . . . . . . . . . 5–3

DAC Signal-to-Distortion + Noise . . . . . . . . . . 5–3

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.3.12

5.3.13

DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Logic DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 5–4

Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

Flash Write Enable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

8-Ω Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.4

5.5

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.4.1

5.4.2

Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

6

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

A Programmable Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

iv

List of Illustrations

Figure

Title

Page

4–1 Primary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . . . 4–1

4–2 FS High Mode Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . 4–2

4–3 FS Low Mode Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . 4–2

4–4 Secondary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . 4–3

4–5 FS Output During Software Secondary Serial Communication Request

(FS High Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

4–6 FS Output During Software Secondary Serial Communication Request

(FS Low Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

5–1 Serial Communication Timing for FS High Mode . . . . . . . . . . . . . . . . . . . . . . 5–6

5–2 ADC Decimation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5–3 ADC Decimation Filter Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5–4 DAC Interpolation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5–5 DAC Interpolation Filter Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

6–1 Functional Block of a Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6–2 Voice Channel Codec Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

6–3 Data Channel Codec Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

List of Tables

Table

Title

Page

4–1 Least-Significant-Bit Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

v

vi

1 Introduction

The TLC320AD535 dual channel voice/data codec is a mixed-signal broadband connectivity device. The

TLC320AD535 is comprised of a two-channel codec and analog hybrid circuitry with two independent serial ports for

communication with the host processor and external resistors and capacitors for setting gain and filter poles. The

device also contains microphone bias and amplification, audio mixing capabilities in the voice channel,

programmable gain control, and three (SPKR_LEFT, SPKR_RIGHT, and MONOUT) speaker drivers.The device

operates with either a 5-V analog, a 5-V digital, and a 5-V monitor power supply or a 3.3-V analog, a 3.3-V digital,

and a 5-V monitor power supply or 5-V analog, 3.3-V digital, and 5-V monitor power supply. It is available in a single

64-pin PM (QFP) package.

1.1 Features

•

Analog, Digital, and Monitor Amp Power Supplies: 5 V or 3.3 V

Separate Software Power-Down Modes for Data and Voice Channels

Independent Voice and Data Channel Sample Rates up to 11.025 kHz

16-Bit Signal Processing

Dynamic Range of 80 dB in the Data and Voice Channels

Total Signal-to-Noise + Distortion of 77 dB for the ADCs

Total Signal-to-Noise + Distortion of 74 dB for the DACs

Programmable Gain Amplifiers

600-Ω TAPI Audio and Data Channel Drivers

60-Ω Headphone Driver With Programmable Gain Amplifier

8-Ω AT41 Differential Speaker Driver With Programmable Gain Amplifier

Maximum Microphone Bias of 5 mA at 2.5 V/1.5 V

Maximum Handset Reference of 2.5 mA at 2.5 V/1.5 V

Maximum Data Channel Reference of 10 mA at 2.5 V/1.5 V

5-V MV

Power Reset Circuit

DD

Flash Write Enable Circuit, for Writing the Flash Memory Device

Available in a 64-Pin PM (QFP) Package Operating From –40°C to 85°C

1–1

1.2 Functional Block Diagram

H

Y

B

R

I

Data

Channel

Serial

Port

Data Channel

Codec

D

A

M

P

Power

Reset

Circuit

DRVR

Control

Logic

Flash

Write

Enable

DRVR

Voice Channel

Codec

Voice

Channel

Serial

Port

BIAS/

AMPL

1–2

1.3 Voice Channel Codec Logic Diagram

–

+

TAPI_IN

TAPI Preamp

20/0 dB Gain

2.5 V/1.5 V

–

MIC_AUDIO

MIC_BIAS

M

I

X

E

R

+

–

+

16-Bit

ADC

Mic Preamp

20/0 dB Gain

–1

2.5 V/1.5 V

Line_In PGA

12 to –36 dB

1.5 dB Noiseless Steps

31 Steps and Mute

+

–

Phantom Power

2.5 V/1.5 V @ 5 mA

SPKR_LEFT

HSRX_FB

60-Ω Pwr Spkr Buffer

0 dB or Mute

( Same Polarity)

–

+

HSRXM

HSRXP

Handset RX (Hybrid)

+

–

SPKR_RIGHT

TAPI_OUT

16-Bit

DAC

–

HS_REF

2.5 V/1.5 V

HSTX_OUT

+

2.5 V/1.5 V

+

–

Line_Out PGA

12 to –36 dB

1.5 dB Noiseless Steps

31 Steps and Mute

HSTX_IN

–

+

2.5 V/1.5 V

Internal

Handset TX (Hybrid)

600-Ω

Out Buffer

0 dB or Mute

+

–

HS_BUF

600-Ω Handset Out Buffer

0 dB or Mute

1–3

1.4 Data Channel Codec Logic Diagram

DTRX_FB

–

+

DTRXM

DTRXP

–

+

16-Bit

ADC

Mon_Out PGA

0-3-6-9-12 dB Gain

with Mute

Data (Hybrid)

–1

Data_In PGA

2.5 V/1.5 V

@ 10 mA

DT_REF

0/6/12/18 dB Gain

with Mute

DTTX_OUT

–

+

16-Bit

DAC

M

U

X

–

+

DTTX_IN

2.5 V/1.5 V

Data (Hybrid)

MONOUTP

MONOUTM

–

+

–

DT_BUF

+

2.5 V/1.5 V

8 Ω Speaker Buffer

0/–6/–12/–18 dB or Mute

600-Ω Data_Out PGA

0 dB or Mute

1.5 Terminal Assignments

6463 62 61 60 59 58 57 56 55 5453 5251 50 49

V

DAV

DREFP_DAC

DREFM_DAC

1

2

3

4

5

SS

DD

VAV

VREFP_ADC

VREFM_ADC

VAV

48

47

46

45

DD

SS

DAV

SS

VREFP_DAC

VREFM_DAC

NC

HSRX_FB

HSRXM

44

43

42

DREFP_ADC

DREFM_ADC

NC

6

7

8

9

41

40

39

TLC320AD535C/I

DTRX_FB

DTRXM

10

HSRXP

DTRXP 11

38 HS_REF

DT_REF

DTTX_OUT

DTTX_IN

DT_BUF

NC

12

13

14

15

16

37 HSTX_OUT

36

35

34

33

HSTX_IN

HS_BUF

NC

SI_SEL

1718 19 20 21 22 23 2425 26 27 282930 31 32

NC–Make no external connection

1–4

1.6 Ordering Information

1.7 Terminal Functions

PACKAGE

PLASTIC QUAD FLATPACK (PM)

TLC320AD535

T

A

0°C to 70°C

–40°C to 85°C

TLC320AD535I

TERMINAL

I/O

DESCRIPTION

NAME

NO.

2

DAV

I

Data channel analog power supply (5 V/3.3 V)

Data channel analog ground

DD

DAV

5

SS

DREFM_ADC

DREFM_DAC

DREFP_ADC

7

O

Data channel ADC voltage reference filter output. DREFM_ADC provides low-pass filtering for the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_ADC

and DREFP_ADC. The nominal DC voltage at this terminal is 0 V.

4

6

O

Data channel DAC voltage reference filter output. DREFM_DAC provides low-pass filtering for the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_DAC

and DREFP_DAC. The nominal dc voltage at this terminal is 0 V.

Data channel ADC voltage reference filter output. DREFP_ADC provides low-pass filtering for the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_ADC

and DREFP_ADC. The dc voltage at this terminal is 3.375 V at 5-V DAV

supply.

supply and 2.25 V at 3.3-V DAV

DD

DREFP_DAC

3

O

Data channel DAC voltage reference filter output. DREFP_DAC provides low-pass filtering for the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_DAC

andDREFP_DAC. Thedcvoltageatthisterminalis3.375Vat5-DAV

supplyand2.25Vat3.3-DAV supply.

DD

DT_BUF

DT_DIN

DT_DOUT

DT_FS

15

26

22

21

O

I

Data channel buffer amp analog output. DT_BUF is programmed for 0-dB gain or is muted using the control

registers. This output is normally fed to the DTTX_IN terminal through an input resistor.

Data channel digital data input. DT_DIN handles DAC input data as well as control register programming

information during the data channel frame sync interval and is synchronized to DT_SCLK.

O

Data channel digital data output. Data channel ADC output bits are transmitted during the data channel frame

sync period that is synchronized to DT_SCLK. DT_DOUT is at high impedance when DT_FS is not activated.

Data channel serial port frame sync signal. DT_FS signals the beginning of transmit for ADC data and receiving

of DAC data in the data channel. This signal can be active high (FS high mode) or active low (FS low mode)

depending on the voltage applied to SI_SEL (See Section 4, Serial Communications for more details).

DT_MCLK

DT_REF

27

12

I

Data channel master clock input. All of the internal clocks for the data channel are derived from this clock.

O

Handset amplifier reference voltage. The voltage at this pin is set at 2.5 V for a 5-V DAV supply and 1.5 V for

DD

a 3.3-V DAV

supply. The maximum source current at this terminal is 2.5 mA.

DD

DTRX_FB

9

O

Datachannel receive path amplifier feedback node. DTRX_FB connects to the output of the data channel receive

path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain

and filter poles.

DTRXM

DTRXP

10

11

25

I

Data channel receive path amplifier analog inverting input

Data channel receive path amplifier analog noninverting input.

DT_SCLK

O

Data channel shift clock signal. This signal clocks serial data into DT_DIN and out of DT_DOUT during the data

channel frame-sync interval. DT_SCLK = DT_MCLK/2

DTTX_IN

14

I

Data channel transmit amplifier analog inverting input. This node is normally fed by the DT_BUF output through

an input resistor. The noninverting input of the amplifier is connected internally to 2.5 V for 5 V supply and 1.5

V for 3.3 V supply.

DTTX_OUT

13

24

23

O

I

Data channel transmit amplifier analog output

Digital power supply (5 V/3.3 V).

Digital ground

DV

DD

SS

I

FILT

57

O

Bandgap filter node. FILT provides decoupling of the 3.375-V bandgap reference. The optimal capacitor value

is 0.1 µF (ceramic). This node should not be used as a voltage source.

1–5

1.7 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

FLSH_IN

NO.

18

I

External logic input. When brought low FLSH_IN enables the FLSH_OUT output.

FLSH_OUT

17

O

Power output to write/erase flash EEPROM device (such as Intel 28F400B or AMD Am29F400). Outputs 5 V

(± 10%) at 45 mA maximum when FLSH_IN is brought low. FLSH_OUT does not go to a logic high state when

off. ThereisaninternalNMOSpulldowntomaintainthespecifiedvoltage. Anexternalpulldownisnotrequired.

HS_BUF

HS_REF

HSRX_FB

35

38

41

O

Handset buffer amplifier analog output. HS_BUF can be programmed for 0-dB gain or muted using the control

registers. This output is normally fed to the HSTX_IN terminal through an input resistor.

Handset amplifier reference voltage HS_REF is set at 2.5 V for 5-V supply and 1.5 V for 3.3-V supply. The

maximum source current at this terminal is 2.5 mA.

Feedback node for handset receive path amplifier. HSRX_FB is connected to the output of the handset receive

path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain

and filter poles.

HSRXM

HSRXP

HSTX_IN

40

39

36

I

Handset receive path amplifier analog inverting input

Handset receive path amplifier analog noninverting input

Handset transmit amplifier analog inverting input. This node is normally fed by the HSBUF output through an

input resistor. The noninverting input of the amplifier is connected internally to 2.5 V for 5 V supply and 1.5 V

for 3.3 V supply.

HSTX_OUT

MIC_AUDIO

37

55

O

I

Handset transmit amplifier analog output

Microphonepreamplifier analog input. MIC_AUDIO can be programmed to add either 0-dB or 20-dB gain using

the control registers.

MIC_BIAS

MONOUTM

MONOUTP

56

60

62

O

Output that provides 2.5 V/1.5 V bias for electret microphone. The maximum source current at this terminal

is 5 mA.

8 Ω monitor speaker amplifier analog output. MONOUTM is set for 0-dB gain or is muted using the control

registers.

8 Ω monitor speaker amplifier analog output. MONOUTP is set for 0-dB gain or is muted using the control

registers.

MV

NC

61

59

I

Monitor amplifier supply (5 V/3.3 V)

Monitor amplifier ground

DD

SS

All terminals marked NC should be left unconnected.

POR

20

19

33

51

O

I

Power on reset signal. POR remains low while the 5-V supply at MV

40 ms after it rises above the reset threshold.

is below its threshold voltage and for

DD

RESET

SI_SEL

SPKR_LEFT

Codec device reset. RESET initializes all device internal registers to their default values. This signal is active

low.

I

Serial interface mode select. When SI_SEL is tied to DV the serial port is in FS high mode. When SI_SEL

DD,

is tied to DV , the serial port is in FS low mode (See Section 4, Serial Communications for more details).

SS

O

Analog output from 60-Ω speaker line amplifier. SPKR_LEFT is set for 0-dB gain or is muted using the control

registers.

SPKR_RIGHT

TAPI_IN

52

50

49

O

I

Analog output from 60-Ω speaker line amplifier. SPKR_RIGHT is set for 0-dB gain or is muted using the control

registers.

Analog input to the TAPI (or sound card) preamplifier which can be programmed to add either 0 dB or 20 dB

gain via the control registers.

TAPI_OUT

O

TAPI buffer amplifier analog output. This 600-Ω amplifier is set for 0-dB gain or is muted using the control

registers.

TEST1

TEST2

54

53

48

45

28

I/O Test input/output port. TEST1 is for factory testing only and should be left unconnected.

I/O Test input/output port. TEST2 is for factory testing only and should be left unconnected.

VAV

I

Voice channel analog power supply (5 V/3.3 V)

Voice channel analog ground

DD

SS

VC_DIN

Voice channel digital data input. VC_DIN handles DAC input data as well as control register programming

information during the voice channel frame sync interval. VC_DIN is synchronized to VC_SCLK.

1–6

1.7 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

VC_DOUT

29

O

Voicechanneldigitaldataoutput. VoicechannelADCoutputbitsaretransmittedduringthevoicechannelframe

sync period synchronized to VC_SCLK. VC_DOUT is at high impedance when VC_FS is not activated.

VC_FS

32

Voice channel serial port frame sync signal. VC_FS signals the beginning of transmit for ADC data and receive

of DAC data in the voice channel. This signal can be active high (FS high mode) or active low (FS low mode)

depending on the voltage applied to SI_SEL (see Section 4, Serial Communication for more details).

VC_MCLK

VC_SCLK

30

31

I

Voice channel master clock input. All internal clocks for the voice channel are derived from this clock.

O

Voice channel shift clock signal. VC_SCLK clocks serial data into VC_DIN and out of VC_DOUT during the

voice channel frame-sync interval. VC_SCLK = VC_MCLK/2

VREFM_ADC

VREFM_DAC

VREFP_ADC

46

43

47

O

Voice channel ADC voltage reference filter output. VREFM_ADC provides low-pass filtering of the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_ADC

and VREFP_ADC. The nominal dc voltage at this terminal is 0 V.

Voice channel DAC voltage reference filter output. VREFM_DAC provides low-pass filtering of the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_DAC

and VREFP_DAC. The nominal dc voltage at this terminal is 0 V.

Voice channel ADC voltage reference filter output. VREFP_ADC provides low-pass filtering the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_ADC

and VREFP_ADC. The dc voltage at this terminal is 3.375 V with a 5-V VAV

supply and 2.25 V with a 3.3-V

DD

VAV

DD

supply.

VREFP_DAC

44

1

O

I

Voice channel DAC voltage reference filter output. VREFP_DAC provides low-pass filtering the internal

bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_DAC

and VREFP_DAC. The dc voltage at this terminal is 3.375 V with a 5-V VAV

supply and 2.25 V with a 3.3-V

DD

VAV

DD

supply.

V

SS

Internal substrate connection. V

SS

should be tied to either DAV or VAV

SS

for normal operation.

SS

1–7

1–8

2 Functional Description

2.1 Device Requirements and System Overview

The TLC320AD535 device consists of two codec channels, a hybrid circuit with external resistors and capacitors for

setting gain and filter poles, two independent serial ports, and other miscellaneous logic functions.

2.2 Codec Functions

The codec portion of the TLC320AD535 device performs the functions required for two channels of analog-to-digital

conversion, digital-to-analog conversion, lowpass filtering, control of analog input and output gains, internal

oversampling coupled with internal decimation and interpolation, and two 16-bit serial port interfaces to the host

processor. The two serial ports operate independently and are capable of operating at different sample rates. The

maximum sample rate of either codec channel is 11.025 kHz.

2.3 Hybrid Functions

The hybrid circuitry in the data channel includes integrated amplifiers whose gains and filter pole frequencies are set

by external resistors and capacitors. This allows maximum flexibility to make adjustments for board variations and

international standards while providing integration of the function. The filter amplifier stages in the data channel are

followed by a programmable gain amplifier, which feeds 8-Ω differential speaker drivers for the AT41 call progress

monitor speakers. The monitor speaker driver can be programmed for 0-dB gain or muted through the control 2

register. The source for the monitor speaker input can be either the output of the amplified DAC output (Data_Out

PGA) or the ADC input signal through control register 1 (See Appendix A).

A 2.5 V/1.5 V reference voltage (DT_REF) is provided as a reference for the transformer. It is necessary to reference

to 2.5 V/1.5 V (rather than ground), since the amplifiers are powered off by single-rail supplies. DT_REF is 2.5 V when

DAV

is 5 V and 1.5 V when DAV

is 3.3 V.

DD

2.4 Voice Channel Analog

The analog circuitry in the voice channel includes a microphone bias, which sources a maximum of 5 mA at 2.5 V/

1.5 V, and preamplifiers for the microphone, which can be selected for 0-dB or 20-dB gain. The device also has a

handset interface with receive and transmit amplifiers. These three inputs can be summed in any combination and

the result sent to a Line_In programmable gain amplifier (PGA) stage with gain range from 12 dB to –36 dB in 1.5

dB noiseless steps. This feeds the voice channel ADC. In the DAC path, the output of the DAC is sent to a Line-Out

PGA with gain range from 12 dB to –36 dB in 1.5 dB noiseless steps. This feeds both a 600-Ω TAPI output driver and

a 60-Ω mono speaker driver that can be muted or programmed for 0-dB gain. The time-out for noiseless gain change

or the maximum time the system can wait for a zero crossing of a signal before it will effect the gain change request

is approximately 9 ms.

2.5 Miscellaneous Logic and Other Circuitry

The logic functions include the circuitry required to implement two independent serial ports and control register

programming through secondary communication on those serial ports. There are five control registers that are

programmed during secondary communications from either the data channel serial port or the voice channel serial

port. These control registers set amplifier gains, choose multiplexer inputs, select loopback functions, and read the

ADC overflow flags. The device also includes a power-on reset (POR) circuit to monitor the 5-V MV

power supply

DD

inthesystemandprovidesaresetsignalwhenthesupplyMV voltagedropsbelowitsthresholdvoltage. Inaddition,

DD

there is a flash write enable (FWE) circuit that takes an external logic input and provides 40 mA of current to power

the write enable circuit of an external memory device. The flash write enable circuit is powered from the digital power

supply.

2–1

2–2

3 Codec Functional Description

3.1 Operating Frequencies

The TLC320AD535 is capable of supporting any sample rate up to the maximum sample rate of 11.025 kHz in either

the data channel or voice channel. The sample rate is set by the frequency of the codec master clock that is input

to the serial port for that channel.

The sampling (conversion) frequency is derived from the internally-generated codec master clock divider circuit by

the following equation:

f

Sampling (conversion) frequency

XX_SCLK XX_MCLK 2

XX_MCLK 512

(1)

s

Where XX_MCLK refers to either the voice channel or data channel codec clock (VC_MCLK or DT_MCLK) fed to

the codec externally by the clock rate divider circuit. The clock rate divider circuit divides the system master clock

to obtain the necessary clock frequency to feed the codecs.

The inverse of the sampling frequency is the conversion period. The sample rates of the voice and data channels

can be set independently by their respective codec master clocks. The two codec channels can be sampled at

different rates simultaneously.

3.2 ADC Signal Channel

The input signals are amplified and filtered by on-chip buffers before being applied to their respective ADC input. In

the case of the voice channel, inputs from a microphone input and the handset input may be summed together before

being amplified/attenuated by the ADC line PGA. The ADC converts the signal into discrete output digital words in

2s-complement format, corresponding to the analog signal value at the sampling time. These 16-bit digital words,

representing sampled values of the analog input signal, are sent to the host through the serial port interface for their

respective channels. If the ADC reaches its maximum value, a control register flag is set. This overflow bit resides

at D0 in the data channel control register 2 or the voice channel control register 5. These bits can only be read from

their respective serial ports, and the overflow flag is cleared only if it is read through the voice channel serial port,

and similarly for the data channel. The ADC and DAC conversions are synchronous and phase-locked.

3.3 DAC Signal Channel

The DAC receives the 16-bit data words (2s complement) from the host through the serial port interface for each

channel. The data is converted to analog voltages by their respective sigma-delta DACs comprised of a digital

interpolation filter and a digital modulator. The outputs of the DACs are each then passed to internal low pass filters

to complete the signal reconstruction resulting in an analog signal. Those analog signals are then buffered and

amplified by an output driver capable of driving the required load. The gain of these output amplifiers is programmed

by the

+codec control registers, as shown in Appendix A.

3.4 Sigma-Delta ADC

Each ADC is an oversampling sigma-delta modulator. The ADC provides high resolution and low noise performance

using oversampling techniques and the noise shaping advantages of sigma-delta modulators.

3.5 Decimation Filter

Each decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating with a

ratio equal to the oversampling ratio. The output of this filter is a 16-bit 2s-complement data word clocking at the

selected sample rate.

3–1

3.6 Sigma-Delta DAC

Each DAC is an oversampling sigma-delta modulator. The DAC performs high-resolution, low-noise digital-to-analog

conversion using oversampling sigma-delta techniques.

3.7 Interpolation Filter

Each interpolation filter resamples the digital data at a rate of N times the incoming sample rate, where N is the

oversampling ratio. The high-speed data output from this filter is then applied to the sigma-delta DAC.

3.8 Analog and Digital Loopbacks

The test capabilities include an analog loopback and digital loopback. The loopbacks provide a means of testing the

ADC/DAC channels and are used for in-circuit system-level tests. The loopback feeds the ADC output to the DAC

input on the IC for each individual channel. The analog loopback functions test only the codec portions of the device

and do not include the hybrid amplifiers.

Analog loopback loops the DAC output back into the ADC input of the same channel. Digital loopback loops the ADC

output back into the DAC input of the respective channel. Analog loopback is enabled by setting the D4 bit in the

control register 1 for the data channel or control register 3 for the voice channel. Digital loopback is enabled by setting

the D5 bit high in control register 1 for the data channel or control register 3 for the voice channel.

3.9 Software Power Down

The software power down resets all internal counters, but leaves the contents of the programmable control registers

unchanged for the selected channel. The device has separate and independent software power down bits for the

voice and data channels. The software power down feature is invoked by setting the D6 bit high in control register

1 for the data channel or setting the D6 bit in control register 3 for the voice channel. There is no hardware power

down function in the TLC320AD535.

3.10 Reset Circuit

This circuit monitors the 5-V MV

power supply coming into the device from the bus and asserts an active low

DD

power-on-reset ( POR) signal whenever this supply voltage drops below its threshold voltage. The reset signal

remainslowwhilethesupplyvoltageisbelowthethresholdvoltage. Itremainslowfor40ms(nominal)afterthesupply

voltage has risen above the reset threshold voltage. Once the voltage rises above the threshold, an internal counter

is activated and holds the POR signal low for an additional 40 ms (nominal). The signal then goes high and remains

high as long as the MV

supply remains in the acceptable voltage range. This circuit is, in effect, on initial power

DD

up of the device and POR is held low until the supply voltage rises above the threshold. In addition, a reset is triggered

if a transient spike of sufficient magnitude and duration occurs. The supply must drop below the threshold voltage

for a period of time greater than the delay time shown in the following table (delay time, MV

to reset). If a spike

DD

occurs that drops below the threshold, but the supply voltage returns above the threshold within the delay time, POR

remains in the high state.

3–2

V

MV

0 V

(TO)

DD

POR

40 ms

20 µs

40 ms

Detection of Threshold

Crossing as MV

DD

Goes Low

Crossing as MV

DD

Goes High

Crossing as MV

Goes High

DD

PARAMETER

MIN

10

NOM MAX UNIT

Delay time, MV

DD

to reset

20

40

80

µs

ms

V

Delay time reset pulse (POR)

Threshold voltage V

20

5-V MV

DD

4.5

4.63

4.75

(TO)

3.11 Test Module

Thetestmoduleservesthepurposeoffacilitatingdesignverificationtestingandsimplifyingfactoryproductiontesting.

There are two input/output terminals (TEST1 and TEST2) dedicated to implementing the test functions. The function

of these terminals is for factory self-test only, and no connection (NC) should be made to either of these terminals.

3–3

3–4

4 Serial Communications

DT_DOUT, DT_DIN, DT_SCLK, and DT_FS are the serial communication signals for the data channel serial port,

while VC_DOUT, VC_DIN, VC_SCLK, and VC_FS are the serial communication signals for the voice channel serial

port. The digital output data from the ADC is taken from DT_DOUT (or VC_DOUT). The digital input data for the DAC

is applied to DT_DIN (or VC_DIN). The synchronization clock for the serial communication data and the frame-sync

is taken from DT_SCLK and VC_SCLK for the data and voice channels, respectively. The frame-sync pulse which

signals the beginning of the ADC and DAC data transfer interval is taken from DT_FS and VC_FS for the data and

voice channels, respectively.

For signal data transmitted from the ADC or to the DAC, a primary serial communication is used. A secondary

communication reads or writes words to the control registers, which control both the options and the circuit

configurations of the device.

The purpose of primary and secondary communications is to allow conversion data and control data to be transferred

across the same serial port. A primary transfer is always dedicated to conversion data. A secondary transfer is used

to set up or read the control register values described in Appendix A, Programmable Register Set. A primary transfer

occurs for every conversion period. A secondary transfer occurs only when requested. Secondary serial

communication is requested by software - D0 of the primary data input to DT_DIN for the data channel serial port or

to VC_DIN for the voice channel serial port. A secondary request can be made for the voice channel without making

a secondary request for the data channel, or vice versa. Control registers 1 and 2 can only be written to or read from

the data channel serial port. Control registers 3 through 6 can only be written to or read from the voice channel serial

port.

4.1 Primary Serial Communication

Primary serial communication transmits and receives conversion signal data. The DAC word length is 15 bits and

the last bit of the primary 16-bit serial communication word is a control bit used to request secondary serial

communication. For all serial communications, the most significant bit is transferred first. For the 16-bit ADC word,

D15 is the most significant bit, and D0 is the least significant bit. For the 15-bit DAC data word in a primary

communication, D15 is the most significant bit, D1 is the least significant bit, and D0 is used for the secondary

communication request control. All digital data values are in 2s-complement data format. Refer to Figure 4–1.

XX_DIN

D15–D1

D0

Secondary

Communication Request

D/A Data

A/D Data

D15–D0

XX_DOUT

Figure 4–1. Primary Communication DIN and DOUT Data Format

4–1

4.1.1 FS High Mode Primary Communication Timing

There are two possible modes for serial data transfer. One mode is the FS high mode which is selected by tying the

SI_SEL pin to DV . Figure 4–2 shows the timing relationship for XX_SCLK, XX_FS, XX_DOUT and XX_DIN in a

DD

primary communication for either the voice or data channel when in FS high mode. The timing sequence for this

operation is as follows:

1. XX_FS is brought high and remains high for one XX_SCLK period, then goes low.

2. A16-bitwordistransmittedfromtheADC(DT_DOUTandVC_DOUT)anda16-bitwordisreceivedforDAC

conversion (DT_DIN and VC_DIN).

XX_SCLK

XX_FS

XX_DIN

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

XX_DOUT

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 4–2. FS High Mode Primary Serial Communication Timing

4.1.2 FS Low Mode Primary Communication Timing

The second possible serial interface mode is the FS low mode, which is selected by tying the SI_SEL pin to DV

.

SS

This mode differs from the FS high mode in that the frame sync signal (FS) is active low, data transfer starts on the

falling edge of XX_FS, and XX_FS remains low throughout the data transfer. Figure 4–3 shows the timing relationship

for XX_SCLK, XX_FS, XX_DOUT and XX_DIN in a primary communication for either the voice or data channel when

in FS low mode. The timing sequence for this operation is as follows:

1. XX_FS is brought low by the TLC320AD535.

2. A16-bitwordistransmittedfromtheADC(DT_DOUTandVC_DOUT)anda16-bitwordisreceivedforDAC

conversion (DT_DIN and VC_DIN).

3. XX_FS is brought high signaling the end of the data transfer.

XX_SCLK

XX_FS

XX_DIN

D15 D14 D13 D12

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D11

XX_DOUT

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D11 D10

Figure 4–3. FS Low Mode Primary Serial Communication Timing

4–2

4.2 Secondary Serial Communication

Secondary serial communication reads or writes 16-bit words that program both the options and the circuit

configurations of the device for either the voice channel or the data channel. Register programming always occurs

during secondary communication for that channel. Control registers 1 and 2 can only be written to or read from the

data channel serial port. Control registers 3 through 6 can only be written to or read from the voice channel serial port.

Four primary and secondary communication cycles are required to program the four voice channel registers. In the

same manner, two primary and secondary communication cycles are necessary to program the data channel control

registers. If the default value for a particular register is desired, then the register addressing can be omitted during

secondary communications. The NOOP (no operation) command addresses a pseudo-register, register 0, and no

register programming takes place during this secondary communication. This can be used for either the data channel

or the voice channel serial port.

During a secondary communication, a register is written to or read from. When writing a value to a register, the

DT_DIN (or VC_DIN) line contains the value to be written. The data returned on DT_DOUT (or VC_DOUT) is 00h.

The method for requesting a secondary communication is by asserting the least significant bit (D0) of DT_DIN (or

VC_DIN) high as shown in Table 4–1.

Table 4–1. Least-Significant-Bit Control Function

CONTROL BIT D0

CONTROL BIT FUNCTION

No secondary communication request

Secondary communication request

0

1

Figure 4–4 shows the data format XX_DIN and XX_DOUT during secondary communication.

Don’t Care

D15

XX_DIN

(Read)

––

1

0

D12 D11 D10 D9 D8

D7–D0

R/W

––

Register Address

D12 D11 D10 D9 D8

AII 0

Register Data

D7–D0

D15

––

XX_DIN

(Write)

Register Data

D7–D0

XX_DOUT

(Read)

D15–D8

AII 0

XX_DOUT

(Write)

D15–D0

Figure 4–4. Secondary Communication DIN and DOUT Data Format

4–3

4.2.1 FS High Mode Secondary Communication Timing

On the rising edge of SCLK, coinciding with the falling edge of FS for that channel, D15–D0 is input serially to DT_DIN

(or VC_DIN), and D15–D0 is output serially on DT_DOUT (or VC_DOUT). If a secondary communication request is

made, FS goes high again 128 SCLKs after the beginning of the primary frame to signal the beginning of the

secondary frame one SCLK period later. See Figure 4–5.

128 XX_SCLKs

P

S

P

XX_FS

Data (D0=1)

Register R/W

Data (D0=0)

XX_DIN

Secondary Communication

Request

No Secondary

Communication Request

Figure 4–5. FS Output During Software Secondary Serial Communication Request (FS High Mode)

4.2.2 FS Low Mode Secondary Communication Timing

On the falling edge of XX_FS for that channel, D15–D0 is input serially to XX_DIN and D15–D0 is output serially on

XX_DOUT. XX_FS remains low during the data transfer and then returns high. If a secondary communication request

ismade, XX_FSgoeslow128SCLKsafterthebeginningoftheprimaryframetosignalthebeginningofthesecondary

frame. See Figure 4–6.

128 XX_SCLKs

XX_FS

P

S

P

XX_DIN

Data (D0=1)

Register R/W

Data (D0=0)

Secondary Communication

Request

No Secondary

Communication Request

Figure 4–6. FS Output During Software Secondary Serial Communication Request (FS Low Mode)

4–4

5 Specifications

5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range

†

(Unless Otherwise Noted)

Supply voltage range, DV , AV

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

DD

Output voltage range, all digital output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV

Input voltage range, all digital input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV

Case temperature for 10 seconds: PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

+ 0.3 V

DD

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

.

SS

5.2 Recommended Operating Conditions

MIN NOM

MAX

3.6

5.5

2

UNIT

3.3-V supply

5-V supply

3.3-V supply

5-V supply

3

3.3

5

Supply voltage, DAV , VAV , MV , DV

DD DD DD

(see Note 2)

V

DD

4.5

V

Analog signal peak-to-peak input voltage , DT_RXM, DT_RXP, MIC_AUDIO, TAPI_IN,

HS_RXM, HS_RXP, V

I(analog)

3

Differential output load resistance, TAPI_OUT, DT_BUF, HS_BUF, R

600

8

Ω

L

Differential output load resistance, MONOUTP, MONOUTM, R

Ω

L

Differential output load resistance, SPKR_RIGHT, SPKR_LEFT, R

60

Ω

L

Input impedance, MIC_AUDIO

50

8

kΩ

MHz

pF

kHz

°C

Master clock

5.645

20

Load capacitance, C

L

ADC or DAC conversion rate

Operating free-air temperature, T

11.025

85

–40

A

†

Preamplifier gain set to 0 dB

NOTE 2: Voltages at analog inputs and outputs and xV

are with respect to the xV

SS

terminal.

DD

5.3 Electrical Characteristics Over Operating Free-Air Temperature Range,

DV = 5 V/3.3 V, xAV = 5 V/3.3 V, MV =5 V/3.3 V

DD

5.3.1 Digital Inputs and Outputs, f = 8 kHz, Outputs Not Loaded

s

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High-level output voltage, any digital output

Low-level output voltage, any digital output

High-level input current, any digital input

Low-level input current, any digital input

Input capacitance, any digital input

I

= –360 µA

2.4

DV +0.5

DD

OH

O

= 2 mA

DV –0.5

SS

0.4

10

V

OL

O

I

V

= 5 V

µA

pF

µA

IH

= 0.6 V

IL

C

10

i

Output capacitance, any digital output

Input leakage current, any digital input

Output leakage current, any digital output

o

I

30

I(lkg)

OZ

I

5–1

5.3.2 ADC Channel, f = 8 kHz (see Note 3)

s

PARAMETER

TEST CONDITIONS

0 to 300 Hz

300 Hz to 3 kHz

3.3 kHz

MIN

–0.5

TYP

MAX UNIT

0.2

0.25

0.3

dB

–3

Filter gain relative to gain at 1020 Hz

3.6 kHz

4 kHz

–35

–74

≥ 4.4 kHz

NOTE 3: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test signal is a sine wave with

0 dB = 3 V at 5-V supply and 0 dB = 2 V at 3.3-V supply voltage as the reference level for the ADC analog input signal. The

I(PP)

–3-dB passband is 0 to 3600 Hz for an 8-kHz sample rate. This pass-band scales linearly with the sample rate.

5.3.3 ADC Dynamic Performance, f = 8 kHz

s

5.3.3.1 ADC Signal-to-Noise (see Note 4)

PARAMETER

TEST CONDITIONS

V = –1 dB

MIN

75

TYP MAX

UNIT

80

72

36

I

Signal-to-noise ratio (SNR)

V = –9 dB

I

67

dB

V = –40 dB

I

36

NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referred to 2.5 V for 5-V supply and

1.5 V for 3.3-V supply. The output configuration is in a 3.3 V single ended mode.

5.3.3.2 ADC Signal-to-Distortion (see Note 4)

PARAMETER

TEST CONDITIONS

V = –3 dB

MIN

73

TYP

78

MAX

UNIT

I

Signal-to-total harmonic distortion (THD)

V = –9 dB

I

77

82

dB

V = –40 dB

I

56

61

NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referred to 2.5 V for 5-V supply and

1.5 V for 3.3-V supply. The output configuration is in a 3.3 V single ended mode.

5.3.3.3 ADC Signal-to-Distortion + Noise (see Note 4)

PARAMETER

TEST CONDITIONS

V = –3dB

MIN

72

TYP

77

MAX

UNIT

I

Signal-to-total harmonic distortion + noise (THD + N)

V = –9 dB

I

68

73

dB

V = –40 dB

I

37

42

NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referred to 2.5 V for 5-V supply and

1.5 V for 3.3-V supply. The output configuration is in a 3.3 V single ended mode.

5–2

5.3.4 ADC Characteristics

PARAMETER

TEST CONDITIONS

Preamp gain = 0 dB

MIN

TYP

MAX

UNIT

V

I(PP)

Peak-input voltage, TAPI_IN, MIC_AUDIO

Dynamic range

3

80

85

dB

Intrachannel isolation

Gain error

E

V = –1 dB at 1020 kHz

I

±0.6

G

With a 0.1-µF capacitor between

CAP_D and DTRX_FB

ADC channel offset error including hybrid amplifiers

5

mV

O(ADC)

With no capacitor between CAP_D

and DTRX_FB

E

20

26

O(ADC)

Idle channel noise (on-chip reference)

Channel delay

75 µV rms

17/f

s

5.3.5 DAC Channel, f = 8 kHz (see Note 5)

s

PARAMETER

TEST CONDITIONS

0 to 300 Hz

300 Hz to 3 kHz

3.3 kHz

MIN

–0.5

TYP

MAX

UNIT

0.3

0.25

0.3

–0.25

–0.35

Filter gain relative to gain at 1020 Hz

dB

3.6 kHz

–3

4 kHz

–35

–70

≥ 4.4 kHz

NOTE 5: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the digital equivalent of a

sine wave (digital full scale = 0 dB). The –3 dB passband is 0 to 3600 Hz for an 8-kHz sample rate. This pass band scales linearly with

the sample rate.

5.3.6 DAC Dynamic Performance

5.3.6.1 DAC Signal-to-Noise (see Note 6)

PARAMETER

TEST CONDITIONS

V = 0 dB

MIN

71

TYP

76

MAX

UNIT

I

Signal-to-noise ratio (SNR)

V = –9 dB

I

62

67

dB

V = –40 dB

I

31

36

NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 3.3 V single ended mode.

5.3.6.2 DAC Signal-to-Distortion (see Note 6)

PARAMETER

TEST CONDITIONS

V = –3 dB

MIN

78

TYP

83

MAX

UNIT

I

Signal-to-total harmonic distortion (THD)

V = –9 dB

I

70

75

dB

V = –40 dB

I

56

61

NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 3.3 V single ended mode.

5.3.6.3 DAC Signal-to-Distortion + Noise (see Note 6)

PARAMETER

TEST CONDITIONS

V = –3 dB

MIN

69

TYP MAX

UNIT

74

68

35

I

Signal-to-total harmonic distortion + noise (THD + N)

V = –9 dB

I

63

dB

V = –40 dB

I

30

NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 3.3 V single ended mode.

5–3

5.3.7 DAC Characteristics

PARAMETER

Dynamic range

TEST CONDITIONS

MIN

TYP

79

MAX

UNIT

dB

Intrachannel isolation

85

dB

E

G

Gain error

V = –1 dB at 1020 kHz

I

±0.7

dB

Idle channel narrow-band noise

Channel delay

0 kHz to 4 kHz (see Note 7)

125 µV rms

18/f

s

V

Output offset voltage, HS_BUF, DT_BUF

DIN = All zeros

25

mV

OO

Differential with respect to MV /2

DD

and full-scale digital input

(see Note 8)

5 V

–1.78

1.78

V

Analog output voltage, MONOUTP-MONOUTM

O

3.3 V

5 V

–1.2

–2

1.2

2

V

Analog output voltage, TAPI_OUT, SPKR_LEFT, Single-ended with respect to

SPKR_RIGHT HS_REF and full-scale digital input

V

O

3.3 V

–1.5

1.5

NOTES: 7. The conversion rate is 8 kHz.

8. This amplifier should only be used in differential mode. Common mode: 2.5 V in 5 V supply and 1.5 V in 3.3 V supply.

5.3.8 Logic DC Electrical Characteristics

PARAMETER

MIN

–0.3

2.4

TYP

MAX

UNIT

V

Low-level input voltage

High-level input voltage

Input leakage current

Output leakage current

1.5

IL

DV

0.3

DD+

10

V

IH

I

µA

V

I(lkg)

O(lkg)

10

V

High-level output voltage at rated load current

Low-level output voltage at rated load current

2.4

DV –0.5

DD

OH

OL

V

DV –0.5

SS

0.4

V

5.3.9 Power Supply Rejection (see Note 9)

PARAMETER

TEST CONDITIONS

f = 0 to f /2

MIN

TYP

MAX

UNIT

V

DD1

V

DD2

V

DD3

V

DD4

Supply-voltage rejection ratio, ADC channel DAV

and VAV

DD

50

40

50

DD

i

s

Supply-voltage rejection ratio, ADC channel, DV

f = 0 to f /2

i s

DD

dB

Supply-voltage rejection ratio, DAC channel, DAV

DD

and VAV

DD

f = 0 to f /2

i s

Supply-voltage rejection ratio, DAC channel, DV

DD

f = 0 to 30 kHz

i

NOTE 9: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200 mV peak-to-peak signal

applied to the appropriate supply.

5.3.10 Power Supply

PARAMETER

TEST CONDITIONS

MIN

TYP

40

MAX

UNIT

mA

I

Codec power supply current, analog (including hybrid and drivers) Operating

60

DD(analog)

DD(digital)

DD(monitor)

Codec power supply current, digital

Operating

10

mA

Power supply current, 8 Ω monitor speaker driver

135

315

mA

5–4

5.3.11 Reset Circuit

PARAMETER

Reset threshold voltage

TEST CONDITIONS

T = –40°C to 85°C for 5 V

MIN

TYP

MAX

4.75

0.3

UNIT

V

4.50

(TO)

A

POR output low-level voltage

I

= 1.2 mA

= 3.2 mA

V

OL

(SINK)

POR output low-level voltage

0.4

V

OL

(SINK)

POR output high-level voltage

I = –500 µA

0.8 DV

V

OH

DD

20

t

POR low delay time after threshold exceeded

Delay time after threshold crossed before POR activates

40

20

80

40

ms

µs

d(RPD)

d(RDD)

t

10

5.3.12 Flash Write Enable Circuit

PARAMETER

TEST CONDITIONS

MIN

4.5

2.5

0

TYP

5

MAX

5.5

3.5

1.5

45

UNIT

FLSH_IN low (5 V supply)

FLSH_IN low (3.3 V supply)

FLSH_IN high

V

Output high-level voltage, FLSH_OUT

Output low-level voltage, FLSH_OUT

Output current, FLSH_OUT

V

OH(FLSH_OUT)

OL(FLSH_OUT)

O(FLSH_OUT)

3

V

FLSH_IN low (5 V supply)

40

25

mA

I

FLSH_IN low (3.3 V supply)

mA

5.3.13 8-Ω Drive

PARAMETER

TEST CONDITIONS

MIN

TYP

–96

0.7

MAX

UNIT

Output gain when PGA gain is mute

Output gain when PGA gain is 0 dB

Output gain when PGA gain is 12 dB

–12 dB (input)

–1.5

10.5

1.5

dB

12.5

13.5

5.4 Timing Characteristics (see Parameter Measurement Information)

5.4.1 Timing Requirements

PARAMETER

Delay time, XX_SCLK↑ to XX_FS↓

MIN

TYP

MAX

UNIT

ns

t

0

d1

Setup time, XX_DIN, before XX_SCLK low

Hold time, XX_DIN, after XX_SCLK high

Delay time, XX_MCLK↓ to XX_SCLK↑

Pulse duration, XX_MCLK high

25

ns

su1

h1

20

50

ns

d3

32

20

ns

wH

wL

Pulse duration, XX_MCLK low

ns

t

RESET input pulse width

10MCLKS

ns

pW

5.4.2 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

20

UNIT

t

Delay time, XX_SLCK↑ to XX_DOUT

Enable time, XX_FS↓ to XX_DOUT

Disable time, XX_FS↑ to XX_DOUT Hi-Z

d2

C

= 20 pF

L

25

ns

en1

dis1

20

5–5

5.5 Parameter Measurement Information

t

wH

XX_MCLK

XX_SCLK

t

d3

wL

t

d1

XX_FS

XX_DOUT

XX_DIN

t

dis1

t

d2

D15

D14

t

en1

t

su1

D15

t

h1

Figure 5–1. Serial Communication Timing for FS High Mode

0

–20

–40

–60

–80

–100

– 120

0.8

1.6

2.4

3.2

4

4.8

5.6

6.4

7.2

f – Input Frequency – kHz

I

Figure 5–2. ADC Decimation Filter Response

5–6

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

0.4

0.8

1.2

1.6

2

2.4

2.8

3.2

f – Input Frequency – kHz

I

Figure 5–3. ADC Decimation Filter Passband Ripple

0

–20

–40

–60

–80

–100

– 120

0.8

1.6

2.4

3.2

4

4.8

5.6

6.4

7.2

f – Input Frequency – kHz

I

Figure 5–4. DAC Interpolation Filter Response

5–7

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

0.4

0.8

1.2

1.6

2

2.4

2.8

3.2

f – Input Frequency – kHz

I

Figure 5–5. DAC Interpolation Filter Passband Ripple

5–8

6 Application Information

H

Y

B

R

I

Data

Channel

Serial

Port

Matching

Network

Data Channel

Codec

POTS

D

A

M

P

Power

Reset

Circuit

AT41

SPKR

DRVR

Control

Logic

Headset I/F

Flash

Write

Enable

SPKR

DRVR

Voice Channel

Codec

TAPI I/F

MIC

Voice

Channel

Serial

Port

BIAS/

AMPL

Figure 6–1. Functional Block of a Typical Application

6–1

–

+

TAPI_IN

TAPI Preamp

20/0 dB Gain

2.5 V/1.5 V

Voice Channel Codec

–

MIC_AUDIO

MIC_BIAS

M

I

X

E

R

+

0.33 µF

2.2 kΩ

–

+

16-Bit

ADC

Mic Preamp

20/0 dB Gain

2.5 V/1.5 V

–1

Line_In PGA 12 to –36 dB

1.5 dB Noiseless Steps

31 Steps and Mute

Phantom Power

2.5 V/1.5 V @ 5 mA

HSRX_FB

+

–

†

SPKR_LEFT

2.2 µF

HSRXM

From

Hand Set

60 Ω Pwr Spkr Buffer

0 dB or Mute

( Same Polarity)

–

+

†

HSRXP

†

Handset RX (Hybrid)

†

+

–

†

SPKR_RIGHT

TAPI_OUT

16-Bit

DAC

–

+

2.2 µF

HS_REF

2.5 V/1.5 V

+

–

HSTX_OUT

†

Line_Out PGA 12 to –36 dB

1.5 dB Noiseless Steps

31 Steps and Mute

†

600 Ω TPI Out Buffer

0 dB or Mute

†

HSTX_IN

–

+

Handset TX (Hybrid)

2.5 V/1.5 V

Internal

HS_BUF

+

–

600 Ω Handset Out Buffer

0 dB or Mute

†

Required to meet communication standards

Figure 6–2. Voice Channel Codec Typical Application

6–2

†

DTRXM

T1

–

+

†

–

+

Primary

(Line)

16-Bit

ADC

DTRXP

†

Data (Hybrid)

2.5 V/1.5 V

Mon_Out PGA

0-3-6-9-12 dB Gain

with Mute

Data_In PGA

0/6/12/18 dB Gain

With Mute

–1

†

DTREF (2.5 V @ 10 mA)

–

+

16-Bit

DAC

M

U

X

DTTX_OUT

†

2.5 V/1.5 V

†

DTTX_IN

MONOUTP

AT41

–

+

–

+

Data (Hybrid)

2.5 V/1.5 V

MONOUTM

8 Ω Speaker Buffer

0 dB or Mute

DT_BUF

+

–

2.5 V/1.5 V

0/-6/-12/-18 dB or Mute

600 Ω Data_Out PGA

†

Required to meet communication standards

Figure 6–3. Data Channel Codec Typical Application

6–3

6–4

Appendix A

Programmable Register Set

Bits D12–D8 in a secondary serial communication comprise the address of the register that is written with data carried

in bits D7–D0. D13 determines a read or write cycle to the addressed register. When low (0), a write cycle is selected.

Table A–1 shows the register map.

Table A–1. Register Map

REGISTER NO. D15 D14 D13 D12 D11 D10

D9

0

D8

0

REGISTER NAME

No operation

Control 1

0

1

2

3

4

5

6

0

R/W

0

1

0

1

0

Control 2

1

Control 3

0

Control 4

0

1

Control 5

1

0

Control 6

Table A–2. Control Register 1, Data Channel Control

†

D7

1

D6

—

1

D5

—

1

D4

0

D3

D2

—

1

D1

—

D0

—

1

DESCRIPTION

Software reset for data channel asserted

—

1

0

Software reset for data channel not asserted

S/W power down for data channel enabled

S/W power down for data channel disabled

Data channel digital loopback asserted

Data channel digital loopback not asserted

Select data_in PGA for monitor amp input

Select DAC output for monitor amp input

Monitor amp PGA gain = 12 dB

—

0

—

0

—

0

—

1

0

Monitor amp PGA gain = 9 dB

0

1

0

1

Monitor amp PGA gain = 6 dB

0

Monitor amp PGA gain = 3 dB

0

1

Monitor amp PGA gain = 0 dB

0

Monitor amp PGA gain = mute

†

D4 = reserved

Default value: 00000000

A–1

Table A–3. Control Register 2, Data Channel Control

D7

1

D6

0

D5

0

D4

—

D3

—

D2

—

D1

—

D0

—

DESCRIPTION

Data in (DTRX) PGA gain = mute

Data in (DTRX) PGA gain = 18 dB

Data in (DTRX) PGA gain = 12 dB

Data in (DTRX) PGA gain = 6 dB

Data in (DTRX) PGA gain = 0 dB

0

1

0

1

0

1

0

—

1

0

1

0

1

—

1

—

X

DAC data out PGA gain = mute

DAC data out PGA gain = –18 dB

DAC data out PGA gain = –12 dB

DAC data out PGA gain = –6 dB

DAC data out PGA gain = 0 dB

0

1

0

1

0

—

8 ohm monitor speaker driver gain = 0 dB

0

8 ohm monitor speaker driver gain = mute

Data channel ADC overflow indicator: ← 1 = overflow

—

Default value: 00000000

Table A–4. Control Register 3, Voice Channel Control

D7

1

D6

—

1

D5

—

1

D4

—

1

D3

—

1

D2

—

1

D1

—

1

D0

—

1

DESCRIPTION

Voice channel software reset

0

Voice channel software reset not asserted

Software power down for voice channel enabled

Software power down for voice channel disabled

Voice channel digital loopback

—

0

—

0

Voice channel digital loopback not asserted

Voice channel digital loopback

—

0

Voice channel digital loopback not asserted

TAPI preamp seleted for ADC input

—

0

TAPI preamp not selected for ADC input

Microphone preamp selected for ADC input

Microphone preamp not selected for ADC input

Handset preamp not selected for ADC input

Handset preamp selected for ADC input

TAPI output buffer gain = mute

—

0

—

0

—

0

TAPI output buffer gain = 0 dB

Default value: 00000000

A–2

Table A–5. Control Register 4, Voice Channel Control

D7

1

D6

—

1

D5

—

1

D4

—

1

D3

—

0

D2

—

0

D1

—

0

D0

—

0

DESCRIPTION

TAPI_IN preamp gain = 20 dB

TAPI preamp gain = 0 dB

0

—

Microphone preamp gain = 20 dB

Microphone preamp gain = 0 dB

Voice ADC input PGA gain = mute

0

—

1

0

1

Voice ADC input PGA gain = 12 dB

Voice ADC input PGA gain = 10.5 dB

Voice ADC input PGA gain = 9 dB

Voice ADC input PGA gain = 7.5 dB

Voice ADC input PGA gain = 6 dB

Voice ADC input PGA gain = 4.5 dB

Voice ADC input PGA gain = 3 dB

Voice ADC input PGA gain = 1.5 dB

Voice ADC input PGA gain = 0 dB

Voice ADC input PGA gain = –1.5 dB

Voice ADC input PGA gain = –3 dB

Voice ADC input PGA gain = –4.5 dB

Voice ADC input PGA gain = –6 dB

Voice ADC input PGA gain = –7.5 dB

Voice ADC input PGA gain = –9 dB

Voice ADC input PGA gain = –10.5 dB

Voice ADC input PGA gain = –12 dB

Voice ADC input PGA gain = –13.5 dB

Voice ADC input PGA gain = –15 dB

Voice ADC input PGA gain = –16.5 dB

Voice ADC input PGA gain = –18 dB

Voice ADC input PGA gain = –19.5 dB

Voice ADC input PGA gain = –21 dB

Voice ADC input PGA gain = –22.5 dB

Voice ADC input PGA gain = –24 dB

Voice ADC input PGA gain = –25.5 dB

Voice ADC input PGA gain = –27 dB

Voice ADC input PGA gain = –28.5 dB

Voice ADC input PGA gain = –30 dB

Voice ADC input PGA gain = –31.5 dB

Voice ADC input PGA gain = –33 dB

Voice ADC input PGA gain = –34.5 dB

Voice ADC input PGA gain = –36 dB

Voice ADC input PGA gain = 0 dB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Default value: 00000000

A–3

Table A–6. Control Register 5, Voice Channel Control

D7

1

0

—

D6

1

0

1

0

—

D5

0

1

0

1

0

—

D4

0

1

0

1

0

1

0

1

0

—

D3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

D2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

D1

—

1

D0

—

X

DESCRIPTION

Voice DAC output PGA gain = mute

Voice DAC output PGA gain = 12 dB

Voice DAC output PGA gain = 10.5 dB

Voice DAC output PGA gain = 9 dB

Voice DAC output PGA gain = 7.5 dB

Voice DAC output PGA gain = 6 dB

Voice DAC output PGA gain = 4.5 dB

Voice DAC output PGA gain = 3 dB

Voice DAC output PGA gain = 1.5 dB

Voice DAC output PGA gain = 0 dB

Voice DAC output PGA gain = –1.5 dB

Voice DAC output PGA gain = –3 dB

Voice DAC output PGA gain = –4.5 dB

Voice DAC output PGA gain = –6 dB

Voice DAC output PGA gain = –7.5 dB

Voice DAC output PGA gain = –9 dB

Voice DAC output PGA gain = –10.5 dB

Voice DAC output PGA gain = –12 dB

Voice DAC output PGA gain = –13.5 dB

Voice DAC output PGA gain = –15 dB

Voice DAC output PGA gain = –16.5 dB

Voice DAC output PGA gain = –18 dB

Voice DAC output PGA gain = –19.5 dB

Voice DAC output PGA gain = –21 dB

Voice DAC output PGA gain = –24 dB

Voice DAC output PGA gain = –25.5 dB

Voice DAC output PGA gain = –27 dB

Voice DAC output PGA gain = –28.5 dB

Voice DAC output PGA gain = –30 dB

Voice DAC output PGA gain = –31.5 dB

Voice DAC output PGA gain = –33 dB

Voice DAC output PGA gain = –34.5 dB

Voice DAC output PGA gain = –36 dB

Voice DAC output PGA gain = 0 dB

60 Ω Spkr_L/R buffer gain = 0 dB

0

60 Ω Spkr_L/R buffer gain = mute

—

Voice channel ADC overflow: 1 = overflow

Default value: 00000000

Table A–7. Control Register 6, Voice Channel Control

D7

1

D6

—

X

D5

—

X

D4

—

X

D3

—

X

D2

—

X

D1

—

X

D0

—

X

DESCRIPTION

Handset out buffer gain = mute

Handset out buffer gain = 0 dB

Reserved

0

—

Default value: 00000000

A–4

Appendix B

Mechanical Data

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,50

48

M

0,08

0,17

33

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

9,80

SQ

0,25

12,20

11,80

0,05 MIN

0°–7°

1,45

1,35

0,75

0,45

Seating Plane

1,60 MAX

0,08

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

B–1

B–2


型号：	TLC320AD535PM
厂家：	Rochester Electronics
描述：	SPECIALTY TELECOM CIRCUIT, PQFP64, PLASTIC, TQFP-64
文件：	总43页 (文件大小：887K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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