W181-53SZ_技术文档

W181

Peak-Reducing EMI Solution

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low power CMOS design

Features

• Cypress PREMIS™ family offering

• Generates an EMI optimized clocking signal at the out-

put

• Available in 8-pin Small Outline Integrated Circuit (SO-

IC)or14-pinThinShrinkSmallOutlinePackage(TSSOP

select options only)

• Selectable input to output frequency

• Single 1.25% or 3.75% down or center spread output

Simplified Block Diagram

Pin Configurations

3.3 or 5.0V

SOIC

CLKIN or X1

NC or X2

GND

FS2

1

2

3

4

8

7

6

5

FS1

X1

VDD

XTAL

Input

SS%

CLKOUT

X2

Spread Spectrum

Output

(EMI suppressed)

W181

40 MHz

Max.

CLKIN or X1

NC or X2

SSON#

FS1

1

2

8

7

GND

SS%

VDD

3

4

6

5

3.3 or 5.0V

CLKOUT

TSSOP

FS2

CLKIN or X1

14

13

12

NC

1

2

3

Oscillator or

FS1

NC

NC or X2

GND

Reference Input

Spread Spectrum

Output

4

5

6

7

W181

11

10

9

VDD

NC

SS%

(EMI suppressed)

NC

CLKOUT

8

Cypress Semiconductor Corporation

Document #: 38-07152 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 25, 2003

W181

Pin Definitions

Pin No.

(SOIC)

Pin No.

Pin Name

(TSSOP)(-01) Type

Pin Description

CLKOUT

5

8

2

O

I

Output Modulated Frequency: Frequency modulated copy of the un-

modulated input clock (SSON# asserted).

CLKIN or X1

1

2

Crystal Connection or External Reference Frequency Input: This pin

has dual functions. It may either be connected to an external crystal, or

to an external reference clock.

NC or X2

SSON#

3

I

Crystal Connection: If using an external reference, this pin must be left

unconnected.

8(02/03/52/53

)

--

Spread Spectrum Control (Active LOW): Asserting this signal (active

LOW) turns the internal modulation waveform on. This pin has an internal

pull-down resistor.

FS1:2

SS%

7, 8 (01/51)

4

12, 1

6

I

Frequency Selection Bit(s) 1 and 2: These pins select the frequency

range of operation. Refer to Table 2. These pins have internal pull-up

resistors.

Modulation Width Selection: When Spread Spectrum feature is turned

on, this pin is used to select the amount of variation and peak EMI reduc-

tion that is desired on the output signal. This pin has an internal pull-up

resistor.

VDD

GND

6

3

10

4

P

Power Connection: Connected to 3.3V or 5V power supply.

G

Ground Connection: Connect all ground pins to the common system

ground plane.

NC

5, 7, 9, 11, 13,

14

NC No Connection

Key Specifications

Overview

Supply Voltages: .........................................V_DD= 3.3V ± 5%

.................................................................or V_DD= 5V ± 10%

The W181 products are one series of devices in the Cypress

PREMIS family. The PREMIS family incorporates the latest

advances in PLL spread spectrum frequency synthesizer

techniques. By frequency modulating the output with a

low-frequency carrier, peak EMI is greatly reduced. Use of this

technology allows systems to pass increasingly difficult EMI

testing without resorting to costly shielding or redesign.

Frequency Range: ............................ 28 MHz ≤ F_in≤ 75 MHz

Crystal Reference Range.................. 28 MHz ≤ F_in≤ 40 MHz

Cycle to Cycle Jitter: ....................................... 300 ps (max.)

Selectable Spread Percentage: ................... 1.25% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output Rise and Fall Time: .................................. 5 ns (max.)

In a system, not only is EMI reduced in the various clock lines,

but also in all signals which are synchronized to the clock.

Therefore, the benefits of using this technology increase with

the number of address and data lines in the system. The

Simplified Block Diagram on page 1 shows a simple imple-

mentation.

Table 1. Modulation Width Selection

SS% W181-01, 02, 03 Output W181-51, 52, 53 Output

Functional Description

0

–1.25%

(Down Spread)

±0.625

(Center Spread)

The W181 uses a phase-locked loop (PLL) to frequency

modulate an input clock. The result is an output clock whose

frequency is slowly swept over a narrow band near the input

signal. The basic circuit topology is shown in Figure 1. The

input reference signal is divided by Q and fed to the phase

detector. A signal from the VCO is divided by P and fed back

to the phase detector also. The PLL will force the frequency of

the VCO output signal to change until the divided output signal

and the divided reference signal match at the phase detector

input. The output frequency is then equal to the ratio of P/Q

times the reference frequency. (Note: For the W181 the output

frequency is equal to the input frequency.) The unique feature

of the Spread Spectrum Frequency Timing Generator is that a

modulating waveform is superimposed at the input to the VCO.

This causes the VCO output to be slowly swept across a

predetermined frequency band.

1

–3.75%

(Down Spread)

±1.875%

(Center Spread)

Table 2. Frequency Range Selection

W181 Option#

-02, 52

-01, 51

(MHz)

-03, 53

(MHz)

FS2 FS1

(MHz)

0

1

0

1

0

1

28 ≤ F_IN≤ 38 28 ≤ F_IN≤ 38

38 ≤ F_IN≤ 48 38 ≤ F_IN≤ 48

N/A

46 ≤ F_IN≤ 60

58 ≤ F_IN≤ 75

N/A

46 ≤ F_IN≤ 60

58 ≤ F_IN≤ 75

Document #: 38-07152 Rev. *C

Page 2 of 9

W181

Because the modulating frequency is typically 1000 times

slower than the fundamental clock, the spread spectrum

process has little impact on system performance.

Using frequency select bits (FS1:2 pins), the frequency range

can be set. Spreading percentage is set to be 1.25% or 3.75%

(see Table 1).

A larger spreading percentage improves EMI reduction.

However, large spread percentages may either exceed

system maximum frequency ratings or lower the average

frequency to a point where performance is affected. For these

reasons, spreading percentages between 0.5% and 2.5% are

most common.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI

reduction depends on the shape, modulation percentage, and

frequency of the modulating waveform. While the shape and

frequency of the modulating waveform are fixed for a given

frequency, the modulation percentage may be varied.

V_DD

Clock Input

CLKOUT

Freq.

Divider

Q

Phase

Detector

Charge

Pump

Post

Dividers

Reference Input

(EMI suppressed)

Σ

VCO

Modulating

Waveform

Feedback

Divider

P

PLL

GND

Figure 1. Functional Block Diagram

The output clock is modulated with a waveform depicted in

Figure 3. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions.

Figure 3 details the Cypress spreading pattern. Cypress does

offer options with more spread and greater EMI reduction.

Contact your local Sales representative for details on these

devices.

Spread Spectrum Frequency Timing

Generation

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the ampli-

tudes of the radiated electromagnetic emissions are reduced.

This effect is depicted in Figure 2.

As shown in Figure 2, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is:

dB = 6.5 + 9*log₁₀(P) + 9*log₁₀(F)

where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

Document #: 38-07152 Rev. *C

Page 3 of 9

W181

EMI Reduction

SSFTG

Typical Clock

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Frequency Span (MHz)

Center spread

Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

Frequency Span (MHz)

Down Spread

MAX.

MIN.

Figure 3. Typical Modulation Profile

Document #: 38-07152 Rev. *C

Page 4 of 9

W181

.

Absolute Maximum Conditions^[2]

Parameter

Description

Rating

–0.5 to +7.0

–65 to +150

0 to +70

Unit

V_DD, V_IN

T_STG

T_A

Voltage on any pin with respect to GND

Storage Temperature

V

°C

W

Operating Temperature

T_B

Ambient Temperature under Bias

Power Dissipation

–55 to +125

0.5

P_D

DC Electrical Characteristics: 0°C < T_A< 70°C, V_DD= 3.3V ±5%

Parameter

I_DD

Description

Supply Current

Test Condition

Min.

Typ.

18

–

Max.

Unit

mA

ms

–

32

5

t_ON

Power-Up Time

First locked clock cycle after Power

Good

V_IL

V_IH

V_OL

V_OH

I_IL

Input Low Voltage

–

2.4

–

0.8

–

V

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

–

0.4

–

V

2.4

–

V

Note 3

–

–100

10

–

µA

mA

pF

kΩ

Ω

I_IH

Input High Current

Output Low Current

Output High Current

Input Capacitance

Input Pull-Up Resistor^[3]

Clock Output Impedance

Note 3

–

I_OL

I_OH

C_I

@ 0.4V, V_DD= 3.3V

@ 2.4V, V_DD= 3.3V

All pins except CLKIN

CLKIN pin only

–

15

v

–

7

C_I

–

6

10

–

R_P

–

500

25

Z_OUT

–

DC Electrical Characteristics: 0°C < T_A< 70°C, V_DD= 5V ±10%

Parameter

I_DD

Description

Supply Current

Test Condition

Min.

Typ.

Max.

50

Unit

mA

ms

30

t_ON

Power-Up Time

First locked clock cycle after

Power Good

5

V_IL

V_IH

V_OL

V_OH

I_IL

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

Input High Current

Output Low Current

Output High Current

Input Capacitance

Input Pull-Up Resistor

0.15V_DD

0.4

V

0.7V_DD

2.4

V

Note 3

–100

10

µA

mA

pF

kΩ

I_IH

Note 3

I_OL

I_OH

C_I

@ 0.4V, V_DD= 5V

@ 2.4V, V_DD= 5V

All pins except CLKIN

CLKIN pin only

24

7

C_I

6

10

R_P

500

Notes:

1. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at

these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may

affect reliability

2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.

3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.

Document #: 38-07152 Rev. *C

Page 5 of 9

W181

AC Electrical Characteristics: T_A= 0°C to +70°C, V_DD= 3.3V ±5% or 5V±10%

Parameter

Description

Input Frequency

Test Condition

Input Clock

Min.

28

Typ.

Max.

75

5

Unit

MHz

ns

f_IN

f_OUT

t_R

Output Frequency

Output Rise Time

Output Fall Time

Output Duty Cycle

Input Duty Cycle

Jitter, Cycle-to-Cycle

Harmonic Reduction

Spread Off

28

V_DD, 15-pF load 0.8V–2.4V

V_DD, 15-pF load 2.4V–0.8V

15-pF load

2

t_F

5

ns

t_OD

t_ID

40

60

300

%

t_JCYC

250

ps

f_out= 40 MHz, third harmonic

measured, reference board,

15-pF load

8

dB

CLKOUT Frequency Offset (Shift)^[4,5]:T_A= 0°C to +70°C, V_DD= 3.3V ±5% or 5V±10% (For only W181-02, -02 and -03 products)

Parameter

FOFFSET-1

FOFFSET-2

FOFFSET-3

FOFFSET-4

Description

Frequency Offset (Shift)

Frequency Range (MHz)

FS2=0, FS1=0, 28≤F_IN≤38

FS2=0, FS1=1, 38≤F_IN≤48

FS2=1, FS1=0, 46≤F_IN≤60

FS2=1, FS1=1, 58≤F_IN≤75

Min.

–0.8

–1.1

–0.2

–0.8

Typ.

–1.0

–1.4

–0.5

–1.0

Max.

–1.2

–1.7

–0.8

–1.2

Unit

%

V_DDdecoupling is important to both reduce phase jitter and

EMI radiation. The 0.1-µF decoupling capacitor should be

placed as close to the V_DDpin as possible, otherwise the

increased trace inductance will negate its decoupling

capability. The 10-µF decoupling capacitor shown should be a

tantalum type. For further EMI protection, the V_DDconnection

can be made via a ferrite bead, as shown.

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power

supply decoupling scheme shown in Figure 4 should be used.

Recommended Board Layout

Figure 5 shows a recommended 2-layer board layout.

Reference Input

1

2

3

4

8

7

6

5

NC

GND

Clock

Output

R1

C1

µF

0.1

3.3 or 5V System Supply

FB

C2

10-

µF Tantalum

Figure 4. Recommended Circuit Configuration

Notes:

4. The frequency offset (shift) is given with respect to ideal peak value which is the same as input reference frequency in the case of down spread only for W180-01,-02

and -03 products.

5. There is no offset (shift) for center spread for W180-51,-52 and -53 products.

Document #: 38-07152 Rev. *C

Page 6 of 9

W181

High frequency supply decoupling

µF recommended).

C1 =

C2 =

capacitor (0.1-

Common supply low frequency

µF tantalum

decoupling capacitor (10-

recommended).

Match value to line impedance

Ferrite Bead

R1 =

FB

=

Reference Input

NC

G

=

Via To GND Plane

C1

G

Clock Output

R1

G

C2

Power Supply Input

FB

(3.3 or 5V)

Figure 5. Recommended Board Layout (2-Layer Board)

Ordering Information

Ordering Code

W181-01G

Package Type

8-pin Plastic SOIC (150-mil)

Product Flow

Commercial, 0° to 70°C

W181-01GT

W181-01SZ

W181-01SZT

W181-02G

8-pin Plastic SOIC (150-mil) – Tape and Reel

8 pin Plastic SOIC (150-mil) - (Lead Free)

8-pin Plastic SOIC (150-mil) – Tape and Reel- (Lead Free) Commercial, 0° to 70°C

8 pin Plastic SOIC (150-mil)

Commercial, 0° to 70°C

W181-02GT

W181-02SZ

W181-02SZT

W181-03G

8-pin Plastic SOIC (150-mil) – Tape and Reel

8 pin Plastic SOIC (150-mil)- (Lead Free)

8-pin Plastic SOIC (150-mil) – Tape and Reel- (Lead Free) Commercial, 0° to 70°C

8 pin Plastic SOIC (150-mil

Commercial, 0° to 70°C

W181-03GT

W181-03SZ

W181-03SZT

W181-51G

8-pin Plastic SOIC (150-mil) – Tape and Reel

8 pin Plastic SOIC (150-mil)- (Lead Free)

8 pin Plastic SOIC (150-mil) – Tape and Reel- (Lead Free) Commercial, 0° to 70°C

8-pin Plastic SOIC (150-mil)

Commercial, 0° to 70°C

W181-51GT

W181-51SZ

W181-51SZT

W181-52G

8-pin Plastic SOIC (150-mil) – Tape and Reel

8 pin Plastic SOIC (150-mil)- (Lead Free)

8-pin Plastic SOIC (150-mil) – Tape and Reel- (Lead Free) Commercial, 0° to 70°C

8 pin Plastic SOIC (150-mil)

Commercial, 0° to 70°C

W181-52GT

W181-52SZ

W181-52SZT

W181-53G

8-pin Plastic SOIC (150-mil) – Tape and Reel

8 pin Plastic SOIC (150-mil)- (Lead Free)

8-pin Plastic SOIC (150-mil) – Tape and Reel- (Lead Free) Commercial, 0° to 70°C

8 pin Plastic SOIC (150-mil

Commercial, 0° to 70°C

W181-53GT

W181-53SZ

W181-53SZT

W181-01X

8-pin Plastic SOIC (150-mil) – Tape and Reel

8 pin Plastic SOIC (150-mil)- (Lead Free)

8 pin Plastic SOIC (150-mil) – Tape and Reel- (Lead Free) Commercial, 0° to 70°C

14-pin Plastic TSSOP

Commercial, 0° to 70°C

W181-01XT

14-pin Plastic TSSOP – Tape and Reel

Document #: 38-07152 Rev. *C

Page 7 of 9

W181

Package Drawing and Dimension

14-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z14

PIN 1 ID

1

6.25[0.246]

6.50[0.256]

4.30[0.169]

4.50[0.177]

14

0.65[0.025]

BSC.

0.25[0.010]

BSC

0.19[0.007]

0.30[0.012]

1.10[0.043] MAX.

GAUGE

PLANE

0°-8°

0.076[0.003]

0.50[0.020]

0.70[0.027]

0.05[0.002]

0.15[0.006]

0.85[0.033]

0.95[0.037]

0.09[[0.003]

0.20[0.008]

SEATING

PLANE

4.90[0.193]

5.10[0.200]

51-85117-*A

8 Lead (150 Mil) SOIC - S08

8-lead (150-Mil) SOIC S8

PIN 1 ID

4

1

1. DIMENSIONS IN INCHES[MM] MIN.

MAX.

2. PIN 1 ID IS OPTIONAL,

ROUND ON SINGLE LEADFRAME

RECTANGULAR ON MATRIX LEADFRAME

0.150[3.810]

0.157[3.987]

3. REFERENCE JEDEC MS-012

4. PACKAGE WEIGHT 0.07gms

0.230[5.842]

0.244[6.197]

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

5

8

0.189[4.800]

0.196[4.978]

0.010[0.254]

0.016[0.406]

X 45°

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.004[0.102]

0.0098[0.249]

0°~8°

0.016[0.406]

0.035[0.889]

0.0138[0.350]

0.0192[0.487]

51-85066-*C

PREMIS is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trade-

marks of their respective holders.

Document #: 38-07152 Rev. *C

Page 8 of 9

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

W181

Document History Page

Document Title: W181 Peak Reducing EMI Solution

Document Number: 38-07152

Orig. of

REV. ECN No. Issue Date Change

Description of Change

**

*A

*B

110262

122687

127906

12/15/01

12/27/02

07/07/03

SZV

RBI

IJA

Change from Spec number: 38-00790 to 38-07152

Added power up requirements to maximum ratings information.

Changed Modulation Width Selection values in Table 1

Added CLKOUT Frequency Offset Table

Created Cypress approved drawings to replace old ones

Updated Ordering Information to clarify and match ordering codes to Dev Master

*C

131492

01/22/04

RGL

Added Lead-free for all the SOIC packages in the ordering information

Document #: 38-07152 Rev. *C

Page 9 of 9


型号：	W181-53SZ
厂家：	Rochester Electronics
描述：	75 MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8 时钟光电二极管外围集成电路晶体
文件：	总10页 (文件大小：802K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W181-53SZ [ROCHESTER]

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