BD18351EFV-M_技术文档

Datasheet

LED driver IC series for Automotive lamps

LED Driver with Built-in PWM Signal

Generation Circuit

BD18351EFV-M

General Description

Key Specifications

Input Voltage Range:

Output Voltage Range:

BD18351EFV-M is an LED driver with built-in 1ch boost

controller. It is an optimal IC for LED drive for head lamp /

DRL, tail lamp and turn lamp capable of realizing boost

and buck boost with high-side detection of LED current

setting against output voltage.

4.5 V to 65 V

6.0 V to 65 V

Absolute Maximum Input / Output Voltage:

Minimum PWM Dimming Pulse Width:

70 V

50 µs

Further, cost saving and downsizing of the set can be

realized, since it contains CRTIMER which enables PWM

dimming without microcomputer for applications requiring

PWM dimming of DRL, etc.

Features



AEC-Q100 Qualified ^{(Note 1)}

Package

HTSSOP-B24

W(Typ) × D(Typ) × H(Max)

7.80 mm × 7.60 mm × 1.00 mm

Built-in Switching DC / DC Controller.

LED Current Setting High Side Detection Method

LED Current Precision: ±3.0% (–40 °C to 125 °C)

PWM Signal Generation Circuit with Built-in

CRTIMER (External PWM Dimming Control is

possible.)



Built-in Spread Spectrum Function

Built-in LED Open Detection Function

Built-in LED Anode to Ground Short Function

(Note 1) Grade1

Applications

Head lamp, DRL, front position lamp, tail lamp, turn lamp

HTSSOP-B24

Typical Application Circuit

External

power

VOUT

VB

FAIL

VREG50

VCC

EN

ODT

VREG25

RT

DCD

VOUT

DRL

SWDRV

CS

RS

BD18351EFV-M

COMP

SS

VREG50

VREG

IMP

IMN

DISC

CR

PWMOUT

TDISC

GND

DGND

Figure 1. Typical Application Circuit

〇Product structure: Silicon integrated circuit 〇This product has no designed protection against radioactive rays

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Pin Configuration

HTSSOP-B24

(TOP VIEW)

COMP

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

VCC

EN

SS

GND

DRL

DCD

VREG25

RT

N.C

VREG50

ODT

RS

CR

SWDRV

CS

DISC

16 DGND

FAIL 10

11

N.C

15

14

13

Thermal PAD

TDISC

IMP

IMN

PWMOUT 12

Figure 2. Pin Configuration

Terminal

Pin Description

Terminal

Symbol

No.

Function

Symbol

Function

No.

Error amplifier output phase

compensation terminal

1

2

3

4

5

6

7

COMP

SS

13

IMN

IMP

LED current detection terminal (-)

LED current detection terminal (+)

-

Soft start setting terminal

Small signal GND

14

15

16

17

18

19

GND

DCD

VREG25

RT

N.C.

DGND

CS

DC dimming terminal

Power GND

2.5V standard voltage

(DCD Exclusive terminal)

Over current detection setting terminal

DC / DC oscillation frequency

setting terminal

SWDRV External FET gate drive terminal

Spread spectrum frequency

setting terminal

RS

ODT

LED open detection setting terminal

Built-in CRTIMER

PWM dimming frequency /

Duty setting terminal

Internal constant voltage 5.0 V

output terminal

8

CR

20

VREG50

Built-in CRTIMER

Discharge setting terminal

9

DISC

FAIL

21

22

23

24

N.C.

DRL

EN

-

Terminal for DRL control switching

(High: 100 % mode)

10

11

12

Error flag output terminal

TDISC

PWMOUT

Discharge time setting terminal

EN control terminal (High: Active)

Power voltage terminal

External for PWM dimming

FET gate drive terminal

VCC

(Pay attention that it does not correspond to reverse insertion.)

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Block Diagram

VREG50

FAIL

VCC

VREG

VREG50

UVLO

TSD

VREG25

EN

VREG25

EN

CTL

OPEN

DET

LOGIC CONTROL

ODT

RT

RS

OSC

SLOPE

－

DRV

CTL

PWM

＋

SWDRV

CS

RAMP

OCP

DC

DIMMING

DCD

－

ERRAMP

IMP

IMN

CURRENT

SENSE

＋

COMP

SS

VOUT

DISC

TDISC

DRL

DISC

CR

PWM

DIMMING

DRV

CTL

PWMOUT

GND

DGND

Figure 3. Block Diagram

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Description of Blocks

1. Standard voltage (VREG50)

5 V (Typ) is generated from VCC input voltage. This voltage (VREG) is used as power supply for internal circuit, and is also

used to fix terminal at high voltage outside the IC. Please connect C_VREG50= 2.2 μF (Typ) as phase compensation capacity

for VREG50 terminal. If C_VREG50is not connected, circuit operation will become markedly unstable. In addition, please do not

use VREG50 as a power supply except this IC.

2. Concerning LED current setting and luminance adjustment(CURRENTSENSE)

(1) Concerning LED current setting method

VCC

LED current can be calculated by the following formula.

푉

ꢀ_푆퐸푇

푉_퐷퐶퐷

ꢁ.2ꢁ푉

푅퐸퐹1

퐼_퐿퐸퐷

=

×

SWDRV

CS

However, assign V_DCD= 1.21 V in the case of V_DCD> 1.21 V.

R_SET

(Example)

In the case of connection of RSET = 0.4 Ω, V_DCD= 0.6 V,

0.2푉

0.4훺 ꢁ.2ꢁ푉

0.6푉

IMP

IMN

퐼_퐿퐸퐷

=

×

≒ 0.25퐴

V_REF1

I_LED: LED current

V_REF1: Standard voltage for LED current setting (200 mV (Typ)

R_SET: Resistance for LED current setting

V_DCD: DCD terminal voltage

Figure 4. LED Current Setting Method

(2) Concerning luminance adjustment by PWM dimming control(PWM DIMMING)

PWM dimming control with built-in CR timer

PWM dimming is operated in 100 % by connecting Di to DRL terminal and turning DRL terminal to High as shown in Figure 1

On the other hand, when DRL terminal is turned low and configuration is made as shown in Figure 5, internal CR timer will

operate, triangle wave is generated by CR terminal, PWMOUT terminal will be controlled to turn LED current off in CR

voltage rise zone and turn LED current on in CR voltage fall zone. CR voltage rise / fall time can be set by the values of

external parts (C_CR, R_DISC1, R_DISC2). Refer to the next page for setting method. In addition, the recommended operation

frequency is 100 Hz to 2 kHz, On Duty 2 % to 45 %, and the recommended range of the external component values are 0.01

µF to 1.0 µF for C_CRand 10 kΩ to 33 kΩ for R_DISC2.(PWM min pulse width=50 µs)

VREG50

R_DISC1

DISC

R_DISC2

PWMOUT

DRV

＋

C_CR

CR

1.0V/2.0V

－

VREG50

DRL

PROTECT

SIGNAL

Figure 5. Example of Application Using Built-in CR Timer

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Trise

Tfall

2.0V

VREG50 x 0.4

CR fall

CR terminal

PWMOUT terminal

LED current

CR rise

VREG50 x 0.2

1.0V

LED OFF

LED ON

Trise=0.287×C_CR×（R_DISC1+R_DISC2

）

Tfall=0.693×C_CR×R_DISC2

Figure 6. PWM Dimming Operation

CR terminal rise / fall time can be calculated as shown below.

1. CR terminal rise time T_rise

(

) [ ]

ꢆ

ꢂ_푟푖푠푒= 0.287 × ꢃ_퐶푅× ꢀ_{퐷ꢄ푆퐶1}+ ꢀ_{퐷ꢄ푆퐶ꢅ}

2. CR terminal fall time T_fall

[ ]

= 0.693 × ꢃ_퐶푅× ꢀ_{퐷ꢄ푆퐶ꢅ}ꢆ

ꢂ

푓푎푙푙

3. PWM dimming frequency F_PWM

PWM frequency is determined by T_riseandT_fall.

ꢁ

[ ]

퐻푧

ꢇ_푃푊푀

=

ꢈ

_푓푎푙푙ꢉ

ꢂ_푟푖푠푒+ ꢂ

4. PWM dimming ON Duty (D_PWM

)

ON Duty of PWM is determined by T_riseand T_fallas shown in the description above.

ꢂ

푓푎푙푙

[ ]

× ꢁ00 %

ꢊ_푃푊푀

=

ꢈ

_푓푎푙푙ꢉ

ꢂ_푟푖푠푒+ ꢂ

(Example) when C_CR= 0.1 μF, R_DISC1= 100 kΩ, R_DISC2= 20 kΩ (Typ)

(

)

ꢂ_푟푖푠푒= 0.287 × ꢃ_퐶푅× ꢀ_{퐷ꢄ푆퐶1}+ ꢀ_{퐷ꢄ푆퐶ꢅ}= 3.444 [푚ꢆ]

ꢂ

= 0.693 × ꢃ_퐶푅× ꢀ_{퐷ꢄ푆퐶ꢅ}= ꢁ.386 [푚ꢆ]

ꢁ

푓푎푙푙

ꢇ_푃푊푀

=

= 207 [퐻푧]

ꢈ

_푓푎푙푙ꢉ

ꢂ_푟푖푠푒+ ꢂ

ꢂ

푓푎푙푙

ꢊ_푃푊푀

=

× ꢁ00 = 28.7 [%]

ꢈ

_푓푎푙푙ꢉ

ꢂ_푟푖푠푒+ ꢂ

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PWM dimming control with external signal (microcomputer, etc.)

Dimming is possible by direct input of PWM signal from external microcomputer, etc. Input PWM signal in CR terminal. Set

‘High’ level voltage of input signal from microcomputer at no less than 2.5 V for CR threshold voltage, and set ‘Low’ level

voltage at no more than 0.5 V of CR threshold voltage. Recommended input frequency range is 100 Hz to 2 kHz. Minimum

pulse width is 50 µs. It’s necessary that 51kΩ resister need between μ-con and CR terminal like Figure 7. When filter is

required, configure filter in high side of Figure 7 51kΩ.

However verification with actual application is required as filter may cause difference between Input signal to CR terminal

and PWMOUT terminal.

DISC

＋

－

μ-con

CR

51kΩ

DRV

PWMOUT

VREG50 x 0.2,

VREG50 x 0.4

Figure 7. External Input of PWM Signal

(3) PWM Dimming with PchMOS

PWM dimming can be performed by PchMOS (Figure 8 (a) Q3) with Figure 8 configuration. In this configuration, RPWM1 /

RPWM2 / RPWM3 controls gate voltage of PchMOS. If RPWM2, RPWM3 are bigger and gate capacitance of Q3 is high, this

result in discrepancy in PWM ON width generated by PWMOUT pin output and LED current ON width controlled by Q3 .

Please thereby perform the evaluation with the actual equipment by the constitution using PchMOS enough because it may

cause instable operation such as high brightness lighting or the acoustic noise of capacitor and inductor.

VCC

IMP

RPWM3

SWDRV

IMN

CS

Q3

IMP

IMN

RPWM1

PWMOUT

Q2

RPWM2

Figure 8 (a). PWM Dimming with PchMOS

Figure 8 (b). PWM Dimming with PchMOS

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(4) Brightness control by DC dimming control(DC DIMMING / VREG25)

LED current is linearly controllable corresponding to DCD terminal voltage. DCD terminal is mainly used for derating, and is

used to control deterioration of LED at high temperature or to limit over current to external parts under conditions which

power supply voltage fluctuates by idling stop functions, etc. (Refer to Figure 9). Recommended input range is 0.4 ≤ V_DCD

≤

VREG25 and LED current control starts in V_DCD≤ 1.21 V. In addition, the power supply voltage to control DCD can be

controlled with high precision by using VREG25. When DC dimming is not used, short to VREG25 terminal directly.

VREG25

Calculated Value

R1

Measured Value

DCD

R2

R3

Surrounding Temperature [°C]

R1: 12kΩ

R2: 100 kΩ

R3: NTCG104EF104F

Figure 9. Example of Derating Setting Using Thermistor Resistance

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3. Boost DC / DC controller

(1) Concerning open detection voltage setting(OPEN DET)

Open of LED is detectable by inputting resistance division connected to

anode side of LED (DC / DC output V_OUT) in ODT terminal. LED open

V_OUT

detection voltage is detectable by connecting external resistors (R_ODT1

,

R_ODT2) as shown in Figure 10, and output voltage V_{OUT_ODT}at the time of

LED open detection voltage is calculable as shown below.

R_ODT1

(ꢀ_푂퐷푇1+ ꢀ_푂퐷푇ꢅ

ꢀ_푂퐷푇ꢅ

)

ODT

푉_{푂푈푇_푂퐷푇}

=

× ꢁ.5푉(ꢂ푦푝)

＋

R_ODT2

(Example)

LED open detection will operate with V_{OUT_ODT}= 34.5 V

when R_ODT1= 660 kΩ and R_ODT2= 30 kΩ.

－

1.5V/1.4V

LED open detection voltage needs higher voltage setting than

overshoot of output voltage at start up to avoid start up failure.

ODT resistor will be the current discharge path for the output

capacitor when PWM = Low. Recommended value for R_ODT1is 600

Figure 10. ODT terminal Equivalent Circuit

kΩ to 1000 kΩ as Vout ripple may be large and cause LED flickering when PWM = Low with inadequate ohmic value range.

Moreover, the behavior differs by characteristic of output capacitor or LED, therefore sufficient verification with actual

application is required.(Vout drop can be prevented by inserting bigger output capacitor or ODT resistance.)

(2) Concerning number of LED series stages

As shown in Figure 11, although IMP terminal is connected to

VCC

boost DC / DC output at highest voltage among applications.

The number of the steps of the LED which can be driven is decided

by the LED opening detection voltage instead of 65V that is

withstand voltage. For example, when the ODT terminal voltage

V_ODT= 1.35 V at driving a normal LED, the maximum output

voltage V_{OUT_MAX}is as follows.

SWDRV

ꢁ.35푉

ꢁ.575푉

65푉 ×

≒ 55.7푉

R_SET

CS

In other words, drivable LED series stage N is calculable by the

formula below.

IMP

IMN

푉

× 푁 + 푉

< 55.7푉

퐹_푀ꢋ푋

푅퐸퐹_푀ꢋ푋

V_REF

VF_MAX: maximum value of VF of LED

N: number of LED series stages

VREF_MAX: maximum value of standard voltage

for LED current setting

(Example)

When V_{F_MAX}= 3.5 V and V_{REF_MAX}= 0.206 V, number of drivable LED

series stages N is as shown below.

Figure 11. Example of Application Circuit

(

)

푁 < 55.7푉 − 0.206푉 ∕ 3.5푉 = ꢁ5.86

LED drivable number of LED stages is 15.

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(3) Concerning oscillation frequency F_OSC(OSC)

Connection of resistance with RT terminal enables setting of

oscillation frequency as shown in Figure12. Connection of R_RT

decides charge and discharge current for internal capacitor

and changes DC / DC oscillation frequency. Set R_RTby

reference to the theoretical formula below. Recommended

range is 14 kΩ to 51 kΩ. Pay attention that switching may stop

if recommended frequency setting range is exceeded, and

operation assuranceis not possible.

99 × ꢁ0^ꢅ

ꢇ_푂푆퐶[푘퐻푧] =

ꢀ_푅푇[푘훺]

Figure 12. R_RTvs DC / DC Oscillation Frequency F_OSC

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(4) Concerning spread spectrum setting(RAMP)

Connection of capacitor to RS terminal enables operation in Spread spectrum mode (SSCG mode). Comparator of

0.6 V (Typ) / 0.75 V (Typ) standard voltage is built in RS terminal, and DC / DC oscillation frequency is diffused by changing

RT terminal voltage to triangle waveform with the capacitor connected to RS terminal in SSCG mode. Theoretical attenuation

ΔD [dB] is calculable by the formula below.

F_{OSC_RAMP}: oscillation frequency when SSCG mode is

ON (Center)

F_OSC: oscillation frequency when SSCG mode is OFF

C_RS: RS terminal connection capacitor

R_RT: RT terminal connection resistance

ꢇ_푅푆[푘퐻푧]

ꢇ_{푂푆퐶_푅ꢋ푀푃}[푘퐻푧] × 0.222

[

]

훥ꢊ 푑퐵 = ꢁ0 × log ꢌ

ꢍ

However, setting value of DC / DC oscillation frequency differs depending on ON / OFF of SSCG mode. In order to operate

when SSCG mode is ON in the same frequency zone as when SSCG mode is OFF, select from Figure 12 RT resistance for

1.18 times as high DC / DC oscillation frequency as the DC / DC oscillation frequency. When SSCG mode is not used,

short-circuit RS terminal and VREG50 terminal.

Further, F_RScan be calculated by the formula below. Setting should satisfy the formula of 0.3 kHz ≤ F_RS≤ 10 kHz.

9

ꢇ_푅푆[푘퐻푧] =

[

]

8 × ꢀ_푅푇[푘훺] × ꢃ_푅푆휇ꢇ

(Example) When using at DC / DC oscillation frequency (F_{OSC_RAMP}) of 300 kHz with SSCG mode is ON, select RRT ≈ 28 kΩ

from Figure 12 to make DC / DC oscillation frequency (F_OSC) to be 354 kHz. When operating under this condition with

connection of CRS = 0.047µF and with SSCG mode ON, effect of ΔD = -18.9 dB can be predicted.

VREG50

CURRNET

MIRROR

ON/

OFF

RS

＋

OFF/

ON

C_RS

－

V_RT

15/16×V_RT

3/4×V_RT

＋

CURRENT

CONTROL

－

RT

R_RT

Figure 13. Equivalent Circuit Diagram of RS and RT terminals

F_OSC

±11.1%

⊿D[dBµV]

F_{OSC_RAMP}

F_OSC

(F_OSC=F_{OSC_RAMP}× 1.18)

Frequency Band

Figure 14. Noise Level Comparison with SSCG Mode ON / OFF

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SSCG:OFF(RS terminal connect to VREG50)

SSCG=OFF (VREG50 short-circuits with RS terminal)

SSCG:ON(RS terminal connect to Capacitance)

SSCG ON (A capacitor is connected to RS terminal)

0.8V(=V_RT

)

RS

0.75V(=15/16V_RT

)

V_RT

0.6V(=3/4V_RT

)

As for the period of I_RS, it is setable in C_RS

.

V_RT/2R_RT

I_RS

15/32×VRT/R_RT

3/8×V_RT/R_RT

I_RS

Switching output

SWDRV

It is output in same switching frequency（F_OSC

）

Switching frequency changes by

the change of F_OSC±11.1%.

Figure 15. Timing Chart when SSCG Mode is ON / OFF

Because switching frequency changes in High

section of the PWM like Figure 16 when spectrum

spreading is controlled in a PWM dimming, an

output voltage ripple changes in A and B. In addition,

the LED current is also affected by the ripple as it

may seem that LED flickers when this occurs

periodically, please thoroughly verify with the actual

equipment. As countermeasures, make the

frequency of the RS pin fast to reduce a ripple in

High section of the PWM.

PWM

RS

Vertical Scale)

Swti ching Frequ ency

FO SC3

FO SC2

FO SC4

FO SC1

330 kHz

Th e fre quen cy depe nds on

the attach in g exte rnally

(PWM doe s not d epend)

A

B

ILED

Even if On width of the PWMis the same as A in B, the voltage states o f the RS pin are different. Th eref ore, in th e spectrum

spr eading, the swit ching freque ncy is different f rom a timing of A in B.

A ripple of the outp ut voltag e chan ges, and LED curr ent may be t here by differ ent f rom Ain B.

Figure 16. Spectrum Spread Action in the PWM Dimming

(5) Soft start function(SS)

Soft start function is built-in so that incoming current can be prevented by insertion of external capacitor. The charge current

of the soft start is 5 μA (Typ) and will be as Figure 17 independent to PWM. The inrush current can be suppressed by

increasing soft start capacity, but boot-time becomes longer. On the other hand, as for the boot-time, it becomes faster by

lowering soft start capacity, attention is necessary because an inrush current becomes bigger, and may cause acoustic noise

of the coil during the startup. The soft start capacity is recommended to be 0.01 μF to 1 μF to suspend the overshoot of the

LED current during start up.

EN

The RS terminal is pulled up by VREG50 until SS terminal

arrives at 70%of VREG50 as soon as EN terminal is

inputted High voltage . After that, RS terminal starts to be

controlled.

(See the timing chart of SS terminal and RS terminal in the

P.28 Figure.44)

CR

Therefore, Spread spectrum don’t operate as soon as

EN terminal is inputted High voltage, even if connect a

capacitor to RS terminal

PWMOUT

SS

Figure 17. SS Operation Timing Chart

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(6) Concerning start up time(ERRAMP)

Startup time difference between PWM = 100 % (DRL = High) and PWM dimming control is described in this paragraph

EN

PWMOUT

0.7V

SS

COMP

V_OUT

I_LED

COMP terminal is charged when PWM=High

V_OUT

I_LED

Figure 18 (b). PWM Dimming start up

Figure 18 (a). PWM = 100% start up

During PWM control, SS terminal is charged synchronized

with EN while COMP terminal is charged synchronized with

PWM. Startup time is basically same with previous

description but as charge of COMP terminal is synchronized

with PWM, COMP voltage rise to the voltage which can

output required switching duty will be slower resulting In

longer start up time compared with PWM = 100 % operation.

Especially by reducing PWM dimming rate, start up time will

be longer.

SS terminal and COMP terminal is charged, When EN is

inputted. Until SS terminal reaches 0.7 V, COMP terminal is

fixed at 0.7 V. When SS terminal exceeds 0.7V, COMP

terminal starts to rise up to voltage which can output required

switching duty determined by input/output voltage difference.

Figure 19 describes actual measurement result of startup time.

Measurement Condition: V_CC= 12 V, F_PWM= 200 Hz, V_OUT= 25 V (LED 7series), Ta = 27deg, other condition as described in

P.38.

(Startup time will be from UVLO release to V_OUTreaching 90 %.)

Larger the C_PCconstant is, and smaller D_PWMis, start

up time will be longer. Startup time shall be

sufficiently evaluated in actual application.

Figure 19. Startup time measurement data

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4. Self-assessment function

Table 1. Concerning detection condition and operation after detection of each protection function (when VCC = 13 V)

Detection condition

Protection

function

Operation after detection

Error flag output ^{(Note 1)}

[Detection]

[Release]

At time of detection:

FAIL High→Low

At time of recovery:

FAIL Low→High

Shut down of all blocks

(Other than VREG50 / VREG25)

UVLO

V_CC< 3.9 V

V_CC> 4.25 V

Shut down of all blocks

(VREG50 / VREG25 are included)

-

TSD

OCP

Tj > 175 C

Tj < 150 C

Switching output is Off

V_CS≥ 300 mV

V_CS< 300 mV

V_IMP- V_IMN< 0.3 V

(Timer time

At time of detection:

FAIL High→Low

At time of recovery:

FAIL Low→High

Shut down of all blocks

SCP

V_IMP-V_IMN≥ 0.3 V

depends on

(Other than VREG50 / VREG25)

TDISC setting)

At time of detection:

FAIL High→Low

At time of recovery:

FAIL Low→High

LED open

detection

Shut down of all blocks

V_ODT> 1.5 V

V_ODT< 1.4 V

(Other than VREG50 / VREG25)

(Note1) FAIL output shown above is FAIL terminal voltage in the case of pull-up resistance such ad external power.

FAIL

TSD

UVLO

OPEN

SCP

TIMER

(TDISC)

Figure 20. Protection Flag Output Part Block Diagram

(1)Low voltage malfunction protection function (UVLO)

The UVLO shuts down all the circuits except VREG50, VREG25 when V_CC< 3.9V (Typ) And UVLO is released by Vcc > 4.25 V

(Typ).

(2) Temperature protection function (TSD)

TSD shuts circuits other than VREG at 175 C (Typ) and recovers them at 150 C (Typ).

(3) Over current protection function (OCP)

Over current is detected by the detection resistance with which current flowing in power FET is connected to source side. Over

current protection function operates when CS terminal voltage is no less than 300 mV (Typ).The over current protection function

controls DC / DC switching outputs.

(4) Output ground detection function (SCP)

When, in an application circuit such as Figure 45, LED Anode- GND short-circuits, the potential difference of IMP terminal and the

IMN terminal is more than 0.3 V (Typ), and a ground detection function works, and the output is off. When ground protection is

activated, charge (11 μA (Typ)) is started to a capacitor connected to TDISC terminal (recommend range: 0.01μF to 0.47μF).

After TDISC terminal voltage arrived at 1.0V (Typ), the TDISC terminal discharges and Low → High outputs SWDRV / PWMOUT

again. A ground detection function works again afterwards when the potential difference of IMP terminal and the IMN terminal

becomes than 0.3 V (Typ). In addition, it works normally when TDISC terminal voltage becomes less than 0.3V (Typ), and the

potential differences of IMP terminal and the IMN terminal become less than 0.3 V (Typ). As for the details, please refer to Figure

21. (Note that GND short-circuit of the IMP terminal cannot be detected.)

(5) LED open detection function

When ODT terminal voltage is above 1.5 V (Typ), LED open detection operates to reset SWDRV / PWMOUT = Low, and

discharges SS again, outputs Fail High → Low, and the output voltage decreases by ODT resistance. When ODT terminal

voltage is less than 1.4 V (Typ), begins to recharge SS, re-starts DC / DC operation and outputs FAIL Low→High.

Timing chart at the time of protection circuit operation (DRL = High)

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Output ground short protection function

①

VCC

V_OUT

4.25V

VCC

V_OUT

GND short

open

④

⑤

IMP

⑥

SWDRV

0.3V

②

0.2V

IMN

IMP-IMN

TDISC

CS

⑧

⑨

TDISC

⑦

1.0V

0.3V

V_OUT

GND short

⑨

PWMOUT

TDISC

③

⑥

SWDRV

PWMOUT

FAIL

C_TDISC

Figure 21. Output Ground short protection operation timing chart

When GND short circuit occurs in such conformation as shown

in Figure 1, large current continues to flow from VCC.

①

②

③

④

⑤

⑥

UVLO is cancelled when VCC > 4.25 V (Typ).

IMP-IMN terminal voltage rises to become 200 mV.

Switching Duty gradually expands and is stabilized at IMP-IMN of 200 mV.

Output voltage is stabilized.

LED Anode-GND short-circuits.

It becomes IMP-IMN ≥ 0.3 V (Typ) and performs output Short circuit detection (SCP) and outputs SWDRV / PWMOUT =

Low. Discharges an SS terminal and the FAIL terminal changes into High → Low.

When SCP is detected, capacitor connected to TDISC will be charged (11 µA (Typ)) until V_TDISCbecomes 1.0 V (Typ).

Once SCP detection is released at V_TDISC≥ 1.0 V (Typ), capacitor connected to TDISC starts to discharge, and SS

charging, SWDRV / PWMOUT operate normally.

⑦

⑧

⑨

If SCP condition V_TDISC≥ 0.3 V (Typ) is fulfilled restarts from condition “6” operates normally if SCP condition is not

fulfilled.

Operation described above is performed in the LED anode ground

short fault. However, even if SCP is detected by the potential

difference of IMP pin and the IMN pin, there is delay time of internal

circuit after detection and require time before PchMOS is off.

Therefore allowable current of PchMOS may be exceeded

transiently.(It may be exceeded in “8” of the timing mentioned above.)

Therefore, like Figure 22, PMOS can be turned off on an expressway

by adding PNP Tr externally.

When Output shorts to ground while supply voltage dropping, Gate

voltage may not be turned off. If sufficient Gate voltage cannot be

secured SCP may not be detected.

Figure 22. LED Anode Ground Fault Protection

Attaching Externally Circuitry

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LED open protection function (DRL = High)

VCC

Connector comes off

（LED open）

③

Connector return

⑦

V_OUT

①

VCC

IMP-IMN

ODT

4.25V

SWDRV

C_OUT

②

0.2V

R_SET

Open

CS

④

Discharge by ODT resistance

1.5V

1.4V

IMP

⑤

⑥

⑧

V_REF

IMN

I_LED

SWDRV

PWMOUT

V_OUT

PWMOUT

ODT

Figure 23. Output Ground Short Protection Operation Timing Chart

①

②

③

④

⑤

UVLO is released when VCC > 4.25 V (Typ).

IMP-IMN terminal voltage rises to become 200 mV.

Connector of LED opens.

Output voltage over boost due to IMP-IMN ≈ 0 V. (ODT which is resistor divided voltage of output voltage will steeply rise.)

When ODT ≥ 1.5 V, LED open is detected and SWDRV / PWMOUT becomes Low. Also, SS pin will be discharged and Fail

pin becomes High → Low.

⑥

The LED open detection is released at ODT ≤ 1.4 V, and the FAIL terminal becomes Low → High.

Then DC / DC restarts the operation, however due to LED open condition voltage will be over boosted again.

LED is connected again.

⑦

⑧

When ODT ≤ 1.4 V, will be re-started and resumes to normal operation.

(During “8” condition if PWMOUT = High is applied while capacitors are still charged above nominal Vout, it could detect SCP

detection due to IMP-IMN ≥ 0.3 V. After T_TDISCresumes to normal operation.)

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VCC

5. Output electric charge electric discharge circuit (VOUTDISC)

When supply voltage of LSI is turned off in such configuration as shown in Figure 24,

output capacitor may not be fully discharged and may remain charged in some

cases. When power is supplied again while output capacitor is charged,transient

current flows through the route of output capacitor→R_SET→LED→PWM dimming

FET→GND which cause LED flashing. Later, when switching duty is output, LED is

lit. In order to suppress such a flash phenomenon, this LSI incorporates output

charge discharge circuit.

In order for output discharge circuit to operate, discharge of output capacitor starts

when either one of the conditions of UVLO is detected (VCC ≤ 3.9 V) or V_EN≤ 1.35 V

are satisfied. (Output discharge circuit is also operated at LED open detection.)

V_OUT

SWDRV

CS

C_OUT

R_SET

I_DISC

IMP

IMN

V_REF1

I_LED

Turn off PWM after EN turned off power supply OFF sequence when PWM input is

controlled with an external signal.

PWMOUT

TDISC

V_OUT

Figure 24. Application Example

There is no output

discharge circuit

There is an output

discharge circuit

T_OFF

V_CC

Output discharge

circuit

ON

OFF

PWMOUT

output

PWMOUT

output

Output voltage

V_OUT

Output voltage

V_OUT

LED current

I_LED

LED current

I_LED

B

C

E

F

A

D

A. Because V_CCis off, and the PWMOUT terminal is off,

the LED current does not flow. Because PWMOUT

terminal is OFF, output capacitor C_OUTis discharged by

resistance connected to ODT terminal, and output

voltage V_OUTgradually decreases.

D. Because V_CCis off, and the PWMOUT terminal is off,

the LED current does not flow. Because PWMOUT

terminal is OFF, output capacitor COUT is discharged by

resistance connected to ODT terminal. However, the

output electric charge electric discharge circuit in the IMP

terminal works, and output voltage V_OUTgreatly decreases.

B. When V_CCis turned on again, getting started of output E. When V_CCis turned on again, getting started of output

voltage V_OUTis late by a soft start function. On the other

hand, the PWMOUT terminal is turned on in sync with a

reintroduction of V_CC. Therefore LED current flows from

an output capacitor transiently, and LED shines for an

instant, and LED darkens when the electric charge of the

output capacitor is discharged besides.

voltage V_OUTis late by a soft start function. On the other

hand, the PWMOUT terminla is turned on in sync with a

reintroduction of V_CC, but the LED does not shine because

V_Fcannot open.

C. Output voltage stands up, and LED turns on again.

F. Output voltage stands up, and LED turns on.

Figure 25. Output Discharge Circuit Operation Explanation at the time of the VCC Drop

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Concerning output discharge circuit operation at the time of UVLO detection

①3.95V

V_CC

①

②

UVLO is detected when VCC < 3.95 V.

When UVLO is detected, discharge circuit is turned

on to discharge charge accumulated in output

UVLO

signal

capacitor, and output voltage falls by I_DISC

.

Output voltage

V_OUT

③

I_DISCfalls accompanying fall of output voltage.

(Refer to electric properties of output voltage V_OUT

and discharge current I_DISC.)

1A

②

Discharge current

I_DISC

③

10mA

Discharge circuit

operation limit

Normal

operation

Discharge circuit operation

Figure 26. Explanation of Output Discharge Circuit Operation at UVLO Detection

Concerning output discharge circuit operation by EN control

①1.35V

EN

①

②

When EN ≤ 1.35 V, EN is turned off.

Output is discharged during output discharge time (T_TDISC

set by capacitor connected to TDISC.

T_TDISC

)

VREG50

×0.7

TDISC

②

푉ꢀꢎ퐺50 × 0.7 × ꢃ_{푇퐷ꢄ푆퐶}

ꢂ_TDISC

=

Output voltage

出力電圧V_OUT

V_OUT

ꢁꢁ휇퐴

1A

③

When discharge time T_TDISCelapsed, output discharge

circuit stops operation.

Discharge current

10mA

③

放電電流I_DISC

I_DISC

放電回路

Discharge circuit

Normal

Operation

Discha放rg電e 回cir路cu動it o作peration

正常動作

動作限界

Operation limit

Figure 27. Explanation of Output Discharge Circuit Operation when EN is off

The recommended capacitance value for this function is 0.01 μF to 0.47 μF, Please do not to connect TDISC to GND.

Caution that even if the values are within recommended range, when output voltage is higher and C_TISCis higher heat

dissipation by discharge is to be considered. Sufficient verification by actual application is required.

Flash phenomena is affected by Vf characteristic of LED and time to re-enter power supply. This is also to be sufficiently

verified with actual application.

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6. About EN terminal setting (EN CTL)

ON / OFF of the LSI can be controlled by applying resistor devided voltage from power supply to EN terminal. Setting of the

EN terminal voltage to control ON / OFF of the LSI is as follows.

(ꢀ_퐸ꢏ1+ ꢀ_퐸ꢏꢅ

ꢀ_퐸ꢏꢅ

)

VCC

푉

퐶퐶푂ꢏ

=

× ꢁ.45푉(ꢂ푦푝)

R_EN1

(ꢀ_퐸ꢏ1+ ꢀ_퐸ꢏꢅ

ꢀ_퐸ꢏꢅ

)

푉

퐶퐶푂퐹퐹

=

× ꢁ.35푉(ꢂ푦푝)

EN

＋

－

Ex)

R_EN2

The VCC terminal voltage to stop / start operation is as

follows with REN1 = 150 kΩ, REN2 = 51 kΩ condition

The operation start voltage

1.45V / 1.35V

1.3V/1.5V

(

)

ꢁ50푘훺 + 5ꢁ푘훺

5ꢁ푘훺

( )

× ꢁ.45푉 ꢂ푦푝 = 5.7ꢁ푉

푉

퐶퐶푂ꢏ

=

The operation stop voltage

Figure 28. About EN terminal setting

(

)

ꢁ50푘훺 + 5ꢁ푘훺

5ꢁ푘훺

( )

× ꢁ.35푉 ꢂ푦푝 = 5.32푉

푉

퐶퐶푂퐹퐹

=

For PWM dimming, do not control PWM with the EN terminal as it may result in unstable operation.

PWM dimming, is to be controlled with CR terminal. (Please refer to P.4 to 6 for the details.)

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Absolute Maximum Ratings (Ta = 25 °C)

Parameter

Symbol

V_CC

Rating

-0.3 to 70

-0.3 to VCC+0.3

-0.3 to 70

3

Unit

V

Power Voltage

EN, DRL Terminal Voltage

IMP, IMN Terminal Voltage

The Voltage between IMP and IMN

V_EN, V_DRL

V_IMP, V_IMN

V_IMP- V_IMN

V

VREG50, CS, RS, RT, VREG25,

DISC, ODT, PWMOUT, DCD, SS

V_VREG50, V_CS, V_RS, V_RT, V_VREG25

V_CR, V_DISC, V_ODT, V_PWMOUT, V_DCD

,

-0.3 to 7 < VCC

V

COMP, SWDRV, FAIL , TDISC terminal voltage V_SS, V_COMP, V_SWDRV, V_FAIL,V_TDISC

-40 to 125

-55 to 150

150

°C

Operation Temperature Range

Storage Temperature Range

Junction Temperature

Topr

Tstg

Tjmax

Caution: Deterioration or break may occur when absolute maximum ratings of applied voltage, operation temperature range, etc. are exceeded. Also, breaking

situation such as short circuit mode or open mode cannot be assumed. If special mode exceeding absolute maximum rating is assumed, please consider

physical safety measures such as fuse.

Thermal Resistance^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 3)}

2s2p^{(Note 4)}

HTSSOP-B24

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 2)}

θ_JA

143.8

7

26.4

2

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A (Still-Air)

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using a PCB board based on JESD51-3.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3mm x 76.2mm x 1.57mmt

Top

Copper Pattern

Thickness

Footprints and Traces

70μm

(Note 4) Using a PCB board based on JESD51-5, 7.

Thermal Via^{(NOTE 5)}

Layer Number of

Material

Board Size

114.3mm x 76.2mm x 1.6mmt

2 Internal Layers

Measurement Board

Pitch

Diameter

4 Layers

FR-4

1.20mm

Φ0.30mm

Top

Bottom

Copper Pattern

Thickness

Copper Pattern

Thickness

Copper Pattern

Thickness

70μm

Footprints and Traces

70μm

74.2mm x 74.2mm

35μm

74.2mm x 74.2mm

(Note 5) This thermal via connects with the copper pattern of all layers.

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Recommended Operating Ratings (Ta = 25 °C)

Parameter

Power Voltage ^{(Note 1)}

Symbol

Min

4.5

6.0

200

100

2

Typ

Max

65

Unit

V

V_CC

V_IMP

12

40

-

Output Voltage^{(Note 2)}

65

V

DC / DC Switching Frequency

(With Spread Spectrum Control OFF)

F_OSC1

F_OSC2

F_PWM

F_DUTY

F_RS

700

600

2000

45

kHz

Hz

%

DC / DC Switching Frequency

(With Spread Spectrum Control ON)

-

CRTIMER Frequency

-

CRTIMER Output Duty

-

Spectrum Spread Frequency

0.3

-

10

kHz

(Note 1) Apply voltage of no less than 5 V once at the time of stat-up. The value is voltage range after once setting at no less than 5 V.

(Note 2) When become the condition mentioned above except for startup at Boost application, it’s possible that large current flow in LED.

Recommended External Constant Range

Min

0.01

10

Max

1.0

Unit

μF

kΩ

μF

kΩ

Parameter

Symbol

C_CR

Capacitance for CRTIMER Frequency/Duty

Setting ^{(Note 3)}

Resistance for CRTIMER Frequency/Duty

Setting ^{(Note 3)}

R_DISC2

R_RT

33

Resistance for DC/DC Frequency

14

51

Capacitance for Soft-Start Setting ^{(Note 4)}

Capacitance for TDISC Setting ^{(Note 5)}

Resistance of OVP Setting of VOUT Side ^{(Note 3)}

C_SS

0.01

600

1.0

C_TDISC

0.47

R_OVP1

1000

(Note 3) Since the above values are reference values, when using constants outside the range, please thoroughly check the PWM dimming characteristics.

(Note 4) Since the above values are reference values, when using constants outside the range, please thoroughly check the characteristics at startup

(rush current etc.).

(Note 5) Since the above values are reference values, when using a capacitor outside the range, the hiccup time of SCP operation changes, so please fully check

the heat generation of the external FET during SCP operation.

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Electrical Characteristics (Unless otherwise specified V_CC= 13 V, V_IMP= 40 V, Ta = -40 °C to 125 °C)

Limit

Parameter

Symbol

Unit

Condition

Min

-

Typ

3

Max

6

C_VREG= 2.2 μF,

V_CS= V_ODT= 0 V

V_EN= V_DRL= V_CR= GND

V_RS= V_VREG50

Circuit Current

[VREG]

I_CC

mA

V_DCD= V_RT= V_VREG25

C_VREG50= 2.2 μF

Load current = 0mA to 20

mA

VREG50 Standard Voltage

VREG25 Standard Voltage

V_VREG50

4.5

5.0

5.5

V

No switching

V_VREG25

2.425

-

2.50

50

2.575

100

V

I_VREG25= 0μA

VREG25

Load Regulation Voltage

ΔV_VREG25

mV

I_VREG25= 0μA to 250 μA

[SWDRV]

SWDRV Upper Side ON Resistance

SWDRV Lower Side ON Resistance

Overcurrent Protection Voltage

[LED Current Setting Block]

R_SWP

R_SWN

V_OCP

-

4

3

8

6

Ω

I_ON= -10 mA

I_ON= 10 mA

V_CS: Sweep up

250

300

350

mV

Voltage between V_IMP- V_IMN

terminals.

LED Current Setting Standard Voltage

V_REF1

194

200

206

mV

LED Ground Short Detection Voltage

LED Open Detection Voltage

V_SCPON

V_OPEN

V_HYSOPEN

I_TDISC

V_DTDISC

V_RTDISC

0.24

1.42

-

0.3

1.5

0.1

11

0.36

1.575

-

V

V_SCP≥ V_IMP- V_IMN

V_ODT: Sweep up

V_ODT: Sweep down

V_TDISC= 0V

LED Open Hysteresis Voltage

TDISC Charge Current

V

4

18

μA

V

TDISC Short Timer Detection Voltage

TDISC Short Timer Release Voltage

0.9

0.2

1.0

0.3

1.1

0.4

V_TDISC: Sweep up

V_TDISC: Sweep down

V

EN OFF TDISC Discharge Stop

Voltage

V_VREG50V_VREG50V_VREG50

V_TDISC

V

× 0.55

× 0.7

× 0.85

Vout Discharge Time

Output Charge Discharge Current

[CR TIMER]

T_TDISC

I_DISC

20

35

55

ms

C_TDISC= 0.1 μF

3

10

-

mA

V_IMP= 12 V

V_VREG50V_VREG50V_VREG50

× 0.18 × 0.20 × 0.22

V_VREG50V_VREG50V_VREG50

CR Threshold Voltage 1

V_CRTH1

V

CR Threshold Voltage 2

V_CRTH2

T_PWM

V

μs

Ω

× 0.36

× 0.40

× 0.44

PWM Minimum Pulse Width

50

-

PWMOUT Upper Side

ON Resistance

R_PWMOUTP

-

20

5

40

10

I_ON= -10 mA

I_ON= 10 mA

PWMOUT Lower Side

ON Resistance

R_PWMOUTN

Ω

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Electrical Characteristics (Unless otherwise specified V_CC= 13 V, V_IMP= 40 V, Ta = -40 °C to 125 °C)

Limit

Parameter

Symbol

Unit

Condition

Min

Typ

Max

[ERRAMP]

V_COMP= 1.2 V,

COMP Source Current

COMP Sink Current

V_DCD= VREG25

V_IMP- V_IMN= 0 mV

I_COMPSO

-90

30

-60

60

-30

90

μA

V_COMP= 1.2 V,

V_DCD= VREG25

V_IMP- V_IMN= 400 mV

I_COMPSI

[Soft start]

Soft Start Charge Current

[Oscillator]

I_SS

3

5

7

μA

V_SS= 0 V

DC / DC Switching Frequency

Max Duty Output

R_RT= 33 kΩ

F_OSC

D_MAX

270

-

300

95

330

-

kHz

%

[RAMP]

RS Frequency

F_RS

V_RSH

V_RSL

-

0.75

0.60

-

kHz

V

R_RT= 33 kΩ, C_RS= 0.047 µF

V_RS: Sweep up

RS Terminal High Voltage

RS Terminal Low Voltage

[UVLO]

V

V_RS: Sweep down

UVLO Detection Voltage

UVLO Hysteresis Width

[EN/DRL]

V_UVLO

V_UHYS

V

V_CC: Sweep down

V_CC: Sweep up

3.6

3.9

4.2

mV

250

350

450

EN Terminal ON Threshold Voltage

EN Terminal Hysteresis Voltage Width

DRL Terminal Input Current

DRL Terminal ON Threshold Voltage

DRL Terminal OFF Threshold Voltage

V_ENON

V_HYSEN

I_DRL

1.35

1.45

100

13

-

1.55

-

V

mV

μA

V

V_EN: Sweep up

V_EN: Sweep down

V_DRL= 13 V

-

4

3

-

22

-

V_DRLON

V_DRLOFF

V_DRL: Sweep up

V_DRL: Sweep down

-

0.8

V

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Typical Performance Curves (Reference Data)

6

5

4

3

2

1

0

3.5

3.0

2.5

2.0

1.5

1.0

-40℃

25℃

0.5

125℃

0.0

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Supply Voltage: VCC [V]

Figure 29. Circuit Current vs Supply Voltage

Figure 30. Output Voltage vs Supply Voltage

(VREG50)

3.0

2.5

2.0

1.5

206

204

202

200

198

196

194

1.0

-40℃

0.5

0.0

25℃

125℃

-40 -15 10

35

60

85 110

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Supply Voltage: VCC [V]

Temperature: Ta [°C]

Figure 32. Reference voltage vs Temperature

Figure 31. Output Voltage vs Supply Voltage

(VREG25)

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Typical Performance Curves (Reference Data) - Continued

5.2

5.1

5.0

4.9

4.8

2.55

2.53

2.50

2.48

2.45

-40

-10

20

50

80

110

-40

-10

20

50

80

110

TEMPERATURE: Ta [°C]

Figure 34. Output Voltage vs Temperature

(VREG25)

Figure 33. Output Voltage vs Temperature

(VREG50)

325

320

315

310

305

300

295

290

285

280

275

600

500

400

300

200

100

0

-40 -15 10

35

60

85 110

0.0

0.5

1.0

1.5

2.0

Temperature: Ta [°C]

DCD Terminal Voltage [V]

Figure 36. ILED Current vs DCD Terminal Voltage

Figure 35. Frequency vs Temperature

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Typical Performance Curves (Reference Data) - Continued

R_RT= 30kΩ

C_RS= 0.047μF

Figure 38. Spectrum Spread (OFF)

(RS = VREG50 Short)

Figure 37. Spectrum Spread (ON)

Figure 40. PWM Control Start (DRL = Low)

Figure 39. PWM Control Operation Start (DRL = Low)

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Typical Performance Curves (Reference Data) - Continued

Figure 41. PWM Control Operation Start (DRL = High)

Figure 42. PWM Control Operation Stop (DRL = High)

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Timing Chart 1

4.25V

VCC

3.9V

VCC=4.25V

UVLO release

VCC=3.9V

UVLO detect

VREG50

It is ±11.1% for switching frequency

VRT×15/16

VRT×3/4

RS

EN

EN ON

1.45V

EN ON

EN OFF

1.35V

EN OFF

(VCC resistance division）

DRL=Low

DRL

2.0V

1.0V

CR

PWMOUT

0.7V

SS

VREG50×0.7

COMP

SWDRV

V_OUT

I_LED

Output discharge

ON

circuit

ON

(Output discharge at 10mA)

Figure 43. Start / Stop Sequence Timing chart (At time of PWM Control)

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Timing Chart 2

4.25V

VCC

VCC=4.25V

UVLO release

3.95V

VCC=3.95V

UVLO detect

VREG50

It is ±11.1% for switching frequency

VRT×15/16

RS

EN

VRT×3/4

EN OFF

EN ON

EN OFF

1.35V

1.45V

(VCC resistance division）

DRL ON

DRL OFF

DRL

At the time of the use of DRL, it is

necessary to start faster than EN.

(Note 1)

2.0V

1.0V

CR

PWMOUT

SS

VREG50×0.7

0.7V

COMP

SWDRV

V_OUT

I_LED

Output discharge

circuit

ON

(Output discharge at 10mA)

Figure 44. Start / Stop Sequence Timing chart (At time of PWM 100 % Control)

^{(Note 1)}Please apply the logic fix possible voltage to the Hi side before EN by all means when DRL terminal is used on the

High side (PWM 100 % state).

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Application Examples

External

power

VB

VOUT

VCC

VREG50

FAIL

ODT

EN

RT

VREG25

DCD

VOUT

DRL

RS

SWDRV

CS

COMP

BD18351EFV-M

VREG50

SS

IMP

IMN

DISC

CR

PWMOUT

TDISC

GND

DGND

Figure 45. Boost Application (with PchMOS)

VCC

External

power

VB

VOUT

VCC

VREG50

FAIL

ODT

EN

RT

VREG25

VREG50

DCD

VOUT

DRL

RS

SWDRV

CS

COMP

BD18351EFV-M

SS

IMP

IMN

DISC

CR

PWMOUT

VCC

TDISC

GND

DGND

Figure 46. The application returning LED cathode to the power supply

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Application Parts Selection Method (Boost mode Application)

Select application parts by the following procedure.

1. Set EN terminal operation voltage.

2. Set PWM dimming rate / frequency.

3. Set switching frequency.

4. Derive input peak current I_{L_MAX}from use condition.

Feedback

of L value

5. Set R_CSto make overcurrent protection current value as I_OCP> I_{L_MAX}

6. Set L constant value as (V_OUT- V_CC) / L × R_CS× R_RT< 13 × V_RT.

7. Set LED open protection voltage

.

8. Select coil, SBD, MOSFET to satisfy rated current and rated voltage.

9. Set output capacitor to satisfy output ripple voltage condition.

10. Set output discharge time

11. Select input capacitor.

12. Set phase compensation circuit.

13. Set soft start time, start up time.

14. Confirm operation of actual equipment

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1. Setting of EN terminal operation voltage

This device can be turned ON / OFF by inputting resistor divided voltage to EN terminal.

EN terminal voltage to controls ON / OFF can be set as shown below.

VCC

(ꢀ_퐸ꢏ1+ ꢀ_퐸ꢏꢅ

ꢀ_퐸ꢏꢅ

)

푉

퐶퐶푂ꢏ

=

× ꢁ.45푉(ꢂ푦푝)

R_EN1

EN

＋

－

(ꢀ_퐸ꢏ1+ ꢀ_퐸ꢏꢅ

ꢀ_퐸ꢏꢅ

)

푉

퐶퐶푂퐹퐹

=

× ꢁ.35푉(ꢂ푦푝)

R_EN2

Figure 47. Concerning EN terminal Setting Method

2. Setting of PWM dimming rate / frequency

PWM dimming frequency (F_PWM) and PWM dimming ON Duty (D_PWM) can be set with resistance and capacitor by means of

CR timer function which is built in this device. PWM dimming is 100 % dimming when DRL terminal voltage ≥ 3.0 V and is

controlled by dimming rate set with external C and R in the other range. Also, In addition, the recommended operating

frequency is 100 Hz to 2 kHz. The recommended external components values are; DISC2 to be between 10kΩ to 33 kΩ, C_CR

to be between 0.01 µF to 1.0 µF.

Trise

Tfaｌｌ

VREG50

2.0V

VREG50 x 0.4

CR falling

R_DISC1

CR

CR rising

DISC

CR

R_DISC2

1.0V

VREG50 x 0.2

＋

C_CR

DRV

PWMOUT

－

1.0V/2.0V

I_LED

LOGIC

DRL

LED OFF

LED ON

F_PWM= 1 / (T_rise+ T_fall) [Hz]

Trise=0.287×C_CR×（R_DISC1+R_DISC2

T_fall= 0.693 × CCR × RDISC2

T_rise= 0.287 × CCR × (RDISC1 + RDISC2)

D_PWM= T_fall/ (T_rise+ T_fall) [%]

）

Tfall=0.693×C_CR×R_DISC1

Figure 48. Concerning CR Timer Setting Method

3. Setting of switching frequency

A noise can be reduced using a spread spectrum function built-in the device. When spread spectrum is controlled, the

switching does not work in frequency F_OSC1decided by RT resistance shown in P. 9 Figure 12 and Frequency of F_OSC1× 0.84

as a center, it works at the frequency that modulated 11.1 %. The quantity of modulation frequency F_RSand noise decrement

can be calculated from formula listed in P.10. (Because frequency is modulated at the time of the spread spectrum, it

becomes maximum when frequency including the coil current is low. When each fixed number is calculated, please use it.

(Please refer to P.10, 11 for the details.)) When a spread spectrum function is not used, please short-circuit with VREG50

terminal with RS terminal. Because the frequency setting changes, please be careful.

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4. Derivation of input peak current IL_MAX (V_DCD> 1.21 V)

1. Calculation of output voltage (V_OUT

)

V_Fof LED for driving: V_F

LED current setting standard voltage: V_REF1

ON resistance of FET for PWM dimming:

R_{ON_PWMFET}

푉_푂푈푇= 푉 × 푁 + 푉

+ ꢀ_{푂ꢏ_푃푊푀퐹퐸푇}× 퐼_퐿퐸퐷

퐹

푅퐸퐹1

2. Calculation of output current I_LED

LED current: I_LED

Resistance for LED current setting: R_SET

Maximum coil current: I_{L_MAX}

Coil mean current: I_{L_AVE}

Ripple current: ΔI_L

푉

ꢀ_푆퐸푇

푅퐸퐹1

퐼_퐿퐸퐷

=

Power voltage: V_CC

Output voltage: V_OUT

3. Calculation of input peak current I_{L_MAX}

Efficiency: η

DC / DC oscillation frequency: F_OSC

ꢁ

퐼_{퐿_푀ꢋ푋}= 퐼_{퐿_ꢋꢐ퐸}+ 훥퐼_퐿

2

ꢁ

퐼_{퐿_푀ꢄꢏ}= 퐼_{퐿_ꢋꢐ퐸}− 훥퐼_퐿

2

푉_푂푈푇× 퐼_퐿퐸퐷

퐼_{퐿_ꢋꢐ퐸}

=

휂 × 푉

퐶퐶

푉

ꢑ

(푉_푂푈푇− 푉 )

ꢁ

ꢇ_푂푆퐶

퐶퐶

훥퐼_퐿=

×

푉_푂푈푇

●Since minimum input voltage is the worst case of V_CC,assign minimum input voltage for calculation.

●BD18351EFV-M adopts current mode DC / DC converter control. When I_{L_Min}is positive, it becomes to be in the

consecutive modes, and it will be in the discontinuity mode when I_{L_MIN}is negative. Phase characteristics are easy to

become insufficient in the discontinuous mode, and responsiveness turns worse, and a switching wave pattern becomes

irregular, and stability is easy to turn worse. Therefore it is sufficient validation of phase characteristics are recommended.

●η (efficiency) is about 90 %.

●In the case of V_DCD<1.21 V, please calculate I_LEDusing the formula which lists P.4 2(1) in "about a setting method of the

LED current".

5. Setting of overcurrent protection current value

Select R_CS(resistance for overcurrent detection) to realize below.

푉_{푂퐶푃_푀ꢄꢏ}

퐼_{푂퐶푃_푀ꢄꢏ}

=

> 퐼ꢑ_{_푀ꢋ푋}

ꢀ_퐶푆

Since values of coil L may vary about ±30 %, set with sufficient margin.

6. Selection of coil L constant value

For the purpose of stabilizing current mode DCDC converter operation, adjustment of L value within the following condition is

recommended.

푉_푂푈푇− 푉 × ꢀ_퐶푆× ꢀ_푅푇× ꢁ0^ꢒꢓ

)

(

퐶퐶

< ꢁ3 × 푉

푅푇

ꢑ × ꢁ0^ꢔ

Reduction of calculated value will increase stability, but may reduce responsiveness such as power voltage variation. Bigger

values which do not satisfy the above formula may cause sub-harmonic oscillation, destabilize switching duty and cause

blinking of LED.

Further, assign V_RT= 0.8 V when RS terminal short-circuits with VREG and spread spectrum is not used, and assign

V_RT= 0.675 V when capacitor is connected to RS terminal and spectrum is diffused.

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7. Setting of LED open protection voltage

LED open detection voltage needs higher voltage setting than overshoot of

output voltage at start up to avoid start up failure. Further, output voltage at

the time of LED open detection (V_{OUT_ODT}) is calculable as shown below by

V_OUT

setting R_ODT1and R_ODT2

.

R_ODT1

(ꢀ_푂퐷푇1+ ꢀ_푂퐷푇ꢅ

ꢀ_푂퐷푇ꢅ

)

푉_{푂푈푇_푂퐷푇}

=

× ꢁ.5푉(ꢂ푦푝)

ODT

＋

R_ODT2

ODT resistor will be the current discharge path for the output capacitor

when PWM = Low Recommended value for R_ODT1is 600 kΩ to 1000 kΩ as

Vout ripple may be large and cause LED flickering when PWM = Low with

inadequate ohmic value range.

－

Sufficient verification for LED flickering is required with actual application

as behavior differs by characteristic of output capacitor and LED.

1.5V/1.4V

(Vout drop can be prevented by inserting bigger output capacitor or ODT

resistance.)

Figure 49. ODT terminal Equivalent Circuit

8. Selection of power element, diode D1, MOSFET Q1 and Q2

VCC

L

D_i

V_OUT

SWDRV

Q₁

C_OUT

R_SET

CS

R_CS

IMP

V_REF1

IMN

PWMOUT

Q₂

Figure 50. Boost Application Circuit

Selection of MOSFET Q1

Select MOSFET (Q1) to have V_DSrating higher than the Max output voltage which LED open function is activated.

(푅

ꢙ푅

)

ꢕꢖꢗꢘ

ꢕꢖꢗꢚ

( )

× ꢁ.575푉 ꢛꢜ푥

푉_{푂푈푇_푂퐷푇_푀ꢋ푋}

>

V_DS: Voltage between drain and source

푅

ꢕꢖꢗꢚ

In addition, the RMS current limit flowing between drain - sources of Q1 can be calculated as follows.

D_SW: Switching Duty

√ꢈ

ꢉ

퐼_{퐷푆_푅푀푆}= ꢁ.3 × 퐼ꢑ_{_ꢋꢐ퐸}^2 × ꢊ_푆푊

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A loss of Q1 is calculated next. The loss of Q1 will be the Ploss2 which is switching loss and Ploss1 the On resistance of Q1.

Switching loss Ploss1 and Q1 On resistance loss Ploss2 can be calculated as follows.

^{ꢈ푇 ꢙ푇 ꢉ}× ꢇ_푂푆퐶× 푉_푂푈푇+ 푉_퐷푖× 퐼_{퐿_ꢋꢐ퐸}

ꢞ

ꢟ

(

)

ꢝ

푙표푠푠1

=

ꢅ

Tr / Tf: Drain source rise / fall time

Ron: Ron of Q1

ꢝ

푙표푠푠ꢅ

= 퐼_{퐿_ꢋꢐ퐸}^ꢅ× ꢀ_표푛× ꢊ_푆푊

Selection of rectifier diode Di

For power consumption reduction, please use a Schottky Barrier diode for rectification diode Di. The withstand voltage rating

of the diode shall be higher than the LED Open protection voltage. In addition, Schottky Barrier diode with low leakage

current shall be selected if PWM dimming is used. Because the leakage current increases with higher temperature

environment, the output capacitor can be discharged in PWM = Low which may result that LED current will be unstable.

The current limit of Di can be calculated in following formula.

(

)

퐼_퐷푖= 퐼_{퐿_ꢋꢐ퐸}× ꢁ − ꢊ_푆푊× ꢁ.5

Selection of MOSFET Q2

Consider margin and set the rated voltage rather higher than the actual usage condition for LED current and output voltage.

9. Selection of output capacitor C_OUT

Output capacity includes two purposes. The first is to reduce output ripple. The second is to supply current to LED when

MOSFET (Q1) is switched on. The output voltage ripple is influenced by both bulk capacity and ESR. (When a ceramic

capacitor is used, bulk capacity causes most of the ripple.) Bulk capacity and the ESR can be calculated in lower formula.

ꢊꢆ푤

ΔV_COUT: influence with the capacitor among output ripple

ΔV_ESR: Ripple which occurs in the ESR of the output capacitor

ꢃ_푂푈푇≥ 퐼_퐿퐸퐷

×

∆푉

× ꢇ_푂푆퐶

퐶푂푈푇

∆푉

퐼_{퐿_푀ꢋ푋}

퐸푆푅

ꢀ_퐸푆푅

<

The total output ripple permitted here can be expressed as product of LED current ripple and the equivalent resistance of the

LED. This equivalent resistance is defined as "ΔV / ΔI of the LED current", and it is necessary to calculate from I-V properties

in the data sheet of the selected LED. Assuming that number of the driven LED = 8 pcs (equivalent resistance 0.2 Ω / LED),

LED current = 1 A (IL_MAX = 4.5 A), switching Duty = 60 %, switching frequency = 300 kHz, it is supposed that LED current

ripple is 5%.Then the total output ripple can be calculated as follows.

(

)

푉_{푂푈푇_푟푖ꢠꢠ푙푒}= ꢁ퐴 × 5% × 0.2훺 × 8 = 80푚푉

If bulk capacity causes 95 % among total output ripple, the output capacitor is calculated as follows.

0.6

ꢁ

ꢃ_푂푈푇≥ ꢁ ×

×

= 26.4휇ꢇ

0.08 × 0.95 300푘퐻푧

(

)

푉_{푂푈푇_푟푖ꢠꢠ푙푒}

0.08 × 0.05

4.5

ꢀ_퐸푆푅

<

=

= 0.88푚훺

퐼ꢑ_{_푀ꢋ푋}

However the capacitance of output capacitor mentioned above is minimum capacitance. Therefore please select

components considering the tolerance of the capacitor and DC bias properties. Furthermore, because small external

component connected to output may lead to bigger ripple on output voltage, which may result in LED flickering, sufficient

verification of the actual application is required. Increase output capacitors if judged to be required from the verification. In

addition, an acoustic noise may be produced by the piezoelectric effect of the ceramic capacitor during PWM dimming.

Electrolytic capacitor used together with a ceramic capacitor may reduce this noise. But capacitance may largely decrease

with a change of the voltage with the ceramic capacitor and may not accord with the numerical value calculated from theory.

Thorough consideration is required.

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10. Setting of TDISC terminal

Output discharge time and Output short protection time can be set by connecting capacitor to TDISC terminal.

Recommended range of capacitor will be 0.01 μF to 0.47 μF, however if capacitor at TDISC (C_TDISC) is smaller, output

discharge time will be short which may result in LED flashing when restarting the supply voltage. On the other hand if C_TDISC

is large discharge time will be longer. If Vout is high and discharge time is longer, heat generation of LSI will be larger

therefore verification with actual application is required with caution.

11. Selection of input capacitor

In DC / DC converter, since peak current flows between input and output, a capacitor is also required in the input side.

Therefore, low ESR capacitors with capacitor of no less than 10 µF and ESR component of no more than 100 mΩ are

recommended as input capacitors. Selection of capacitors out of the range may cause malfunction of IC because excessive

ripple voltage will overlap input voltage.

12. Setting of phase compensation circuit

●Concerning stability condition of application

Stability condition for system with negative feedback is as shown below.

Phase-lag when gain is 1 (0 dB) is no more than 150 ° (namely, phase margin is no less than 30 °).

Further, since DC / DC converter application is sampled by switching frequency, GBW of the entire system is set to be

no more than 1 / 10 of switching frequency. To wrap up, target characteristics of application are as shown below.

●Phase-lag when gain is 1 (0 dB) is no more than 150 ° (namely, phase margin is no less than 30 °)

●GBW at the time (namely, frequency when gain is 0 dB) is no more than 1/10 of switching frequency. Therefore, in

order to raise responsiveness by limiting GBW, higher switching frequency is required.

The knack for securing stability by phase compensation is to insert phase-lead F_Z1near GBW. GBW is determined by C_OUT

and phase-lag fp1 due to output impedance RL (= V_OUT/ I_LED).

They are shown in the following formulae.

Phase-lead

V_OUT

IMP

ꢁ

ERRAMP

ꢇ_푍1

=

-

+

CURRENT

SENSE

COMP

2휋 × ꢃ_푃퐶× ꢀ_푃퐶

Phase-lag

C_PC

R_PC

IMN

VOUT

DISC

ꢁ

ꢇ_푃=

2휋 × ꢀ_퐿× ꢃ_푂푈푇

Figure 51. ERRAMP Equivalent Circuit

푉_푂푈푇

퐼_퐿퐸퐷

ꢀ_퐿=

As described above, please secure phase margin. For R_Lvalue at max load should be inserted. In addition, with boost

DC/DC, right half plane zero (RHP zero) is to be considered. This zero has a characteristic of zero as a gain and as the pole

with phase. Because it causes an oscillation when this zero effects on a control loop, it is necessary to bring GBW just before

RHP zero. RHP zero can be calculated with an equation below and shows good characteristic by setting GBW to be lower

than 1 / 10 of RHP zero.

푉

퐶퐶

푉_푂푈푇

ꢅ

ꢀ_퐿× (

)

ꢇ_푍ꢅ

=

2휋 × ꢑ

Particularly when supply voltage rises and gets close to output voltage, the switching output becomes irregular and ripple of

the output voltage increases. Ripple of the LED current may thereby get bigger.

Since this setting is obtained by simplified, not strict, calculation, adjustment by actual equipment may be required in some

cases.

Further, since these characteristics will vary depending upon substrate layout, load condition, etc., confirm satisfactorily with

actual equipment when planning mass production.

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13. Soft start time and confirmation of the boot-time

A soft start function is incorporated, and an inrush current can be prevented by inserting an external capacitor. Charge

current of the soft start is 5 μA (Typ) and charges it without depending on PWM. The inrush current can be suppressed by

increasing soft start capacity, but boot-time becomes longer. On the other hand, as for the boot-time, it becomes faster by

lowering soft start capacity, but an inrush current grows bigger and it leads to the sound rumble of the coil in the startup,

therefore attention is necessary. 0.01 μF to 1 μF is recommended to control overshoot of the LED current in the startup.

In addition, the boot-time varies according to PWM dimming control condition. Refer to details described in P11 and 12.

14. Confirmation of actual equipment operation

Select external components based on verification with actual equipment since characteristics will vary depending on various

factors such as load current, input voltage, output voltage, inductor value, load capacity, switching frequency and mounting

pattern.

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PCB Application Circuit diagram

VCC = 9 V to 16 V, LED drive stage number: 7 (V_OUT≈ 23 V), LED current: 500 mA,

DC / DC oscillation frequency: 280 kHz, SSCG mode ON

VCC VCC

CIN1

VREG50

CN1

VFAIL

FAIL

CVREG51 CVREG50

L1

RFL

VREG50

VOUT1

CIN2

RODT1

EN

REN1

REN2

EN

ODT

VREG25

CEN

RODT2

DI

RT

DCD

RDCD1

RDCD2

VOUT

RRT

VOUT

RVOUT

DCD

DRL

U1

RDCD3

COUT1 COUT2 COUT3 COUT4 COUT5

DGND DGND DGND DGND DGND

DRL

RS

RSET

SWDRV

CS

RSW

CRS

M1

BD18351EFV-M

COMP

RPC

CPC

SS

VREG50

RCS1

RCS2

CSS

CN2

RDISC1

RIMP

RIMN

IMP

IMN

DISC

CR

RDISC2

CCR

CR

PWMOUT

CTDISC

Figure 52. Boost application (PWM Dimming Application)

About the attention point at the time of the PCB layout

VCC

L

D_i

V_OUT

SWDRV

Q₁

7.

C_OUT

R_SET

CS

1

R_CS

IMP

IMN

V_REF1

PWMOUT

Q₂

Figure 53. Boost High Side PWM Dimming Application

1. Please locate the decoupling capacitor of C_IN2, C_VREG50, C_VREG51close to an LSI pin as much as possible

2. R_RTlocates it close to RT pin, and prevent there from being capacity

3. Because high current may flow in DGND, please lower impedance.

4. Prevent noise to be applied to EN, DRL, COMP, SS, RT, DCD, IMP, and IMN terminals.

5. As the CR, DISC, RS, SWDRV, PWMOUT terminals are switching, please be careful not to affect the neighboring patterns.

6. There is heat dissipation PAD on the back side of the package.

7. For noise reduction, DGND of R_CS1, R_CS2and DGND of C_OUTrecommend to have one common grounds. In addition, consider

the PCB layout so that the current path of M1 → R_CS1, R_CS2→ DGND and the current path of Di → C_OUT→ DGND are the

shortest and with the lowest impedance.

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List of PCB board attaching externally parts

Bom_No

Value

10μF

0.1μF

2.2μF

1000pF

100kΩ

39kΩ

1000pF

30kΩ

0.047μF

5.1kΩ

0.047μF

100kΩ

20kΩ

0.1μF

100kΩ

10µH

680kΩ

33kΩ

12kΩ

100kΩ

-

Parts No

GCM32EC71H106KA01

GCM188R11H104KA01

GCM21BR71C225KA49

GCM155R11H102KA01

MCR03

Product Maker

Murata

Rohm

CIN1

CIN2

CVREG50

CVREG51

REN1

REN2

CEN

MCR03

Rohm

GCM155R11H102KA01

MCR03

Murata

Rohm

RRT

CRS

GCM188R11H473KA01

MCR03

Murata

Rohm

RPC

CPC

GCM188R11H473KA01

MCR03

Murata

Rohm

RDISC1

RDISC2

CCR

MCR03

Rohm

GCM188R11H104KA01

MCR03

Murata

Rohm

CSS

CTDISC

RFL

L1

IHLP-3232DZ-11

MCR03

Vishay

Rohm

RODT1

RODT2

RDCD1

RDCD2

RDCD3

M1

MCR03

Rohm

MCR03

Rohm

MCR03

Rohm

NTCG104EF104F

RSD150N06FRA

MCR03

TDK

Rohm

RSW

22Ω

Rohm

RCS1

RCS2

Di

150mΩ

-

LTR18

Rohm

LTR18

Rohm

RB058L150

Rohm

RIMP

RIMN

COUT1

COUT2

COUT3

COUT4

COUT5

RVOUT

RSET

M2

0Ω

MCR03

Rohm

0Ω

MCR03

Rohm

0.1µF

10μF

0Ω

GCM188R11H104KA01

GCM32EC71H106KA01

LTR18

Murata

Rohm

680mΩ

-

LTR10

Rohm

RTR020N05

Rohm

IC

-

BD18351EFV-M

Rohm

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I/O Equivalent Circuits

1. COMP

2. SS

4. DCD

VREG50

ꢀ

VREG50

SS

CM

COMP

DCD

COMP

5. VREG25

6. RT

7. RS

VREG50

RS

VREG50

CM

VREG25

RT

8. CR, 9. DISC

10. FAIL

FAIL

11. TDISC

VREG50

CR

TDISC

DISC

×1

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BD18351EFV-M

I/O Equivalent Circuits - Continued

12. PWMOUT

13. IMN, 14. IMP

17. CS

VREG50

IMP

VREG50

IMP

IMN

PWMOUT

CS

ꢀ

18. SWDRV

19. ODT

20. VREG50

VCC

VREG50

ODT

VREG50

SWDRV

Internal

Circuit

22. DRL

23. EN

24. VCC

VCC

VREG50

EN

DRL

BG

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BD18351EFV-M

Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Thermal Consideration

Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in

deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when

the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating,

increase the board size and copper area to prevent exceeding the Pd rating.

6. Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.

The electrical characteristics are guaranteed under the conditions of each parameter.

7. Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush

current may flow instantaneously due to the internal powering sequence and delays, especially if the IC

has more than one power supply. Therefore, give special consideration to power coupling capacitance,

power wiring, width of ground wiring, and routing of connections.

8. Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

9. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

10. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

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Operational Notes – continued

11. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

12. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 54. Example of monolithic IC structure

13. Ceramic Capacitor

When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

14. Area of Safe Operation (ASO)

Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe

Operation (ASO).

15. Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction

temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below

the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

16. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

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Ordering Information

B D 1 8 3 5 1 E F V - M E 2

Part Number

Package

EFV: HTSSOP-B24

Packaging and forming specification

M : High reliability

E2 : Embossed tape and reel

(HTSSOP-B24)

Marking Diagrams

HTSSOP-B24 (TOP VIEW)

Part Number Marking

LOT Number

D 1 8 3 5 1 E F

1PIN MARK

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Physical Dimension, Tape and Reel Information

Package Name

HTSSOP-B24

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Revision history

Date

Revision

Changes

New Release

2016.3.4

001

P.11 Figure 16. Erratum modified

P.13 (4), P14 Output short detection function (SCP)

Previous rev. ”IMN terminal GND short-circuits”→ Revised ”When LED anode short to GND”

P.19 Thermal resistance

Previous74.2mm(square) → Revised 74.2mm x 74.2mm

P.20 Recommended operation condition

2016.5.12

002

CRTIMER output Duty Min Previous rev. ”5%”→ Revised ”2%”

P.27 Figure 43. Erratum modified

P.31 Figure 48. Erratum modified

P.39,40 Modified equivalent circuit

P.1 Previous rev. “Minimum PWM Dimming Pulse Width: 100 µs”

Revised “Minimum PWM Dimming Pulse Width: 50 µs”

P.4 Previous rev. “(PWM min pulse width=100 µs)”

Revised “(PWM min pulse width=50 µs)”

P.6 Previous rev. “Minimum pulse width is 100 µs”

Revised “Minimum pulse width is 50 µs”

P.8 V_{OUT_MAX}, V_{F_MAX}, The number of drivable LED series stages Formula revised.

P.20 Previous rev. “Operating Condition (External Constant Range)”

Revised “Recommended External Constant Range”

P.20 Add (Note3), (Note4), (Note5).

2018.11.7

003

P.21 Electrical Characteristics LED Open Detection Voltage Min

Previous rev. ”1.35” Revised ”1.42”.

P.21 Electrical Characteristics LED Open Detection Voltage Max

Previous rev. ”1.65” Revised ”1.575”.

P.21 Electrical Characteristics PWM Minimum Pulse Width Min

Previous rev. ”100” Revised “50”.

P.33 V_{OUT_ODT_MAX}Formula revised.

P.21 Output short detection function (SCP)

Previous rev. ”C_VREG50= 2.2 μF”→ Revised ” C_VREG50= 2.2 μF I_VREG50= 0mA to 20 mA ”

P.32 6. Selection of coil L constant value Formula revised.

2019.09.02

004

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BD18351EFV-M
厂家：	ROHM
描述：	BD18351EFV-M是内置1ch升压控制器的LED驱动器。本LSI通过对LED电流设定进行相对于输出电压的高边检测实现升压/降压，适合车头灯/DRL、车尾灯、转向灯的LED驱动。内置了CRTIMER，在需要进行DRL等的PWM调光的应用中，无需微控制器即可进行PWM调光，可实现组件的低成本化和小型化。驱动控制器微控制器驱动器
文件：	总48页 (文件大小：2759K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD18351EFV-M [ROHM]

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