BD3551HFN-TL [ROHM]
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| 型号： | BD3551HFN-TL |
| 厂家： | 
ROHM |
| 描述： | 暂无描述 外围驱动器 稳压器 驱动程序和接口 接口集成电路 光电二极管 PC |
| 文件： | 总17页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators for PC
BD3550HFN, BD3551HFN, BD3552HFN
(0.5～2.0A)
● Description
BD3550HFN,BD3551HFN,BD3552HFN ultra low-dropout linear chipset regulator operates from a very low input supply, and
offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power
transistor to minimize the input-to-output voltage differential to the ON resistance (RON=100mΩ <BD3552HFN>) level. By
lowering the dropout voltage in this way, the regulator realizes high current output (Iomax=2.0A <BD3552HFN>) with
reduced conversion loss, and thereby obviates the switching regulator and its power transistor, choke coil, and rectifier
diode. Thus, BD3550HFN,BD3551HFN,BD3552HFN is designed to enable significant package profile downsizing and cost
reduction. An external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the
NRCS (soft start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power
supply sequence is required.
● Features
1) Internal high-precision reference voltage circuit(0.65V±1%)
2) Built-in VCC undervoltage lockout circuit
3) NRCS (soft start) function reduces the magnitude of in-rush current
4) Internal Nch MOSFET driver offers low ON resistance (100mΩ <BD3552HFN typ>)
5) Built-in current limit circuit
6) Built-in thermal shutdown (TSD) circuit
7) Variable output (0.65～2.7V)
8) Small package HSON8 : 2.9×3×0.6(mm)
9) Tracking function
● Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
● Line-up
It is available to select power supply voltage and maximum output voltage.
Maximum Output Voltage
Package
HSON8
Vcc=5V
0.5A
1.0A
2.0A
BD3550HFN
BD3551HFN
BD3552HFN
Oct. 2008
●Absolute maximum ratings
◎BD3550HFN,BD3551HFN,BD3552HFN
Limit
BD3551HFN
+6.0 *1
Parameter
Input Voltage 1
Symbol
Unit
BD3550HFN
BD3552HFN
VCC
VIN
V
V
Input Voltage 2
+6.0 *1
Enable Input Voltage
Ven
-0.3～+6.0
0.63 *2
V
Power Dissipation 1
Pd1
W
W
W
℃
℃
℃
Power Dissipation 2
Pd2
1.35 *3
Power Dissipation 3
Pd3
1.75 *4
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Topr
Tstg
Tjmax
-10～+100
-55～+150
+150
*1 Should not exceed Pd.
*2 Reduced by 5.04mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 0.2% (percentage occupied by copper foil.
*3 Reduced by 10.8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 7.0% (percentage occupied by copper foil.
*4 Reduced by 14.0mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 65.0% (percentage occupied by copper foil.
2/16
◎BD3550HFN,BD3551HFN,BD3552HFN
●Operating Voltage(Ta=25℃)
Parameter
Input Voltage 1
Symbol
VCC
VIN
Min.
4.3
Max.
5.5
Unit
V
Input Voltage 2
0.95
VFB
0
VCC-1 *5
V
Output Voltage Setting Range
Enable Input Voltage
NRCS Capacity
Vo
2.7
V
Ven
5.5
V
CNRCS
0.001
1
μF
*5 VCC and VIN do not have to be implemented in the order listed.
★This product is not designed for use in radioactive environments.
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, Ven=3V, VIN=1.8V, R1=3.9KΩ, R2=3.3KΩ)
Limit
Parameter
Symbol
Unit
Condition
Min.
Typ.
0.5
Max.
1.0
10
Bias Current
ICC
IST
-
-
-
mA
uA
V
VCC Shutdown Mode Current
Output Voltage
0
Ven=0V
VOUT
1.200
-
Output Voltage Temperature
Coefficient
Tcvo
-
0.01
-
%/℃
Feedback Voltage 1
Feedback Voltage 2
VFB1
VFB2
0.643
0.637
0.650
0.650
0.657
0.663
V
V
Tj=-10 to 100℃
Io=0 to 1A
Load Regulation
Reg.L
-
0.5
10
mV
(BD3550HFN Io=0A to 0.5A)
Line Regulation 1
Line Regulation 2
Standby Discharge Current
[ENABLE]
Reg.l1
Reg.l2
Iden
-
-
0.1
0.1
-
0.5
0.5
-
%/V VCC=4.3V to 5.5V
%/V VIN=1.2V to 3.3V
1
mA
Ven=0V, Vo=1V
Enable Pin
Enhi
2
-
-
V
Input Voltage High
Enable Pin
Enlow
Ien
0
-
-
0.8
10
V
Input Voltage Low
Enable Input Bias Current
[FEEDBACK]
7
μA
Ven=3V
Feedback Pin Bias Current
[NRCS]
IFB
-100
0
100
nA
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
Inrcs
14
-
20
0
26
50
μA
Vnrcs=0.5V
Ven=0V
VSTB
mV
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
[AMP]
VccUVLO
Vcchys
3.5
3.8
4.1
V
Vcc:Sweep-up
100
160
220
mV
Vcc:Sweep-down
Gate Source Current
Gate Sink Current
IGSO
IGSI
Io
-
-
1.6
4.7
-
-
mA
mA
A
VFB=0, VGATE=2.5V
-
-
VFB=VCC, VGATE=2.5V
BD3550HFN
Maximum output
BD3551HFN
current
0.5
1.0
2.0
-
Io
-
-
A
BD3552HFN
Io
-
-
A
BD3550HFN
Minimum dropout
BD3551HFN
voltage
dVo
dvo
dVo
200
200
200
300
300
300
mV
mV
mV
Io=0.5A, VIN=1.2V, Ta=-10 to 100℃
Io=1.0A, VIN=1.2V, Ta=-10 to 100℃
Io=2.0A, VIN=1.2V, Ta=-10 to 100℃
-
BD3552HFN
-
3/16
●Reference Data(BD3550HFN)
Vo
Vo
Vo
50mV/div
50mV/div
50mV/div
40mV
22mV
26mV
Io
Io
Io
0.5A/div
0.5A/div
0.5A
0.5A/div
0.5A
0.5A
Io=0A→1A/μsec
t(10μsec/div)
Io=0A→1A/μsec
t(10μsec/div)
Io=0A→1A/μsec
t(10μsec/div)
Fig.1 Transient Response
(0→0.5A)
Fig.2 Transient Response
(0→0.5A)
Fig.3 Transient Response
(0→0.5A)
Co=100μF, Cfb=1000pF
Co=47μF, Cfb=1000pF
Co=22μF, Cfb=1000pF
Vo
Vo
Vo
50mV/div
50mV/div
50mV/div
33mV
23mV
14mV
Io
Io
Io
0.5A
0.5A
0.5A
0.5A/div
0.5A/div
0.5A/div
Io=1A→0A/μsec
t(100μsec/div)
Io=1A→0A/μsec
t(100μsec/div)
Io=1A→0A/μsec
t(100μsec/div)
Fig.4 Transient Response
(0.5→0A)
Fig.5 Transient Response
(0.5→0A)
Fig.6 Transient Response
(0.5→0A)
Co=100μF, Cfb=1000pF
Co=47μF, Cfb=1000pF
Co=22μF, Cfb=1000pF
●Reference Data(BD3551HFN)
Vo
Vo
Vo
50mV/div
50mV/div
50mV/div
46mV
35mV
55mV
Io
Io
Io
1.0A
1.0A
1.0A
1.0A/div
1.0A/div
1.0A/div
Io=0A→1A/μsec
t(10μsec/div)
Io=0A→1A/μsec
t(10μsec/div)
Io=0A→1A/μsec
t(10μsec/div)
Fig.8 Transient Response
(0→1.0A)
Fig.9 Transient Response
(0→1.0A)
Fig.7 Transient Response
(0→1.0A)
Co=47μF, Cfb=1000pF
Co=22μF, Cfb=1000pF
Co=100μF, Cfb=1000pF
Vo
Vo
Vo
56mV
46mV
50mV/div
50mV/div
50mV/div
36mV
Io
Io
Io
1.0A
1.0A
1.0A
1.0A/div
1.0A/div
1.0A/div
Io=1A→0A/μsec
t(100μsec/div)
Io=1A→0A/μsec
t(100μsec/div)
Io=1A→0A/μsec
t(100μsec/div)
Fig.10 Transient Response
(1.0→0A)
Fig.11 Transient Response
(1.0→0A)
Fig.12 Transient Response
(1.0→0A)
Co=100μF, Cfb=1000pF
Co=47μF, Cfb=1000pF
Co=22μF, Cfb=1000pF
4/16
●Reference Data(BD3552HFN)
Vo
50mV/div
26mV
Vo
Vo
50mV/div
50mV/div
89mV
117mV
Io
Io
Io
2.0A
2.0A
2.0A
2.0A/div
2.0A/div
2.0A/div
Io=0A→1A/μsec
t(10μsec/div)
Io=0A→1A/μsec
t(10μsec/div)
Io=0A→1A/μsec
t(10μsec/div)
Fig.15 Transient Response
(0→2.0A)
Fig.13 Transient Response
(0→2.0A)
Fig.14 Transient Response
(0→2.0A)
Co=22μF, Cfb=1000pF
Co=100μF, Cfb=1000pF
Co=47μF, Cfb=1000pF
Vo
Vo
Vo
117mV
83mV
54mV
50mV/div
50mV/div
50mV/div
Io
Io
Io
2.0A/div
2.0A/div
2.0A/div
2.0A
2.0A
2.0A
Io=1A→0A/μsec
t(100μsec/div)
Io=1A→0A/μsec
t(100μsec/div)
Io=1A→0A/μsec
t(100μsec/div)
Fig.16 Transient Response
(2.0→0A)
Fig.17 Transient Response
(2.0→0A)
Fig.18 Transient Response
(2.0→0A)
Co=100μF, Cfb=1000pF
Co=47μF, Cfb=1000pF
Co=22μF, Cfb=1000pF
●Reference Data(BD3551HFN)
VCC
Ven
Ven
2V/div
2V/div
Ven
VIN
Vo
VNRCS
2V/div
VNRCS
2V/div
Vo
Vo
1V/div
1V/div
t(2msec/div)
VCC→VIN→Ven
t(200μsec/div)
Fig.19 Waveform at output
start
Fig.20 Waveform at output OFF
Fig.21 Input sequence
VCC
VCC
VCC
Ven
VIN
Vo
Ven
VIN
Vo
Ven
VIN
Vo
VIN→VCC→Ven
Ven→VCC→VIN
VCC→Ven→VIN
Fig.22 Input sequence
Fig.24 Input sequence
Fig.23 Input sequence
5/16
●Reference Data(BD3551HFN)
1.25
1.23
1.21
1.19
1.17
1.15
VCC
Ven
VCC
Ven
VIN
Vo
VIN
Vo
100
90
-10
10
30
50
Ta(℃)
70
VIN→Ven→VCC
Ven→VIN→VCC
Fig.26 Input sequence
Fig.25 Input sequence
Fig.27 Ta-Vo (Io=0mA)
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
1.2
1.0
0.8
0.6
0.4
0.2
0.0
100
100
90
-10
10
30
50
Ta(℃)
70
90
-60 -30
0
30 60
Ta(℃)
90 120 150
-10
10
30
50
Ta(℃)
70
Fig.29 Ta-ISTB
Fig.30 Ta-IIN
Fig.28 Ta-ICC
20
15
10
5
25
24
23
22
21
20
19
18
17
16
15
30
25
20
15
10
5
0
-5
-10
-15
-20
0
100
100
90
-10
10
30
50
70
90
-10
10
30
50
70
-60 -30
0
30
60
90 120 150
Ta(℃)
Ta(℃)
Ta(℃)
Fig.31 Ta-IINSTB
Fig.32 Ta-INRCS
Fig.33 Ta-IFB
10
9
8
7
6
5
4
3
2
1
0
150
140
130
120
110
100
90
150
140
130
120
110
100
90
2
4
6
8
100
90
-10
10
30
50
Ta(℃)
70
100
90
-10
10
30
50
Ta(℃)
70
Vcc(V)
Fig.34 Ta-Ien
Fig.36 VCC-RON
Fig.35 Ta-RON
(VCC=5V/Vo=1.2V)
6/16
●Block Diagram
VCC
VCC
VCC
VIN
VIN
UVLO
Current
Limit
EN
CL
Reference
Block
VCC
Vo
VO
CL
UVLO
TSD
EN
FB
Thermal
Shutdown
GATE
NRCS
TSD
NRCS
GND
●Pin Layout
PIN No.
PIN name
PIN Function
1
VCC
EN
Power supply pin
Enable input pin
Gate pin
2
3
GATE
VIN
4
Input voltage pin
Output voltage pin
5
VO
6
FB
Reference voltage feedback pin
7
8
NRCS
GND
FIN
In-rush current protection (NRCS) capacitor connection pin
Ground pin
reverse
Connected to heatsink and GND
●Pin Function Table
◎HSON8
(2.2) (0.05)
B D 3
5 5 X
+0.1
0.13
−0.05
4 3 2 1
Lot No.
1PIN MARK
(Unit : mm)
7/16
●Operation of Each Block
・AMP
This is an error amp that compares the reference voltage (0.65V) with Vo to drive the output Nch FET (Ron=100m
Ω:BD3552HFN). Frequency optimization helps to realize rapid transient response, and to support the use of ceramic
capacitors on the output. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC.
When EN is OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF.
・EN
The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin Vo, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g., between the VCC pin and the ESD prevention Diode), module operation is
independent of the input sequence.
・UVLO
To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF,
and (like the EN block) discharges NRCS and Vo. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on
reset is triggered and output continues.
・CURRENT LIMIT
When output is ON, the current limit function monitors the internal IC output current against the parameter value (2.0A or
more:BD3552HFN). When current exceeds this level, the current limit module lowers the output current to protect the load
IC. When the overcurrent state is eliminated, output voltage is restored to the parameter value.
・NRCS (Non Rush Current on Start-up)
The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20
μA (TYP) constant current source to charge the external capacitor. Output start time is calculated via formula (1) below.
0.65V
t = C
・・・(1)
20μA
Tracking sequence is available by connecting the output voltage of external power supply instead of external capacitor. And
then, ratio-metric sequence is also available by changing the resistor division ratio of external power supply output voltage.
(See the next page)
・TSD (Thermal Shut down)
The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to
protect the IC against “thermal runaway” and heat damage. Because the TSD circuit is provided to shut down the IC in the
presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter not be
exceeded in the thermal design.
・VIN
The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical
connection (such as between the VCC pin and the ESD protection Diode) is necessary, VIN operates independent of the
input sequence. However, since an output NchFET body Diode exists between VIN and Vo, a VIN-Vo electric (Diode)
connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from Vo.
8/16
●Timing Chart
EN ON/OFF
VIN
VCC
EN
0.65V(typ)
NRCS
Vo
Startup
t
VCC ON/OFF
VIN
VCC
EN
UVLO
Hysteresis
0.65V(typ)
NRCS
Vo
Startup
t
Tracking sequence
1.8V Output
1.2V Output
DC/DC
(R1=3.9kΩ, R2=3.3kΩ)
NRCS
V0
1.8V
Vo
Tracking sequence
1.2V
3.3kΩ
R2
R1
FB
1.8V
1.2V
3.9kΩ
Ratio-metric sequence
9/16
●Evaluation Board
■ BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Schematic
GND_S
GND
VCC
C1
1
8
VCC
VCC
GND
SW1
R8
GND
U1
GND
2
3
4
7
6
5
BD355XHFN
(HSON8)
NRCS
EN
C12
C10
GND
R1
GND
GND
FB
C11
GATE
VIN_S
C13
R4
R2
Vo_S
GND
Vo
VIN
R3
C9
C6
C2
C3
C5
C4
C7
C8
R5
7568
GND
R6
R7
GND GND
GND
GND
GND
GND
GND
4
U2
TP1
GND
VCC
321
TP2
JPF1
GND
GND
U3
JPF2
5
GND GND
2
GND
4
3
R9
C14
■ BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Standard Component List
Component Rating Manufacturer Product Name
Component Rating Manufacturer Product Name
U1
C1
C10
R8
C5
-
ROHM
BD355XHFN
C2
22uF
KYOCERA
CM32X5R226M10A
GRM188B11H102KD
MCR03EZPF3301
MCR03EZPF3901
1uF
MURATA
GRM188B11A105KD
GRM188B11H103KD
Jumper
C13
R1
1000pF MURATA
0.01uF MURATA
3.9kΩ
3.3kΩ
ROHM
ROHM
0Ω
-
R2
22uF
KYOCERA
CM32X5R226M10A
■ BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Layout
(2nd layer and 3rd layer is GND Line.)
Silkscreen
Bottom Layer
TOP Layer
10/16
●Recommended Circuit Example
1
2
3
8
7
6
5
VCC
EN
GND
C1
R4
C4
R1
FB
R2
C5
4
VOUT1(1.2V)
VIN
C3
C2
Recommended
Value
Component
R1/R2
Programming Notes and Precautions
3.9k/3.3k
IC output voltage can be set with a configuration formula using the values for the internal
reference output voltage (VFB)and the output voltage resistors (R1, R2). Select resistance
values that will avoid the impact of the VREF current (±100nA). The recommended total
resistance value is 10KΩ.
C3
22μF
To assure output voltage stability, please be certain the Vo1, Vo2, and Vo3 pins and the
GND pins are connected. Output capacitors play a role in loop gain phase compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature and
load conditions. Also, note that connecting different types of capacitors in series may result
in insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation across a variety of temperature and load conditions.
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC) input pins. If the impedance of this power supply were to increase, input voltage
(VCC) could become unstable, leading to oscillation or lowered ripple rejection function.
While a low-ESR 1 μ F capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.
C1
C2
C4
1μF
22μF
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VIN) input pins. If the impedance of this power supply were to increase, input voltage
(VIN) could become unstable, leading to oscillation or lowered ripple rejection function.
While a low-ESR 22 μ F capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.
0.01μF
The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (VIN to VO) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.
C5
R4
-
This component is employed when the C3 capacitor causes, or may cause, oscillation. It
provides more precise internal phase correction.
Several kΩ
It is recommended that a resistance (several kΩ to several 10kΩ) be put in R4, in case
～several 10kΩ negative voltage is applied in EN pin.
11/16
●Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 100℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
① Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
＜Reference values＞
1-layer substrate (copper foil density 0.2%)
1-layer substrate (copper foil density 7%)
2-layer substrate (copper foil density 65%)
θj-a:HSON8 198.4℃/W
92.4℃/W
71.4℃/W
Substrate size: 70×70×1.6mm3 (substrate with thermal via)
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 2.9mm×3.0mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below).
enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and
the number is designed suitable for the actual situation.).
Most of the heat loss that occurs in BD3550HFN,BD3551HFN,BD3552HFN is generated from the output Nch FET. Power
loss is determined by the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage
and the output current conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in
mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package
incorporated in BD3550HFN,BD3551HFN,BD3552HFN) make certain to factor conditions such as substrate size into the
thermal design.
Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) (Vo≒VREF) ×Io(Ave)
Example) Where VIN=1.8V, VO=1.2V, Io(Ave) = 1A,
Power consumption (W)
= 0.6(W)
=
1.8(V)-1.2(V) ×1.0(A)
12/16
●Input-Output Equivalent Circuit Diagram
VCC
VCC
1kΩ
1kΩ
VIN
NRCS
1kΩ
1kΩ
1kΩ
10kΩ
10kΩ
1kΩ
VCC
VCC
1kΩ
EN
VFB
1kΩ
VO1
VO2
350kΩ
100kΩ
100kΩ
1kΩ
50kΩ
10kΩ
20pF
●Reference landing pattern
MIE
E3
L2
(Unit:mm)
Lead pitch
Lead pitch
landing length
landing pitch
e
MIE
2.50
≧l2
b2
0.65
0.40
0.35
central pad length
central pad pitch
D3
E3
2.90
1.90
*It is recommended to design suitable for the actual application.
13/16
●Operation Notes
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Please add a protection diode when a large inductance component is connected to the output terminal, and reverse-polarity
power is possible at startup or in output OFF condition.
(Example)
OUTPUT PIN
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed
only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed.
TSD on temperature [°C]
Hysteresis temperature [°C]
(typ.)
175
(typ.)
15
BD3550HFN,BD3551HFN,BD3552HFN
10. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.
Use similar precaution when transporting or storing the IC.
14/16
11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate,
such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
B
Pin A
Pin B
Pin B
C
E
Pin A
B
C
E
N
N
N
P+
P+
P+
P+
N
P
P
Parasitic
element
N
N
Parasitic
element
P substrate
P substrate
GND
GND
GND
GND
Parasitic element
Parasitic element
Other adjacent elements
12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring
pattern of any external components, either.
●Heat Dissipation Characteristics
◎HSON8
[W]
2.0
(3) 1.75W
(1) Substrate (copper foil density: 0.2%…1-layer)
θj-a=198.4℃/W
(2) Substrate (copper foil density: 7%…1-layer)
1.5
θj-a=92.4℃/W
(3) Substrate (copper foil density: 65%…1-layer)
θj-a=71.4℃/W
(2) 1.35W
(1) 0.63W
1.0
0.5
0
0
25
50
75
100
125 150
[℃]
Ambient Temperature [Ta]
15/16
●Type Designations (Ordering Information)
B
D
3
5
5
X
H
F
N
T
R
-
Package Type
Product Name
TR Emboss tape reel opposite draw-out side: 1 pin
・BD355X
・HFN : HSON8
HSON8
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
3000pcs
2.90 0.2
0.475
(2.2) (0.05)
Direction
of feed
TR
(The direction is the 1pin of product is at the upper light when you hold
reel on the left hand and you pull out the tape on the right hand)
8
7
6
5
5
6
7
8
+0.1
0.13
−0.05
1
2
3
4
4
3
2
1
0.32 0.10
X X
X
X X
X
X X
X
X X
X
X X
X
0.65
X
X
X
X
X
X X
X
X X
X
X X
X
X X
X
X X
X
Direction of feed
1Pin
Reel
(Unit:mm)
※When you order , please order in times the amount of package quantity.
Catalog No.08T416A '08.10 ROHM ©
Appendix
Notes
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The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no respon-
sibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or
exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
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Appendix1-Rev3.0
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