BD37067FV-E2_技术文档

Datasheet

Analog Sound Processors series

Sound Processor for car audio

built-in 2^ndorder post filter

BD37067FV-M

General Description

Key Specifications

It is built-in input selector of 6 stereo source and output

to ADC after adjusting signal level. And built-in 2^ndorder

post filter to reduce out of band noise and 6ch Volume

circuit. Moreover, it is simple to design set by built-in

TDMA noise reduction systems.

 TotalHarmonic Distortion：

 Maximum Input Voltage：

0.003%(Typ)

2.2V_RMS(Typ)

55dB(Min)

2.1V_RMS(Typ)

8μV_RMS(Typ)

2.5μV_RMS(Typ)

-70dB (Typ)

 Common Mode Rejection Ratio：

 Maximum Output Voltage：

 Output Noise Voltage：

 Residual Output Noise Voltage：

 Ripple Rejection:

Features

 AEC-Q100 (Grade3) Qualified

 Built-in differential input selector that can select

single-ended / differential input

 Operating Temperature Range:

-40 ˚C to +85˚C

 Reduce the pop noise when switching gain due to

built-in advanced switch circuit

Package

SSOP-B40

W(Typ) x D(Typ) x H(Max)

13.60mm x 7.80mm x 2.00mm

 Less out-of-band noise of DAC by built-in 2^ndorder

post filter.

 Built-in buffered ground isolation amplifier to realize

high CMRR characteristics

 Built-in TDMA noise reduction circuit reduces the

additional components for external filter.

 Package is SSOP-B40. Putting same direction

input-terminals and output-terminals make PCB

layout easier and PCB area smaller.

 Available to control by 3.3V / 5V for I²C-bus

controller.

Applications

It is the optimal for the car audio. Besides, it is

possible to use for the audio equipment of mini

Compo, micro Compo.

SSOP-B40

Typical Application Circuit

VCC

INC

INS

IG1

IG2

10µF 10µF

OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 INF1 INR2

INR1

GND

24

SDA

23

SCL

10µF 10µF

10µF

10µF 10µF

2.2µF 2.2µF 2.2µF 2.2µF 2.2µF 2.2µF

10µF

27

VREF

VCC2

VCC1

26

40

39

38

37

35

34

33

32

31

30

29

28

22

21

25

36

VREF

100kΩ

I²C-bus LOGIC

Front Mixing

Sub

Selector

★

■Fader : +23dB to -79dB、-∞/1dBstep

■Input Gain : +23dB to -15dB/1dBstep

■Front Mixing : on/off

Sub

Gain Adjust

Main Gain Adjust

Fader

ATT★

★ Advanced Switch

2nd order LPF

Fader

Boost★

■2nd order LPF: fc=70kHz

■Main/Sub Gain Adjust 0dB/6dB

■Anti-TDMA noise circuit

Rear

Selector

Front

Selector

★ Input Gain

Input selector (2 single

GND

-

end and

GND

4

stereo ISO)

GND

Differential

amp

Differential

amp

GND

ISO

GND

ISO

GND

ISO

amp

ISO

amp

ISO

100kΩ

250kΩ

250kΩ 250kΩ

250kΩ

250kΩ 250kΩ 250kΩ

250kΩ

100kΩ

250kΩ 250kΩ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

TEST1 TEST2

2.2µF 2.2µF 2.2µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 10µF 2.2µF 2.2µF

MIN

A1

A2

B1

B2

CP1

CN

CP2

DP1 DN

DP2

EP1

EN

EP2

FP1

FN1

FN2

FP2

Figure 1. Typical Application Circuit

○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays.

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Contents

General Description ................................................................................................................................................... 1

Features..................................................................................................................................................................... 1

Applications................................................................................................................................................................ 1

Key Specifications...................................................................................................................................................... 1

Typical Application Circuit.......................................................................................................................................... 1

Contents..................................................................................................................................................................... 2

Pin Configuration ....................................................................................................................................................... 3

Pin Descriptions......................................................................................................................................................... 3

Block Diagram............................................................................................................................................................ 4

Absolute Maximum Ratings (Ta=25˚C)...................................................................................................................... 4

Operating Range ....................................................................................................................................................... 4

Electrical Characteristic ............................................................................................................................................. 5

Typical Performance Curve(s) ................................................................................................................................... 7

1.

2.

3.

4.

5.

6.

7.

Electrical specifications and timing for bus lines and I/O stages....................................................................................9

I²C-bus Format ............................................................................................................................................................10

I²C-bus Interface Protocol............................................................................................................................................10

Slave Address..............................................................................................................................................................10

Select Address & Data................................................................................................................................................. 11

About power on reset ..................................................................................................................................................17

About start-up and power off sequence on IC .............................................................................................................17

About Advanced Switch Circuit................................................................................................................................19

Application Example ................................................................................................................................................25

Thermal Derating Curve ..........................................................................................................................................26

I/O Equivalence Circuit ............................................................................................................................................27

Application Information ............................................................................................................................................29

1.

2.

3.

4.

5.

6.

Absolute maximum rating voltage................................................................................................................................29

About a signal input part..............................................................................................................................................29

About output load characteristics.................................................................................................................................29

About TEST1,2 terminal(19,20pin) ..............................................................................................................................30

About signal input terminals ........................................................................................................................................30

About changing gain of Input Gain and Fader Volume................................................................................................30

Operational Notes....................................................................................................................................................31

1.

2.

3.

4.

5.

6.

7.

8.

Reverse Connection of Power Supply.........................................................................................................................31

Power Supply Lines.....................................................................................................................................................31

Ground Voltage............................................................................................................................................................31

Ground Wiring Pattern.................................................................................................................................................31

Thermal Consideration ................................................................................................................................................31

Recommended Operating Conditions..........................................................................................................................31

Inrush Current..............................................................................................................................................................31

Operation Under Strong Electromagnetic Field ...........................................................................................................31

Testing on Application Boards .....................................................................................................................................31

Inter-pin Short and Mounting Errors ............................................................................................................................32

Regarding the Input Pin of the IC ................................................................................................................................32

9.

10.

11.

Ordering Name Selection ........................................................................................................................................33

Physical Dimension Tape and Reel Information......................................................................................................33

Marking Diagram......................................................................................................................................................33

Revision History.......................................................................................................................................................34

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Pin Configuration

SSOP-B40

(TOP VIEW)

A1

A2

1

2

3

4

5

6

7

8

9

40 OUTC

39 OUTS

38 OUTR1

37 OUTR2

36 OUTF1

35 OUTF2

34 INF2

33 INF1

32 INR2

31 INR1

30 INS

B1

B2

CP1

CN

CP2

DP1

DN

DP2 10

EP1 11

EN 12

29 INC

28 IG1

EP2 13

FP1 14

FN1 15

FN2 16

FP2 17

MIN 18

TEST1 19

TEST2 20

27 IG2

26 VCC1

25 VREF

24 GND

23 SDA

22 SCL

21 VCC2

Figure 2. Pin configuration

Pin Descriptions

Pin No.

Pin Name

Description

A input terminal of 1ch

Pin No.

21

Pin Name

VCC2

Description

1

A1

A2

VCC2 terminal for power supply

I²C Communication clock terminal

I²C Communication data terminal

GND terminal

2

3

A input terminal of 2ch

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

SCL

SDA

B1

B input terminal of 1ch

4

B2

B input terminal of 2ch

GND

5

CP1

CN

C positive input terminal of 1ch

C negative input terminal

C positive input terminal of 2ch

D positive input terminal of 1ch

D negative input terminal

D positive input terminal of 2ch

E positive input terminal of 1ch

E negative input terminal

E positive input terminal of 2ch

F positive input terminal of 1ch

F negative input terminal of 1ch

F negative input terminal of 2ch

F positive input terminal of 2ch

Mixing input terminal

VREF

VCC1

IG2

BIAS terminal

6

VCC1 terminal for power supply

Input Gain output terminal of 2ch

Input Gain output terminal of 1ch

Center input terminal

7

CP2

DP1

DN

8

IG1

9

INC

10

11

12

13

14

15

16

17

18

19

20

DP2

EP1

EN

INS

Subwoofer input terminal

Rear input terminal of 1ch

Rear input terminal of 2ch

Front input terminal of 1ch

Front input terminal of 2ch

Front output terminal of 2ch

Front output terminal of 1ch

Rear output terminal of 2ch

Rear output terminal of 1ch

Subwoofer output terminal

Center output terminal

INR1

INR2

INF1

EP2

FP1

FN1

FN2

FP2

MIN

TEST1

TEST2

INF2

OUTF2

OUTF1

OUTR2

OUTR1

OUTS

OUTC

TEST terminal

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Block Diagram

INC

29

INS

30

IG1

28

IG2 VCC1

OUTC OUTS OUTR1OUTR2 OUTF1 OUTF2 INF2 INF1 INR2 INR1

VREF GND

25

VCC2

21

SCL

22

SDA

23

40

39

38

37

35

34

33

32

31

27

26

24

36

VREF

100kΩ

100kΩ 100kΩ 100kΩ

100kΩ

I²C-bus LOGIC

Front Mixing

Sub

★

Selector

■Fader : +23dB to -79dB、-∞/1dBstep

■Input Gain : +23dB to -15dB/1dBstep

Sub

Main Gain Adjust

Fader

Gain Adjust

■Front Mixing : on/off

ATT★

★ Advanced Switch

2nd order LPF

Fader

Boost★

Fader

Boost★

Fader

Boost★

Fader

Boost★

Fader

Boost★

Fader

Boost★

■2nd order LPF: fc=70kHz

■Main/Sub Gain Adjust 0dB/6dB

■Anti-TDMA noise circuit

Rear

Selector

Front

Selector

★ Input Gain

Input selector (2 single-end and 4 stereo ISO)

Differential

amp

Differential

amp

GND

ISO

GND

ISO

GND

ISO

GND

ISO

GND

ISO

GND

ISO

amp

100kΩ

250kΩ

250kΩ 250kΩ

250kΩ

250kΩ 250kΩ 250kΩ

100kΩ

250kΩ 250kΩ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

MIN

19

20

TEST1 TEST2

A1

A2

B1

B2

CP1

CN

CP2

DP1 DN

DP2 EP1

EN EP2

FP1

FN1 FN2

FP2

Figure 3. Block diagram and pin assign

Absolute Maximum Ratings (Ta=25˚C)

Parameter

Symbol

Rating

10

Unit

V

Power Supply Voltage

VCC (VCC1,2)

VCC+0.3 to GND-0.3

Input Voltage

V_IN

V

Only SCL, SDA 7 to GND-0.3

Power Dissipation

Pd

1.12^(Note1)

W

Storage Temperature

T_STG

-55 to +150

˚C

(Note1) This value decreases 9mW/°C for Ta=25°C or more.

ROHM standard board shall be mounted. Thermal resistance θja = 111.1(°C/W).

ROHM Standard board size：70x70x1.6(㎣)

material：A FR4 grass epoxy board(3% or less of copper foil area)

Operating Range

Parameter

Power Supply Voltage

Temperature

Symbol

VCC (VCC1,2)

Topr

Min

7.0

-40

Typ

8.5

-

Max

9.5

Unit

V

+85

˚C

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Electrical Characteristic

(Unless specified particularly, Ta=25˚C, VCC1,2=8.5V, f=1kHz, V_IN=1V_RMS, R_G=600Ω, R_L=10kΩ,

A input, Input Gain 0dB, Gain Adjust +6dB, LPF ON, Fader 0dB, Input point=A1/A2, Monitor point=IG1/IG2)

Limit

Parameter

Symbol

I_{Q_VCC}

Unit

mA

Conditions

Min

Typ

Max

53

Current upon no signal

－

35

No signal

(I_{Q_VCC1}+I_{Q_VCC2}

)

Input Impedance (A)

R_{IN_S}

R_{IN_D}

70

100

250

130

325

kΩ

Input Impedance (B, C, D, E, F)

175

Voltage Gain

G_V

CB

-1.5

－

+0

+1.5

0.05

dB

%

Gv=20log(V_OUT/V_IN)

CB = G_V1-G_V2

Channel Balance

TotalHarmonicDistortion

V_OUT=1V_RMS

BW=400-30kHz

THD+N

0.003

R_G= 0Ω

BW = IHF-A

V_IMat THD+N(V_OUT)=1%

BW=400-30kHz

R_G= 0Ω

CTC=20log(V_OUT/V_OUT´)

BW = IHF-A

R_G= 0Ω

CTS=20log(V_OUT/V_OUT´)

Output Noise Voltage^(Note1)

Maximum Input Voltage

V_NO1

V_IM

－

3.1

2.2

8.0

μV_RMS

2.0

－

V_RMS

Crosstalk Between Channels^(Note1)

Crosstalk Between Selectors^(Note1)

CTC

CTS

－

-100

-90

dB

BW = IHF-A

XP1 and XN input

XP2 and XN input

CMRR=20log(V_IN/V_OUT

Common Mode Rejection Ratio

(C, D, E, F) ^(Note1)

CMRR

55

65

－

dB

)

BW = IHF-A, [X=C,D,E,F]

Input gain -15dB

Gin=20log(V_OUT/V_IN)

Minimum Input Gain

Maximum Input Gain

G_{IN MIN}

-17

21

-15

23

-13

25

dB

Input gain 23dB

V_IN=100mV_RMS

G_{IN MAX}

Gin=20log(V_OUT/V_IN)

Gain Set Error

G_{IN ERR}

R_OUT

-2

-

+0

+2

50

dB

GAIN=-15 to +23dB

Output Impedance

－

Ω

V_IN=100mV_RMS

THD+N=1%

BW=400-30kHz

Maximum Output Voltage

V_OM

2.0

2.2

－

V_RMS

(Note1) VP-9690A (Average value detection, effective value display) filter by Panasonic is used for measurement. Input and output are in-phase.

(Unless specified particularly, Ta=25˚C, VCC1,2=8.5V, f=1kHz, V_IN=0.9V_RMS, R_G=600Ω, R_L=10kΩ,

A input, Input Gain 0dB, Gain Adjust +6dB, LPF ON, Fader 0dB,

Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS)

Limit

Parameter

Symbol

Unit

Conditions

Min

-

Typ

Max

50

Output Impedance

Maximum OutputVoltage

R_OUT

V_OM

－

Ω

V_IN=100mV_RMS

THD+N=1%

BW=400-30kHz

2.0

2.1

－

V_RMS

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(Unless specified particularly, Ta=25˚C, VCC1,2=8.5V, f=1kHz, V_IN=0.9V_RMS, R_G=600Ω, R_L=10kΩ,

A input, Input Gain 0dB, Gain Adjust +6dB, LPF ON, Fader 0dB,

Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS)

Limit

Parameter

Symbol

Unit

Conditions

Gain=23dB

V_IN=100mV_RMS

G_F=20log(V_OUT/V_IN)

Gain Adjust=0dB

Min

21

Typ

Max

25

Maximum Boost Gain

Channel Balance

G_{F BST}

23

dB

CB

-1.5

+0

+1.5

CB = G_V1-G_V2

TotalHarmonicDistortion

THD+N

V_NO1

－

0.003

8

0.05

16

%

BW=400-30KHz

R_G= 0Ω

BW = IHF-A

Output Noise Voltage^(Note1)

μV_RMS

Fader = -∞dB

μV_RMSR_G= 0Ω

BW = IHF-A

Residual Output Noise Voltage^(Note1)

Maximum Input Voltage

V_NOR

－

2.0

－

2.5

2.1

8.0

－

V_IMat THD+N(V_OUT)=1%

BW=400-30KHz

Gain Adjust = 0dB

R_G= 0Ω

CTC=20log( V_OUT/V_OUT´)

BW = IHF-A

Fader = -∞dB

G_F=20log( V_OUT/ V_IN)

BW = IHF-A

V_IM

V_RMS

dB

Crosstalk Between Channels^(Note1)

Maximum Attenuation^(Note1)

CTC

G_{F MIN}

-100

-90

－

dB

Gain Set Error

G_{F ERR}

G_{F ERR1}

G_{F ERR2}

-2

-3

+0

+2

+3

dB

Gain=+1 to +23dB

Attenuation Set Error 1

Attenuation Set Error 2

Attenuation=0 to -15dB

Attenuation=-16 to -47dB

Attenuation Set Error 3

G_{F ERR3}

-4

+0

+4

dB

Attenuation=-48 to -79dB

f=1kHz

Ripple Rejection

Input Impedance

MaximumInput voltage

PSRR

R_{IN_M}

V_{IM_M}

－

70

-70

100

2.2

-40

130

-

dB

kΩ

V_RR=100mV_RMS

RR_VCC=20log(V_OUT/VCC)

VIM at THD+N(V_OUT)=1%

BW=400-30KHz

MIN input

2.0

V_RMS

Front Mixing=OFF

G_MX=20log( V_OUT/V_IN

BW=IHF-A

)

Maximum Attenuation^(Note1)

G_{MX MIN}

-

-100

-85

dB

MIN input

Front Mixing=ON

G_MX=20log( V_OUT/V_IN

Mixing Gain

G_MX

-2

+0

+2

dB

)

Input Impedance

R_{IN_M}

70

100

130

kΩ

Gain=6dB

V_IN=100mV_RMS

G_F=20log(V_OUT/VI_IN)

Boost Gain

G_{F BST}

4

6

8

dB

-1.5

+0

+1.5

dB

CB = G_V1-G_V2

Channel Balance

CB

(Note1) VP-9690A (Average value detection, effective value display) filter by Panasonic is used for measurement. Input and output are in-phase.

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Typical Performance Curve(s)

40

35

30

25

20

15

10

8

6

4

2

0

-2

-4

-6

-8

-10

(I_{Q_VCC}=I_{Q_VCC1}+I_{Q_VCC2}

)

5

0

1

2

3

4

5

6

7

8

9

10

100

1k

10k

100k

VCC [V]

Frequency [Hz]

Figure 4. I_{Q_VCC}vs. VCC

Figure 5. Gain vs. Frequency

10

1

10

8

6

f=10kHz

1

4

f=100,1kHz

2

0.1

0.01

0.001

0

-2

-4

-6

-8

-10

0.01

0.001

0.01

0.1

1

10

100

1k

10k

100k

V_IN[V_RMS

]

Frequency [Hz]

Figure 7. THD+N, V_Ovs V_IN

(Gain Adjust=+6dB)

Figure 6. Gain vs. Frequency

(Gain Adjust=+6dB)

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0

-20

-40

-60

-80

0

-20

R_G=1kΩ

-40

R_G=470Ω

R_G=0Ω

-60

-80

-100

-120

-100

10

100

1k

10k

100k

100

1k

Frequency [Hz]

10k

100k

Frequency [Hz]

Figure 9. CTC vs. Frequency

Figure 8. CMRR vs. Frequency

0

-20

5

0

LPF Pass

-40

-5

LPF ON

-60

-10

-15

-20

-80

-100

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency [Hz]

Figure 10. PSRR vs. Frequency

Figure 11. Gain vs Frequency

(LPF ON/Pass)

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I²C-bus Control Signal Specification

1. Electrical specifications and timing for bus lines and I/O stages

SDA

^tBUF

^tHD;STA

^tSP

^tLOW

SCL

^tSU;STO

^tSU;STA

^tHD;STA

^tSU;DAT

^tHD;DAT

^tHIGH

Sr

S

P

Figure 12. Definition of timing on the I²C-bus

Table 1. Characteristics of the SDA and SCL bus lines for I²C-bus devices

Parameter

Fast-modeI²C-bus

Symbol

Unit

Min

Max

400

kHz

1

2

SCL Clock Frequency

fSCL

tBUF

0

Bus Free time between a STOP and START condition

1.3

－

μsec

Hold Time (repeated) START condition. After this period, the first clock

pulse is generated

3

tHD;STA

0.6

－

μsec

4

5

6

LOW Period of the SCL Clock

tLOW

1.3

0.6

－

μsec

HIGH Period of the SCL Clock

tHIGH

tSU;STA

Set-up time for a Repeated START Condition

7

8

9

Data Hold Time

tHD;DAT

tSU;DAT

tSU;STO

0*

－

μsec

Data set-up Time

100

0.6

Set-up Time for STOP Condition

All values referred to VIH min. and VIL max. Levels (see Table 2.).

Table 2. Characteristics of the SDA and SCL I/O stages for I²C- bus devices

Fast-modeI²C-bus

Parameter

Symbol

Unit

Min

-0.5

2.3

Max

+1

-

10 LOW level input voltage: Fixed input levels

11 HIGH level input voltage: Fixed input levels

VIL

V

VIH

12 Pulse width of spikes, which must be suppressed by the input filter.

tSP

VOL1

I_i

0

50

0.4

+10

nsec

V

LOW level output voltage (open drain or open collector): At 3mA sink

current

13

Input current each I/O pin with an input voltage between 0.4V and 0.9

VDD max.

14

-10

μA

HD;STA

HD;DAT

SU;DAT

SU;STO

ｔ

2µsec

：

1µsec

：

1µsec

：

2µsec

：

SCL

SDA

BUF

4µsec

LOW

3µsec

HIGH

ｔ

1µsec

：

SCL clock frequency:250kHz

Figure 13. I²C data transmission timing

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2. I²C-bus Format

MSB

Slave Address

8bit

LSB

MSB

Select Address

8bit

LSB

MSB

LSB

S

1bit

A

1bit

A

1bit

Data

8bit

A

P

1bit 1bit

S

= Start condition (Recognition of start bit)

Slave Address = Recognition of slave address. 7 bits in upper order are optional.

The last bit must be “L” for writing.

A

= Acknowledge bit (Recognition of acknowledgement)

Select Address = Address for each function

Data

P

= Data of each function

= Stop condition (Recognition of stop bit)

3. I²C-bus Interface Protocol

1) Basic form

S

Slave Address

MSB LSB

A

Select Address

MSB LSB

A

Data

MSB LSB

A

P

2) Automatic increment(Select Address increases (+1) according to the number of data)

Slave Address Select Address Data1 Data2

MSB LSB MSB LSB MSB LSB MSB LSB

S

A

････ Data N

MSB LSB

A

P

(Example)①Data 1 shall be set as data of address specified by Select Address.

②Data 2 shall be set as data of address specified by Select Address +1.

③Data N shall be set as data of address specified by Select Address +(N-1).

3) Configuration unavailable for transmission (In this case, only Select Address 1 is set.)

S

Slave Address

A

Select Address1

A

Data

A

Select Address 2

A

Data

A

P

MSB LSB MSB

LSB MSB LSB MSB

LSB MSB LSB

(Note)If any data is transmitted as Select Address 2 next to data,

It is recognized as data, not as Select Address 2.

4. Slave Address

MSB

A6

1

LSB

R/W

0

A5

0

A4

0

A3

0

A2

0

A1

0

A0

0

80(hex)

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5. Select Address & Data

Select

MSB

D7

Data

D3

LSB

D0

Address

(hex)

Items

D6

0

D5

D4

D2

0

D1

0

Advanced

Switch

ON/OFF

Advanced Switch

time of Input

Initial Setup 1

01

0

Gain/Fader

Rear

Front

Selector Selector

Initial Setup 2

Input Selector

02

05

0

Sub Selector

0

Input Selector

Input Gain

06

28

29

2A

2B

2C

2D

Fader 1ch Front

Fader 2ch Front

Fader 1ch Rear

Fader 2ch Rear

Fader Center

Fader Gain / Attenuation

Fader Subwoofer

Front

Mixing

ON/OFF

Sub

Gain

Adjust

Main

Gain

Adjust

LPF setup

Mixing

30

LPF fc

0

System Reset

FE

1

0

1

Advanced switch

Note) Set up bit (It is written with “0” by the above table) which hasn’t been used in “0”.

Notes on data format

1. “Advanced switch” function is available for the hatched parts on the above table.

2. In case of transferring data continuously, Select Address(hex) flows by Automatic increment function, as shown

below.

→01→02→05→06→28→29→2A→2B→2C→2D→30

3. Input selector that is not corresponded for “Advanced switch” function, cannot reduce the noise caused when

changing the input selector. Therefore, it is recommended to turn on mute when changing these settings.

4. In case of setting to infinite “-∞” by using Fader when input selector setting is changed, please consider “Advanced

switch” time.

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Select Address 01 (hex)

Advanced Switch time of

Input Gain/Fader

MSB

D7

LSB

D0

Mode

D6

0

D5

0

1

D4

0

D3

D2

0

D1

0

4.7 msec

7.1 msec

11.2 msec

14.4 msec

Advanced

Switch

ON/OFF

1

0

1

MSB

D7

0

Advanced Switch ON/OFF

LSB

D0

Mode

D6

0

D5

D4

D3

D2

0

D1

0

Advanced Switch

time of Input

Gain/Fader

OFF

ON

0

1

Select Address 02 (hex)

Mode

MSB

D7

Front Selector

LSB

D0

0

D6

0

D5

D4

D3

D2

0

D1

Rear

Selector

FRONT

INSIDE THROUGH

0

Sub Selector

1

MSB

D7

Rear Selector

LSB

D0

Mode

D6

0

D5

D4

D3

D2

0

D1

0

REAR

Front

Selector

0

Sub Selector

FRONT COPY

1

MSB

D7

Sub Selector

LSB

D0

Mode^(Note1)

D6

0

D5

0

D4

D3

D2

0

D1

OUTC(INS)

OUTS(INS)

OUTC(INR1)

OUTS(INR2)

OUTC (INC)

OUTS(INS)

0

1

0

1

0

1

Rear

Selector

Front

Selector

0

Prohibition

(Note1) xxx(INxx) : “xxx” means “Output terminal”, “(INxx)” means “Output signal”

: Initial condition

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Select Address 05 (hex)

MSB

D7

Input Selector

LSB

Mode

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

A

B single

C single

D single

E single

F single

C diff

0

1

0

1

0

1

0

1

0

1

0

1

0

D diff

E diff

1

0

F full-diff

1

0

1

：

1

0

：

1

：

1

0

：

1

Prohibition

: Initial condition

List of active input terminal when set input selector

Lch positive input

terminal

Lch negative

input terminal

Rch positive

input terminal

Rch negative

input terminal

Mode

A

1pin(A1)

3pin(B1)

-

2pin(A2)

4pin(B2)

-

B

-

C single

D single

E single

F single

C diff

5pin(CP1)

8pin(DP1)

11pin(EP1)

14pin(FP1)

5pin(CP1)

8pin(DP1)

11pin(EP1)

-

7pin(CP2)

10pin(DP2)

13pin(EP2)

17pin(FP2)

7pin(CP2)

10pin(DP2)

13pin(EP2)

-

6pin(CN)

9pin(DN)

12pin(EN)

6pin(CN)

9pin(DN)

12pin(EN)

D diff

E diff

F full-diff

14pin(FP1)

15pin(FN1)

17pin(FP2)

16pin(FN2)

〔About Ground Isolation Amplifier〕

EP1

1ch Signal Input

11

1ch

GND Isolation

Amplifie

Ground Isolation Amplifier ：C diff to E diff

EN

12

Please select this mode when you use them as

a ground isolation amplifier.

2ch

EP2

13

GND Isolation

Amplifie

2ch Signal Input

FP1

14

1ch

1ch Signal Input

2ch Signal Inptu

FN1

15

Differential

Amplifier

Full Differential Amplifier : F full-diff

FN2

16

Please select this mode when you use it as

a differential amplifier

2ch

Differential

Amplifier

FP2

17

Figure 14. About Ground Isolation Amplifier

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Select Address 06 (hex)

Mode

MSB

D7

Input Gain

D4

LSB

D0

0

D6

D5

0

：

0

1

D3

0

：

1

0

1

0

1

0

：

1

D2

0

：

0

1

0

1

0

1

0

1

0

1

0

：

1

D1

0

：

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

：

1

0

：

0

1

0

1

：

1

Prohibition

：

0

+23dB

+22dB

+21dB

+20dB

+19dB

+18dB

+17dB

+16dB

+15dB

+14dB

+13dB

+12dB

+11dB

+10dB

+9dB

+8dB

+7dB

+6dB

+5dB

+4dB

+3dB

+2dB

+1dB

0dB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

：

1

0

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

-8dB

-9dB

-10dB

-11dB

-12dB

-13dB

-14dB

-15dB

1

：

1

Prohibition

: Initial condition

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Select Address 28, 29, 2A, 2B, 2C, 2D (hex)

MSB

D7

0

Fader Gain / Attenuation

LSB

D0

0

Gain & ATT

Prohibition

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

：

0

1

：

0

：

1

：

1

：

0

：

1

：

0

：

0

+23dB

+22dB

+21dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

・

+10dB

+9dB

+8dB

+7dB

+6dB

+5dB

+4dB

+3dB

+2dB

+1dB

0dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-1dB

-2dB

-3dB

・・

-78dB

-79dB

1

0

1

0

1

0

1

0

Prohibition

：

1

：

1

：

1

：

1

：

1

：

1

：

1

：

0

-∞dB

1

: Initial condition

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Select Address 30(hex)

Mode

MSB

D7

Main Gain Adjust

LSB

D0

0

D6

D5

0

D4

D3

D2

0

D1

0dB

Front

Mixing

Sub Gain

Adjust

LPF fc

0

+6dB

1

MSB

D7

Sub Gain Adjust

LSB

D0

Main

Gain

Adjust

Mode

D6

D5

0

D4

D3

D2

0

D1

0

0dB

Front

Mixing

LPF fc

0

+6dB

1

MSB

D7

LPF fc

LSB

D0

Main

Gain

Adjust

Mode

D6

0

D5

0

D4

0

D3

0

D2

0

D1

70kHz

PASS

Front

Mixing

Sub Gain

Adjust

1

MSB

D7

0

Front Mixing ON/OFF

LSB

D0

Main

Gain

Adjust

Mode

D6

D5

0

D4

D3

D2

0

D1

OFF

ON

Sub Gain

Adjust

LPF fc

0

1

: Initial condition

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6. About power on reset

It is possible for the reset circuit inside the IC to initialize when supply voltage is turned on. Please send data to all

address as initial data when the supply is turned on, and turn on mute until all initial data are sent.

Limit

Item

Symbol

t_RISE

Unit

Condition

Min

33

Typ

Max

Rise time of VCC1,2

VCC1,2 voltage of

release power on

reset

－

μsec VCC rise time from 0V to 5V

V_POR

－

4.1

－

V

7. About start-up and power off sequence on IC

VCC Typ

t2-t1≧250µsec

7.0V

VCC1

/VCC2

5.0V

POR Max.

POR Min.

3.0V

～

OFF Voltage

1.0V

t1 t2

20msec

I²C-bus Select

Address

01(hex)

External

MUTE

normal term

power off

start-up

Figure 15. Power off and start-up sequence

This IC will become active-state by sending data of Select Address 01(hex) on I²C-bus after 20msec from that VCC1 and

VCC2 reaches over 7.0V. Therefore, this command must always send in start-up sequence. In addition, External MUTE

means recommended period that the muting outside IC.

About output terminal(27,28,35 to 40pin) vs. VCC

Bias voltage of output terminal (27,28,35 to 40pin) keep fixed voltage in operational range of VCC.

Figure 16. OUT(27,28,35 to 40pin)_DC-Bias = 4.15V fixed.

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Fader Volume Attenuation of the Detail

(dB)

+23

+22

+21

+20

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

D7 D6 D5 D4 D3 D2 D1 D0

(dB)

-29

-30

-31

-32

-33

-34

-35

-36

-37

-38

-39

-40

-41

-42

-43

-44

-45

-46

-47

-48

-49

-50

-51

-52

-53

-54

-55

-56

-57

-58

-59

-60

-61

-62

-63

-64

-65

-66

-67

-68

-69

-70

-71

-72

-73

-74

-75

-76

-77

-78

-79

-∞

D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

：Initial condition

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About Advanced Switch Circuit

【1】Advanced switch technology

1-1. Advanced switch effects

Advanced switch technology is ROHM original technology that can prevent from switching pop noise. If changing the

gain setting (for example Fader) immediately, the audible signal will become discontinuously and pop noise will be

occurred. This Advanced switch technology will prevent this discontinuous signal by completing the signal waveform

and will significantly reduce the noise.

select

slave

data

I²C-bus

28 86

80

If the gain instantly changes after the data is transmitted, the DC

fluctuation will occur as much as before and after the oscillation

different. This technology makes this fluctuation changes slow.

DC level change

Advanced switch

waveform

Figure 17. The explanation of advanced switch waveform

This Advanced switch circuit will start operating when the data is transmitted from microcontroller.

Advanced switch waveform is shown as the figure above. For preventing switching noise, this IC will operate

optimally by internal processing after the data is transmitted from microcontroller.

However, sometimes the switching waveform is not like the intended form depends on the transmission timing.

Therefore, below is the example of the relationship between the transmission timing and actual switching time. Please

consider this relationship for the setting.

1-2. The kind of the Transferring Data

・Data setting that is not corresponded to Advanced switch

(Page11 Select Address & Data Data format without hatching)

There is no particular rule about transferring data.

・Data setting that is corresponded to Advanced switch

（Page11 Select Address & Data Data format with hatching）

There is no particular rule about transferring data, but Advanced switch must follow the switching sequence as

mentioned in【2】as follows.

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【2】Data transmission that is corresponded to Advanced switch

2-1. Switching time of Advanced switch

Switching time includes [t_WAIT(Wait time)], [t_SFT(A→B switching time)] and [t_SFT(B→A switching time)].

25msec is needed per 1 switching. (t_SOFT= t_WAIT+ 2 * t_SFT

,

t_WAIT=2.3msec, t_SFT=11.2msec)

[wait time]

=t_WAIT

[A→B switching time]

=t_SFT

[B→A switching time]

=t_SFT

Current XdB

Send YdB

Change YdB

W

A → B

B → A

Advanced Switch Timeꢀ(t_SOFT

)

In the figure above, Start/Stop state is expressed as “A” and temporary state is expressed as “B”.

The switching sequence of Advanced switch consists of the cycle “A(start)→B(temporary)→A(stop)”. Therefore, switching

sequence will not stop at B state.

For example, switching is performed from A(Initial gain)→B(set gain)→A(set gain) when switching from initial gain to set

gain. And switching time (t_SFT) of A→B or B→A are equal.

2-2. About the data transmission’s timing in same block state and switching operation

■ Transmitting example 1

This is an example when transmitting data in same block with “enough interval for data transmission”.

(enough interval for data transmission : 1.4 x t_SOFT* ”1.4” includes tolerance margin.)

Definition of example expression :

F1=Fader 1ch Front, F2=Fader 2ch Front, R1=Fader 1ch Rear, R2=Fader 2ch Rear

C=Fader Center, S=Fader Subwoofer, MIX=Front Mixing

slave select data ack

I²C-bus

80 28 80

(F1 0dB)

80 28 FF

(F1 -∞dB)

t_SOFT* 1.4 msec

W

A → B

B → A

W

A → B

B → A

Advanced Switch time

F1 output

■ Transmitting example 2

This is an example when the transmission interval is not enough (smaller than “Transmission example 1”). When

the data is transmitted during first switching operation, the second data will be reflected after the first switching

operation. In this case, there is no wait time (t_WAIT) before the second switching operation.

slave select data ack

I²C-bus

80 28 80

(F1 0dB)

80 28 FF

(F1 -∞dB)

W

A → B

B → A

A → B

B → A

Advanced Switch time

F1 output

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■ Transmitting example 3

This is an example of switching operation when transmission interval is smaller than “Transmission example 2”).

When the data is transmitted during the first switching operation, and transmission timing is just during A→B

switching operation, the second data will be reflected at B→A switching term.

slave select data ack

I²C-bus

80 28 80

(F1 0dB)

80 28 FF

(F1 -∞dB)

W

A → B

B → A

Advanced Switch time

F1 output

■ Transmitting example 4

The below figure shows an example of switching operation that the data are transmitted serially with smaller

transmission interval than “Transmission example 3”.

IC has internal data-storage buffer and buffer transmitted data as storage data constantly.

However, only the latest data is kept so, in this example, +4dB data transmitted secondly is ignored.

slave select data ack

I²C-bus

80 28 80

(F1 0dB)

80 28 7C

(F1 +4dB)

80 28 FF

(F1 -∞dB)

W

B → A

A → B

F1 output

A → B

Advanced Switch time

■ Transmitting example 5

Transmitted data is firstly buffered and written to setting data which set gain. However, when there is no

difference between transmitted data and setting data such as refresh data, advanced switch operation doesn’t

start.

slave select data ack

I²C-bus

80 28 80

(F1 0dB)

80 28 80

(F1 0dB)

Refresh Data

F1 Advanced Switch

W

A → B

B → A

Advanced Switch time

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2-3. Mixing ON/OFF switching operation of Front Mixing

The action of the Mixing switching waveform is different in OFF to ON or ON to OFF.

■ Transmission example 1

This is an example of Mixing OFF to ON state.

slave select data ack

I²C-bus

80 30 80

(MIX ON)

W

A → B

B → A

Advanced Switch time

F1 output

This is an example of Mixing ON to OFF state

slave select data ack

I²C-bus

80 30 00

(MIX OFF)

W

A → B

B → A

Advanced Switch time

F1 output

■ Transmission example 2

This is an example when transmission ON to OFF in short interval during to Mixing switching operation.

This is an example of in case of transmitted data of another status(MIX OFF) in during A→B transmission timing.

slave select data ack

I²C-bus

80 30 80

(MIX ON)

80 30 00

(MIX OFF)

W

B → A

A → B

Advanced Switch time

F1 output

This is an example of in case of transmitted data of another status(MIX OFF) in during B→A transmission timing.

slave select data ack

I²C-bus

80 30 80

(MIX ON)

80 30 00

(MIX OFF)

W

B → A

A → B

Advanced Switch time

F1 output

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■ Transmission example 3

This is an example when transmission OFF to ON in short interval during to Mixing switching operation.

This is an example of in case of transmitted data of another status(MIX ON) in during A→B transmission timing.

slave select data ack

I²C-bus

80 30 00

(MIX OFF)

80 30 80

(MIX ON)

W

B → A

A → B

Advanced Switch time

F1 output

This is an example of in case of transmitted data of another status(MIX ON) in during B→A transmission timing.

slave select data ack

I²C-bus

80 30 00

(MIX OFF)

80 30 80

(MIX ON)

W

B → A

A → B

Advanced Switch time

F1 output

2-3. About the data transmitting timing and the switching movement in several block state

When data are transmitted to several blocks, treatment in the BS (block state) unit is carried out inside the IC. The

order of advanced switch movement start is decided in advance dependent on BS.

S0

S1

S２

S３

Input Gain

06(hex)

Mixing

Fader R1

2A(hex)

Fader R2

2B(hex)

Fader C

2C(hex)

Fader S

2D(hex)

30(hex)

Fader F1

28(hex)

Fader F2

29(hex)

Select address

The order of advanced switch start

Note) It is possible that blocks in the same BS start switching at the same timing.

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■ Transmitting example 1

About the transmission to several blocks also, as explained in the previous section, though there is no restriction of the

I²C-bus data transmitting timing, the start timing of switching follows the figure of previous page, the order of advanced

switch start.

Therefore, it isn't based on the data transmitting order, and an actual switching order becomes as the figure of previous

page, “The order of advanced switch start”.

Each block data is being transmitted separately in the transmitting example 1, but it becomes the same result even if data

are transmitted by automatic increment.

slave select data ack

I²C-bus

80 28 80

(F1 0dB)

80 2A 80

(R1 0dB)

80 2C 80

(C 0dB)

F1 Advanced Switch

R1 Advanced Switch

C Advanced Switch

W

A → B

B → A

A → B

B → A

A → B

B → A

Advanced Switch time

F1 output

R1 output

C output

■ Transmitting example 2

In the case that data transmission order and actual switching order is different, or data is transmitted to the block in

other BS before the advanced switch operation finished, switching of next BS starts after current switching.

ex：①F1 -6dB

80 xx ｘｘ

ꢀ ②F1 -20dB

①

② ③ ④

ꢀ ③C -6dB

ꢀ ④R1 -6dB

I²C-bus

F1 Advanced Switch

R1 Advanced Switch

C Advanced Switch

F1 Advanced Switch

W

A → B

B → A

A → B

B → A

A → B

B → A

A → B

B → A

Advanced Switch time

Active channel

OutputꢀF1

Initial Initial → ①

①

① → ②

②

Active channel

OutputꢀR1

OutputꢀC

Initial

Initial → ④

④

Active channel

Initial → ③

③

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Application Example

VCC

INC

INS

IG1

IG2

10µF 10µF

OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 INF1 INR2

INR1

SCL

GND SDA

10µF 10µF

10µF

10µF 10µF

10µF

2.2µF 2.2µF 2.2µF 2.2µF 2.2µF 2.2µF

10µF

VREF

VCC2

VCC1

28

40

39

38

37

35

34

33

32

31

30

29

27

26

24

22

25

23

21

36

VREF

100kΩ

I²C-bus LOGIC

Front Mixing

Sub

Selector

★

■Fader : +23dB to -79dB、-∞/1dBstep

■Input Gain : +23dB to -15dB/1dBstep

■Front Mixing : on/off

Sub

Gain Adjust

Main Gain Adjust

Fader

ATT★

★ Advanced Switch

2nd order LPF

Fader

Boost★

■2nd order LPF: fc=70kHz

■Main/Sub Gain Adjust 0dB/6dB

■Anti-TDMA noise circuit

Rear

Selector

Front

Selector

★ Input Gain

Input selector (2 single

GND

- end and 4 stereo ISO)

Differential

amp

Differential

amp

GND

ISO

GND

ISO

GND

ISO

GND

ISO

GND

ISO

amp

ISO

100kΩ

250kΩ

250kΩ 250kΩ

250kΩ

250kΩ 250kΩ 250kΩ

250kΩ

100kΩ

250kΩ 250kΩ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

TEST1 TEST2

2.2µF 2.2µF 2.2µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 10µF 2.2µF 2.2µF

MIN

A1

A2

B1

B2

CP1

CN

CP2

DP1 DN

DP2

EP1

EN

EP2

FP1

FN1

FN2

FP2

Figure 18. Application Example

Notes on wiring

①Please connect the decoupling capacitor of a power supply as close as possible to GND.

②Lines of GND shall be one-point connected.

③Wiring pattern of Digital shall be away from that of analog unit and cross-talk shall not be acceptable.

④Lines of SCL and SDA of I²C-bus shall not be parallel if possible. The lines shall be shielded, if they are adjacent

to each other.

⑤Lines of analog input shall not be parallel if possible. The lines shall be shielded, if they are adjacent to each other.

⑥About TEST1,2 terminal(19,20pin), please use with OPEN.

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Thermal Derating Curve

About the thermal design by the IC

Characteristics of an IC have a great deal to do with the temperature at which it is used, and exceeding absolute maximum

ratings may degrade and destroy elements. Careful consideration must be given to the heat of the IC from the two

standpoints of immediate damage and long-term reliability of operation.

Reference data

SSOP-B40

1.5

Measurement condition: ROHM

Standard board

board Size：70mm x 70mm x 1.6mm

1.12W

material：A FR4 grass epoxy board

1.0

0.5

0.0

(3% or less of copper foil area)

θja = 111.1˚C /W

85

0

25

50

75

100

125

150

Ambient Temperature Ta（˚C）

Figure 19. Temperature Derating Curve

Note) Values are actual measurements and are not guaranteed.

Note) Power dissipation values vary according to the board on which the IC is mounted.

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I/O Equivalence Circuit

Terminal

No

Terminal

Name

Terminal

Voltage

Equivalent Circuit

Terminal Description

Terminal for signal input

VCC

1

A1

A2

4.15V

2

The input impedance is 100kΩ(Typ).

29

30

31

32

33

34

18

INC

.

INS

INR1

INR2

INF1

INF2

MIN

100kΩ

GND

Input terminal

3

4

B1

B2

4.15V

Single/Differential mode is selectable.

The input impedance is 250kΩ(Typ).

5

CP1

CN

6

7

CP2

DP1

DN

VCC

8

9

10

11

12

13

14

15

16

17

DP2

EP1

EN

250kΩ

EP2

FP1

FN1

FN2

FP2

GND

Input Gain output terminal

VCC

27

28

IG2

IG1

4.15V

GND

VCC

Fader output terminal

35

36

37

38

39

40

OUTF2

OUTF1

OUTR2

OUTR1

OUTS

4.15V

OUTC

GND

The figures in the pin explanation and input/output equivalent circuit is designed value, it doesn’t guarantee the value.

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Terminal

No

Terminal

Name

Terminal

Voltage

Equivalent Circuit

Terminal Description

Power supply terminal

21,26

VCC

8.5V

(VCC1,2)

Terminal for clock input of I²C-bus

communication

－

22

SCL

VCC

(Note) When this pin is shorted to next pin(VCC), it

may result in property degradation and destruction of

the device.

1.65V

GND

VCC

Terminal for data input of I²C-bus

communication

－

23

SDA

1.65V

GND

VCC

Ground terminal

BIAS terminal

24

25

GND

0V

VREF

4.15V

Voltage for reference bias of analog signal

system. The simple precharge circuit and

simple discharge circuit for an external

capacitor are built in.

12.5kΩ

4.15V

GND

The figures in the pin explanation and input/output equivalent circuit is designed value, it doesn’t guarantee the value.

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Application Information

1. Absolute maximum rating voltage

When voltage is impressed to VCC exceeding absolute maximum rating voltage, circuit current increases rapidly

and it may result in property degradation and destruction of a device.

When impressed by a VCC terminal (21,26pin) especially by serge examination etc., even if it includes an of

operation voltage +serge pulse component, be careful not to impress voltage (about 14V VCC terminal) much higher

than absolute maximum rating voltage.

2. About a signal input part

In the signal input terminal, the value of the input coupling capacitor C(F) should be sufficient to match the value of input

impedance R_IN(Ω) inside the IC. The first HPF characteristic of CR is as shown below.

G[dB]

C [F]

0

A(f)

G

R_IN

Frequency[Hz]

f

(2πf・C・R_IN)²

A(f)=

1+(2πf・C・R_IN)²

Figure 20. Input Equivalent Circuit

3. About output load characteristics

The usages of load for output are below (reference). Please use the load more than 10 kΩ(Typ).

Output terminal

Terminal

No.

Terminal

Name

IG1

Terminal

No.

Terminal

Name

OUTF1

OUTF2

Terminal

No.

Terminal

Name

OUTR1

OUTR2

Terminal

No.

Terminal

Name

OUTC

OUTS

28

27

36

35

38

37

40

39

IG2

3

2.5

2

3

2.5

2

1.5

1

1.5

1

IG1/IG2

VCC1,2=8.5V

THD+N=1%,f=1kHz

BW=400 to 30kHz

OUTF1/F2/R1/R2/C/S

VCC1,2=8.5V

THD+N=1%,f=1kHz

BW=400 to 30kHz

0.5

0

0.5

0

100

1k

10k

100k

100

1k

10k

100k

Load Resistance [Ω]

Figure 21. Output load characteristic at VCC1,2=8.5V (Reference)

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Application Information – continued

4. About TEST1,2 terminal(19,20pin)

About TEST1,2 terminal(19,20pin), please use with OPEN.

5. About signal input terminals

Because the inner impedance of the terminal becomes 100 kΩ or 250 kΩ when the signal input terminal makes a

terminal open, the plunge noise from outside sometimes becomes a problem. When there is an unused signal input

terminal, design so it is shorted to ground.

6. About changing gain of Input Gain and Fader Volume

In case of the boost of the input gain and fader volume when changing to the high gain which exceeds

20 dB especially, the switching pop noise sometimes becomes big.

In this case, we recommend changing every 1 dB step without changing a gain at once.

Also, the pop noise sometimes can reduce by making advanced switch time long, too.

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Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3.

4.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

Thermal Consideration

Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip

may result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating,

increase the board size and copper area to prevent exceeding the maximum junction temperature rating.

6.

7.

Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately

obtained. The electrical characteristics are guaranteed under the conditions of each parameter.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may

flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,

and routing of connections.

8.

9.

Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

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Operational Notes – continued

10. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)

and unintentional solder bridge deposited in between pins during assembly to name a few.

11. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should

be avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 22. Example of monolithic IC structure

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Ordering Name Selection

F

V

B D 3

7

0

6

7

‐

ME 2

Package

FV: SSOP-B40

Product Rank

M: for Automotive

Part Number

Packaging and forming specification

E2: Embossed tape and reel

(SSOP-B40)

Physical Dimension Tape and Reel Information

Marking Diagram

SSOP-B40(TOP VIEW)

Part Number Marking

LOT Number

BD37067FV

1PIN MARK

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Revision History

Date

Revision

Changes

13.MAR.2014

14.NOV.2016

001

002

New Release

・Additional specification about advanced switch operation

・Additional specification of power supply sequence

・Change document style of specification

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.003

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.003


型号：	BD37067FV-E2
厂家：	ROHM
描述：	Sound Processor for car audio built-in 2nd order post filter
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BD37067FV-E2 [ROHM]

相关型号：

BD37067FV-M

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BD37068FV-ME2

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BD37069FV-E2

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BD370A

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BD370B-16