BD57020MWV-E2 [ROHM]
Power Supply Support Circuit, Fixed, 1 Channel, UQFN-40;
| 型号： | BD57020MWV-E2 |
| 厂家： | 
ROHM |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, UQFN-40 |
| 文件： | 总42页 (文件大小：1380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Wireless Power Consortium / Qi Compliant series
Wireless Power Transmitter IC
BD57020MWV
General Description
Key Specifications
Input Power Supply Voltage Range: 4.2 V to 5.3 V
BD57020MWV is an integrated IC for the wireless power
transmitter. This device is composed of inverters for the
coil drive, controller for the communication of the Qi
compliant and demodulating circuit, GPIO, TCXO buffer,
and I2C interface.
Input Adapter Voltage Range:
Drive Frequency Range:
4.6 V to 20 V
110kHz to 205kHz
-20°C to +85°C
Operating Temperature Range:
BD57020MWV works as a controller in the wireless
power transmitter based on the Qi compliant by using it
with a general-purpose microcomputer.
Package
UQFN040V5050
W(Typ) x D(Typ) x H(Max)
5.00mm x 5.00mm x 1.00mm
BD57020MWV is applied to Qi ver.1.2 BPP / EPP
(Baseline Power Profile / Extended Power Profile).
Features
WPC / Qi ver.1.2 BPP / EPP (Baseline Power Profile
/ Extended Power Profile) support.
Half Bridge / Full Bridge inverter
Foreign object detection
GPIO 4CH
I2C bus interface
5.0mm x 5.0mm UQFN package 40 pin
Applications
WPC compliant devices
PC
Cradle for charge stand
Typical Application Circuit
3.3V
CS
+
-
ADPIN
19V
BD57015GWL
Power
BD57020MWV
MOSFET
NN
Rectification
LDO
Mod
Load
Driver
Full Bridge
1
MCU
OVPIN
SW1 30
29
Data
3.3V
2
LDO33B
HSIDE1
Voltage
&
Current
Sensing
3.3V
3
4
LDO33A
VDD
LSIDE1 28
PGND 27
LSIDE2 26
Voltage
&
Current
Sensing
Demodulator
Qi packet
Controller
5
6
7
8
9
TCXOEN
TCXOIN
TCXOOUT
GPIO0
BD57020MWV
25
HSIDE2
SW2 24
Transmitter(TX)
Receiver(RX)
BOOT2
23
GPIO1
Figure 2. Product position in wireless
power supply system
22
21
TEST
COIL_IN
10 GPIO2
ADPIN
I2C IF
MONI1
CS
ADC
ML610Q772
Figure 1. Typical application circuit
〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays
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Absolute Maximum Ratings
Parameter
VIN, ADPV, ADPI, SW1, SW2 voltage
BOOT1, BOOT2 voltage
Symbol
VIN_H1
VIN_H2
VOUT_H
Rating
Unit
V
-0.3 to 24.0
-0.3 to 31.0
-0.3 to 31.0
V
HSIDE1, HSIDE2 voltage
V
OVPIN, VDDIO, CLKIN, CLKSET, FSKIN,
SCL, RESETB, TEST, ADDR voltage
VIN_L1
-0.3 to 7.0
V
VDD, TCXOIN voltage
COIL_IN voltage
VIN_L2
VIN_L3
-0.3 to 4.5
-4.5 to 7.0
V
V
LDO33A, LDO33B , INTB, LSIDE1, LSIDE2,
OVPOUT, MONI0, MONI1 voltage
VOUT_L1
-0.3 to 7.0
V
TCXOEN, TCXOOUT voltage
SDA voltage
VOUT_L2
VINOUT_L1
VINOUT_L2
Pd
-0.3 to 4.5
-0.3 to7.0
-0.3 to 4.5
V
V
GPIO0, GPIO1, GPIO2, GPIO3 voltage
Power dissipation
V
3.26 (Note 1
)
W
°C
°C
Operating ambient temperature range
Ta
-20 to +85
Storage temperature range
Tstg
-55 to +150
(Note 1) Derate by 26 mW/°C when operating above Ta=25°C (Mount on 4-layer 74.2mm x 74.2mm x 1.6mm board with front and back layer heat radiation
copper foil 4.5 mm x 4.5 mm, second and third layer heat radiation copper foil 74.2 mm x 74.2 mm).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta= -20°C to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
VIN terminal input voltage range
VDD terminal input voltage range
VDDIO terminal voltage range
Adapter input voltage range
VIN
4.2
3.1
3.1
4.6
32
5.0
3.3
3.3
-
5.3
3.5
3.5
20
V
V
VDD
VDDIO
VADPV
V
V
TCXO terminal input frequency range FTCXO
-
52
MHz
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Electrical Characteristics (Unless otherwise specified VIN=5V VDD=3.3V Ta=25°C)
Limit
Typ
Parameter
Symbol
Unit
Conditions
Min
Max
Whole Chip
Operating circuit current 1
Operating circuit current 2
Protection block (the IC outside)
External OCP operating voltage
Protective circuit (the IC inside)
VIN Over voltage lockout
Hysteresis on OVLO
ICC1
ICC2
-
-
2.0
3.0
mA
mA
TCXOIN=0kHz
15.0
23.0
TCXOIN=32MHz
VOCP
125
160
195
mV
RS=100mΩ
VOVLO_VIN
VOVLO_HYS
VUVLO_VIN
6.1
140
3.3
6.4
200
3.6
6.7
260
3.9
V
mV
V
VIN: 5.0 → 8.0V
VIN: 8.0 → 5.0V
VIN: 5.0 → 0V
VIN Under voltage lockout
Hysteresis on UVLO
VUVLO_HYS
VUVLOD_VDD
VUVLOR_VDD
VUVLOD_VDDIO
VUVLOD_VDDIO
IOCP
140
2.25
2.55
2.25
2.55
-
200
2.50
2.80
2.50
2.80
0.48
260
2.75
3.05
2.75
3.05
0.65
mV
V
VIN: 0 → 5.0V
VDD UVLO detection voltage
VDD UVLO release voltage
VDDIO UVLO detection voltage
VDDIO UVLO release voltage
Internal OCP operating current
LDO33A block
VDD: 3.3 → 0V
VDD: 0 → 3.3V
VDDIO: 3.3 → 0V
VDDIO: 0 → 3.3V
V
V
V
A
LDO33A output voltage
VLDO33A
ILDO33A
3.2
-
3.3
-
3.4
30
V
Isource=10mA
Isource=10mA
LDO33A maximum output current
LDO33B block
mA
LDO33B output voltage
LDO33B maximum output current
Demodulating circuit block
COIL_IN leak current 1
VLDO33B
ILDO33B
3.2
-
3.3
-
3.4
30
mV
mA
ILEAKCOILIN1
ILEAKCOILIN2
-
-
-
50
-
µA
µA
VCOIL_IN=3.3V
VCOIL_IN=-3.3V
COIL_IN leak current 2
-150
TCXO_BUFF block
TCXOIN input current
ITCXOIN
-
-
0
-
1.0
52
µA
VDD=VTCXOIN=4.5V
Input frequency range
FTCXOIN
MHz
VDD
x 0.2
TCXOEN L level output voltage
TCXOEN H level output voltage
VOHTXCOEN
-
-
V
Isink=1.0mA
VDD
x 0.8
VOLTXCOEN
ZOTCXOOUT
-
-
-
V
Isource=1.0mA
TCXOOUT output impedance
Inverter block
-
1.0
kΩ
Drive frequency
Minimum Duty Ratio
Dead Time
FDRIVE
Dutymin
TDead
110
-
205
kHz
%
-
-
-
-
25
-
-
-
-
200
1.0
0.8
ns
Ω
TCXOIN=32MHz
Source resistance
Sink resistance
RSOURCE
RSINK
Ω
GPIO block
VDD
x 0.3
GPIO L level input voltage
GPIO H level input voltage
VOLGPIO
VOHGPIO
-
-
-
V
V
VDD
x 0.7
-
GPIO pull-down resistor
GPIO pull-up resister
RPDGPIO
RPUGPIO
-
-
100
100
kΩ
kΩ
-
VDD
x 0.2
GPIO L level output voltage
GPIO H level output voltage
VILGPIO
VIHGPIO
-
-
-
V
V
Isink=1.0mA
VDD
x 0.8
-
Isource=1.0mA
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Limit
Typ
Parameter
Symbol
Unit
Conditions
Min
-
Max
FSKIN terminal
VDDIO
x 0.3
FSKIN L level input voltage
VILFSKIN
VIHFSKIN
-
-
V
V
VDDIO
x 0.7
FSKIN H level input voltage
CLKIN terminal
-
VDDIO
x 0.3
CLKIN L level input voltage
VILCLKIN
VIHCLKIN
-
-
-
V
V
VDDIO
x 0.7
CLKIN H level input voltage
ADDR terminal
-
VDDIO
x 0.3
ADDR L level input voltage
VILADDR
VIHADDR
-
-
-
V
V
VDDIO
x 0.7
ADDR H level input voltage
-
INTB terminal
Open Drain ability on INTB
INTB leak current
RESETB terminal
VLINTB
-
-
380
-
500
2.0
mV
µA
Isink=5.0mA
VINTB=7.0V
ILEAKINTB
VDD
x 0.3
RESETB L level input voltage
RESETB H level input voltage
VILRSTB
-
-
V
VDD
x 0.7
VIHRSTB
-
-
-
V
RESETB pull-up resister
I2C interface
RPDRSTB
-
100
kΩ
SCL, SDA L level input voltage
SCL, SDA H level input voltage
SCL, SDA L level input current
SCL, SDA H level input current
SDA L level output voltage
VILI2C
VIHI2C
IILI2C
-
1.50
-1.0
-
-
-
-
-
-
0.50
-
V
V
-
µA
µA
mV
IIHI2C
1.0
400
VOLI2C
-
Isink=3.0mA
Pin Configuration
(TOP VIEW)
30
29
28
1
2
3
4
OVPIN
SW1
HSIDE1
LSIDE1
LDO33B
LDO33A
VDD
27
26
25
PGND
LSIDE2
HSIDE2
5
6
7
8
9
TCXOEN
TCXOIN
TCXOOUT
GPIO0
24
23
SW2
BOOT2
22
21
GPIO1
TEST
10
COIL_IN
GPIO2
Figure 3. Pin Configuration
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Pin Description
Pin No.
1
Pin Name
OVPIN
LDO33B
LDO33A
VDD
Function
I/O
5.0V input, connected to OVPOUT.
3.3V LDO output.
I
O
O
I
2
3
3.3V LDO output.
4
3.3V supply.
5
TCXOEN
TCXOIN
TCXOOUT
GPIO0
GPIO1
GPIO2
GPIO3
VDDIO
CLKIN
CLKSET
FSKIN
SCL
Connected to External oscillator. Control signal output.
Connected to External oscillator.
O
I
6
7
Connected to External oscillator.
O
I/O
I/O
I/O
I/O
I
General-purpose input and output terminal.
8
General-purpose input and output terminal.
General-purpose input and output terminal.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
General-purpose input and output terminal.
3.3V supply.
Clock input terminal, leave this pin open.
Test terminal, leave this pin open.
FSK control signal input.
I
I
I
I2C clock input
I
SDA
I2C Data input and output.
I/O
O
I/O
I
INTB
Interrupt detection output.
RESETB
AGND
COIL_IN
TEST
Control logic reset
Analog ground.
Coil current / voltage input.
I
Test terminal, connected to GND.
Connected to Boot strap capacitor.
Connected to the source of high side FET and the drain of low side FET.
Connected to the gate of high side FET.
Connected to the gate of low side FET.
Power ground.
I
BOOT2
SW2
I
I
HSIDE2
LSIDE2
PGND
LSIDE1
HSIDE1
SW1
O
O
I
Connected to the gate of low side FET.
Connected to the gate of high side FET.
Connected to the source of high side FET and the drain of low side FET.
Connected to Boot strap capacitor.
Slave Address change.
O
O
I
BOOT1
ADDR
I
I
OVPOUT
VIN
5.0V output, connected to OVPIN.
5.0V Input power supply
O
I
VIN
5.0V Input power supply
I
MONI0
MONI1
ADPI
Coil current value output.
O
O
I
Input voltage value output.
Sense transmitter Input current.
Sense transmitter Input voltage.
Reference ground.
ADPV
I
REFGND
I
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Block Diagram
UVLO
OVP
BOOT1
HSIDE1
OVPIN
POWER_SENSE
DRIVER
DRIVER
SW1
LDO33B
LDO
VDD
LSIDE1
BOOT2
HSIDE2
SW2
LDO33A
VDD
LDO
TSD
OSC
VDD
CONTROL
Logic
LSIDE2
PGND
TCXOEN
TCXOIN
TCXOOUT
VDD
VDD
TCXO Buff
COIL_IN
MONI0
DEMOD
GPIO0
GPIO1
GPIO
IO
GPIO2
GPIO3
Figure 4. Block diagram
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Description of Blocks
1. Pre-driver block
Transmitter (Tx) includes inverter circuits to input AC electricity into both ends of the primary coil and to produce the
electromotive force on the secondary side by electromagnetic induction. BD57020MWV includes two pre-driver blocks to
support Half Bridge inverter and Full Bridge inverter configurations. For the Half Bridge inverter configuration, it is
necessary to set the pre-driver 1 (PWM0 signal). For the Full Bridge inverter configuration, it is necessary to set the
pre-driver 1 and pre-driver 2 (PWM1 signal). The output power control modes are the frequency control, the duty control
and the phase control. The pre-driver block prevents a through current by monitoring the on/off timing of low side FET and
high side FET.
For high efficiency, the bootstrap drive system which sets the H side-L side to Nch FET is adopted. It is necessary to put a
capacitor (0.1 – 0.47 µF) between the BOOT1 (BOOT2) terminal and the SW1 (SW2) terminal to maintain the voltage
potential between these pins. Install a ceramic capacitor as close to these pins as possible.
2. Digital Ping
Tx inputs AC electricity into the primary coil and by electromagnetic induction develops an electromotive force on the
secondary coil which starts the Receiver (Rx). This phase is called Digital Ping. Tx keeps transmitting power as long as it
receives Digital Ping from the Rx. Tx controls the transmission power based on a packet including the power incoming
information from Rx. The following registers are used to configure Digital Ping.
(1) PWM0PRD: Setting register for the period of PWM0 signal
This register is used to set the period of PWM0 signal. The PWM0 signal sets the period of the pulse to be output from
pre-driver 1 with a count level. The relation between the period of PWM0 signal and source clock is determined by the
following formula:
SourceClock
TargetClock
PWM 0PRD round
1
Where “round” means rounding off to the nearest whole number and the source clock is from the TCXO.
For example, if source clock=32MHz and target clock=100kHz, PWM0PRD register is set to the following value:
32000
100
PWM 0PRD round
1 319 0x013F
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
PWM0
PRDL
PWM0
PRDH
PWM0
PRD7
PWM0
PRD15
PWM0
PRD6
PWM0
PRD14
PWM0
PRD5
PWM0
PRD13
PWM0
PRD4
PWM0
PRD12
PWM0
PRD3
PWM0
PRD11
PWM0
PRD2
PWM0
PRD10
PWM0
PRD1
PWM0
PRD9
PWM0
PRD0
PWM0
PRD8
0x20
0x21
0x00
0x00
R/W
R/W
After PWM0DTYH (0x23) is written, this register is updated with the new data.
(2) PWM0DTY: Setting register for the duty of PWM0 signal
This register is used to set the duty of PWM0 signal. PWM0 signal is the output signal at pre-driver 1. The duty of PWM0
signal is set with the count number of the source clock. After this register has been written, when the counter number of
PWM0 signal becomes 0, the data of PWM0PRD register and PWM0DTY register are updated with the new data. The
relation between the duty of PWM0 signal and source clock is determined by the following formula:
Duty
PWM 0DTY int
PWM 0PRD 1
100
Where “int” means rounding down to the nearest whole number and the source clock is from TCXO.
For example, if source clock= 32MHz and target clock=100kHz with duty=50%, PWM0DTY register is set to the following
value:
50
PWM 0DTY int
320 1
160 0x00A0
100
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Duty is defines as the ratio between the amount of time when the output is high in one period to the whole period of
PWM0 signal. The enable range of PWM0DTY register is from 0x0001 to (PWM0PRD-1). PWM0 will not be generated if
the PWM0DTY register is set to a value greater than or equal to the value in PWM0PRD register.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
PWM0
DTYL
PWM0
DTYH
PWM0
DTY7
PWM0
DTY15
PWM0
DTY6
PWM0
DTY14
PWM0
DTY5
PWM0
DTY13
PWM0
DTY4
PWM0
DTY12
PWM0
DTY3
PWM0
DTY11
PWM0
DTY2
PWM0
DTY10
PWM0
DTY1
PWM0
DTY9
PWM0
DTY0
PWM0
DTY8
0x22
0x23
0x00
R/W
R/W
0x00
(3) PWM1PHS: Setting register for the phase difference between PWM1 signal and PWM0 signal
This register is used to set the phase difference between PWM1 signal and PWM0 signal with the count number of the
source clock. PWM1 signal is a signal with the same period and duty as PWM0 signal. After PWM0DTYH register (0x23)
is written and the counter number of PWM0PRD register becomes 0, the data of this register is updated with the new
data. The enable range of this register is from 0x0001 to (PWM0PRD). PWM1 signal will not be generated if the
PWM1PHS register is set to a value greater than or equal to the value in PWM0PRD register. It is also necessary to write
0x23 in PWM0DTYH register after this register has been written.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
PWM1
PHSL
PWM1
PHSH
PWM1
PHS7
PWM1
PHS15
PWM1
PHS6
PWM1
PHS14
PWM1
PHS5
PWM1
PHS13
PWM1
PHS4
PWM1
PHS12
PWM1
PHS3
PWM1
PHS11
PWM1
PHS2
PWM1
PHS10
PWM1
PHS1
PWM1
PHS9
PWM1
PHS0
PWM1
PHS8
0x24
0x25
0x00
R/W
R/W
0x00
(4) PWM0GEN: Setting register for the dead time of PWM0 signal
This register is used to set the dead time of PWM0 signal. The relation between the dead time and the source clock is
defined by the following formula:
2
DeadTime
SourceClock
For example, if source clock=32MHz, Dead Time is the smallest value and it is 62.5nsec.
Additionally, please set this register to the following value.
Full Bridge inverter: PWMGEN0= 0x49
Half Bridge inverter: PWMGEN0= 0x10
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
P0DLY
D1
P0DLY
D0
P0DLY
C2
P0DLY
C1
P0DLY
C0
P0DLY
B2
P0DLY
B1
P0DLY
B0
PWMGEN0
0x30
0x92
(5) PWM1GEN: Setting register for the dead time of PWM1 signal
This register is used to set the dead time of PWM1 signal. The relation between the dead time and source clock is
determined by the following formula:
2
DeadTime
SourceClock
For example, if source clock=32MHz, Dead Time is the smallest value and it is 62.5nsec.
Additionally, please set this register to the following value.
Full Bridge inverter: PWMGEN1= 0x49
Half Bridge inverter: PWMGEN1= 0x10
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
P1DLY
D1
P1DLY
D0
P1DLY
C2
P1DLY
C1
P1DLY
C0
P1DLY
B2
P1DLY
B1
P1DLY
B0
PWMGEN1
0x31
0x92
(6) PWRCTRL: Setting register for the operation mode
This register is used to set the operation mode and the base clock for the internal movement. By setting the power mode
bit (PWMD0, PWMD1), the operation mode is changed. The operation mode is Digital Ping when PWMD=0x0.
Meanwhile, the operation mode is Analog Ping, which is also the low power consumption mode, when PWMD=0x1. On
the other hand, the operation is Stop Mode when PWMD=0x3. During Stop Mode, all blocks are stopped.
BD57020MWV uses the input clock signal from TCXOIN terminal for source clock of the internal movement.
Please set this register with TCXSEL = 1, and connect TCXO with frequency between 32 to 52MHz to TCXOIN terminal.
When TCXSEL = 1 and TCXEN = 1, TCXOEN terminal becomes high output but when TCXSEL = 1 and TCXEN = 0,
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TCXOEN terminal becomes low output. Please set this register with OSCSEL= 1 to use an internal oscillator clock for
measuring Analog Ping internal period.
・[7:6]
・[5:4]
Reserved
PWMD0, PWMD1: Setting bit for operation mode
(0x0: Digital Ping mode
0x1: Analog Ping mode
0x2: Reserved
0x3: Stop mode)
・[3]
・[2]
Reserved
OSCSEL: Control bit for using internal oscillator
(0x1: Enable
0x0: Disable)
・[1]
・[0]
TCXEN: Control bit for using external TCXO
(0x1: Enable (High output)
0x0: Disable (Low output))
TCXSEL: Selection bit for using external TCXO
(0x1: Enable
0x0: Disable)
Initial
R/W
Address
Name
b7
b6
b5
b4
b3
b2
OSCSEL
b1
TCXEN
b0
TCXSEL
Value
* 1
* 1
* 1
PWRCTRL
0x0F
-
-
PWMD1
PWMD0
-
0x07
R/W
*1 prohibited
(7) PDCTRL: Control register for the pre-driver output
This register is used to enable pre-driver 1 and pre-driver 2. Pre-driver 1 drives HSIDE1 terminal and LSIDE1 terminal
while pre-driver 2 drives HSIDE2 terminal and LSIDE2 terminal. When PDEN=1, the pulse is produced at HSIDE1
terminal and LSIDE1 terminal. When PDEN=0, the pulse is stopped. When PWM1EN=1, the pulse is produced at
HSIDE2 terminal and LSIDE2 terminal. When PWM1EN=0, the pulse is stopped.
Refer to 3. FSK (Frequency Shift Keying) for the explanation of PSWEN and PS256.
・[7:5]
・[4]
Reserved
PWM1EN: Control bit for pre-driver 2
(0x1: Enable
Reserved
0x0: Disable)
・[3]
・[2]
・[1]
・[0]
PS256: Change the PWM output to every 256 cycles
PSWEN: Control of the PWM change function
PDEN: Control bit for pre-driver 1
(0x1: Enable
0x0: Disable)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
PWM1
EN
* 1
* 1
* 1
* 1
PDCTRL0
0x12
-
-
-
-
PS256
PSWEN
PDEN
0x00
*1 prohibited
3. FSK (Frequency Shift Keying)
BD57020MWV transmits a packet to Rx using Frequency Shift Keying (FSK) to establish communication with Rx. When Tx
transmits a packet using FSK, Tx changes the frequency of the PWM0 signal by pre-driver 1 into the drive frequency (fd)
and the modulation frequency (fmod) every 256 periods. That drive frequency is the frequency of the PWM0 signal which
set in 2.(1).That FSK modulation frequency is the frequency of the PWM0 signal which set in 3. The setting of FSK sets the
following registers.
(1) PWMXPRD: Setting register for the period of the PWM0 signal at FSK
This register is used to set the period of PWM0 signal when PSWEN=1 (PDCTRL0: 0x12) and FSKIN terminal = high.
The relation between the period of PWM0 signal and source clock is determined by the formula below, and it is
expressed in the same formula as PWM0PRD.
SourceClock
TargetClock
PWMXPRD round
1
Where “round” means rounding off to the nearest whole number.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
PWMX
PRDL
PWMX
PRDH
PWMX
PRD7
PWMX
PRD15
PWMX
PRD6
PWMX
PRD14
PWMX
PRD5
PWMX
PRD13
PWMX
PRD4
PWMX
PRD12
PWMX
PRD3
PWMX
PRD11
PWMX
PRD2
PWMX
PRD10
PWMX
PRD1
PWMX
PRD9
PWMX
PRD0
PWMX
PRD8
0x26
0x27
0x00
0x00
R/W
R/W
(2) PWMXDTY: Setting register for the duty of the PWM0 signal at FSK
This register is used to set the duty of PWM0 signal when PSWEN=1 (PDCTRL0: 0x12) and FSKIN terminal = high. The
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relation between the duty of PWM0 signal and source clock is determined by the formula below, and it is expressed in a
same formula as PWM0DTY.
Duty
PWMXDTY int
PWMXPRD 1
100
Where “int” means rounding down to the nearest whole number.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
PWMX
DTYL
PWMX
DTYH
PWMX
DTY7
PWMX
DTY15
PWMX
DTY6
PWMX
DTY14
PWMX
DTY5
PWMX
DTY13
PWMX
DTY4
PWMX
DTY12
PWMX
DTY3
PWMX
DTY11
PWMX
DTY2
PWMX
DTY10
PWMX
DTY1
PWMX
DTY9
PWMX
DTY0
PWMX
DTY8
0x28
0x29
0x00
0x00
R/W
R/W
(3) PDCTRL: Control register for pre-driver output
This register is used to change the frequency of PWM0 signal by setting PSWEN and PS256. When PSWEN=1, the
frequency and duty of PWM0 signal are changed by input signal of FSKIN terminal.
・When PSWEN = 0, the data of PWM0 signal is updated to the data of PWM0PRD and PWM0DTY.
・When of PSWEN = 1 and FSKIN terminal = Low, the data of PWM0 signal is updated to the data of PWM0PRD
register and PWM0DTY register.
・When of PSWEN = 1 and FSKIN terminal = High, the data of PWM0 signal is updated to the data of PWMXPRD
register and PWMXDTY register.
When PS256 is 1, the period and the duty of PWM0 are changed by input signal of FSKIN terminal every 256 cycles.
After having taken in a change of external terminal FSKIN, during 256 cycles of the output frequency, the next change
isn’t taken. Furthermore, an interrupt occurs every 256 cycles of the output frequency when PXIEN bit of register
INTENB (0x04) is 1. Whenever an interrupt occurs, the output frequency from a pre-driver is changed by changing input
of external terminal FSKIN every 256 cycles. Refer to 2.Digital Ping (7) PDCTRL for the explanation of bits.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
PWM1
EN
* 1
* 1
* 1
* 1
PDCTRL0
0x12
-
-
-
-
PS256
PSWEN
PDEN
0x00
*1 prohibited
4. Analog Ping
BD57020MWV outputs pulse signal from primary coil to detect if Rx was put on the interface of the Tx. The presence of Rx
is confirmed if BD57020MWV detects a change in the coil current or voltage. When the change of the coil current or voltage
reaches the threshold value of the Analog Ping detection, the state shifts to Digital Ping. Additionally, BD57020MWV will
generate an interrupt after Analog Ping executes a set number of times. In Analog Ping, it is necessary to drive a primary
coil near the resonant frequency. The setting of the frequency is performed right before an output of Analog Ping, like Digital
Ping. Set the following registers to configure Analog Ping.
(1) APGCTRL: Control register for Analog Ping
This register is used to set the start and stop of Analog Ping and the expected value of Rx detection by Analog Ping.
BD57020MWV starts Analog Ping when APEN=1 is set. The period and duty of PWM0 should be set before APEN is set
to 1. BD57020MWV stops Analog Ping when APEN=0 is set. When the state of the COIL_IN terminal is matched with the
expected value of this register, BD57020MWV detects Rx. When APEN is 1, BD57020MWV becomes the stand-by state,
the circuit electric current decreases.BD57020MWV will execute Analog ping until any of the two conditions is met: 1.)
Analog Ping finishes the set number of repeated execution without detecting any Rx. 2.) Rx is detected wherein it
generates an interrupt and stops Analog Ping. The expected value of Analog Ping is configured as follows:
・[7]
APEN: Control bit for Analog Ping
(0x1: Enable
Reserved
APEX0, APEX1: Expected value of Analog ping
(0x1: Detect the Rx 0x0: Not detect the Rx
0x0：Disable)
・[6:2]
・[1:0]
0x2, 0x3: Reserved)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
* 1
* 1
* 1
* 1
* 1
APGCTRL
0x16
APEN
-
-
-
-
-
APEX1
APEX0
0x00
*1 prohibited
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(2) APGSTT: Analog Ping status register
This register shows status of Analog Ping.
・[7]
Reserved
・[6:4]
APSTA2, APSTA1, APSTA0: Analog Ping status
0x0: Stop
0x1: Under the standby set in APGIVT
0x3: Under the power output set in APGIDUR
0x5: Under the measurement set in APGMSR
0x6: A state of the input accorded with a value of the APEX.
BD57020MWV generates an interrupt and stop.
0x7: The number of Analog Ping cycles reaches the set number.
BD57020MWV generates an interrupt and stop.
Others: Reserved
・[3:0]
Reserved
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
* 1
* 1
* 1
* 1
* 1
APGSTT
0x17
-
APSTA2
APSTA1
APSTA0
-
-
-
-
0x00
*1 prohibited
(3) APGITVL: Setting register for the interval time of Analog Ping
This register is used to set the interval time of Analog Ping. If The Analog Ping detection interval is set short, time from
Rx establishment on Tx to Tx starting power feeding is short. However, the power consumption of Tx increases The
Analog Ping detection interval is set by interval with internal oscillation clock (typ.100kHz). The relation between the
interval time and input clock is determined by the following formula:
APGITV
IntervalTimeInputClock 1
For example, if Input Clock=100kHz and time of Interval Time=500msec, the value of APGITV register is set to the
following value:
APGITV
500100 1 49999 0xC34F
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
APG
ITV7
APG
ITV15
APG
ITV6
APG
ITV14
APG
ITV5
APG
ITV13
APG
ITV4
APG
ITV12
APG
ITV3
APG
ITV11
APG
ITV2
APG
ITV10
APG
ITV1
APG
ITV9
APG
ITV0
APG
ITV8
APGITVL
APGITVH
0x18
0x19
0x00
0x00
R/W
R/W
(4) APGDUR: Setting register for the duration time of Analog Ping
This register is used to set the duration time of Analog Ping. Duration time is defined as the time frame wherein
BD57020MWV produces the pulse output and drives the primary coil. The input clock from TCXOIN terminal is a source
clock. The relation between the duration time and source clock is determined by the following formula:
1
APGDUR int DurationTimeSourceClock
1
1000
Where “int” means rounding down to the nearest whole number.
For example, if the time of duration is 100µsec and Source Clock is 32MHz, the value of APGDUR register is set to the
following value:
1
APGDUR int 10032000
1 3199 0x0C7F
1000
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
APG
DUR7
APG
DUR6
APG
DUR5
APG
DUR4
APG
DUR3
APG
APG
DUR2
APG
APG
DUR1
APG
APG
DUR0
APG
APGDURL
0x1A
0x1B
0x00
0x00
R/W
R/W
* 1
* 1
* 1
* 1
APGDURH
-
-
-
-
DUR11
DUR9
DUR8
DUR7
*1 prohibited
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BD57020MWV
(5) APGMSR: Setting register for the measurement time of Analog Ping
This register is used to set the measurement time of Analog Ping. Measurement time is defined as the time frame after
the duration time wherein BD57020MWV monitors the state of COIL_IN to confirm the presence of Rx. The input clock
from TCXOIN terminal is a source clock. The relation between the measurement time and source clock is determined by
the following formula:
1
APGMSR int MeasurementTimeSourceClock
1
1000
Where “int” means rounding down to the nearest whole number.
For example, if Measurement Time=10µsec and Source Clock is 32MHz, APGMSR register is set to the following value:
1
APGMSR int 1032000
1 319 0x013F
1000
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
APG
MSR7
APG
MSR6
APG
MSR5
APG
MSR4
APG
MSR3
APGMS
R11
APG
MSR2
APGMS
R10
APG
MSR1
APGMS
R9
APG
MSR0
APGMS
R8
APGMSRL
0x1C
0x1D
0x00
0x00
R/W
R/W
* 1
* 1
* 1
* 1
APGMSRH
-
-
-
-
*1 prohibited
(6) APGCNT: Setting register for the execution number of times of Analog Ping
This register is used to set the number of times Analog Ping carries out automatically. If APGCNT= 0, Analog Ping is
carried out until APEN bit of APGCTRL register is 0. If APIEN=1 in the INTENB register, when the number of Analog Ping
execution times reaches the set number, BD57020MWV generates an interrupt signal. BD57020MWV keeps generating
an interrupt signal until APEN bit of APGCTRL register is 0.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
APG
CNT7
APG
CNT6
APG
CNT5
APG
CNT4
APG
CNT3
APG
CNT2
APG
CNT1
APG
CNT0
APGCNT
0x1E
0x00
5. Interrupt control
BD57020MWV generates various interrupt signals. These are configured by the following registers.
(1) INTSTT: Interrupt status register
This register shows an interrupt status when an interrupt factor occurred. When any bit of this register is set,
BD57020MWV generates an interrupt signal on INTB terminal. When the bit is set to 1, the interrupt signal is cleared.
・[7]
・[6]
・[5]
・[4]
・[3]
・[2]
・[1]
・[0]
Reserved
APINT: An interrupt signal of Analog Ping occurs.
Reserved
AGINT: An interrupt signal by the protection movement occurs.
EINT: An interrupt signal due to the parity error or the framing error of the received packet.
CINT: An interrupt signal due to the check sum error of the received packet.
RINT2: An interrupt signal due to the normal completion of reception by demodulator 2.
RINT1: An interrupt signal due to the normal completion of reception by demodulator 1.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
* 1
* 1
INTSTT
0x03
-
APINT
-
AGINT
EINT
CINT
RINT2
RINT1
0x00
*1 prohibited
(2) INTENB: Control register for an interrupt
This register is used to control an interrupt signal. When the interrupt factor that is set to 1 by this register occurred, a bit
to support of the interrupt status register is set. But there is no bit of the interrupt status register (INTSTT) corresponding
to PXIEN of the interrupt enable register (INTENB). Because the admitted interrupt occurs in 1 pulse by PXIEN, the
status at the time of the outbreak of interrupt is not maintained.
・[7]
・[6]
・[5]
・[4]
・[3]
PXIEN: Control bit for an interrupt signal every 256 cycles by PWM change function
APINT: Control bit for an interrupt signal in Analog Ping
Reserved
AGINT: Control bit for an interrupt signal by protection movement
EINT: Control bit for an interrupt signal by the parity error or the framing error during the packet reception
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BD57020MWV
・[2]
・[1]
CINT: Control bit for an interrupt signal by the check sum error during the packet reception
RINT2: Control bit for an interrupt signal by normal completion at demodulator 2 during the packet
reception
・[0]
RINT1: Control bit for an interrupt signal by normal completion at demodulator 1 during the packet
reception
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
* 1
INTENB
0x04
PXIEN
APIEN
-
AGIEN
EIEN
CIEN
RIEN2
RIEN1
0x00
*1 prohibited
6. AM demodulator block
BD57020MWV has the two AM demodulator blocks for communication with Rx. The characteristics of demodulator blocks
are different to improve communication stability. The following registers are used for the configuration of the demodulator
blocks.
(1) RXCTRL: Control register for Packet reception
This register is used to control the demodulating blocks. If PRE1 bit=1, the demodulator 1 is enabled to receive the
packets. If PRE2 bit=1, the demodulator 2 is enabled to receive the packets. It is possible to set both PRE1 bit and PRE2
bit to 1 at the same time, then demodulator 1 and demodulator 2 works independently. The digital filters of the
demodulators are enabled if FTE1 bit and FTE2 bit are set to 1 in this register. In order to raise communication stability,
please be sure that the digital filters are enabled.
If other demodulator is receiving a packet even if reception error (frame error, parity error or check sum error) occurs in
demodulator 1 or demodulator 2 while CTRL is 0, it does not generate an interrupt.
If CTRL bit = 1 and a reception error occurs on demodulator 1 or demodulator 2, BD57020MWV generates an interrupt
signal immediately.
・[7]
CTRL: Setting bit of exclusive control function
(0x1: Enable
Reserved
0x0: Disable)
・[6]
・[5]
FTE2: Setting bit for the digital filter of the demodulator 2
(0x1: Enable 0x0: Disable)
FTE1: Setting bit for the digital filter of the demodulator 1
・[4]
(0x1: Enable
Reserved
PRE2: Setting bit for the demodulator 2
(0x1: Enable 0x0: Disable)
PRE1: Setting bit for the demodulator 1
0x0: Disable)
・[3:2]
・[1]
・[0]
(0x1: Enable
0x0: Disable)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
* 1
* 1
* 1
RXCTRL
0x01
CTRL
-
FTE2
FTE1
-
-
PRE2
PRE1
0x00
*1 prohibited
(2) RXSTT: Packet reception status register
This register holds the status of the packet reception of the demodulator. If packet reception with demodulator 1 is
completed normally, RCV1 becomes 1. If packet reception with demodulator 2 is completed normally, RCV2 becomes 1.
If check sum error occurs during the packet reception with demodulator 1 or demodulator 2, CERR becomes 1. If parity
error or framing error occurs during the packet reception with demodulator 1 or demodulator 2, PERR becomes 1.
The factors of the framing error during packet reception are as follows:
・Stop bit is not found.
・Reception was completed in the middle of a byte.
・The packet size that is calculated from the value of the header byte is different from the one that is received.
In addition, RCV1, RCV2, CERR and RERR, latch when packet reception is completed. These are cleared if RINT1,
RINT2, CINT and RINT (INTSTT: 0x03) are written 1.These are overwritten when the next packet is received.
When demodulator 1 is receiving packet, BSY1 becomes 1. When demodulator 2 is receiving packet, BSY2 becomes 1.
・[7]
・[6]
・[5:4]
・[3]
BSY2: Demodulator 2 is busy receiving a packet
BSY1: Demodulator 1 is busy receiving a packet
Reserved
PERR: Parity error or framing error occurred during the packet reception with either demodulator 1 or
demodulator 2
・[2]
・[1]
・[0]
CERR: Check sum error occurred during the packet reception with either demodulator 1 or demodulator 2
RCV2: Packet reception is completed normally with demodulator 2.
RCV1: Packet reception is completed normally with demodulator 1.
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BD57020MWV
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
* 1
* 1
RXSTT
0x02
BSY2
BSY1
-
-
RERR
CERR
RCV2
RCV1
0x00
*1 prohibited
(3) CLKDIV: Register for setting Clock frequency division
This register sets the fundamental period of the demodulator. This set the fundamental period (CLKDIV) with a count
level. The value of CLKDIV must be set so that Target Clock becomes 16kHz (62.5µsec). CLKDIV is determined by the
following formula:
SourceClock
CLKDIV int
1
TargetClock 2
Where “int” means rounding down to the nearest whole number.
For example, if Source Clock is 32MHz, CLKDIV set to the following value:
32000
CLKDIV int
1 999 0x03E7
162
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
CLK
0x0C
CLK
DIV6
CLK
CLK
DIV5
CLK
CLK
DIV4
CLK
CLK
DIV3
CLK
CLK
DIV2
CLK
CLK
DIV1
CLK
DIV9
CLK
DIV0
CLK
DIV8
CLKDIV1L
CLKDIV1H
0xE7
0x03
R/W
R/W
DIV7
CLK
0x0D
DIV15
DIV14
DIV13
DIV12
DIV11
DIV10
(4) FLTPRD: Register for setting filter fundamental period
This register appoints the fundamental period of the digital filter. This set the fundamental period (FLTPRD) with a count
level. The value of CLKDIV must be set so that Target Clock becomes 2kHz (500µsec). FLTPRD is determined by the
following formula:
SourceClock
TargetClock
FLTPRD round
1
Where “round” means rounding off to the nearest whole number.
For example, when Source Clock is 32MHz, CLKDIV is set to the following value:
32000
2
FLTPRD round
115999 0x3E7F
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
FLT
PRD7
FLT
FLT
PRD6
FLT
FLT
PRD5
FLT
FLT
PRD4
FLT
FLT
PRD3
FLT
FLT
PRD2
FLT
FLT
PRD1
FLT
FLT
PRD0
FLT
FLTPRDL
FLTPRDH
0xA0
0xA1
0x00
0x00
R/W
R/W
PRD15
PRD14
PRD13
PRD12
PRD11
PRD10
PRD9
PRD8
(5) RXSTT_1: Packet reception status register 1
This register shows the packet reception status of demodulator 1.
・[7]
・[6]
・[5]
・[4]
・[3]
・[2]
・[1]
・[0]
PRE1: In searching the preamble of the packet with demodulator 1
BSY1: In receiving a packet with demodulator 1
RDN1:Packet reception is completed with demodulator 1
ERF1:Framing error occurs during the packet reception with demodulator 1
ERP1:Parity error occurs during the packet reception with demodulator 1
ERC1:Check sum error occurs during the packet reception with demodulator 1
RCV2:Packet reception is completed with demodulator 2 normally
RCV1:Packet reception is completed with demodulator 1 normally
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
RXSTT_1
0x52
PRE1
BSY1
RDN1
ERF1
ERP1
ERC1
RCV2
RCV1
0x00
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BD57020MWV
(6) RXSTT_2: Packet reception status register 2
This register shows the packet reception status of demodulator 2.
・[7]
・[6]
・[5]
・[4]
・[3]
・[2]
・[1]
・[0]
PRE2: In searching the preamble of the packet with demodulator 2
BSY2: In receiving a packet with demodulator 2
RDN2:Packet reception is completed with demodulator 2
ERF2:Framing error occurs during the packet reception with demodulator 2
ERP2:Parity error occurs during the packet reception with demodulator 2
ERC2:Check sum error occurs during the packet reception with demodulator 2
RCV1:Packet reception is completed with demodulator 1 normally
RCV2:Packet reception is completed with demodulator 2 normally
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
RXSTT_2
0x53
PRE2
BSY2
RDN2
ERF2
ERP2
ERC2
RCV1
RCV2
0x00
(7) RXCNT_X: Reports the Rx byte counter
This register reports the total number of bytes received from demodulator 1 or 2.
・[7:5]
・[4]
・[3]
・[2]
・[1]
・[0]
Reserved
RXxCNT4 (x: 0, 1)
RXxCNT3 (x: 0, 1)
RXxCNT2 (x: 0, 1)
RXxCNT1 (x: 0, 1)
RXxCNT0 (x: 0, 1)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
RX1
CNT4
RX2
RX1
CNT3
RX2
RX1
CNT2
RX2
RX1
CNT1
RX2
RX1
CNT0
RX2
*1
*1
*1
RXCNT_1
0x50
0x51
-
-
-
0x00
0x00
R
R
*1
*1
*1
RXCNT_2
-
-
-
CNT4
CNT3
CNT2
CNT1
CNT0
*1 prohibited
(8) RXDAT_1: Packet data register 1
This enables to show the data of the packet that is received with demodulator 1. Size of the buffers receiving Qi packet
is 32 bytes. The longest packet prescribed in Qi is 29 bytes (including a header and the check sum byte). So
BD57020MWV receive the packet of all kinds. The buffer to receive Qi packet is one to be 32 bytes, and the packet that
is received is stored by the top of the buffer memory and is overwritten when BD57020MWV receive the next packet.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
0x60
:
RXDAT_1
Last 32 Bytes received by Demodulator 1
0x00
0x7F
(9) RXDAT_2: Packet data register 2
This enables to show the data of the packet that is received with demodulator 2. Size of the buffers receiving Qi packet
is 32 bytes. The buffer to receive Qi packet is one to be 32 bytes, and the packet that is received is stored by the top of
the buffer memory and is overwritten when BD57020MWV receive the next packet.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
0x80
:
RXDAT_2
Last 32 Bytes received by Demodulator 2
0x00
0x9F
7. About the input power detection
During wireless power transmission, when a foreign object such as a piece of metal exists on the charge interface between
Tx and Rx, it generates heat, which poses a risk to cause burns and may even damage the Rx. BD57020MWV monitors
the input power to the Tx and finds transmission electricity and detects the existence of the foreign object by comparing the
transmission electricity with the received power electricity information (Received Power Packet) from Rx. BD57020MWV
calculates the input power by monitoring the input voltage and the input current of the Tx.
About the input voltage (ADPV terminal voltage) detection, BD57020MWV can output the voltage of ADPV terminal voltage
×0.1 from MONI1 terminal by the following register setting. In addition, it uses an external current detection amplifier about
the input current detection. From them, the transmission electricity is calculated.
(1) AINSEL: Analog input choice register
By this register, MONI1 terminal outputs the voltage of ADPV terminal voltage ×0.1.
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BD57020MWV
・[7:2]
・[1]
Reserved
AIN1SEL1
(0x1： ADPV terminal voltage)
Reserved
・[0]
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
AIN1
SEL1
* 1
* 1
* 1
* 1
* 1
* 1
*1
AINSEL
0x08
-
-
-
-
-
-
-
0x00
*1 prohibited
8. Low Drop OUT (LDO) block
BD57020MWV is equipped with two LDO blocks. On LDO33A terminal, it is assumed that the power supply of the
microcomputer is connected. Capacitors (0.47 ~ 2.0µF) are necessary between the LDO terminals (LDO33A and LDO33B)
and GND. Please place the capacitors as close to LDO33A and LDO33B terminals as possible.
9. About a general-purpose terminal (GPIO)
BD57020MWV has four GPIO terminals as a general-purpose terminal. The following registers are used to configure the
GPIO terminals.
(1) GPDIR: Input and output direction setting register of the GPIO port
This register sets each GPIO port as an input terminal or output terminal. If set to 1, the port becomes an output
terminal. On the other hand, if set to 0, the port becomes an input terminal.
・[7:4]
・[3:0]
Reserved
PDX (X: 0- 3)
(0x1: Enable output on GPIOX
0x0：Enable input on GPIOX)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
* 1
* 1
* 1
* 1
GPDIR
0x42
-
-
-
-
PD3
PD2
PD1
PD0
0x00
*1 prohibited
(2) GPIN: Input state confirmation register of the GPIO terminal
This register defines the state of the GPIO port. Only the bit set as an input port in the input and output direction
setting registers of the GPIO port is enabled. When H is input into the port, the corresponded register becomes 1.
When L was input into the port, the corresponded register becomes 0.
・[7:4]
Reserved
・[3:0]
PIX (X: 0- 3)
(0x1: High input on GPIOX
0x0：Low input on GPIOX)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
* 1
* 1
* 1
* 1
GPIN
0x40
-
-
-
-
PI3
PI2
PI1
PI0
-
*1 prohibited
(3) GPOUT: Output setting register of the GPIO terminal
This register sets an output level to the GPIO port. Only the bit set as an output port in the input and output direction
setting registers of the GPIO port is enabled. When the register is 1, the corresponded port outputs H. When the
register is 0, the corresponded port outputs L.
・[7:4]
Reserved
・[3:0]
POX (X: 0- 3)
(0x1: High output on GPIOX
0x0：Low output on GPIOX)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
* 1
* 1
* 1
* 1
GPOUT
0x41
-
-
-
-
PO3
PO2
PO1
PO0
0x00
*1 prohibited
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BD57020MWV
(4) GPPU: The pull-up resistance of GPIO port setting register
This register sets the pull-up resistance of each GPIO port. If set to 1, the resistance connected to VDD power supply is
enabled. If set to 0, it is disabled.
・[7:4]
・[3:0]
Reserved
PPUX (X: 0- 3)
(0x1: Enable pull-up resistor on GPIOX
0x0：Disable)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
PPU3
b2
b1
b0
R/W
R/W
* 1
* 1
* 1
* 1
GPPU
0x43
-
-
-
-
PPU2
PPU1
PPU0
0x00
*1 prohibited
(5) GPPD: The pull-down resistance of GPIO port setting register
This register sets the pull-down resistance of each GPIO port. If set to 1, the resistance connected to GND is enabled. If
set to 0, it is disabled. The initial value of this register is 0x0F, and the pull-down resistance is enabled.
・[7:4]
・[3:0]
Reserved
PPDX (X: 0- 3)
(0x1: Enable pull-down resistor on GPIOX
0x0：Disable)
Initial
Value
Address
Name
b7
b6
b5
b4
b3
PPD3
b2
b1
b0
R/W
R/W
* 1
* 1
* 1
* 1
GPPD
0x44
-
-
-
-
PPD2
PPD1
PPD0
0x0F
*1 prohibited
10. Reporting the identify
BD57020MWV has a register to report its identify and version. These are read only.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
IDENT
0x00
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
0x21
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BD57020MWV
11. Protective circuit
BD57020MWV has the following functions as a protection feature.
Protection
name
Detection
terminal
Detection condition
VIN > 6.4V
Release condition
VIN <6.2V
Protection type
System disabled
OVLO_VIN
UVLO_VIN
VIN
VIN
VIN
VIN <3.4V
VIN > 3.6V
System disabled
System disabled
ICC <IOCP =
0.48A
Internal OCP
ICC > IOCP = 0.48A
ADPV - ADPI
<160mV
And
ADPV
ADPI
ADPV - ADPI > VOCP
= 160mV
Pre-driver block stop
The LSIDE = HSIDE = L output
External OCP
Register (Note 1
)
0xB1 = 0x08 *
Pre-driver block stop (Note 2
LSIDE = H, HSIDE = L
)
UVLO_ADPV
UVLO_VDD
ADPV
VDD
VIN <4.3V
VDD <2.5V
VDDIO <2.5V
VIN > 4.5V
Power-on reset cancellation
RESETB = L
VDD > 2.8V
UVLO_VDDIO
VDDIO
VDDIO > 2.8V
IO block Disable
(Note1) It is necessary to reset it from a register to cancel external overcurrent protection. It can reset external overcurrent protection by writing in 0x08 at
address 0xB1. However, please set 0 by all means because this register does not automatically return to 0 after setting it to 0x08.
(Note2) BD57020MWV can mask the pre-driver block stop even if it detects UVLO_ADPV depending on the register setting.
(1) ANA_STAT: Status register for internal blocks
This register reports the status for internal blocks.
・[7:5]
・[4]
Reserved
TCX_READY
(0x1: Fault detected
OCP
(0x1: Fault detected
TSD
(0x1: Fault detected
UVLO42
(0x1: Fault detected
OVLO_VIN
0x0：No fault)
0x0：No fault)
0x0：No fault)
0x0：No fault)
0x0：No fault)
・[3]
・[2]
・[1]
・[0]
(0x1: Fault detected
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R
TCX_RE
ADY
*1
*1
*1
ANA_STAT
0xB0
-
-
-
OCP
TSD
UVLO
OVLO
0x00
*1 prohibited
(2) ANA_ERR_CRL: OCP error configure register
This register configures the reset for OCP. If OCP_ERCL is set to 1, the OCP error is cleared. However, please set 0 by
all means because this bit does not automatically return to 0 after setting it to 1.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
ANN_ERR_
CRL
OCP
ERCL
*1
*1
*1
*1
*1
*1
*1
0xB1
-
-
-
-
-
-
-
0x00
*1 prohibited
(3) ERR_MODE: Error mode setting register in UVLO_ADPV
This register configures the error mode in UVLO_ADPV. If ERR_SEL = 1, the pre-driver block works regardless of
UVLO_ADPV. If ERR_SEL = 0, the pre-driver block stops if it detects UVLO_ADPV.
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
ERR_
SEL
* 1
* 1
* 1
* 1
* 1
* 1
* 1
ERR_MODE
0xC4
-
-
-
-
-
-
-
0x00
*prohibited
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BD57020MWV
About External OCP movement
BD57020MWV monitors the input current to the Tx. If there is an excessive flow of electric current, it will stop the operation
of the pre-driver block. Then, LSIDE1 (LSIDE2) terminal and the
HSIDE1 (HSIDE2) terminal become the L output.
The relation of current limit ILIM and the current sense resistor RS, is
determined by the following formula:
Adapter
Voltage
RS
V
ILIM
OCP [A]
RS
ADPV
ADPI
Where VOCP is the OCP detecting voltage.
For example, ILIM becomes 1.6A if RS=100mΩ and VOCP=160mV (typ).
The value of RS is between 30 ~ 47mΩ when Adapter Voltage is 5V. And
the value of RS is between 30 ~ 100mΩ when Adapter Voltage is 12V or
19V. Please be careful enough on the occasion of the value setting with
the set.
Figure 5. The input current detection
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BD57020MWV
12. Command interface
12-1.Command Interface
I2C bus method is used in command interface with host CPU on BD57020MWV.
In BD57020MWV, not only writing but read-out is possible except for some registers.
Besides the slave address in BD57020MWV, one byte select address can be Specified, written and readout.
The format of I2C bus slave mode is shown below.
The slave address of BD57020MWV is 0x44 (7Bit) while ADDR terminal input is L. It is 0x45 (7Bit) while ADDR terminal
input is H.
MSB
Slave Address
LSB
MSB
LSB
MSB
A
LSB
S
A
Select Address
Data
A
P
S:
Start condition
Slave Address: Putting up the bit of read mode (H") or write mode (L") after slave address (7bit) set with ADDR, the data
of eight bits in total will be sent. (MSB first)
A:
The acknowledge bit in each byte adds into the data when acknowledge is sent and received. When data
is correctly sent and received, "L" will be sent and received. There was no acknowledging for "H".
1 byte select address is used in BD57020MWV. (MSB first)
Select Address:
Data:
P:
Data byte, data (the MSB first) sent and received
Stop Condition
MSB
6
5
LSB
SDA
SCL
Start Condition
Stop Condition
When SDA↓, SCL=”H”
When SDA↑, SCL=”H”
Figure 6. Command Interface
SDA
SCL
S
Sr
Repeated Start
Condition
Start Condition
Figure 7. Repeated Start Condition
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BD57020MWV
12-2.Data Format
Write format
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
A
C
K
A
C
K
A
C
K
S
P
Slave Address
(7bit)
R
/W
Select Address
(8bit)
Write Data
(8bit)
Acknowledge from
slave device
Acknowledge from
slave device
Acknowledge from
slave device
Start Condition
'0' Write
Stop Condition
Figure 8. Write Data Format
Read format
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
A
C
K
A
C
K
N
A
K
S
P
Slave Address
(7bit)
R
/W
Read Data
(8bit)
Read Data
(8bit)
Acknowledge from
slave device
Acknowledge from
master device
Non acknowledge
from master device
Start Condition
'1' Read
Stop Condition
Figure 9. Read Data Format
Read Data from specified Select Address
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Read Data
A
C
K
A
C
K
A
C
K
N
A
C
S
Sr
P
Slave Address
(7bit)
R
/W
Select Address
(8bit)
Slave Address
(7bit)
R
/W
Read Data from Select Address
'0' Write
Repeated Start Condition
'1' Read
Figure 10. Read Data from specified Select Address (1)
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Read Data
A
C
K
A
C
K
A
C
K
N
A
C
S
P
S
P
Slave Address
(7bit)
R
/W
Select Address
(8bit)
Slave Address
(7bit)
R
/W
Read Data from Select Address
'0' Read
'1' Read
Figure 11. Read Data from specified Select Address (2)
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BD57020MWV
12-3.Control signal specifications
○Bus line, I/O stage electrical specification and timing
S D A
tB U F
tF
tH D S T A
tR
tL O W
S C L
tH D S T A
tH D D A T
tH IG H
tS U D A T
tS U S T A
tS U S T O
P
S
S r
P
Figure 12. Timing chart
Table 12-1. SDAI and SCLI bus-line characteristic (Unless specified, Ta = 25 degrees Celsius, VDD=3.3V)
Draft mode
Parameter
Sign
fSCL
tBUF
Unit
kHz
μs
Min.
0
Max.
400
1
2
SCL clock frequency
Bus free time between a "stop" condition and "start"
conditions
1.3
－
It is a "start" condition (retransmission) in hold time.
After this period,
3
tHDSTA
0.6
－
μs
The first clock pulse is generated.
LOW state hold time of the SCL clock
HIGH state hold time of the SCL clock
Setup time of the retransmission "start" condition
Data hold time
4
5
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
1.3
0.6
－
－
μs
μs
μs
μs
ns
ns
ns
μs
pF
6
0.6
0 Note1)
－
7
－
8
Data setup time
100
－
9
Rise time of SDA and the SCL traffic light
Fall time for SDA and SCL signaling
Setup time of the "stop" condition
Capacitive load of each bus line
20+0.1Cb
20+0.1Cb
0.6
300
300
－
10
11
12
tF
tSUSTO
Cb
－
400
The above-mentioned numerical values are all the values corresponding to VIH min and VIL max level.
Note1) To exceed an undefined area on falling edged of SCLI, transmission device should internally offer the hold-time of 300ns or more for SDAI signal
(VIH min of SCLI signal).
The above-mentioned characteristic is a theory value in IC design and it doesn't be guaranteed by shipment inspection.
When problem occurs by any chance, we talk in good faith and correspond.
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BD57020MWV
12-4.List of registers
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
IDENT
0x00
0x01
0x02
0x03
0x04
0x05
:
DID7
CTRL
BSY2
DID6
-
BSY1
APINT
APIEN
DID5
FTE2
DID4
FTE1
-
AGINT
AGIEN
DID3
-
RERR
RINT
RIEN
DID2
-
CERR
CINT
CIEN
DID1
PRE2
RCV2
RINT2
RIEN2
DID0
PRE1
RCV1
RINT1
RIEN1
0x21
0x00
0x00
0x00
0x00
R
R/W
R
R/W
R/W
* 1
* 1
* 1
RXCTRL
RXSTT
INTSTT
INTENB
* 1
* 1
-
* 1
* 1
-
-
* 1
PXIEN
-
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
AINSEL
-
-
-
-
-
-
-
-
-
0x00
-
-
0x07
AIN1
SEL1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
0x08
-
-
-
-
-
-
-
R/W
0x09
:
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
0x0B
CLK
DIV7
CLK
CLK
DIV6
CLK
CLK
DIV5
CLK
CLK
DIV4
CLK
CLK
DIV3
CLK
CLK
DIV2
CLK
CLK
DIV1
CLK
DIV9
CLK
DIV0
CLK
DIV8
CLKDIV1L
CLKDIV1H
0x0C
0x0D
0xE7
0x03
R/W
R/W
DIV15
DIV14
DIV13
DIV12
DIV11
DIV10
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
PWRCTRL
0x0E
0x0F
0x10
:
-
-
-
-
-
-
-
-
-
-
* 1
* 1
* 1
-
-
PWMD1
PWMD0
-
OSCSEL
TCXEN
TCXSEL
0x07
R/W
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
PDCTRL0
Reserved
-
-
-
-
-
-
-
-
-
0x00
-
-
0x11
PWM1
EN
* 1
* 1
* 1
* 1
0x12
-
-
-
-
PS256
PSWEN
PDEN
R/W
0x13
:
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
-
-
-
-
-
-
-
-
-
0x15
0x16
0x17
* 1
* 1
* 1
* 1
* 1
APGCTRL
APGSTT
APEN
-
-
-
-
-
-
APEX1
-
APEX0
-
0x00
0x00
R/W
R/W
* 1
* 1
* 1
* 1
* 1
APSTA2
APSTA1
APSTA0
-
-
APG
ITV7
APG
ITV15
APG
APG
ITV6
APG
ITV14
APG
DUR6
APG
ITV5
APG
ITV13
APG
DUR5
APG
ITV4
APG
ITV12
APG
DUR4
APG
ITV3
APG
ITV11
APG
DUR3
APG
DUR11
APG
ITV2
APG
ITV10
APG
DUR2
APG
DUR9
APG
ITV1
APG
ITV9
APG
APG
ITV0
APG
ITV8
APG
APGITVL
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
APGITVH
APGDURL
APGDURH
APGMSRL
APGMSRH
DUR7
DUR1
APG
DUR0
APG
* 1
* 1
* 1
* 1
-
-
-
-
DUR8
APG
MSR1
APGMS
R9
DUR7
APG
MSR0
APGMS
R8
APG
MSR7
APGMS
R15
APG
MSR6
APGMS
R14
APG
MSR5
APGMS
R13
APG
MSR4
APGMS
R12
APG
APG
MSR3
APGMS
R11
MSR2
APGMS
R10
APG
APG
APG
APG
APG
APG
APG
APG
APGCNT
0x1E
0x1F
0x20
0x00
-
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
PWM0
PRD7
PWM0
PRD15
PWM0
DTY7
PWM0
DTY15
PWM1
PHS7
PWM1
PHS15
PWMX
PRD7
PWMX
PRD15
PWMX
DTY7
PWMX
DTY15
PWM0
PRD6
PWM0
PRD14
PWM0
DTY6
PWM0
DTY14
PWM1
PHS6
PWM1
PHS14
PWMX
PRD6
PWMX
PRD14
PWMX
DTY6
PWMX
DTY14
PWM0
PRD5
PWM0
PRD13
PWM0
DTY5
PWM0
DTY13
PWM1
PHS5
PWM1
PHS13
PWMX
PRD5
PWMX
PRD13
PWMX
DTY5
PWMX
DTY13
PWM0
PRD4
PWM0
PRD12
PWM0
DTY4
PWM0
DTY12
PWM1
PHS4
PWM1
PHS12
PWMX
PRD4
PWMX
PRD12
PWMX
DTY4
PWMX
DTY12
PWM0
PRD3
PWM0
PRD11
PWM0
DTY3
PWM0
DTY11
PWM1
PHS3
PWM1
PHS11
PWMX
PRD3
PWMX
PRD11
PWMX
DTY3
PWMX
DTY11
PWM0
PRD2
PWM0
PRD10
PWM0
DTY2
PWM0
DTY10
PWM1
PHS2
PWM1
PHS10
PWMX
PRD2
PWMX
PRD10
PWMX
DTY2
PWMX
DTY10
PWM0
PRD1
PWM0
PRD9
PWM0
DTY1
PWM0
PRD0
PWM0
PRD8
PWM0
DTY0
PWM0PRDL
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM0PRDH
PWM0DTYL
PWM0DTYH
PWM1PHSL
PWM1PHSH
PWMXPRDL
PWMXPRDH
PWMXDTYL
PWMXDTYH
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PWM0
DTY9
PWM0
DTY8
PWM1
PHS1
PWM1
PHS9
PWMX
PRD1
PWMX
PRD9
PWMX
DTY1
PWM1
PHS0
PWM1
PHS8
PWMX
PRD0
PWMX
PRD8
PWMX
DTY0
PWMX
DTY9
PWMX
DTY8
0x2A
:
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
-
0x2F
P0DLY
D1
P0DLY
D0
P0DLY
C2
P0DLY
C1
P0DLY
C0
P0DLY
B2
P0DLY
B1
P0DLY
B0
PWMGEN0
*1 prohibited
0x30
0x92
R/W
*0x in the head of for each character means a hex digit.
If there is nothing, it means decimal numeral
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TSZ22111 • 15 • 001
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BD57020MWV
Initial
Value
Address
Name
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
P1DLY
D1
P1DLY
D0
P1DLY
C2
P1DLY
C1
P1DLY
C0
P1DLY
B2
P1DLY
B1
P1DLY
B0
PWMGEN1
0x31
0x92
0x32
:
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
-
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
:
* 1
* 1
* 1
* 1
GPIN
-
-
-
-
PI3
PO3
PD3
PPU3
PPD3
PI2
PO2
PD2
PPU2
PPD2
PI1
PO1
PD1
PPU1
PPD1
PI0
PO0
PD0
PPU0
PPD0
-
R
* 1
* 1
* 1
* 1
GPOUT
GPDIR
GPPU
GPPD
-
-
-
-
0x00
0x00
0x00
0xFF
R/W
R/W
R/W
R/W
* 1
* 1
* 1
* 1
-
-
-
-
* 1
* 1
* 1
* 1
-
-
-
-
* 1
* 1
* 1
* 1
-
-
-
-
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
-
0x4F
RX1
CNT4
RX2
CNT4
ERF1
ERF2
RX1
CNT3
RX2
CNT3
ERP1
ERP2
RX1
CNT2
RX2
CNT2
ERC1
ERC2
RX1
CNT1
RX2
CNT1
RCV2
RCV2
RX1
CNT0
RX2
CNT0
RCV1
RCV1
* 1
* 1
* 1
RXCNT_1
RXCNT_2
0x50
0x51
-
-
-
0x00
0x00
R/W
R/W
* 1
* 1
* 1
-
-
-
RXSTT_1
RXSTT_2
0x52
0x53
0x54
:
0x5F
0x60
:
0x7F
0x80
:
PRE1
PRE2
BSY1
BSY2
RDN1
RDN2
0x00
0x00
R
R
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
RXDAT_1
RXDAT_2
-
-
-
-
-
-
-
-
-
-
Last 32 Bytes received by Demodulator 1
Last 32 Bytes received by Demodulator 2
0x00
0x00
R
R
0x9F
FLT
PRD7
FLT
FLT
PRD6
FLT
FLT
PRD5
FLT
FLT
PRD4
FLT
FLT
PRD3
FLT
FLT
PRD2
FLT
FLT
PRD1
FLT
FLT
PRD0
FLT
FLTPRDL
FLTPRDH
0xA0
0xA1
0x00
0x00
R/W
R/W
PRD15
PRD14
PRD13
PRD12
PRD11
PRD10
PRD9
PRD8
0xA2
:
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
-
0xAF
TCX_RE
ADY
* 1
* 1
* 1
ANA_STAT
0xB0
0xB1
-
-
-
OCP
TSD
UVLO
OVLO
0x02
0x00
R
ANA_ERR_
CLR
OCP
ERCL
* 1
* 1
* 1
* 1
* 1
* 1
* 1
-
-
-
-
-
-
-
R/W
0xB2
:
0xC3
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
0x00
-
-
ERR_
SEL
* 1
* 1
* 1
* 1
* 1
* 1
* 1
ERR_MODE
0xC4
-
-
-
-
-
-
-
R/W
0xC5
:
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Reserved
-
-
-
-
-
-
-
-
-
0xFF
*1 prohibited
*0x in the head of for each character means a hex digit.
If there is nothing, it means decimal numeral
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© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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BD57020MWV
Typical Performance Curves
2.40
2.20
2.00
1.80
1.60
1.40
16.0
15.0
14.0
13.0
12.0
-20
0
20
40
60
80
-20
0
20
Temp [℃]
40
60
80
Temp [℃]
Figure 13. ICC1 [mA] vs. Temp. [°C]
(TCXOIN CLK = 0kHz)
Figure 14. ICC2 [mA] vs. Temp. [°C]
(TCXOIN CLK = 32MHZ)
3.60
3.50
3.40
3.30
3.20
3.10
3.00
3.60
3.50
3.40
3.30
3.20
3.10
3.00
-20
0
20
40
60
80
0
10
20
30
40
Temp. [℃]
Output Current [mA]
Figure 15. Output Voltage VLDO33A [V] vs. Temp. [°C]
(Output Current = 0mA)
Figure 16. Output Voltage VLDO33A [V] vs
Output current [mA]
(Temp. = 25°C)
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TSZ22111 • 15 • 001
BD57020MWV
Typical Performance Curves - continued
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
0.0
2.0
4.0
6.0
8.0
10.0
0.0
1.0
2.0
3.0
4.0
5.0
RxOutput Power [W]
RxOutput Power [W]
Figure 17-2. System Efficiency [%] vs Rx Output Power [W]
(Rx=BD57015GWL,Vout=10V)
Figure 17-1. System Efficiency [%] vs Rx Output Power [W]
(Rx=BD57011GWL,Vout=5V)
Timing Chart
19V
ADPV
5V
VIN
3.3V
LDO33A
3.3V
LDO33B
TCXOEN
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
LSIDE1
Analog Ping
100 usec
Digital Ping
70msec
Min = 1msec
Figure 18. Start up sequence
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TSZ22111 • 15 • 001
BD57020MWV
Application Example
1) Recommended Circuit Diagram
RVIN2
U4
INA199A1
RVIN3
RTVIN
DTVIN
RVIN1
RSOUT
1
2
3
6
5
REF
GND
V+
OUT
MONI0_PA0
3.3V
CSOUT
RSIN-
PGND
CSIN
IN-
IN+
M9
PGND
4
RSIN+
CPA2
PGND
PGND PGND
RS1
GND
COM-CH
CADP3
CADP4
RPPH
M1
VADPV
RS2
GNDADPV
CADP1
CADP2
RPPG
GND PGND
CS1
5V
M2
CVIN1
RPPEN
CS2
CS3
GND
LTX1
LED4
CDC1 CDC2
RDCH
GND
GND
RLED4
M8
DCHCTRL
RGPU
M6
GND
GND
GND
M7
RTVQ RVQ1
RVQ2
GND
CBOOT1
RGPD
GND
RH1
MOS_H1
RH2
RHD2
MOS_H2
M3
HSIDE2
LSIDE2
3.3VB
GND
GND
RHD1
3.3V
DVQ
RQPD
1
30
29
28
27
26
25
RQIN1
RQIN2
LTX2
OVPIN
SW1
CV33B
CV33A
RL1
RLD1
RL2
2
3
MOS_L1
LDO33B
LDO33A
VDD
HSIDE1
LSIDE1
PGND
GND
GND
MOS_L2
M5
RLD2
GND
4
5
CCOILV
U1
BD57020MWV
3.3V
5V
TCXOEN
LSIDE2
HSIDE2
LSIDE2
HSIDE2
CQOUT1
CQOUT2
PGND
U3
BU7241G
6
RQOUT1
TCXOIN
TCXOOUT
GPIO0
3.3V
RREFH
7
24
23
22
21
1
5
4
GND GND
TCXOIN
SW2
BOOT2
TEST
IN+
VDD
OUT
CBOOT2
8
RVDH
CPA
GND
RQOUT2
TG_GPIO0
TG_GPIO1
RCLMP
CCLMP
RREFL1
2
3
RTCXOUT
OSC
VSS
IN-
9
GPIO1
GND
GND
10
GND
RREFL2
GND
ROSC
TG_GPIO2
GPIO2
COIL_IN
RVDL
PGND
* Thermal Pad is connected to the GND.
3.3V
COSC1
COSC2
RVDL2
M4
GND
GND
GND
GND
TG_GPIO3
M10
RCOILIN_CPO
RSCL
GND
RSDA
PGND
CSCL
CSDA
JP5
JP6
GND
3.3VB
LED3
PGND
GND
RLED3
CAIN0
GND
1
2
3
4
24
PB7
TEST
PD1
PB0
C2
C8
23
22
21
20
19
18
17
PC7
VDD
U2
ML610Q772
NC4
VSS
NC20
PB6
PB5
PB4
5
6
RX-D
PB1
PB2
PB3
PA2
3.3VB
GND
R8
RCOILIN_GPO
7
8
RESET_N
TEST
GND
PWRPATH_EN_GPO
LED2
LED1
VPP
For Debugger
RLED2
RLED1
GND
MONI1-PA1
CAIN1
C4
GND
Changing the software may cause the changing the circuit diagram.
Figure 19. Typical application circuit diagram
2) Parts list
Parts Name
Recommended Value
24
Unit
µH
Recommended Part
760 308 110
Maker
Würth
Number
1
Tx Coil
LTX
IC
U1
-
-
-
-
-
BD57020MWV
ML610Q772
BU7241G
ROHM
LAPIS
ROHM
TI
1
1
1
1
1
U2
-
U3
U4
-
-
INA199A1
OSC
32
MHz NX3225GA
NDK
FET/Tr
MOS_H2, MOS_L2
MOS_H1, MOS_L1, M7
M1
10
10
-7
A
A
A
A
A
RQ3E100GN
RQ3E100GN
RQ1E070RP
RUE002N02
RUR020N02
ROHM
ROHM
ROHM
ROHM
ROHM
2
3
1
5
3
M2, M4, M6, M8, M10
M3, M5, M9
Diode/LED
0.2
2
DVQ
6.8
V
V
-
EDZTE616.8B
EDZTE616.2B
SML-P11MT
ROHM
ROHM
ROHM
1
1
4
DTVIN
6.2
LED1, LED2, LED3, LED4
VF<2.0V
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TSZ22111 • 15 • 001
BD57020MWV
Parts Name
Coil/Trans
COM_CH
Capacitor
CADP1
Recommended Value
-
Unit Recommended Part
Maker
-
Number
SHORT
ohm
-
0.1
10
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
pF
F
-
-
-
-
MURATA
MURATA
MURATA
MURATA
1
1
1
CADP2
CADP3
10
22
CADP4
1
1
0.033
0.033
0.033
1
CS1
CS2
GRM32D7U2E333JW31 MURATA
GRM32D7U2E333JW31 MURATA
GRM32D7U2E333JW31 MURATA
1
CS3
1
CVIN1
-
-
-
-
-
-
-
-
-
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
-
1
1
0.22
10
1
CBOOT1, CBOOT2
CDC1, CDC2
CV33B
2
1
1
1
CV33A
10
-
CSCL
1
OPEN
1
CSDA
CAIN0
0.1
0.01
1000
-
µF
µF
pF
F
MURATA
MURATA
CAIN1
1
1
CCOILV
CCLMP
GRM21A7U2E102JW31 MURATA
-
-
-
-
-
-
-
-
-
-
-
-
OPEN
0.01
0.01
0.1
-
CPA
µF
µF
µF
F
MURATA
MURATA
MURATA
-
1
CPA2
CSIN
1
1
CSOUT
CQOUT1
CQOUT2
COSC1, COSC2
C2
OPEN
47
µF
µF
F
MURATA
MURATA
-
1
1
1
-
1
OPEN
µF
pF
pF
MURATA
MURATA
MURATA
1
1
1
4700
2200
C4
C8
Resistor
RS1, RS2
RTCXOUT
RH1, RH2
RHD1, RHD2
RL1, RL2
RLD1, RLD2
RTVIN
100
1
20
mΩ
MΩ
Ω
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ROHM
ROHM
ROHM
ROHM
ROHM
-
2
1
2
2
MΩ
Ω
2
2
20
-
Ω
OPEN
100
680
1
kΩ
Ω
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
1
3
1
1
1
3
1
1
1
1
1
2
1
1
RVIN1, RVIN2, RVIN3
RDCH
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
Ω
1.5
3.3
1.5
3
RSCL
RSDA
RLED1, RLED2, RLED3
RLED4
RPPH
100
100
100
100
47
RPPEN
RPPG
RTVQ
RVQ1, RVQ2
RQPD
RGPD
100
100
kΩ
kΩ
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TSZ22111 • 15 • 001
BD57020MWV
Parts Name
RGPU
Recommended Value
Unit Recommended Part
Maker
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
-
Number
10
12
2
kΩ
Ω
-
1
RQIN1, RQIN2
RQOUT1
RQOUT2
RREFH
RREFL1
RREFL2
ROSC
-
2
kΩ
kΩ
kΩ
MΩ
kΩ
Ω
-
-
1
1
200
100
1
-
1
-
-
1
1
4.7
-
-
SHORT
33
6.2
6.2
-
RVDH
RVDL
kΩ
kΩ
kΩ
Ω
MCR10EZHF333
ROHM
ROHM
ROHM
-
ROHM
ROHM
ROHM
ROHM
1
1
-
-
-
-
-
-
-
RVDL2
RCLMP
RSIN-
1
OPEN
1
1
Ω
1
1
1
1
RSIN+
Ω
1
RSOUT
R8
kΩ
kΩ
36
3) Selection of Components Externally Connected
Component
Symbol
CBOOT1, CBOOT2
CV33A, CV33B
RL1, RL2
Limit
Unit
µF
µF
Ω
BOOT1 (2) terminal strapping
capacity
0.1 to 0.47
0.47 to 2.0
1.0 to 30
1.0 to 30
30 to 100
LDO33A (B) terminal
strapping capacity
L Side FET gate resistance
H Side FET gate resistance
Input current sense resistance
RH1, RH2
Ω
RS
mΩ
About the above operating condition, it is the value in the IC only. Please be careful enough on the occasion of the value setting with the set.
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BD57020MWV
Power Dissipation
(UQFN040V5050 Package)
Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in
actual operating conditions.
3.5
3.26W
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
AMBIENT TEMPERATURE : Ta [°C]
* 74.2mm x 74.2mm x 1.6mm Glass Epoxy Board
75
100
125
150
(front and back layer heat radiation copper foil 4.5 mm x 4.5 mm,
second and third layer heat radiation copper foil 74.2 mm x 74.2 mm)
Figure 20. Power Dissipation Curve (Pd-Ta Curve)
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BD57020MWV
I/O equivalent circuits
VIN, OVPOUT terminal
BOOT1, HSIDE1, SW1, LSIDE1, PGND terminal
(BOOT2, HSIDE2, SW2, LSIDE2)
OVPOUT
VIN
BOOT1 (2)
HSIDE1 (2)
SW1 (2)
OVPOUT
LSIDE1 (2)
PGND
OVPIN, LDO33A (LDO33B) terminal
VDD,TCXOIN, TCXOOUT terminal
VDD
VDD
VDD
OVPIN
TCXOIN
LDO33A(B)
VDD
TCXOOUT
TCXOEN terminal
VDDIO,
FSKIN (CLKSET, CLKIN, ADDR, TEST) terminal
VDD
VDDIO
VDDIO
TCXOEN
CLKIN
CLKSET
FSKIN
ADDR
TEST
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TSZ22111 • 15 • 001
BD57020MWV
GPIO0 (GPIO1, 2, 3) terminal
SCL terminal
SDA terminal
VDD
VDDIO
VDDIO
VDD
SDA
SCL
VDD
GPIO0
GPIO1
GPIO2
GPIO3
VDD
INTB terminal
MONI0 terminal
RESETB terminal
INTB
VDD
VDD
VDD
MONI0
RESETB
COIL_IN terminal
ADPV, ADPI terminal
ADPV
ADPI
COIL_IN
MONI1 terminal
MONI1
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BD57020MWV
Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6.
7.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8.
9.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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BD57020MWV
Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 21. Example of monolithic IC structure
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
14. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
15. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
16. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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TSZ22111 • 15 • 001
BD57020MWV
Ordering Information
B D 5 7 0 2 0 M W V -
E 2
Part Number
Package
Packaging and forming specification
MWV: UQFN040V5050 E2: Embossed tape and reel
Marking Diagrams
UQFN040V5050 (TOP VIEW)
Part Number Marking
D 5 7 0 2 0
LOT Number
1PIN MARK
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TSZ22111 • 15 • 001
BD57020MWV
Physical Dimension, Tape and Reel Information
Package Name
UQFN040V5050
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BD57020MWV
Revision History
Date
Revision
001
Changes
27.Jul.2015
New Release
P1 Figure2.
Deleted the line.
P2 Recommended Operating Conditions
VADPV Min = 4.8V
→VADPV Min = 4.6V
P5 Pin Description MONI1
Input voltage value and input current value output.
→Input voltage value
10.Aug.2015
002
P15 About the input power detection
Changed the paragraphs.
P25 Figure19.
Circuit diagram modified.
P25 to P27 Parts list
Parts list modified.
P1
Figure 1.
Modified the figure.
P3
Electrical Characteristics
Corrected the font of unit.
P7
1. Pre-driver block
Changed the sentence.
Corrected the font of unit.
P11
Corrected the font of unit.
P12 (5) APGMSR
Corrected the font of unit.
P13 (1) RXCTRL
Changed the sentence.
P14 (3) CLKDIV
Corrected the font of unit.
P14 (4) FLTPRD
Corrected the font of unit.
(4) APGDUR
25.Mar.2016
003
P17
About External OCP movement
Changed the sentence.
P24
Typical Performance Curves
Changed a name of the efficiency data.
Figure 17.
→ Figure 17-1.
Added to the efficiency data. Figure 17-2.
P25
Modified the circuit diagram.
P25 to P27 2) Parts list
Modified the parts list.
1) Recommended Circuit Diagram
P1
General Description / Features / Package
Change the sentence.
P7
(1) PWM0PRD, (2) PWM0DTY
Change the sentence.
P9
Added the explanation.
P9 3. FSK
Modified the sentence.
P9 (1) PWMXPRD
(6) PWRCTRL
Change the sentence.
P10 (2) PWMXDTY
Change the sentence.
P10 (3) PDCTRL
6.Feb.2017
004
Added the explanation.
P11 (2) APGSTT
Modified the sentence.
P11 (4) APGDUR
Change the sentence.
P12 (5) APGMSR
Change the sentence.
P12 5. Interrupt control
Modified the sentence
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BD57020MWV
Date
Revision
Changes
P12 (1) INTSTT
Change the sentence.
P13 (2) INTENB
Change the sentence.
P13 (1) RXCTRL, (2) RXSTT
Change the sentence.
Added the explanation..
P14 (3) CLKDIV, (4) FLTPRD, (5) RXSTT_1
Change the sentence.
P15 (6) RXSTT_2
Change the sentence.
P15 (7) RXCNT
Added the explanation.
P15 (8) RXDAT_1, (6) RXDAT_2
Change the sentence.
6.Feb.2017
004
P16, 17 (1) – (5)
Added the explanation.
P17
10. Reporting the Identify
Added the explanation
P17 (1)ANA_STAT, (2) ANA_ERR_CRL
Added the explanation.
P18
(1)ANA_STAT, (2) ANA_ERR_CRL
Added the explanation.
P19 About External OCP movement
Change the sentence
P23, 24 List of registers
Modified
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TSZ22111 • 15 • 001
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
Datasheet
Buy
BD57020MWV - Web Page
Distribution Inventory
Part Number
Package
Unit Quantity
BD57020MWV
UQFN040V5050
2500
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
2500
Taping
inquiry
Yes
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