BD5LL20AEFV-C (开发中) [ROHM]
BD5LL20AEFV-C is 5-channel SPI-input low side switch developed as engine control. It has built-in open load detection function, over current protection function, thermal shutdown function, and active clamp function. It also has a 5 V output LDO as a power supply for the microcontroller and a built-in K-LINE communication circuit, making it suitable for motorcycle engine control.;
| 型号： | BD5LL20AEFV-C (开发中) |
| 厂家： | 
ROHM |
| 描述： | BD5LL20AEFV-C is 5-channel SPI-input low side switch developed as engine control. It has built-in open load detection function, over current protection function, thermal shutdown function, and active clamp function. It also has a 5 V output LDO as a power supply for the microcontroller and a built-in K-LINE communication circuit, making it suitable for motorcycle engine control. |
| 文件： | 总48页 (文件大小：2165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Automotive IPD Series
5ch Low Side Switch with Built-in LDO
BD5LL20AEFV-C
General Description
Key Specifications
BD5LL20AEFV-C is 5-channel SPI-input low side switch
developed as engine control. It has built-in open load
detection function, over current protection function,
thermal shutdown function, and active clamp function. It
also has a 5 V output LDO as a power supply for the
microcontroller and a built-in K-LINE communication
circuit, making it suitable for motorcycle engine control.
◼ Power Supply Operating Range VX:
◼ Power Supply Operating Range VS:
◼ LDO Output Voltage:
◼ LDO Over Current Threshold Value: 250 mA (Min)
◼ On Resistance(Note 1)
200 mΩ / 540 mΩ (Typ)
◼ Over Current Threshold Value: 2.0 A / 0.5 A (Min)
◼ Active Clamp Energy(Note 1)
300 mJ / 250 mJ
6 V to 18 V
6 V to 8 V
5.0 V (Typ)
:
:
◼ Operating Temperature Range: -40 °C to +150 °C
(Note 1) (OUT1 ,OUT2, OUT3) / (OUT4, OUT5) value
Features
◼ AEC-Q100 Qualified(Note 1)
Package
W (Typ) x D (Typ) x H (Max)
6.5 mm x 6.4 mm x 1.0 mm
HTSSOP-B20
◼ Monolithic Power Management IC with Control Block
(CMOS) and a Power MOSFET mounted on a Single
Chip
◼ Each Channel Control/Error can be detected by 16 bit
SPI Commands
◼ Built-in Open Load Detection Function (OLD)
◼ Built-in Over Current Protection Function (OCP)
◼ Built-in Thermal Shutdown Function (TSD)
◼ Built-in Active Clamp Function
◼ Built-in 5 V Output LDO
◼ Built-in K-LINE Communication Circuit
◼ Surface-mount HTSSOP-B20 Packaging
(Note 1) Grade 1
HTSSOP-B20
Application
◼ Driving Resistive and Inductive Load
Typical Application Circuit
Battery
VS
VS
+
V5O
+
OUT1
IN1
CSB
SI
OUT2
OUT3
μ-con
SCLK
SO
OUT4
OUT5
KIO
RX
VX
TX
AGND PGND
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
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BD5LL20AEFV-C
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Application ......................................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Typical Application Circuit ...............................................................................................................................................................1
Contents .........................................................................................................................................................................................2
Pin Configuration ............................................................................................................................................................................3
Pin Descriptions..............................................................................................................................................................................3
Definition.........................................................................................................................................................................................4
Block Diagram ................................................................................................................................................................................4
Absolute Maximum Ratings ............................................................................................................................................................5
Thermal Resistance........................................................................................................................................................................6
Recommended Operating Conditions...........................................................................................................................................10
Electrical Characteristics...............................................................................................................................................................10
Typical Performance Curves.........................................................................................................................................................12
Measurement Circuits...................................................................................................................................................................23
Timing Chart .................................................................................................................................................................................27
K-LINE Timing Chart.....................................................................................................................................................................28
SPI Specification...........................................................................................................................................................................29
Register Map ................................................................................................................................................................................32
Protection Function.......................................................................................................................................................................33
Over Current Protection................................................................................................................................................................34
Thermal Shutdown........................................................................................................................................................................34
Open Load Detection (OLD) .........................................................................................................................................................35
Output Overhead Detection (OFD) ...............................................................................................................................................36
Application Example .....................................................................................................................................................................37
Selection of Components Externally Connected...........................................................................................................................37
I/O Equivalence Circuits................................................................................................................................................................38
Operational Notes.........................................................................................................................................................................40
Ordering Information.....................................................................................................................................................................43
Marking Diagram ..........................................................................................................................................................................43
Physical Dimension and Packing Information...............................................................................................................................44
Revision History............................................................................................................................................................................45
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BD5LL20AEFV-C
Pin Configuration
(TOP VIEW)
VS
IN1
PGND
OUT1
OUT1
OUT2
PGND
OUT3
OUT4
OUT5
VX
V5O
AGND
CSB
SCLK
SI
EXP-PAD
SO
RX
TX
KIO
Pin Descriptions
Pin No.
Pin Name
Function
1
2
VS
LDO power supply
OUT1 control input
Connected to GND via an internal pull-down resistor.
IN1
3
4
V5O
5 V output
AGND
Analog GND
SPI enable
5
6
7
CSB
SCLK
SI
Connected to V5O via an internal pull-up resistor.
Serial clock input
Connected to GND via an internal pull-down resistor.
Serial data input
Connected to GND via an internal pull-down resistor.
8
9
SO
RX
Serial data output
K-LINE output
K-LINE input
Connected to V5O via an internal pull-up resistor.
10
TX
11
12
13
14
15
16
17
18
19
20
-
KIO
VX
K-LINE bus connection
K-LINE power supply
ch5 output
OUT5
OUT4
OUT3
PGND
OUT2
OUT1
OUT1
PGND
EXP-PAD
ch4 output
ch3 output
Power GND
ch2 output
ch1 output
ch1 output
Power GND
The EXP-PAD is connected to GND.
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BD5LL20AEFV-C
Definition
IVS
IIN1
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
VS
OUT1
OUT2
OUT3
OUT4
OUT5
VS
VOUT1
IN1
V5O
CSB
SCLK
SI
VIN1
V5O
VCSB
VOUT2
VOUT3
VOUT4
VOUT5
IV5O
ICSB
ISCLK
ISI
VSCLK
VSI
ISO
SO
VSO
IKIO
RX
KIO
VX
VRX
VKIO
IVX
VX
TX
VTX
GND
Block Diagram
VS
V5O
TSD
OCP
LDO
OUT1
TSD
OCP
OLD
POR
IN1
For OUT1
x2
x2
OUT2
OUT3
TSD
OCP
OLD
CSB
SI
Control
Logic
SPI
SCLK
SO
OUT4
OUT5
TSD
OCP
RX
TX
VX
TSD
OCP
K-LINE
KIO
AGND
PGND
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Absolute Maximum Ratings (Tj = 25 °C)
Parameter
Symbol
Rating
Unit
VX Power Supply Voltage
VS Power Supply Voltage
Output Voltage OUT1, OUT2, OUT3, OUT4, OUT5
Output Current OUT1, OUT2, OUT3
Output Current OUT4, OUT5
Output Voltage SO
VX
VS
-0.3 to +30
-0.3 to +10
-0.3 to +30 (Internal Limit)(Note 1)
2.0 (Internal Limit)(Note 2)
0.5 (Internal Limit)(Note 2)
-0.3 to +7
V
V
VOUT1-5
IOUT123
IOUT45
V
A
A
VSO
V
Output Voltage RX
VRX
-0.3 to +7
V
Input Voltage CSB,SI,SCLK
Input Voltage IN1,TX
VCSB, VSCLK, VSI
VIN1, VTX
VKIO
-0.3 to +7
V
-0.3 to +7
V
Input Voltage KIO
-0.3 to +30
V
Maximum Junction Temperature
Storage Temperature Range
Tjmax
Tstg
150
°C
°C
-55 to +150
Active Clamp Energy (Single Pulse) OUT1, OUT2,
OUT3, Tj(START) = 25 °C, IOUT1(START) = 1.0 A
Active Clamp Energy (Single Pulse) OUT1, OUT2,
OUT3, Tj(START) = 150 °C, IOUT1(START) = 1.0 A
Active Clamp Energy (Single Pulse) OUT4, OUT5
Tj(START) = 25 °C, IOUT2(START) = 0.5 A
Active Clamp Energy (Single Pulse) OUT4, OUT5
Tj(START) = 150 °C, IOUT2(START) = 0.5 A
(Note 1) Limited by the active clamp function.
(Note 2) Limited by the over current protection function.
EAS123(25 °C)
EAS123(150 °C)
EAS45(25 °C)
EAS45(150 °C)
300
75
mJ
mJ
mJ
mJ
250
50
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Caution 3: When IC is turned off with an inductive load, reverse energy has to be dissipated in the IC. This energy can be calculated by the following equation:
1
푉퐵퐴푇
퐸퐿 = ꢀ퐼푂푈푇(푆푇퐴푅푇)ꢁ × ꢂ1 −
2
ꢃ
푉퐵퐴푇 − 푉푂푈푇(퐶퐿)
Where:
L is the inductance of the inductive load.
IOUT(START) is the output current at the time of turning off.
VOUT(CL) is the output clamp voltage.
The IC integrates the active clamp function to internally absorb the reverse energy EL which is generated when the inductive load is turned off.
When the active clamp operates, the thermal shutdown function does not work. Decide a load so that the reverse energy EL is active clamp
energy EAS123 (Figure 1.), EAS45 (Figure 2.) or under when inductive load is used.
10000
1000
100
10
10000
Tj = 25 °C
Tj = 25 °C
Tj = 150 °C
Tj = 150 °C
1000
100
10
1
1
0.0
0.5
1.0
1.5
2.0
2.5
0.3
0.4
0.5
0.6
0.7
0.8
Output Current(Start) :IOUT(START) [A]
Output Current(Start) :IOUT(START) [A]
Figure 1. Active Clamp Energy (Single Pulse) vs
Output Current(Start)
Figure 2. Active Clamp Energy (Single Pulse) vs
Output Current(Start)
(OUT1, OUT2, OUT3)
(OUT4, OUT5)
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Thermal Resistance (Note 1)
Parameter
Symbol
Typ
Unit
Condition
HTSSOP-B20
95.6
33.8
24.4
°C/W
°C/W
°C/W
1s(Note 2)
2s(Note 3)
2s2p(Note 4)
Between Junction and Surroundings Temperature
Thermal Resistance
θJA
(Note 1) The thermal impedance is based on JESD51-2A(Still-Air) standard.
(Note 2) JESD51-3 standard FR4 114.3 mm x 76.2 mm x 1.57 mm 1-layer (1s)
(Top copper foil: ROHM recommended Footprint + wiring to measure, 2 oz. copper.)
(Note 3) JESD51-5 standard FR4 114.3 mm x 76.2 mm x 1.60 mm 2-layers (2s).
(Top copper foil: ROHM recommended Footprint + wiring to measure/
Copper foil area on the reverse side of PCB: 74.2 mm x 74.2 mm, copper (top & reverse side) 2 oz.)
(Note 4) JESD51-5/-7 standard FR4 114.3 mm x 76.2 mm x 1.60 mm 4-layers (2s2p)
(Top copper foil: ROHM recommended Footprint + wiring to measure/
2 inner layers and copper foil area on the reverse side of PCB: 74.2 mm × 74.2 mm, copper (top & reverse side/inner layers) 2 oz./1 oz.)
■ PCB Layout 1 layer (1s)
100 mm2
Figure 3. PCB Layout 1 Layer (1s)
600 mm2
1200 mm2
Footprint
Dimension
Value
Board Finish Thickness
Board Dimension
1.57 mm ± 10 %
76.2 mm x 114.3 mm
FR4
Board Material
Copper Thickness (Top Layer)
Copper Foil Area Dimension
0.070 mm (Cu: 2 oz)
Footprint/100 mm2/600 mm2/1200 mm2
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BD5LL20AEFV-C
Thermal Resistance – continued
■ PCB Layout 2 layers (2s)
Top Layer
Bottom Layer
Top Layer
Bottom Layer
Via
Isolation Clearance Diameter: ≥ 0.6 mm
Cross Section
Figure 4. PCB-layout 2-layer (2s)
Dimension
Value
1.60 mm ± 10 %
76.2 mm x 114.3 mm
FR4
Board Finish Thickness
Board Dimension
Board Material
Copper Thickness (Top/Bottom Layers)
Thermal Vias Separation/Diameter
0.070 mm (Cu +Plating)
1.2 mm/0.3 mm
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BD5LL20AEFV-C
Thermal Resistance – continued
■ PCB Layout 4 layers (2s2p)
TOP Layer
Top Layer
2nd/Bottom Layers
3rd Layer
2nd Layer
3rd Layer
Bottom Layer
Via
Isolation Clearance Diameter: ≥ 0.6 mm
Cross Section
Figure 5. PCB-layout 4-layer (2s2p)
Dimension
Value
Board Finish Thickness
Board Dimension
1.60 mm ± 10 %
76.2 mm x 114.3 mm
FR4
Board Material
Copper Thickness (Top/Bottom Layers)
Copper Thickness (Inner Layers)
Thermal Vias Separation/Diameter
0.070 mm (Cu +Plating)
0.035 mm
1.2 mm/0.3 mm
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BD5LL20AEFV-C
Thermal Resistance – continued
■ Transient Thermal Resistance (Single Pulse)
1000
100
10
1
1s footprint
2s
2s2p
0.1
0.0001 0.001 0.01
0.1
1
10
100 1000
Pulse Time [s]
Figure 6. Transient Thermal Resistance
■ Thermal Resistance (θJA vs Copper Foil area 1s)
120
100
80
60
40
20
0
0
200
400
600
800
1000
1200
Copper Fiol Area 1s [mm2]
Figure 7. Thermal Resistance
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BD5LL20AEFV-C
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VX Power Supply Voltage
VS Power Supply Voltage
Operating Temperature
LDO Output Capacitance
VX
VS
6.0
6.0
-40
68
12.0
7.0
+25
-
18.0
8.0
V
V
Tj
+150
270
°C
µF
CV5O
Electrical Characteristics (Unless otherwise specified VX = 6 V to 18 V, VS = 6V to 8V, Tj = -40 °C to 150 °C)
Parameter
VS Circuit Current
Symbol
IVS
Min
Typ
3.0
Max
6.0
Unit
mA
Conditions
VIN1 = 0 V
-
LDO
V5O Output Voltage
V5O Over Current Threshold Value
Load Regulation
V5O
4.9
5.0
500
-
5.1
-
V
1 mA < IV5O < 250 mA
V5O = 4.5 V
IOCP(V5O)
ΔV5O-Load
ΔV5O-Line
ΔV5O-Drop
250
mA
mV
mV
mV
-
-
-
50
10
500
1 mA < IV5O < 250 mA
IV5O = 1 mA, 6 V < VS < 8 V
IV5O = 250 mA
Line Regulation
-
Low Dropout Voltage
200
Power Supply Ripple Rejection
Ratio
PSRR
-
60
-
dB
CV5O = 220 μF, f = 1 kHz
Input (CSB, SCLK, SI, IN1)
V5O
0.2
x
Low Level Input Voltage
VIL
0
-
V
V5O
0.7
x
High Level Input Voltage
Input Hysteresis Voltage
VIH
VHYS
IIL1
-
0.45
0
V5O
0.7
V
0.2
-10
-100
25
V
Low Level Input Current 1
(except CSB)
+10
-25
100
+10
μA
μA
μA
μA
VSCLK, VSI, VIN1 = 0 V
VCSB = 0 V
Low Level Input Current 2 (CSB)
IIL2
-50
50
0
High Level Input Current 1
(except CSB)
IIH1
VSCLK, VSI, VIN1 = 5 V
VCSB = V5O
High Level Input Current 2 (CSB)
Serial Out Output
IIH2
-10
SO Low Level Output Voltage
SO High Level Output Voltage
Serial Out Output Leakage Current
VSOL
VSOH
-
0.15
0.6
-
V
V
ISO = 1 mA
V5O - 0.6 V5O - 0.3
ISO = -1 mA
VSO = 0 V / 5 V
ISO(OFF)
-5
0
+5
μA
Power MOS Output OUT1, OUT2, OUT3
-
-
200
300
40
6
250
375
90
mΩ
mΩ
μA
μs
IOUT = 1 A, Tj = 25 °C
IOUT = 1 A, Tj = 150 °C
VOUT = 24 V
Output On Resistance
RDS(ON)123
Output Sink Current During OLD
Turn-On Time
IOLD
tON123
15
-
12
RL = 24 Ω, VBAT = 12 V
RL = 24 Ω, VBAT = 12 V
Turn-Off Time
tOFF123
SRON123
SROFF123
VCL123
-
6
12
μs
Slew Rate (On)
1.3
2.0
30
2.5
3.5
35
4.0
6.0
40
V/μs RL = 24 Ω, VBAT = 12 V
V/μs RL = 24 Ω, VBAT = 12 V
Slew Rate (Off)
Output Clamp Voltage
V
IOUT = 1 mA (Output Off)
Power MOS Output OUT1, OUT2, OUT3 Protection Circuit
Over Current Threshold Value
Over Current Detection Time
IOCP123
tOCP123
2
3.5
45
5.5
90
A
22
μs
Open Load Detection
Release Voltage
Open Load Detection
Detect Voltage
Output Overhead Detection
Detect Voltage
Output Overhead Detection
Release Voltage
VOLD(OFF)
VOLD(ON)
VOFD(ON)
VOFD(OFF)
1.2
1.0
1.2
1.0
2.5
2.0
2.5
2.0
3.5
3.1
3.5
3.1
V
V
V
V
Output Off Setting
Output Off Setting
Output On Setting
Output On Setting
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Electrical Characteristics – continued (Unless otherwise specified VX = 6 V to 18 V, VS = 6V to 8V, Tj = -40 °C
to 150 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Power MOS Output OUT4, OUT5
-
-
540
880
0
675
1100
1
mΩ
mΩ
μA
μA
μs
IOUT = 0.2 A, Tj = 25 °C
IOUT = 0.2 A, Tj = 150 °C
VOUT = 24 V, Tj = 25 °C
VOUT = 24 V, Tj = 150 °C
RL = 60 Ω, VBAT = 12 V
RL = 60 Ω, VBAT = 12 V
Output On Resistance
Output Leakage Current
RDS(ON)45
-
IOUT(L)45
-
0.5
15
3
Turn-On Time
tON45
tOFF45
-
25
Turn-Off Time
-
30
50
μs
Slew Rate (On)
Slew Rate (Off)
Output Clamp Voltage
SRON45
SROFF45
VCL45
0.4
0.4
30
1.0
1.0
35
2.2
2.2
40
V/μs RL = 60 Ω, VBAT = 12 V
V/μs RL = 60 Ω, VBAT = 12 V
V
IOUT = 1 mA (Output Off)
Power MOS Output OUT4, OUT5 Protection Circuit
Over Current Threshold Value
Over Current Detection Time
K-LINE
IOCP45
tOCP45
0.5
22
0.9
45
1.4
90
A
μs
VX Circuit Current
IVX
-
0.03
0.10
0.4
-
mA
V
VTX = 0 V
RX Low Level Output Voltage
RX High Level Output Voltage
RX Output Delay Time
VRXL
VRXH
tRXD
-
-
-
-
IRX = 1 mA
IRX = -1 mA
V5O - 0.4
V
-
2
μs
V5O
0.2
x
TX Low Level Input Voltage
TX High Level Input Voltage
VIL(TX)
0
-
-
V
V
V5O
0.7
x
VIH(TX)
VHYS(TX)
RTX
V5O
TX Input Hysteresis Voltage
TX Pull-up Resistor
0.1
0.3
10
-
0.5
20
1.4
3
V
kΩ
V
5
-
KIO Low Level Output Voltage
KIO Output Leakage Current
KIO Over Current Threshold Value
KIO Output Delay Time
VKIOL
RKIO = 480 Ω
VKIO = 18 V
IKIO(L)
IOCP(KIO)
tKIOD
-
0
μA
mA
μs
40
-
-
140
2
-
RKIO = 480 Ω
Switching Time Measurement Waveform
OUT2, OUT3, OUT4, OUT5 (Control by SPI)
OUT1 (Control by IN1)
SRON = (VBAT * 0.8) / tFALL
SROFF = (VBAT * 0.8) / tRISE
[V]
[V]
CSB
IN1
for SPI
[t]
[t]
0
0
[V]
[V]
tON
tOFF
tON
tOFF
VBAT
VBAT*0.9
OUT1
VBAT
VBAT*0.9
OUT2, OUT3
OUT4 ,OUT5
VBAT*0.1
VBAT*0.1
[t]
[t]
0
0
tFALL
tRISE
tFALL
tRISE
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BD5LL20AEFV-C
Typical Performance Curves
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
5
4
3
2
1
0
5
4
3
2
1
0
0
2
4
6
8
10
-50
0
50
100
150
VS Power Supply Voltage: VS [V]
Junction Temperature: Tj [ºC]
Figure 8. VS Circuit Current vs VS Power Supply Voltage
Figure 9. VS Circuit Current vs Junction Temperature
10
5.1
Tj = -40 °C
Tj = 25 °C
8
Tj = 150 °C
5.05
6
4
2
0
5
4.95
4.9
0
2
4
6
8
10
-50
0
50
100
150
VS Power Supply Voltage: VS [V]
Junction Temperature: Tj [ºC]
Figure 10. V5O Output voltage vs VS Power Supply Voltage
Figure 11. V5O Output voltage vs Junction Temperature
www.rohm.com
© 2023 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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12/45
13.Jan.2023 Rev.001
BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
6
5
4
3
2
1
0
1000
800
600
400
200
0
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
0
200
400
600
800
1000
-50
0
50
100
150
V5O Output Current: IV5O [mA]
Junction Temperature: Tj [ºC]
Figure 12. V5O Output voltage vs V5O Output Current
Figure 13. V5O Over Current Threshold Value vs Junction
Temperature
50
40
30
20
10
0
10
8
6
4
2
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj[ºC]
Junction Temperature: Tj[ºC]
Figure 14. Load Regulation vs Junction Temperature
Figure 15. Line Regulation vs Junction Temperature
www.rohm.com
© 2023 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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13/45
13.Jan.2023 Rev.001
BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
500
400
300
200
100
0
100
80
60
40
20
0
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
0
50
100
150
200
250
10
100
1k
10k
100k
V5O Output Current:IV5O [mA]
Frequency: f [Hz]
Figure 16. Low Dropout Voltage vs V5O Output Current
Figure 17. Power Supply Ripple Rejection Ratio vs
Frequency
5
4
100
80
60
40
20
0
VIH
3
IIH1
VIL
2
1
0
IIL1
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj[ºC]
Junction Temperature: Tj [ºC]
Figure 18. High Level Input Voltage / Low Level Input Voltage
vs Junction Temperature
Figure 19. High Level Input Current 1 / Low Level Input
Current 1 vs Junction Temperature
www.rohm.com
TSZ02201-0G5G1G400200-1-2
© 2023 ROHM Co., Ltd. All rights reserved.
14/45
TSZ22111 • 15 • 001
13.Jan.2023 Rev.001
BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
5
4
3
2
1
0
0
-20
IIH2
VSOH
-40
IIL2
-60
-80
VSOL
-100
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj[ºC]
Junction Temperature: Tj [ºC]
Figure 20. High Level Input Current 2 / Low Level Input
Current 2 vs Junction Temperature
Figure 21. SO High Level Output Voltage / SO Low Level
Output Voltage vs Junction Temperature
5
4
3
2
400
350
300
250
200
150
100
50
1
SO = 5 V
SO = 0 V
0
-1
-2
-3
-4
-5
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 22. Serial Out Output Leakage Current vs Junction
Temperature
Figure 23. Output On Resistance vs Junction Temperature
(OUT1, OUT2, OUT3)
www.rohm.com
© 2023 ROHM Co., Ltd. All rights reserved.
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BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
12
10
8
90
65
40
15
tOFF123
6
tON123
4
2
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 24. Output Sink Current During OLD vs Junction
Temperature
Figure 25. Turn-On Time / Turn-Off Time
vs Junction Temperature
(OUT1, OUT2, OUT3)
6
5
4
40
38
36
34
32
30
SROFF123
3
SRON123
2
1
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 26. Slew Rate (On) / Slew Rate (Off)
vs Junction Temperature
Figure 27. Output Clamp Voltage vs Junction Temperature
(OUT1, OUT2, OUT3)
(OUT1, OUT2, OUT3)
www.rohm.com
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BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
90
80
70
60
50
40
30
20
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 28. Over Current Threshold Value vs Junction
Temperature
Figure 29. Over Current Detection Time vs Junction
Temperature
(OUT1, OUT2, OUT3)
(OUT1, OUT2, OUT3)
3.5
3.5
3
2.5
2
3
2.5
2
VOLD(OFF)
VOFD(ON)
VOLD(ON)
VOFD(OFF)
1.5
1.5
1
1
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 30. Open Load Detection Detect Voltage / Open Load
Detection Release Voltage
Figure 31. Output Overhead Detection Detect Voltage /
Output Overhead Detection Release Voltage
vs Junction Temperature
vs Junction Temperature
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BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
1200
1000
800
600
400
200
0
5
4
3
2
1
0
Tj = 25 °C
Tj = 150 °C
-50
0
50
100
150
0
5
10
15
20
25
30
Junction Temperature: Tj [ºC]
Output Voltage: VOUT4, VOUT5 [V]
Figure 32. Output On Resistance vs Junction Temperature
(OUT4, OUT5)
Figure 33. Output Leakage Current vs Output Voltage
(OUT4, OUT5)
3
2
1
0
50
40
30
tOFF45
20
tON45
10
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 34. Output Leakage Current vs Junction Temperature
(OUT4, OUT5)
Figure 35. Turn-On Time / Turn-Off Time
vs Junction Temperature
(OUT4, OUT5)
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BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
2
1.6
1.2
0.8
0.4
40
38
36
34
32
30
SROFF45
SRON45
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 36. Slew Rate (On) / Slew Rate (Off)
vs Junction Temperature
Figure 37. Output Clamp Voltage vs Junction Temperature
(OUT4, OUT5)
(OUT4, OUT5)
1.5
1.0
0.5
0.0
90
80
70
60
50
40
30
20
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 38. Over Current Threshold Value vs Junction
Figure 39. Over Current Detection Time vs Junction
Temperature
Temperature
(OUT4, OUT5)
(OUT4, OUT5)
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19/45
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BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
5
4
3
2
1
0
0.10
0.08
0.06
0.04
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
0.02
0.00
0
5
10
15
20
25
30
-50
0
50
100
150
VX Power Supply Voltage: VX [V]
Junction Temperature: Tj [ºC]
Figure 40. VX Circuit Current vs VX Power Supply Voltage
Figure 41. VX Circuit Current vs Junction Temperature
5
2
RISE
FALL
VRXH
4
3
2
1
1.5
1
0.5
VRXL
0
-50
0
-50
0
50
100
150
0
50
100
150
Junction Temperature: Tj[ºC]
Junction Temperature: Tj [ºC]
Figure 42. RX High Level Output Voltage / RX Low Level
Output Voltage vs Junction Temperature
Figure 43. RX Output Delay Time vs Junction Temperature
www.rohm.com
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BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
5
4
3
2
1
0
20
15
10
5
VIH(TX)
VIL(TX)
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 44. TX High Level Input Voltage / TX Low Level Input
Voltage vs Junction Temperature
Figure 45. TX Pull-up Resistor vs Junction Temperature
1.4
1.2
1
3
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
2
0.8
0.6
0.4
0.2
0
1
0
-50
0
50
100
150
0
5
10
15
20
25
30
Junction Temperature: Tj [ºC]
KIO Output Voltage: VKIO [V]
Figure 46. KIO Low Level Output Voltage vs Junction
Temperature
Figure 47. KIO Output Leakage Current vs KIO Output
Voltage
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BD5LL20AEFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VX = 12 V, VS = 7 V, Tj = 25 °C)
3
2
1
0
140
120
100
80
60
40
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 48. KIO Output Leakage Current vs Junction
Temperature
Figure 49. KIO Over Current Threshold Value vs Junction
Temperature
2
RISE
FALL
1.5
1
0.5
0
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Figure 50. KIO Output Delay Time vs Junction Temperature
www.rohm.com
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BD5LL20AEFV-C
Measurement Circuits
VX
VX
VS
VS
CVS
CVX
CVS
CVX
VS
VX
OUT1
VS
VX
OUT1
RL1
IN1
IN1
RL2
RL3
V5O
OUT2
OUT3
OUT4
OUT5
KIO
V5O
OUT2
OUT3
OUT4
OUT5
KIO
CV5O
CV5O
IV5O
CSB
SCLK
SI
CSB
SCLK
SI
RL4
SO
SO
RL5
RX
TX
RX
TX
RKIO
5 V
AGND
PGND
AGND
PGND
Figure 51.
Figure 52.
VS Circuit Current
VX Circuit Current
V5O Output voltage
Load Regulation
Line Regulation
Low Dropout Voltage
VX
VX
VS
CVS
CVX
CVS
CVX
0.1 Vp-p
1 kHz
VS
VS
VX
OUT1
VS
VX
OUT1
IN1
IN1
V5O
OUT2
OUT3
OUT4
OUT5
KIO
V5O
OUT2
OUT3
OUT4
OUT5
KIO
CV5O
CV5O
CSB
SCLK
SI
CSB
SCLK
SI
SO
SO
RX
TX
RX
TX
AGND
PGND
AGND
PGND
Figure 53.
V5O Over Current Threshold Value
Figure 54.
Power Supply Ripple Rejection Ratio
www.rohm.com
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BD5LL20AEFV-C
Measurement Circuits – continued
VX
VX
VS
VS
CVS
CVX
CVS
CVX
VS
VX
OUT1
VS
VX
OUT1
IN1
IN1
for IN1
V5O
OUT2
OUT3
OUT4
OUT5
KIO
V5O
OUT2
OUT3
OUT4
OUT5
KIO
CV5O
CV5O
for SO
CSB
SCLK
SI
CSB
SCLK
SI
MCU
SO
SO
for SPI
ISO
RX
TX
RX
TX
for RX
for TX
0 V / 12 V
AGND
PGND
AGND
PGND
IRX
for KIO
Figure 55.
Figure 56.
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis Voltage
High Level Input Current 1
Low Level Input Current 1
High Level Input Current 2
Low Level Input Current 2
TX Pull-up Resistor
SO High Level Output Voltage
SO Low Level Output Voltage
RX High Level Output Voltage
RX Low Level Output Voltage
VX
VX
VS
VS
CVS
CVX
CVS
CVX
VS
VX
OUT1
VS
VX
OUT1
OUT2
OUT3
OUT4
OUT5
IN1
IN1
5 V
IOUT1~5
V5O
OUT2
OUT3
OUT4
OUT5
KIO
V5O
CV5O
CV5O
ch On
CSB
SCLK
SI
CSB
SCLK
SI
MCU
SO
SO
RX
TX
RX
TX
KIO
0 V
VSO
AGND
PGND
AGND
PGND
Figure 57.
Serial Out Output Leakage Current
Figure 58.
Output On Resistance
www.rohm.com
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BD5LL20AEFV-C
Measurement Circuits – continued
VX
VX
VS
VS
CVS
CVX
CVS
CVX
VS
VX
OUT1
VS
VX
OUT1
RL1
RL2
RL3
RL4
RL5
RKIO
IN1
IN1
0 V to 5 V
0 V
or
5 V to 0 V
V5O
OUT2
OUT3
OUT4
OUT5
KIO
V5O
OUT2
OUT3
OUT4
OUT5
KIO
CV5O
CV5O
ch Off
ch On/Off
CSB
SCLK
SI
CSB
SCLK
SI
MCU
MCU
SO
SO
RX
TX
RX
TX
0 V to 5 V
or
5 V to 0 V
5 V
VOUT1~5
VKIO
AGND
PGND
AGND
PGND
VBAT
:Monitor
Figure 59.
Figure 60.
Output Sink Current During OLD
Output Leakage Current
KIO Output Leakage Current
Turn-On Time
Turn-Off Time
Slew Rate (On)
Slew Rate (Off)
RX Output Delay Time
KIO Output Delay Time
VX
VX
VS
VS
CVS
CVX
CVS
CVX
VS
VX
VS
VX
OUT1
OUT1
OUT2
OUT3
OUT4
OUT5
IN1
IN1
0 V
5 V
IOUT1~5
V5O
V5O
OUT2
OUT3
OUT4
OUT5
KIO
CV5O
CV5O
ch Off
ch On
CSB
SCLK
SI
CSB
SCLK
SI
MCU
MCU
SO
SO
RX
TX
RX
TX
KIO
0 V
AGND
PGND
AGND
PGND
Figure 61.
Output Clamp Voltage
Figure 62.
Over Current Threshold Value
Over Current Detection Time
KIO Over Current Threshold Value
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BD5LL20AEFV-C
Measurement Circuits – continued
VX
VX
VS
VS
CVS
CVX
CVS
CVX
VS
VX
VS
VX
OUT1
OUT2
OUT3
OUT1
OUT2
OUT3
IN1
IN1
5 V
0 V
V5O
V5O
CV5O
CV5O
ch On
ch Off
CSB
SCLK
SI
CSB
SCLK
SI
MCU
MCU
SO
SO
RX
TX
RX
TX
KIO
KIO
AGND
PGND
AGND
PGND
Figure 63.
Open Load Detection Detect Voltage
Open Load Detection Release Voltage
Figure 64.
Output Overhead Detection Detect Voltage
Output Overhead Detection Release Voltage
VX
VS
CVS
CVX
VS
VX
OUT1
IN1
V5O
OUT2
OUT3
OUT4
OUT5
KIO
CV5O
CSB
SCLK
SI
SO
RX
TX
RKIO
0 V
AGND
PGND
Figure 65.
KIO Low Level Output Voltage
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13.Jan.2023 Rev.001
BD5LL20AEFV-C
Timing Chart
VX
6 V (Min)
Turn on VX to 6 V or more
t
t
t
VS
V5O
CSB
7 V
Turn on VS to 6 V or more
6 V (Min)
LDO Turn on time
2.2 ms (Typ)
5 V
4 V (Max)
t
t
More than 10 ms
SI
SCLK
Access enable
Send SPI signal 10 ms later
after V5O is over 4 V.
IN1
t
t
More than 10 ms
OUTn
VX
n is ch nummber.
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BD5LL20AEFV-C
K-LINE Timing Chart
TX
V5O
0.7 * V5O
0.2 * V5O
0
[t]
[t]
[t]
tKIOD
(H to L)
tKIOD
(L to H)
KIO
VX
0.5 * VX
0
tRXD
(H to L)
tRXD
(L to H)
RX
V5O
0.5 * V5O
0
Output waveform During Inductive Load Operation
[V]
IN1
0
[t]
VCL
[V]
VOUT
VBAT
IOUT x RDS(ON)
[t]
[t]
0
[A]
VBAT
RL + RDS(ON)
IOUT
0
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BD5LL20AEFV-C
SPI Specification
·SPI Overview
When CSB = H
The SO pin is High-Z.
When CSB = L
Outputs to SO at the rising edge of SCLK.
SI is loaded into the register at the falling edge of SCLK.
MSB
LSB
LSB
X
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
SO
SI
MSB
CSB
SCLK
·SPI Protocol
The SO response to SPI access is returned at the next SPI access as shown in the following figure.
SI
frame A
frame B
frame C
(previous
response)
response to
frame A
response to
frame B
SO
·Response when accessing with RE = 0 and with RE = 1
When accessing with RE = 0, respond “Standard Diagnostic”.
When accessing with RE = 1, respond the value of the specified register.
SI
RE = 0
RE = 1 (register A)
(new command)
(previous
response)
Standard
Diagnostic
register A
content
SO
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BD5LL20AEFV-C
SPI Specification – continued
·SPI Timing Chart
tCSB(lead)
tCSB(lag)
tCSB(td)
0.7V5O
0.2V5O
tSCLK(P)
CSB
tSCLK(su)
tSCLK(hd)
tSCLK(H)
tSCLK(L)
0.7V5O
0.2V5O
SCLK
tSI(su)
tSI(hd)
0.7V5O
0.2V5O
SI
Don't care
Hi-Z
TER_IN
MSB
14
1
LSB
Don't care
tSO(td)
tSO(dd)
tSO(dis)
tSO(en)
0.7V5O
0.2V5O
Hi-Z
SO
x
TER
MSB
14
1
LSB
x
Parameter
Symbol
Min
Typ
Max
Unit
SCLK Frequency
SCLK Period
fSCLK
tSCLK(P)
tSCLK(H)
tSCLK(L)
tSCLK(su)
tSCLK(hd)
tCSB(lead)
tCSB(lag)
tCSB(td)
tSI(su)
0
200
50
50
50
50
250
250
250
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
SCLK High Time
SCLK Low Time
SCLK Setup Time
SCLK Hold Time
CSB Lead Time
CSB Lag Time
-
-
-
-
-
-
Transfer Delay Time
Data Setup Time
Data Hold Time
SPI Output Enable Time(Note 1)
SPI Output Disable Time(Note 1)
-
-
tSI(hd)
-
tSO(en)
200
250
100
200
tSO(dis)
tSO(dd)
-
SPI Output Data Delay Time(Note 1)(Note 2)
ERR Output Through Delay Time(Note 1)
-
tSO(td)
-
(Note 1) Not 100 % tested.
(Note 2) SO pin capacitance = 20 pF
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SPI Specification – continued
·SI Data Structure
Bit[15]
RE
Bit[14]
WE
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
Bit[7]
Data
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Address
TEST
RE
0: The SO pin outputs "Standard Diagnostic" at the next SPI access.
1: The SO pin outputs the register value specified by Address at the next SPI access.
WE
0: Not Write.
1: Write.
TEST
Be sure to set 0.
Data
When WE = 1, various settings are enabled by writing '0' or '1' to Data.
For details, refer to "Register Map".
·"Standard Diagnostic" (when RE = 0 setting in the previous SPI access)
Initial Value 0x4000
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
TSD
KLINE
0
INIT
0
0
0
TER
0
OLD3
OLD2
OLD1
ERR5
ERR4
ERR3
ERR2
ERR1
INIT
0: Normal (after power on, from the second time SPI access).
1: After power on, first time SPI access.
TER
0: Normal
1: SPI communication error
When High pulse input of SCLK is other than (16 times + 8 x m, m is an integer 0 or above) in the low level section of CSB, a
communication error is judged.
TSDKLINE
0: Normal
1: Thermal shutdown of K-LINE section
Once detected, it latches." Standard Diagnostic" is cleared by read access.
DIAG_OLDn (n shows ch number)
0: Normal
1: Open load detection of OUT1, OUT2, OUT3
Once detected, it latches." Standard Diagnostic" is cleared by read access.
ERRn (n shows ch number)
0: Normal
1: Over current protection, thermal shutdown, or output overhead detection (OUT1, OUT2, OUT3 only) for OUTn
(Logical OR of DIAG_OCPn, DIAG_TSDn, and DIAG_OFDn)
·SO Output Data Structure (when RE = 1 setting in the previous SPI access)
Bit[15]
1
Bit[14]
WE
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
Bit[7]
Data
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Address
ERRALL
WE, Address
Outputs WE and Address values that were set during the previous SPI access.
ERRALL
Outputs 1 when either open load detection, output overhead detection, over current protection or thermal shutdown is detected
on at least one channel.
(Logical OR of DIAG_OLDn, DIAG_OFDn, DIAG_OCPn, DIAG_TSDn and DIAG_TSD_KLINE for all channels)
Data
Outputs the register value of Address that were set during the previous SPI access.
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Register Map
Address TEST
Bit[13:9] Bit[8]
Data
Register
Access
Register Name
Initial
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
0
OUTCTRL
STATUS_IN
DIAG_OUT32
DIAG_OUT541
HWCR
R/W
RO
0x00
0x06
0x0A
0x0B
0x0C
0x1E
0
0
0
0
0
1
0
0
0
OUTCTRL5
OUTCTRL4
OUTCTRL3
OUTCTRL2
0x00
0x00
0x00
0x00
0x00
0x00
0
0
DIAG_OFD3
DIAG_TSD5
RST
0
0
0
0
0
0
0
0
0
STATUS_IN1
DIAG_TSD2
DIAG_TSD1
0
RO
0
DIAG_OCP3
DIAG_TSD3
DIAG_OFD2
DIAG_OCP2
RO
DIAG_OCP5
DIAG_OCP4
DIAG_TSD4
DIAG_OFD1
DIAG_OCP1
WO
WO
0
0
0
0
0
0
0
0
0
0
T_TESTMODE
0
TESTMODE
Register Name
OUTCTRL
Register Access
Read / Write
Address
0x00h
Explanation of Data
OUTCTRLn bit (n represents the channel number)
'0': OUTn off setting
'1': OUTn on setting
STATUS_IN1 bit
STATUS_IN
Read Only
0x06h
'0': IN1 L input, OUT1 Off Setting
'1': IN1 H input, OUT1 On Setting
Reads the error flags of OUT1 to OUT5.
DIAG_OFDn bit
'0': Normal
'1': Output overhead detection
Once detected, it latches.
Cleared by read access to DIAG_OFDn.
DIAG_OCPn bit
'0': Normal
'1': Over current protection detection
It latches, if over current protection is detected at the same time
as thermal shutdown or if continue detecting over current
protection for a certain period of time.
DIAG_OUT32
DIAG_OUT541
0x0Ah
0x0Bh
Read Only
Cleared by read access to DIAG_OCPn.
If over current protection is detected on OUT2 to OUT5, the
OUTCTRLn bit of the corresponding channel is cleared to '0' and
the output is turned off.
After clearing DIAG_OCPn, OUTn is turned on by setting
OUTCTRLn to '1' again.
DIAG_TSDn bit
'0': Normal
'1': Thermal shutdown detection
Once detected, it latches.
Cleared by read access to DIAG_TSDn.
RST
HWCR
Write Only
Write Only
0x0Ch
0x1Eh
'0': Normal
'1': Hardware reset (auto clear)
TESTMODE
'0': Normal
'1': Test Mode
T_TESTMODE
If IN pin is 5.6 V (Min) or more and "1" is written to this register, IC
enters test mode. For this reason, do not access to this register.
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Protection Function
Protection Function
Detection and Release Conditions
Output Behavior
Current limitation
OUT1
2 A (Min)
2 A (Min)
Output latch after 45 μs (Typ)
of current-limit state has
elapsed
OUT2
OUT3
Detection
Conditions
Output latch after 45 μs (Typ)
of current-limit state has
elapsed
OUT4
OUT5
0.5 A (Min)
Over Current
Protection
2 A (Min) or less
(automatic recovery)
OUT1
Normal operation
Write '1' to OUTCTRL2 or
OUTCTRL3 after read Output latch is released
access to DIAG_OUT32
OUT2
OUT3
Release
Conditions
Write '1' to OUTCTRL4 or
OUTCTRL5 after read Output latch is released
access to DIAG_OUT541
OUT4
OUT5
Low Side
Switch
Detection
Condition
Release
Condition
Detection Output off state and
Tj ≥ 150 °C (Min)
Tj ≤ 125 °C (Min)
Output stop
Thermal Shutdown
Normal operation
Normal operation
Open Load
Detection
Condition Output voltage 2.0 V (Typ) or less
(Only OUT1, OUT2
and OUT3 are
supported)
Output Overhead
Detection
(Only OUT1, OUT2
and OUT3 are
supported)
Release
Output off state and
Normal operation
Normal operation
Normal operation
Condition Output voltage 2.5 V (Typ) or more
Detection Output on and
Condition Output voltage 2.5 V (Typ) or more
Release
Output on and
Condition Output voltage 2.0 V (Typ) or less
Detection
Condition
IV5O ≥ 250 mA (Min)
-
Over Current
Protection
Release
Condition
IV5O < 250 mA (Min)
-
Detection
Tj ≥ 150 °C (Min)
Condition
LDO output stopped
Normal operation
Thermal Shutdown
LDO
Release
Tj ≤ 125 °C (Min)
Condition
Detection
Condition
Low side output stopped
KIO output stopped
V5O ≤ 3.0 V (Min)
Power-on Reset
Release
V5O ≥ 4.0 V (Min)
Condition
Normal operation
Current limitation
Normal operation
KIO output stopped
Normal operation
Detection
Output current 40 mA (Min)
Condition
KIO Over Current
Protection
Release
Output current 40 mA (Min) or less
Condition
K-LINE
Detection
Condition
Tj ≥ 150 °C (Min)
Thermal Shutdown
Release
Tj ≤ 125 °C (Min)
Condition
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Over Current Protection
If a current exceeding the over current detection value flows to the low side output, over current protection is applied and an error
flag (DIAG_OCPn) is output.
For OUT1, the current flowing to the output is limited when over current protection is applied.
Normal
Over Current State
Flag Latch State
Normal
IN1
Battery voltage
OUT1
OUT1
2 A (Min)
IOUT1
DIAG_OCP1
45 µs (Typ)
Read Access to DIAG_OCP1
For OUT2 to OUT5, the output is turned off when over current protection is applied. In this case, OUTCTRLn is set to '0'; read
access to DIAG_OCPn clears the error flag and setting OUTCTRLn to '1' turns on the output.
Over Current
Normal
Latch
Normal
OUTCTRLn
OUTn
Battery voltage
Write 1 to OUTCTRLn
OUT2, OUT3
2 A (Min)
OUT4, OUT5
0.5 A (Min)
IOUTn
DIAG_OCPn
45 µs (Typ)
Read Access to DIAG_OCPn
Thermal Shutdown
Turns off the low side output, LDO output, and KIO output when Tj rises 150 °C (Min) or above. Turns back on when Tj falls
125 °C (Min) or below.
Normal
TSD State
Normal
OUTCTRLn
OUTn
Battery voltage
150 °C (Min)
125 °C (Min)
Tj
DIAG_TSDn
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Open Load Detection (OLD)
VBAT
RL
OUT
Power
MOS
DIAG_OLDn
IOLD
SO
GND
OUT1, OUT2, and OUT3 have an open load detection (OLD) function: output inflow current IOLD is applied to OUT, and as load RL
increases, output voltage VOUT decreases, and when it falls below VOLD(ON) , an open load detection state occurs and an error flag
is output.
The value of RL that detects OLD is obtained from the following formula.
푉퐵퐴푇 − 푉푂퐿퐷(푂푁)
ꢄ퐿 ≥
퐼푂퐿퐷
VBAT : Battery voltage
VOLD(ON) : Open load detection voltage 3.1 V (Max)
IOLD : Output inflow current during open detection operation 90 μA (Max)
Normal
OLD State
Normal
OUTCTRLn
OUTn
Output load is open.
2.5 V (Typ)
2.0 V (Typ)
Open state is
resolved.
Time of mask OLD.
25 µs (Typ)
DIAG_OLDn
Read Access
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Output Overhead Detection (OFD)
VBAT
RL
OUT
Power
MOS
DIAG_OFDn
SO
GND
OUT1, OUT2, and OUT3 have an output overhead detection (OFD) function.
When the output transistor is on, if the output voltage of OUT1 to OUT3 exceeds VOFD(ON), a state of top fault detection occurs,
and an error flag is output.
Normal
OFD State
Normal
OUTCTRLn
OUTn
Short state is
released.
2.5 V (Typ)
Output is shorted
to power.
Time of mask OFD.
25 µs (Typ)
DIAG_OFDn
Read Access
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Application Example
Battery
CVS
VS
V5O
CV5O2 CV5O
TSD
OCP
LDO
RKIO
OUT1
TSD
OCP
OLD
POR
ZOUT1
RIN1
IN1
For OUT1
x2
x2
OUT2
OUT3
TSD
OCP
OLD
RCSB
RSI
CSB
SI
Control
Logic
SPI
RSCLK
SCLK
SO
μcon
OUT4
OUT5
TSD
OCP
RSO
RRX
RTX
RX
TX
VX
TSD
OCP
K-LINE
Other
Device
KIO
CVX
AGND
PGND
Selection of Components Externally Connected
Symbol
Value
Purpose
RIN1, RCSB, RSI, RSCLK, RSO 1 kΩ
Register for microcontroller protection against negative voltage surge.
Register for microcontroller protection against negative voltage surge.
KIO Pull-up Resistor
RRX, RTX
RKIO
1 kΩ
480 Ω
0.1 μF
0.1 μF
220 μF
0.1 μF
CVX
Capacitor for noise rejection on power supply lines(Note 1)
Capacitor for noise rejection on power supply lines(Note 1)
LDO Output Capacitor(Note 1)(Note 2)
CVS
CV5O
CV5O2
LDO Output Capacitor(Note 1)(Note 3)
Zener diode for the reverse energy absorption when inductive load is
ZOUT1
-
turned off(Note 4)
(Note 1) It is recommended to insert capacitors as close as possible between VX and PGND, between VS and AGND, and between V5O and AGND.
(Note 2) Connect large capacitor to stabilize the output.
(Note 3) When using a capacitor with ESR of 1 Ω or more in CV5O, insert a ceramic capacitor (CV5O2) in parallel.
(Note 4) Connect it when driving an inductive load that exceeds active clamp energy of this product. The same is true for OUT2 to OUT5.
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I/O Equivalence Circuits
Pin No.
Pin Name
I/O Equivalence Circuit
1
1
VS
4
2
100 kΩ
2
IN1
4
1
3
3
4
5
V5O
50 kΩ
4
AGND
CSB
-
3
100 kΩ
5
4
6
7
8
SCLK
6.7
100 kΩ
4
SI
3
8
4
SO
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I/O Equivalence Circuits – continued
Pin No.
Pin Name
I/O Equivalence Circuit
3
9
9
RX
16,20
3
10 kΩ
10
10
11
12
TX
KIO
VX
16,20
2.5 kΩ
12
125 kΩ
11
16,20
12
2.5 kΩ
16,20
13
14
15
16
17
OUT5
OUT4
OUT3
PGND
OUT2
13,14,15,
17,18,19
18
19
OUT1
PGND
16,20
20
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Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at all
power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground
caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground
voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions.
The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of
connections.
7. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the
IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be
turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage
from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin
shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional
solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected
operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground
line.
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Operational Notes – continued
10. Regarding the Input and Output Pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or
transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference
among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as
applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 66. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with temperature
and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Function (TSD)
This IC has a built-in thermal shutdown function that prevents heat damage to the IC. Normal operation should always be
within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD function that will turn OFF power output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD function operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD function be used in a set design or for any purpose other than protecting the IC from heat
damage.
13. Over Current Protection Function (OCP)
This IC incorporates an integrated overcurrent protection function that is activated when the load is shorted. This protection
function is effective in preventing damage due to sudden and unexpected incidents. However, the IC should not be used in
applications characterized by continuous operation or transitioning of the protection function.
14. Active Clamp Operation
The IC integrates the active clamp function to internally absorb the reverse energy EL which is generated when the inductive
load is turned off. When the active clamp operates, the thermal shutdown function does not work. Decide a load so that the
reverse energy EL is active clamp tolerance EAS (refer to Figure 1.2.) or under when inductive load is used.
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Operational Notes – continued
15. Power Supply Steep Fluctuation
If the voltage of the power supply pin (VS) falls sharply, the output pin (OUT) may temporarily turn off as shown in Figure 67.
If the power supply pin is expected to fall sharply, take measures such as inserting a capacitor between the power supply pin
and the ground pin so that it falls within the recommended usage range shown in Figure 68.
2.5
V[V]
VS
2.0
1.5
1.0
0.5
0.0
Deprecated use range
VS(FALL)
VS
tVS(FALL)
0
t
VOUT[V]
Recommended use range
≈ VBAT
VOUT
≈ 0 V
0
t
0
10
20
30
[μs]
tVS(FALL)
Figure 67. Output OFF operation when power supply
fluctuates sharply
Figure 68. Recommended use range
16. GND Pin Connection
Connect all ground pins to ground.
17. Same Pin Connection
Connect all OUT1 pins to same line.
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Ordering Information
B D 5 L L 2 0 A E F V
-
CE 2
5: 5ch
Package
Product Rank
L: low side switch
EFV: HTSSOP-B20
C: For Automotive
Packaging Specification
E2: Embossed tape and reel
Marking Diagram
HTSSOP-B20 (TOP VIEW)
Part Number Marking
LOT Number
5 L L 2 0 A
Pin 1 Mark
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Physical Dimension and Packing Information
Package Name
HTSSOP-B20
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Revision History
Date
Revision
001
Changes
13.Jan.2023
New Release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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