BD71815AGW_技术文档

Datasheet

System PMIC for

Battery Powered Systems

BD71815AGW

General Description



Battery Monitoring and Alarm Output

-Under Voltage Alarm while discharging

-Over Current Alarm

-Over/Under Temperature Alarm

-Programmable thresholds and time durations

Real Time Clock with 32.768kHz crystal oscillator

-32.768kHz clock output

BD71815AGW is a single-chip power management IC

for battery-powered portable devices. The IC integrates

5 buck converters, 8 LDOs, a boost driver for LED, and

a 500mA single-cell linear charger. Also included is a

Coulomb counter, a real-time clock (RTC), a 32 kHz

crystal oscillator and a general-purpose output (GPO).

(Open Drain or CMOS Output Selectable)

1 GPO (Open Drain or CMOS Output Selectable)

Power Control I/O

The IC’s buck converters supply power to the application

processor as well as system peripherals such as DDR

memory, wireless modules, and touch controllers. These

regulators maintain high efficiency over a wide range of

current loads by supporting both PFM and PWM modes.

They also operate at a high switching frequency of

6MHz, which allows the use of smaller and cheaper

inductors and capacitors. The regulator supplying the

processor core also supports Dynamic Voltage Scaling

(DVS).



-Power On/Off control input

-Standby Input for switching RUN/SUSPEND State

-Reset Input to reset hung PMIC

-Power On Reset output

1 LED Indicator

-Indicate charger status



I2C interface

Applications

Features



E-Book reader



5 buck converters:

Media players with smart devices, wearables

Portable Navigation Devices with Home POS,

Human Machine Interfaces

- 3 1000mA buck converters

- 1 800mA buck converter

- 1 500mA buck converter



3 general-purpose LDOs

- 2 100mA LDOs

Key Specifications

- 1 50mA LDO



Input Voltage Range (DCIN):

Input Voltage Range (VIN, VSYS): 2.9V to 5.5V

Input Voltage Range (DVDD):

Off Current:

3.5V to 28V



LDO for DDR Reference Voltage (DVREF)

LDO for Secure Non-Volatile Storage (SNVS)

LDO for Low-Power State Retention (LPSR)

LDO for SD Card with dedicated enable terminal

LDO for SD Card Interface with dedicated terminal

to dynamically change output voltage

White LED Boost Converter

1.5V to 3.4V

20 μA (Typ)

[RTC+ Coulomb counter+ LDO_SNVS only]



Operating temperature range:

-40°C to +85°C



-25mA LED Boost Converter

Package

UCSP55M4C

W(Typ) x D(Typ) x H(Max)

4.0mm x 4.0mm x 0.62mm

Single-cell Linear LIB Charger with 30V OVP

-Selectable charging voltage: 3.72 to 4.34 V

-Programmable charge current: 100 to 500mA

-Support for up to 2000mA charge current using

external MOSFET

D71815A

-DCIN over voltage protection

-Battery over voltage protection

-Battery Supplement Mode support

-Battery Short Circuit Detection



Voltage Measurement for Thermistor

-Bias voltage output for External Thermistor

Embedded Coulomb Counter for Battery Fuel

Gauging

-15-bit ΔΣ-ADC with External Current Sense

Resistor (10 mΩ, ±1% or 30mΩ, ±1%)

-1-sec cycle, 28-bit accumulation

-Coulomb count while charging/discharging

(Unit :mm)

〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays

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BD71815AGW

Contents

General Description........................................................................................................................................................................1

Features..........................................................................................................................................................................................1

Applications ....................................................................................................................................................................................1

Key Specifications...........................................................................................................................................................................1

Package

W(Typ) x D(Typ) x H(Max).........................................................................................................................1

Contents .........................................................................................................................................................................................2

Typical Application Circuit ...............................................................................................................................................................3

Block Diagram ................................................................................................................................................................................4

Pin Configuration ............................................................................................................................................................................5

Pin Descriptions..............................................................................................................................................................................6

PCB Layout Recommendations......................................................................................................................................................8

Description of Blocks ......................................................................................................................................................................9

1.

2.

3.

4.

5.

6.

7.

8.

High Efficiency Buck Converters (BUCK1 – 5) and LDOs....................................................................................................9

Power ON/OFF Sequence .................................................................................................................................................11

States of Operation ............................................................................................................................................................12

Dynamic Voltage Scaling (DVS) Control ............................................................................................................................14

LDO4 and LDO5 Control (for SD Card)..............................................................................................................................15

Real Time Clock (RTC) Block.............................................................................................................................................16

Over Voltage Protection (OVP) Block.................................................................................................................................21

Battery Charger Block........................................................................................................................................................21

Coulomb Counter Block .....................................................................................................................................................25

12-bit ADC (SAR) Block .....................................................................................................................................................26

Battery Monitor Block.........................................................................................................................................................26

White LED Boost Converter...............................................................................................................................................27

I2C Bus Interface Block......................................................................................................................................................27

Interrupt Handling...............................................................................................................................................................31

9.

10.

11.

12.

13.

14.

Absolute Maximum Ratings (Ta=25°C).........................................................................................................................................32

Thermal Resistance^{(Note 1)}.............................................................................................................................................................32

Recommended Operating Conditions...........................................................................................................................................32

Electrical Characteristics...............................................................................................................................................................33

Register Map ................................................................................................................................................................................42

Typical Performance Curves.........................................................................................................................................................87

I/O Equivalent Circuits ..................................................................................................................................................................95

Operational Notes.........................................................................................................................................................................98

Ordering Information...................................................................................................................................................................101

Marking Diagrams.......................................................................................................................................................................101

Physical Dimension Tape and Reel Information..........................................................................................................................102

Revision History..........................................................................................................................................................................103

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Typical Application Circuit

BD71815AGW

DVDD

I2C Register

SDA

SCL

WDOGB

READY

INTB

POR

Power Control

PWRON

PMIC_ON_REQ

i.MX7Dual

SNVS domain

STANDBY

PMIC_STBY_REQ

PMIC PAD

ONOFF

LDO_SNVS

3.0V

25mA

SNVSC

VDD_SNVS

_1P8_CAP

LDO_SNVS_1P8

Coin Cell

XIN

CLK32KOUT

RTC_XTALI

32KRTC

X’tal

32K OSC

SNVS &

TAMPER DETECTEON

XOUT

LPSR domain

LDO_LPSR

1.8V

100mA

VOLPSR

VDD_LPSR

LDO_LPSR_1P0

HX6

SOC LPSR LOGIC

LX6

POR_B

NVCC_GPIO1

NVCC_GPIO2

1.8V GPIO PAD

3.3V GPIO PAD

White LED

Boost Converter

SBD

VO6

LDO1

3.3V

100mA

VO1

25mA

(ON/OFF)

FB6

DVS

BUCK1

1.1V

800mA

BUCK1

BUCK2

BUCK3

VDD_ARM

VDD_SOC

VDDA_1P8

NVCC_XXX

Cortex A7 Platform

SOC Logic

BUCK2

1.0V

1000mA

BUCK5

3.3V

1000mA

WiFi

BUCK3

1.8V

500mA

Analog Modules

PMIC_RDY

WDOG_B

SCL

Touch I/O

1.8V GPIO PAD

SDA

LDO2

3.3V

100mA

VO2

VO3

NVCC_XXX

3.3V GPIO PAD

LDO3

3.3V

50mA

VDDA_USB1_3P3

VDDA_USB2_3P3

DCIN

USB OTG1/2 PHY

28V

OVP

VSYS

PGATE

BUCK4

1.2V

1000mA

BUCK4

NVCC_DRAM_CKE

TAMPER9

DRAM_CKE/RESET

DRAM PAD

External MOSFET

(Optional)

VBAT

DVREFIN

NVCC_DRAM

DRAM_VREF

Linear

Charger

DVREF

1/2xDVREFIN

10mA

CHGREF

LPDDR2

SD Card

VODVREF

Battery Pack

TS

VO4

LDO4

3.3V

400mA

LDO4VEN

SD_RESET

BATTP

BATTM

Coulomb

Counter

SDXC I/F PAD

LDO5

3.3V/1.8V

250mA

VO5

LDO5VSEL

SD_VSELECT

Figure 1. Typical Application (E-Book Reader with i.Mx7D)

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Block Diagram

VSYS

PVIN1

LX1

VSYS

4.7uF

0.47uH

BUCK1

1.0V/1.1V

800mA

VDD_ARM

UVLO

TSD

DVS

FB1

10uF

PGND1

PVIN2

BUCK3

10kΩ

VSYS

4.7uF

0.47uH

GPO1

BUCK2

LX2

FB2

VDD_SOC

BUCK2

1.0V

1000mA

DVS

GPO

PGND2

PVIN3

VSYS

4.7uF

BUCK3

LX3

FB3

LDO_SNVS

3.0V

25mA

NVCC_1P8

VDDA_1P8

BUCK3

1.8V

500mA

0.47uH

VDD_SNVS_IN

Coin

SNVSC

10uF

1uF

100

PGND3

PVIN4

22pF

XIN

32kHz

OSC

VSYS

32.768kHz-Xtal

22pF

4.7uF

BUCK4

LX4

FB4

XOUT

BUCK4

1.2V

1000mA

SNVSC

NVCC_DRAM

LPDDR3

0.47uH

10kΩ

CLK32KOUT

10uF

RTC

PGND4

2.2kΩ

DVDD

BUCK3

10kΩ 10k

SDA

SCL

INTB

PVIN5

VSYS

I2C

4.7uF

BUCK5

LX5

FB5

BUCK5

3.3V

1000mA

For_Peripheral

0.47uH

VOLPSR

10uF

10kΩ

POR

PGND5

Control

DVREFIN

1uF

READY

LDO_DVREF

DVREFIN*0.5 V

VODVREF

DDR_VREF

10mA

SNVSC

POWER

CNT

10kΩ

RESETINB

WDOGB

PWRON

LDO LPSR

1.8V

100mA

VDD_LPSR

NVCC_GPIO1

1uF

PMIC_ON_REQ

VOLPSR

STANDBY

PVIN6

PMIC_STBY_REQ

VINL1

1uF

1.5MΩ

VSYS

LDO1

3.3V

100mA

VO1

1uF

HX6

LX6

NVCC_GPIO2

4.7uH

SBD

White LED

Boost

Converter

MAX:25mA

LDO2

3.3V

100mA

VO2

1uF

NVCC_3P3

0.47uF

VO6

VSYS

VINL2

VO3

1uF

LDO3

3.3V

50mA

VDDA_USB1_3P3

VDDA_USB2_3P3

FB6

1uF

VO4

PGND6

SD Card/eMMC

LDO4

3.3V

400mA

2.2uF

1uF

LDO4VEN

1.5MΩ

VO5

SD Card/eMMC

Interface

LDO5

1.8V/3.3V

250mA

LDO5VSEL

1.5MΩ

DCIN

Option(UP to 2A)

VSYS

DCIN

VSYS

1uF

10uF

PGATE

VBAT

10uF

CHGREF

CHGLED

LIB-CHARGER

Charge Current = 500mA max

OVP<30V

5.1kΩ

Battery pack

TS

BATTP

BATTM

Coulomb

Counter

RSENS

10mΩ

CHGGND

Figure 2. IC Block Diagram

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Pin Configuration

BOTTOM VIEW

GND

HX6

FB6

PVIN3

PVIN6

VO6

LX3

FB3

PGND3

SNVSC

PGND4

LX4

VO4

VO5

GND

FB2

VO2

VO1

FB1

LX1

GND

PVIN4

VINL2

PGND2

LX2

J

H

G

F

LX6

PGND5

LX5

SDA

VODVREF

FB4

LDO4

VEN

PGND6

DVDD

GND

SCL

DVREFIN

RESET

INB

GND

INTB

PVIN5

XOUT

XIN

FB5

STANDBY

GND

POR

E

GPO1

PWRON

READY

DCIN

WDOGB

GND

VO3

PVIN2

VINL1

PGND1

D

C

B

A

CLK32K

OUT

LDO5

VSEL

BATTP

CHGGND

VBAT

TS

CHGLED

VOLPSR

PVIN1

DCIN

VIN

PGATE

BATTM

CHGREF

VSYS

1 2 3 4 5 6 7 8 9

Figure 3. Pin Configuration (Bottom View)

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Pin Descriptions

Table 1. BD71815AGW Pin Descriptions

Ball No. Block Name Terminal Name I/O Explanation

Internal Pull up/down

A7

A8

B8

E3

A9

B9

D9

E9

E8

F9

J3

BUCK1

PVIN1

LX1

FB1

STANDBY

PGND1

PVIN2

LX2

I

Input power supply for BUCK1

O Switch node connection for BUCK1

I

-

I

Output voltage feedback for BUCK1

Standby input signal

Power ground for BUCK1

Input power supply for BUCK2

Pull down 1.5MΩ to GND

BUCK2

BUCK3

O Switch node connection for BUCK2

FB2

I

-

I

Output voltage feedback for BUCK2

Power ground for BUCK2

Input power supply for BUCK3

PGND2

PVIN3

LX3

J4

O Switch node connection for BUCK3

H4

J5

H9

J8

FB3

I

-

I

Output voltage feedback for BUCK3

Power ground for BUCK3

Input power supply for BUCK4

PGND3

PVIN4

LX4

BUCK4

O Switch node connection for BUCK4

H7

J7

FB4

I

-

I

Output voltage feedback for BUCK4

Power ground for BUCK4

Input power supply for BUCK5

PGND4

PVIN5

LX5

E1

F1

E2

G1

H3

J2

BUCK5

O Switch node connection for BUCK5

FB5

I

-

I

Output voltage feedback for BUCK5

Power ground for BUCK5

Input power supply for BOOST

PGND5

PVIN6

HX6

LX6

VO6

LED Driver

O Switch node connection for BOOST

O BOOST output

I

-

H1

G3

H2

G2

B7

C9

C8

D8

D7

G9

H8

G8

G6

C4

G7

H6

J6

FB6

Output voltage feedback for BOOST

Power ground for BOOST

PGND6

VOLPSR

VINL1

VO1

VO2

VO3

VINL2

VO4

VO5

LDO4VEN

LDO5VSEL

DVREFIN

VODVREF

SNVSC

LDOLPSR

LDO

O LDO output for LPSR

LDO input for LDO1, LDO2 and LDO3

I

O LDO output for LDO1

O LDO output for LDO2

O LDO output for LDO3

I LDO input for LDO4 and LDO5

O LDO output for LDO4

O LDO output for LDO5

I

LDO4 Enable

LDO5 Output Voltage select

LDO input for DVREF/CLK32KOUT H-level(note3)

Pull down 1.5MΩ to GND

DVREF

SNVS

O LDO output for DVREF

O LDO output for SNVS (requires capasitor)

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Table 2. BD71815AGW Pin Descriptions (continued)

Ball No. Block Name Terminal Name I/O Explanation

Pull up/down

G4

H5

G5

C1

D1

C3

C2

F3

E7

F7

D3

B2

A1

A2

B1

A3

A4

A5

B4

C6

A6

C5

B6

B5

C7

D2

B3

J1

I2C

RTC

DVDD

SDA

SCL

I

Power Supply for I2C interface

I/O I2C data line (Open drain)

I

O 32.768kHz-Xtal output

O 32.768kHz clock output (Open drain/CMOS)

note1

I2C clock

32.768kHz-Xtal input

XIN

XOUT

CLK32KOUT

PWRON

RESETINB

POR

POWRCNT

I

Power on/off control input

Reset input to shutdown this device

Pull down 1.5MΩ to GND

Pull up 10kΩ to SNVSC

note2

Pull up 1.5MΩ to VIN

note2

O Power on reset output (Open drain)

O Interrupt signal to processor (Open drain)

I

INTB

WDOGB

READY

DCIN

VSYS

VBAT

PGATE

TS

CHGREF

BATTP

BATTM

CHGGND

CHGLED

GPO1

VIN

GND

Watchdog input from processor

O PMIC ready output

OVP

I

DCIN input

O System supply output

I/O Charger output / Battery input

O External power MOS gate control output

I

O Internal reference for the Lib charger

I

CHARGER

Battery pack thermistor voltate sense

Current sense input (battery pack side)

Current sense input (ground side)

Ground for Charger

-

O Charging status indication output (Open drain)

O Output for general purpose

GPO

Power/GND

I

-

Input power supply

Signal ground

Signal ground (for reduce Thermal resistance)

J9

F2

F8

D5

D6

E4

E5

E6

F4

F5

F6

GND

note1 : SDAand SCL need pull up resistance to DVDD.

note2 : POR, INTB and READYneed pull up resistance.

note3 : When CLK32KOUT is selected to CMOS output mode.

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BD71815AGW

PCB Layout Recommendations

BUCK1

VOLPSR

LDO1

Crystal

LDO2

LDO3

BUCK5

LDO1-3

BUCK2

LDO5

LDO4

VODVREF

LED Driver

BUCK4

SNVSC

BUCK3

Figure 4. PCB Layout Recommendations (Top View)

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Description of Blocks

1. High Efficiency Buck Converters (BUCK1 – 5) and LDOs

BD71815AGW step down converters operate at a fixed frequency of 6MHz. These converters employ Pulse Width

Modulation (PWM) under moderate to heavy load and enter Power Save Mode when used under light load. In Power Save

Mode, the step down converters operate using Pulse Frequency Modulation (PFM).

Table 3. BD71815AGW Output Power Rails

BD71815AGW

Function

i.MX7 Dual

Usage example

Power Supply Initial Output Voltage Load max Adjustable range

0.8 to 2.000V(25mVstep)

[DVS]

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

LDO1

VDD_ARM

VDD_SOC

PVIN1

PVIN2

PVIN3

PVIN4

PVIN5

VINL1

VINL2

VIN

1.1V

800mA

1000mA

500mA

1000mA

100mA

50mA

400mA

250mA

10mA

25mA

100mA

25mA

-

0.8 to 2.000V(25mVstep)

[DVS]

1.0V

NVCC_1P8 /

VDDA_1P8

NVCC_DRAM/

LPDDR3

1.8V

1.2Vto 2.7V(50mVstep)

1.1 to 1.85V(25mVstep)

1.8 to 3.3V(50mVstep)

0.8 to 3.3V(50mVstep)

0.8Vto 3.3V(50mVstep)

1.2V

Peripheral

3.3V

NVCC_GPIO2

NVCC_3P3

3.3V

LDO2

3.3V

VDDA_USB1_3P3 /

VDDA_USB2_3P3

SD Card /

LDO3

3.3V

LDO4

3.3V

eMMC

SD Card /

eMMC

LDO5

1.8V/ 3.3V

0.55 to 0.925V

(DVREFIN= BUCK4)

VODVREF

SNVSC

LDO LPSR

White LED Driver

I2C

LPDDR3

0.5*DVREFIN

VDD_SNVS

VIN

3.0V

Fixed

VDD_LPSR /

NVCC_GPIO1

VIN

1.8V

Fixed

-

VIN

up to 18V

10uAto 25mA

DVDD

SNVS

VSYS

SNVS

VIN

-

RTC

-

Charger

Coulomb Counter

-

SNVS/VSYS

Voltage monitor

-

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Table 4. Voltage Identification Code for BD71815AGW Output Power Rails

#

I2C Register

00 0000

00 0001

00 0010

00 0011

00 0100

00 0101

00 0110

00 0111

00 1000

00 1001

00 1010

00 1011

00 1100

00 1101

00 1110

00 1111

01 0000

01 0001

01 0010

01 0011

01 0100

01 0101

01 0110

01 0111

01 1000

01 1001

01 1010

01 1011

01 1100

01 1101

01 1110

01 1111

10 0000

10 0001

10 0010

10 0011

10 0100

10 0101

10 0110

10 0111

10 1000

10 1001

10 1010

10 1011

10 1100

10 1101

10 1110

10 1111

11 0000

11 0001

11 0010

11 0011

11 0100

11 0101

11 0110

11 0111

11 1000

11 1001

11 1010

11 1011

11 1100

11 1101

11 1110

11 1111

Voltage step

BUCK1

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100(note1)

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.875

1.900

1.925

1.950

1.975

2.000

BUCK2

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000(note1)

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.875

1.900

1.925

1.950

1.975

2.000

BUCK3

1.200

1.250

1.300

1.350

1.400

1.450

1.500

1.550

1.600

1.650

1.700

1.750

1.800(note1)

1.850

1.900

1.950

2.000

2.050

2.100

2.150

2.200

2.250

2.300

2.350

2.400

2.450

2.500

2.550

2.600

2.650

2.700

BUCK4

1.100

1.125

1.150

1.175

1.200(note1)

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

BUCK5

1.800

1.850

1.900

1.950

2.000

2.050

2.100

2.150

2.200

2.250

2.300

2.350

2.400

2.450

2.500

2.550

2.600

2.650

2.700

2.750

2.800

2.850

2.900

2.950

3.000

3.050

3.100

3.150

3.200

3.250

3.300(note1)

LDO1

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30(note1)

LDO2

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30(note1)

LDO3

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30(note1)

LDO4

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30(note1)

LDO5

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80(note1)

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30(note1)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

25mV

50mV

25mV

50mV

(note1) Default output voltage setting

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2. Power ON/OFF Sequence

3.6V

VBAT

3.6V

2.8V

2.5V

VSYS

3.0V

SNVS

2.35V

2.2V

C32KOUT

Power State SHUTDOWN

PWRON

COIN

over 100ms

SNVS

RUN

(ARM=1GHz mode)

SNVS

COIN

SHUTDOWN

Pull up to SNVS

Up to 0.25ms

0.24ms

1.8V

LPSR

(for LowPowerStateRetention)

0.49ms

0.73ms

0.98ms

1.22ms

1.46ms

1.71ms

1.94ms

2.20ms

2.44ms

3.3V

LDO1

(for NVCC_GPIO2)

1.1V

BUCK1

(for ARM)

1.0V

BUCK2

(for SOC)

1.8V

BUCK2 is turned off after BUCK4 is turned off.

BUCK3

(for VDDA_1P8, VDDA_1P8)

3.3V

LDO2

(for NVCC_3P3)

1.2V

BUCK4

(for NVCC_DRAM)

0.6V

DVREF

(for DDR VREF)

3.3V

BUCK5

(for Periphral)

3.3V

LDO5

(for eMMC)

3.3V

LDO3

(for VDDA_USB1/2_3P3)

LDO4

(for SD card)

3.91ms

POR

(Pull up to LPSR)

READY

(Pull up to DVDD)

Figure 5. Power ON/OFF Sequence

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3. States of Operation

BD71815AGW has six power states: RUN, SUSPEND, LPSR, SNVS, Coin, and Shutdown. Figure 6 shows the state

transition diagram along with the conditions to enter and exit each state.

Thermal shutdown

or

SNVS_UVLO = L

or

RESETINB = L

SHUTDOWN

Any State

SNVS_UVLO = H

(VIN > 2.35V)

SNVS_UVLO = L

(VIN < 2.2V)

VSYS_UVLO = L (VIN < 2.5V)

or

WDOGB = L and WDOGB_PWROFF = H (I2C:Reg)

COIN

SNVS

RUN

VSYS_UVLO = L

(VIN < 2.5V)

VSYS_UVLO = H

(VIN > 2.8V)

PWRON = L and LPSR_MODE = L (I2C:Reg)

PWRON = H

PWRON = L and

LPSR_MODE = L (I2C:Reg)

PWRON = Lꢀand

LPSR_MODE = H (I2C:Reg)

STANDBY = H

STANDBY = L

PWRON = H

SUSPEND

BUCK1 _{BUCK1_LP_ON = L}

and STANDBY = H

LPSR

ON

OFF

STANDBY = L

PWRON = L and LPSR_MODE = H (I2C:Reg)

Figure 6. Power States Transitions

Description of states is provided in the following section. I2C Control is not possible in Shutdown state. However, the interrupt

signal INTB is active during RUN and SUSPEND states.

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Table 5. Voltage Rails ON/OFF for Respective Power States

Power Mode

Output Control

ON/OFF

BD71815AGW

Function

Shutdown

OFF

Coin

OFF

SNVS

OFF

LPSR

OFF

RUN

Auto

SUSPEND

Auto

Sequence order

2

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

LDO1

State or I2C register

LDO4VEN

OFF

Reset

OFF

ON

OFF

ON

OFF

ON

OFF

ON

Auto

ON

Auto

ON

3

4

6

8

1

5

9

7

-

LDO2

OFF

ON

LDO3

ON

LDO4

OFF

ON

OFF/ON

OFF

ON

OFF/ON

ON

OFF/ON

ON

LDO5

State or I2C register

State

VODVREF

SNVSC

LDO LPSR

White LED Driver

I2C

ON

OFF

Disable

ON

OFF

Disable

ON

0

-

OFF

Disable

ON

OFF

Enable

ON

OFF

Enable

ON

-

RTC

State

-

Charger

Coulomb Counter

OFF

ON

ON/OFF

ON

ON/OFF

ON

ON/OFF

ON

ON/OFF

ON

DCIN

-

State

-

SNVS/VSYS

Voltage monitor

ON

-

(Note) Auto : PWM/PFM mode change automatically depending on the load current

(1) Power Control States

(a) Shutdown State

BD71815AGW enters Shutdown State when SNVS falls below 2.2V or when BD71815AGW encounters a thermal

shutdown event. In case of system hang-up, setting RESETINB to LOW will cause the IC to shut down. Only the SNVS

and VSYS voltage measurement block (UVLO) is powered during Shutdown state. Data in all registers are reset to

their initial settings. To exit Shutdown state, SNVS must exceed 2.35V.

(b) Coin State

BD71815AGW enters Coin State when SNVS exceeds 2.35V or VSYS falls below 2.5V. BD71815AGW also enters

Coin State when only the coin battery is connected to SNVSC, or when WDOGB is asserted low. BD71815AGW starts

the Off Sequence in this case.

UVLO, RTC, Battery measurement (Coulomb Counter), and SNVS blocks are powered in Coin State. All BUCK blocks

and other LDOs are powered off. Registers cannot be accessed when BD71815AGW enters this state, but register

data is retained.

(c) SNVS State

BD71815AGW enters SNVS State if PWRON is asserted low while LPSR_MODE registers are set low. SNVS State

can also be accessed from Coin State when VSYS exceeds 2.8V.

In SNVS State, BUCKs and LDOs which have the SNVS_ON register set High are turned ON. Charger is also started

when DCIN input is supplied with the appropriate voltage. These blocks are turned on in addition to blocks powered in

Coin State.

(d) LPSR State

BD71815AGW enters LPSR state if PWRON is asserted Low while LPSR_MODE registers are set high.

In LPSR State, BUCKs and LDOs which have the LPSR_ON register set high are turned ON.

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(d) RUN State

BD71815AGW enters RUN state when PWRON is asserted High. POR is negated in this state.

In RUN State, BUCKs and LDOs which have the RUN_ON register set High are turned ON. I2C registers can be

accessed in this state.

(e) SUSPEND State

BD71815AGW enters SUSPEND State from RUN State when STANDBY is asserted high.

In SUSPEND State, BUCKs and LDOs which have the LP_ON register set low are turned OFF. I2C registers can be

accessed in this state.

H

BUCK1_LP_ON

(I2C Register)

L

H

STANDBY

BUCK1

L

1.1V

0.3mS

1mS

0.3mS

0V

150uS

20mS

Power State

READY

RUN

H

SUSPEND

RUN

SUSPEND

Figure 7 – SUSPEND State Control Timing Diagram

4. Dynamic Voltage Scaling (DVS) Control

BUCK1 and BUCK2 support Dynamic Voltage Scaling (DVS). BUCK1_DVSSEL and BUCK2_DVSSEL registers control the

output voltage of BUCK1 and BUCK2, respectively. BUCK#_H controls the output voltage for when BUCK#_DVSSEL is set

high, and BUCK#_L for when BUCK#_DVSSEL is set low. Slew rate is also set via the BUCK#_RAMPRATE register.

ARM1GHz mode

BUCK1_DVSSEL

(I2C register)

ARM800MHz mode

1.1V

H

80~140uS

1.1V

H

BUCK1

READY

10mV/uS

10~40uS

10mV/uS

10~40uS

1.0V

H

L

Figure 8 - DVS Control Timing Diagram

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5. LDO4 and LDO5 Control (for SD Card)

LDO4 and LDO5 support High Speed SD Card and SD Card Interface power rails, respectively.

LDO4 is turned on and off by LDO4VEN. This function is for High Speed SD Card Reset operation.

LDO5 supports Dynamic Voltage Scaling (DVS). LDO5_H register controls the output voltage for when LDO5VSEL pin is

set high, and LDO5_L register for when LDO5VSEL pin is set low. This function supplies dynamically changing output

voltages for Normal to High Speed operation.

H

LDO4VEN

(SD_RESET)

L

H

LDO5VSEL

(SD_VSEL)

0.3mS

2.5mS

3.3V

2.5mS

3.3V

LDO4

(SD Card Power)

0V

0.5mS

2mS

0.5mS

3.3V

LDO5

0.3mS

1.8V

(SD Card Interface)

1mS

Figure 9 – SD Card Interface Control Timing Diagram

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6. Real Time Clock (RTC) Block

Features

・

RTC is driven by a 32.768 kHz oscillator and provides alarm and timekeeping functions to the nearest second.

Time information is provided in seconds, minutes, and hours.

Calendar information is provided in day, month, year, and day of the week.

Alarm interrupt is sent at the time and day programmed into registers.

Leap year compensation up to 2099

Selectable 12-hour and 24-hour modes

RTC calibration support

Oscillator failure detection

VIN

LDO_SNVS

（3.0V, 25mA）

SNVSC

VDD_SNVS

1uF

DET

XOUT

32.768kHz-Xtal

RTC

XIN

32kHz-OSC

CLK32KOUT

CLK32K_EN

Figure 10. RTC Block Diagram

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(1) Oscillation Adjustment

The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision.

This is done by varying the number of 1-second clock pulses once every 20 or 60 seconds.

When DEV bit in the TRIM Register is set to "0", the Oscillation Adjustment Circuit varies the number of 1-second clock

pulses once every 20 seconds. When the DEV bit in the TRIM Register is set to "1", the Oscillation Adjustment Circuit

varies the number of 1-second clock pulses once every 60 seconds.

The Oscillation Adjustment Circuit can be disabled by writing the settings "*,0,0,0,0,0,*" ( "*" represents "0" or "1" ) to the

TRIM[6:0] bits of the TRIM Register. Conversely, when such oscillation adjustment is to be made, an appropriate

oscillation adjustment value can be calculated using the equation below.

(a) When oscillation frequency is higher than target frequency

When setting DEV bit to 0:



Oscillation frequency - Target Frequency  0.1



Oscillation adjustment value 

Oscillation frequency 3.05110^6

Oscillation frequency - Target Frequency 10 1







When setting DEV bit to 1:



Oscillation frequency - Target Frequency 0.0333



Oscillation adjustment value 

Oscillation frequency 1.01710^6

Oscillation frequency - Target Frequency 30 1







Oscillation frequency: Frequency of clock pulse output from CLK32KOUT pin

Target frequency: Desired frequency to be set

Generally, a 32.768kHz quartz crystal unit has temperature characteristics that support the highest oscillation

frequency at normal temperature. Consequently, the quartz crystal unit is recommended to have target frequency

settings ranging from 32.768 to 32.76810 kHz (+3.05ppm relative to 32.768kHz).

Oscillation adjustment value: Value that is to be written to the TRIM[6:0] bits of the TRIM register

This value is represented in 7-bit coded decimal notation.

(b) When oscillation frequency is equal to target frequency

Oscillation adjustment value = 0, +1, -64, or -63.

(c) When oscillation frequency is lower than target frequency

When setting DEV bit to 0:



Oscillation frequency - Target Frequency



Oscillation adjustment value 

Oscillation frequency 3.05110^6

Oscillation frequency - Target Frequency







10

When setting DEV bit to 1:



Oscillation frequency - Target Frequency



Oscillation adjustment value 

Oscillation frequency 1.01710^6





Oscillation frequency - Target Frequency 30



Sample oscillation adjustment value calculations follow.

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(ex.A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz

When setting DEV bit to 0:

Oscillation adjustment value 

32768.8532768.05 0.1

32768.853.05110^6





32768.8532768.05



10 1

 9

In this instance, write the settings "00001001" in the TRIM register. Thus, an appropriate oscillation adjustment value

in the presence of any time count gain represents a distance from 01h.

When setting DEV bit to 1:

32768.8532768.05 0.0333

Oscillation adjustment value 

32768.851.01710^6





32768.8532768.05



30 1

 25

In this instance, write the settings "10011001" in the TRIM register.

(ex.B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz

When setting DEV bit to 0:

32762.22 32768.05

32762.223.05110^6

Oscillation adjustment value 





32762.22 32768.05



10

 58

To represent an oscillation adjustment value of -58 in 7bit coded decimal notation, subtract 58 (3Ah) from 128 (80h)

to obtain 46h. In this instance, write the settings of "01000110" in the TRIM register. Thus, an appropriate oscillation

adjustment value in the presence of any time count loss represents a distance from 80h.

When setting DEV bit to 1:

32762.22 32768.05

32762.221.01710^6

Oscillation adjustment value 





32762.22 32768.05



30

 175

Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of

range.

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(3) Typical software-based operation

Initialization at Power-on

Start

CPU Power ON

No

PON = 1 ?

Yes

Set SEC ～ YEAR, TRIM,

ALM0_xxx, ALM1_xxx

registers and etc. (*1)

*1) This step involves ordinary initialization including, but not limited to,

the Oscillation Adjustment Register and interrupt cycle settings.

Set PON to 0.

Set XSTB to 1.

Writing Time and Calendar Data

Start Condition

*1) It is recommended to also modify the sec register when one writes to the

min~year registers.

When the seconds digit goes up while accessing I2C, the clock could assume an

unpredictable value.

Write Time Counter and

Calendar Counter (*1)

Writing to the sec register prevents the above behavior because less than 1Hz

counter is cleared.

Stop Condition

Reading Time and Calendar Data

Start Condition

Read from Time Counter

and Calendar Counter (*1)

*1) When reading clock and calendar counters, do not insert

Stop Condition.

Stop Condition

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ALARM0 Interrupt Process

*1) This step is intended to disable the alarm interrupt

circuit once by clearing ALM0_MASK register, in

anticipation of a coincidental match between current time

and preset alarm time as the alarm interrupt function is set.

Clear ALM0_MASK register (*1)

Set Alarm Threshold Registers

(ALM0_SEC ～ ALM0_YEAR)

*2) This step is intended to enable the alarm interrupt

function after completion of all alarm interrupt settings.

Set ALM0_MASK Register (*2)

Generate Interrupt to CPU by INTB pin

0

Check ALM0 bit of INT_STAT_12 register

1

Conduct ALM0 Interrupt

(ALM0 Interrupt cleard by writing 1 ALM0 bit of

INT_STAT_12 register)

Other Interrupt

Processes

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7. Over Voltage Protection (OVP) Block

Features

・

Single-input for the battery charger source: DCIN

30V over voltage protection for DCIN input.

8. Battery Charger Block

Features

・

Supports battery insertion and removal detection

JEITA-compliant Battery Charging Profile with thermal control of charging current and voltage settings. This is achieved

by measuring the temperature of an external thermistor (The Initial setting of BD71815AGW is adjusted to TDK

NTCG163JF103FT1S).

・

Supports battery supplement mode

Automatic or manual (software) control of Watch Dog Timer while Pre–charging and Fast-charging

Charger statuses or Error conditions are indicated on CHGLED output (for LED lighting)

Any State

VIN < 2.5V

DCINOK=L

(DCIN＜3.65V)

Shutdown

or

④

VIN > 2.8V

SUSPEND

Charge stop

①

②

To Bat Error

VBAT_OVP

Temp Err 4

DCINOK=H

(DCIN>3.8V)

BATDET_DONE

③

To SUSPEND

TRICKLE

CHARGE

TSD5

Timer > WDT_PRE

or VBAT_OVP

not ③

①

To Bat Error

Timer > 120m

Temp Err 5

②

VBAT > VPRE_LO

or VBAT_OVP

VBAT < VPRE_LO

To SUSPEND

③

TSD1

Timer > WDT_PRE

or VBAT_OVP

not ③

Batt Error

Charge stop

①

PRE CHARGE

To Bat Error

Timer > 120m

or VBAT_OVP

Temp Err 1

②

VBAT > VPRE_HI

VBAT < VPRE_HI

Timer > WDT_FST

or VBAT_OVP

To SUSPEND

③

TSD2

not ③

VSYS < VBAT

①

FAST CHARGE

To Bat Error

Timer > 120m

or VBAT_OVP

Temp Err 2

VSYS > VBAT

②

IBAT <

IFST_TERM

BATT

IBAT >

IFST_TERM

①

ASSIST 1

BATDET

Charge stop

③

VSYS < VBAT

To SUSPEND

TOP OFF

TSD3

TSD4

not ③

BATT

ASSIST 2

VSYS > VBAT

VBAT < VBAT_MNT

Timer 15sec.

To SUSPEND

③

not ③

BATT

ASSIST 3

DONE

Charge stop

VSYS < VBAT

①

To Bat Error

VBAT_OVP

Temp Err 3

Charge stop

②

VSYS > VBAT

① BAT_TEMP > 58℃ or BAT_TEMP < 2℃

② BAT_TEMP < 58℃ and BAT_TEMP > 2℃

③ Chip Temp > 135℃

④ Chip Temp > 175℃ Chip Thermal Shutdown

Figure 11. State Diagram of Battery Charger

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VBAT

IBAT

IFST

VBATCHG

Battery Voltage

Charge Current

VPRE_HI

VPRE_LO

IPRE

ITRI

IFST_TERM

(CC)

(CV)

Time

Top Off

15[S]

Trickle Charge

Pre Charge

Fast Charge

DONE

Figure 12. Battery Charger Output Control

DCINOK=H

and BATDET_EN(reg)=0

and BDETSTAT = H

Disable Battery

Detection

START

DCINOK=H

and BATDET_EN(reg)=1

DCINOK=H

and BATDET_EN(reg)=1

and BDETSTAT = H

BATLOAD

Discharge for 50ms

VBAT < VPRE_LO(reg)

VBAT > VPRE_LO(reg)

VBAT >

VBAT_MNT(reg)

Trickle Charge

Charge for 50ms

VBAT <

VBAT_MNT(reg)

Battery

Detected

Un-Detected

DCINOK =L

or BDETSTAT=L

or (Charger state = SUSPEND, BATDET, or TOP OFF)

or (Expire 1s timer and (Charger state = SUSPEND, BATDET, or TOP OFF))

or REBATDET_TRG(reg) = 0->1

DCINOK =L

BAT_DET(reg)=0

or BDETSTAT=L

BAT_DET_DONE(reg)=1

or (Charger state = SUSPEND, BATDET, or TOP OFF)

or Expire 1s timer

or REBATDET_TRG(reg) = 0->1

BAT_DET(reg)=1

BAT_DET_DONE(reg)=0

BDETSTAT Power states which is valid Battery detection.

L : Battery detection is invalid ; Power state = SHUTDOWN, or COIN

H : Battery detection is valid ; Power state = SNVS, RUN, LPSR, or SUSPEND

Figure 13. State Diagram of Battery Detection

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BD71815AGW has four Watch Dog Timers.

(a) High Temperature Protection Timer

The High Temperature Protection Timer is a timer to count the duration that battery temperature is higher than T4

(default 58°C) (BAT_TEMP[2:0]=3h) at Temp_err1, Temp_err2 or Temp_err5 state. This timer counts down 1 in

every 64 seconds and shifts to Batt Error state after 121 counts.

(b) Low Temperature Protection Timer

The Low Temperature Protection Timer is a timer to count the duration that battery temperature is less than T2

(default 2°C) (BAT_TEMP[2:0]=5h) at Temp_err1, Temp_err2 or Temp_err5 state. This timer counts down 1 in

every 64 seconds and shifts to Batt Error state after 121 counts.

(c) Watch Dog Timer for TRICKLE CHARGE and PRE CHARGE states

During Trickle-charge or Pre-charge, this timer counts down once every 64 seconds and shifts to Batt Error state

after 121 counts by default. The number of counts can be changed by register settings (WDT_AUTO and

WDT_PRE).

Table 6. Watch Dog Timer for Pre-charging and Trickle-charging

47h: CHG_SET1

threshold to

Batt Error

39h: CHG_STATE

40h: BAT_TEMP[2:0]

Initial set value

countdown value

[7] WDT_DIS

[6] WDT_AUTO

0

TRICKLE

CHARGE(01h)

or PRE CHARGE(02h)

ROOM(0h)

or HOT1(1h) or HOT2(2h)

or Temp. Disable(6h)

0

49h: WDT_PRE

122

-1

1

(d) Watch Dog Timer for FAST CHAREGE and TOP OFF states

During Fast-charge or TOPOFF, this timer counts down in every 512 seconds or 64 seconds, and shifts to Batt

Error state after 601 counts. The counter speed depends on the battery temperature. The number of the counts

can be changed by register settings (WDT_AUTO, WDT_FST, and COLD_ERR_EN).

Table 7. Fast-charging and TOPOFF Watch Dog Timer

47h: CHG_SET1

WDT_AUTO

threshold to

Batt Error

39h:CHG_STATE

40h:BAT_TEMP[2:0]

COLD1(4h)

Initial set value

countdown value

WDT_DIS

COLD_ERR_EN

0

1

0

1

0

1

0

1

0

1

0

1442

WDT_FST * 8

1442

WDT_FST * 8

1442

WDT_FST * 8

1442

-1

-2

3

FAST CHARGE(03h)

or TOP OFF(0Eh)

3

240

ROOM(0h)

or HOT1(1h) or HOT2(2h)

or Temp. Disable(6h)

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(1) Thermal Control for Charging

Charging current is controlled by the battery temperature, measured using an external thermistor.

In low-temperature condition, charging current is reduced to half of the set value ICHG.

[mA]

10°C 13.0°C

58.0°C

ICHG

2°C

1/2 ICHG

0

[°C]

5°C

55.0°C

Figure 14. Charging Current vs. Battery Temperature

Charging voltage is also reduced by temperature and set by control registers.

Table 8. Charging Voltage vs. Battery Temperature

JEITA Temperature Range

Voltage Setting Register

VBAT_CHG1

T2 – T3

2°C to 45°C, (typ)

45°C to 50°C, (typ)

50°C to 58°C, (typ)

T3 – T5

T5 – T4

VBAT_CHG2

VBAT_CHG3

Charging

Voltage

VBAT_CHG1

VBAT_CHG2

VBAT_CHG3

0

T1 T2

T3

T4

(45℃ typ) T5 (58℃ typ)

(50℃ typ)

Temperature of Battery Pack

Figure 15. Charging Voltage vs. Battery Temperature

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9. Coulomb Counter Block

BATTP

BATTM

Interrupt

& Alarm

Control

15

28-bit

Accumulator

15-bit

ΔΣ-ADC

INTB

Figure 16. Coulomb Counter Block Diagram

Features

・

28-bit Coulomb Counter for battery fuel gauging

15-bit ΔΣ-ADC measures the battery’s charge and discharge current by means of an external current sense resistor

(10mΩ, ±1% or 30mΩ, ±1%).

・

Charging/Discharging amount integration period : 1sec

There are three programmable battery capacity thresholds for interrupt.

(1) Functions and Programmabilites

(a) 28-bit accumulator features

28-bit accumulator accumulates 15-bit ΔΣ-ADC results by each 1sec. The accumulated value is shown in CCNTD

register. CCNTD value is accumulated when CCNTENB is set to 1. CCNTD value is held when CCNTENB is set to 0.

When CCNTRST is set to 1, CCNTD value is cleared to 0.

(b) Three programmable Event Alarm outputs from INTB pin

BD71815AGW has alarm events using Coulomb Counter. The elements are shown in Table 9.

Table 9. Alarm events using Coulomb Counter

Status register Interrupt register

Event

Condition

name

Coulomb counter near full capacity alarm

0 : CCNTD ≤ CC_BATCAP1_TH(reg)

1 : CCNTD > CC_BATCAP1_TH(reg)

CC_MON1

CC_MON1_DET (AMBLED is turned off and GRNLED is turned on when

CHGDONE_LED_EN(reg)=1)

0 : CCNTD ≥ CC_BATCAP2_TH(reg)

1 : CCNTD < CC_BATCAP2_TH(reg)

0 : CCNTD ≥ CC_BATCAP3_TH(reg)

1 : CCNTD < CC_BATCAP3_TH(reg)

CC_MON2

CC_MON3

OCUR1

CC_MON2_DET Coulomb counter general alarm 2

CC_MON3_DET Coulomb counter general alarm 3

0 : CURCD < OCURTHR1_TH(reg)

OCUR1_DET

Battery over current alarm 1

OCUR1_RES

1 : CURCD ≥ OCURTHR1_TH(reg) more than OCURDUR1(reg) time

0 : CURCD < OCURTHR2_TH(reg)

OCUR2_DET

OCUR2

Battery over current alarm 2

OCUR2_RES

1 : CURCD ≥ OCURTHR2_TH(reg) more than OCURDUR2(reg) time

0 : CURCD < OCURTHR3_TH(reg)

OCUR3_DET

OCUR3

Battery over current alarm 3

OCUR3_RES

1 : CURCD ≥ OCURTHR3_TH(reg) more than OCURDUR3(reg) time

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10. 12-bit ADC (SAR) Block

Features

・

12-bit Successive Approximation Register A/D Converter

Conversion period: 40μs

Input Voltage range: 0.4V to 5.6V (VBAT for Battery voltage monitor)

Input Voltage range: 0.5V to 7.0V (VSYS for System input voltage monitor)

Input Voltage range: 0.1V to 1.4V (Vf for BD71815AGW die temperature monitor)

Input Voltage range: 0.1V to 1.4V (TS for Battery temperature monitor)

Input Voltage range: -30mV to 30mV (BATTP for Battery current monitor)

Input Voltage range : 1.2V to 16.8V (DCIN for DCIN voltage monitor)

CHGREF

Reference

BATTP

TS

VBAT

Control

Logic

AFE

and

12-bit

SAR ADC

Switch

Vf

VSYS

DCIN

OSC

Figure 17. 12-bit ADC Block Diagram

11. Battery Monitor Block

BD71815AGW has alarm events using 12-bit SAR ADC. The elements are shown in Table 10.

Table 10. Alarm events using 12-bit SAR ADC

Status register

name

Interrupt register

name

Monitor terminal Event

Battery voltage exceeds over voltage

Condition

0 : VBAT ≤ VBAT_OVP(reg) - 150mV

1 : VBAT ≥ VBAT_OVP(reg)

VBAT_OV_DET

VBAT_OV_RES

VBAT_OV

LOW_BAT

VBAT_SHORT

DBAT_DET

VRECHG_DET

N/A

VBAT

VSYS

DCIN

TS

0 : VBAT > VBAT_LO(reg)

1 : VBAT ≤ VBAT_LO(reg)

VBAT_LO_DET

VBAT_LO_RES

Battery voltage fall below low voltage

Battery shorted to GND

0 : VBAT ≥ 1.6V

1 : VBAT ≤ 1.5V

VBAT_SHT_DET

VBAT_SHT_RES

0 : Not detected

DBAT_DET

Dead battery detection

1: Detected = VBAT ≤ VBAT_LO(reg) more than TIM_DBP(reg) time

0 : VBAT > VBAT_MNT(reg)

1 : VBAT ≤ VBAT_MNT(reg)

BAT_MNT_IN

BAT_MNT_OUT

Battery voltage fall below to re-charge voltage

Battery voltage general alarm

VSYS voltage fall below low voltage

VSYS voltage general alarm

Detect :VBAT ≥ VBAT_TH(reg) -> VBAT ≤ VBAT_TH(reg)

Resume : VBAT ≤ VBAT_TH(reg) -> VBAT ≥ VBAT_TH(reg)

VBAT_MON_DET

VBAT_MON_RES

0 : VSYS ≤ VSYS_MIN(reg)

1 : VSYS ≥ VSYS_MAX(reg)

VSYS_LO_DET

VSYS_LO_RES

VSYS_LO

N/A

Detect : VSYS ≥ VSYS_TH(reg) -> VSYS ≤ VSYS_TH(reg)

Resume : VSYS ≤ VSYS_TH(reg) -> VSYS ≥ VSYS_TH(reg)

VSYS_MON_DET

VSYS_MON_RES

0 : DCIN ≥ DCIN_CLPS(reg)

1 : VSYS < DCIN_CLPS(reg)

DCIN_CLPS_IN

DCIN_CLPS_OUT

DCIN_CLPS_DET

N/A

DCIN anti-collapse detection

Detect : DCIN ≥ DCIN_TH(reg) -> DCIN ≤ DCIN_TH(reg)

Resume : DCIN ≤ DCIN_TH(reg) -> DCIN ≥ DCIN_TH(reg)

DCIN_MON_DET

DCIN_MON_RES

DCIN voltage general alarm

OVTMP_DET

OVTMP_RES

0 : Not detected

OVBTMP

LOBTMP

N/A

Battery over temperature detection

Battery low temperature detection

Die temperature general alarm

Die temperature over 125°C detection

1 : Detected : BTMP < OVBTMPTHR(reg) more than OVBTMPDUR(reg) time

LOTMP_DET

LOTMP_RES

0 : Not detected

TS

1 : Detected : BTMP > LOBTMPTHR(reg) more than LOBTMPDUR(reg) time

Detect : VF ≤ VF_TH(reg) -> VF > VF_TH(reg)

Resume : VF > VF_TH(reg) -> VF ≤ VF_TH(reg)

VF_DET

VR_RES

Vf

Detect : VF ≤ 125°C -> VF > 125°C

Resume : VF > 125°C -> VF ≤ 125°C

VF125_DET

VR125_RES

N/A

Vf

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12. White LED Boost Converter

Features

・

Support series 6 LED lights for front light

LED is ON/OFF by I2C register

LED Current range : 10,20,30,50,70,100,200,300,500,700 uA,1~25mA(1mA Step)

Protection Function : Over Current Protection, Over Voltage Protection, Short Circuit Protection

13. I2C Bus Interface Block

The I2C-compatible synchronous serial interface provides access to programmable functions and registers on the

device.

This protocol uses a two-wire interface for bi-directional communication between LSI’s connected to the bus.

The two interface lines are Serial Data Line (SDA), and Serial Clock Line (SCL). These lines should be connected

to the power supply DVDD by a pull-up resistor and remain high even when the bus is idle.

(1) Start and Stop Conditions

When SCL is high, pulling SDA low produces a start condition, while pulling SDA high produces a stop condition.

Every instruction is started when a start condition occurs and terminated when a stop condition happens.

During read, a stop condition causes reading to terminate, after which the chip enters the standby state.

During write, a stop condition causes the fetching of write data to terminate, after which writing starts automatically.

When writing is completed, the chip enters the standby state.

Two or more start conditions cannot be entered consecutively.

t_SU.STA t_HD.STA

t_SU.STO

SCL

SDA

Start

condition

Stop

condition

Figure 18. Start and Stop Conditions

(2) Modifying Data

Data on the SDA input can be modified while SCL is low. When SCL is high, modifying the SDA input means a

start or stop condition.

t_SU.DAT

t_HD.DAT

SCL

SDA

Modify data

Figure 19. Modifying Data

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(3) Acknowledge

Data is transmitted and received in 8-bit units. The receiver sends an acknowledge signal by outputting low on

SDA in the 9th clock cycle, indicating that it has received data normally. The transmitter releases the bus in the 9th

clock cycle to receive an acknowledge signal.

During write, the chip is always the receiver so that it outputs an acknowledge signal each time it has received

eight bits of data.

During read, the chip outputs an acknowledge signal after it receives an address following a start condition. Then,

it outputs read data and releases the bus to wait for an acknowledge signal from the master. When it detects an

acknowledge signal, it outputs data at the next address if it does not detect a stop condition. If the chip does not

detect an acknowledge signal, it stops read operation and enters the standby state wherein a stop condition

occurs subsequently.

If the chip does not detect an acknowledge signal nor a stop condition, it keeps the bus released.

9

1

8

SCL

SDA

Start condition

Acknowledge output

Figure 20. Acknowledge

(4) Device Addressing

After a start condition occurs, a 7-bit device address and a 1-bit read/write instruction code are sent as input to

the chip. The device address occupies the upper seven bits, which must always be “1001011”.

The least significant bit (R/W:READ/WRITE) indicates a read instruction when set to 1 and a write instruction

when set to 0. An instruction is not executed if the device address does not match the specified value.

Device address is “ 1001011”.

Read/write instruction

code

Device address

1

0

1

0

1

１

R/W

MSB

LSB

Figure 21. Device Addressing

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(5) Write/Read operation

Write, single register

S

Slave Address

W

A

Sub Address #a

A

Write Data (a)

A

P

7

0

7

0

7

1

Write, 2 registers

S

Slave Address

W

A

Write Data (a+1)

A P

7

1

7

0

Write, N- registers in continuous addresses

S

Slave Address

W

A

Sub Address #a

7

1

7

0

Write Data (a+1)

A

Write Data (a+N-1)

0

A P

7

Read, single register

_

S

Slave Address

W A

Sub Address #a

A

Sr

Slave Address

R

A

Read Data (a)

P

A

7

1

7

0

7

1

7

0

Read, 2 registers

_

S

Slave Address

W A

R

A

Read Data (a+1)

P

A

7

1

7

0

Read, N- registers in continuous addresses

S

Slave Address

W A

Sub Address #a

7

1

7

0

_

Read Data (a+1)

A

Read Data (a+N-1)

0

P

A

7

: START

condition

: STOP

condition

x

S

Sr

W

R

P

A

: drived by Master

: drived by Slave

A

: Write (=”L”)

: Read (=”H”)

: ACK (=”L”)

: NACK (=”H”)

_

A

Figure 22. I2C Write / Read Operation

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(6) Pulling up the SDA and SCL pins

This IC requires SDA and SCL pins to be pulled up with an external resistor. The values of the pull-up resistors

are determined by the capacitance of the bus. Exceedingly large resistance combined with a given bus

capacitance will result to a rise time that would violate the maximum rise time specification. On the other hand,

insufficiently small resistance will result in a contention with the pull-down transistor on either slave or master. The

recommended pull-up resistance range is 1kohm to 5kohm.

Consider the DVDD related input threshold of VIH = 0.7xVDD and VIL = 0.3xVDD for the purposes of RC time

constant calculation.

V(t1) = 0.3 × DVDD = DVDD (1 − e^{−t1 / RC}); then t1 = 0.3566749 × RC

V(t2) = 0.7 × DVDD = DVDD (1 − e^{−t2 / RC}); then t2 = 1.2039729 × RC

T = t2 − t1 = 0.8473 × RC

To determine the value of the pull-up resistance, you can calculate it by using the equation R=t/(0.8473C)．

t : SDA, SCL rise time to meet the I2C AC specification

C : Total bus capacitance on each SDA, SCL line

(7) Limitation of I2C

Write data is synchronized with the internal clock (32.768 kHz RTC crystal clock). If internal FIFO is full, an

acknowledge is not generated for write operations. An example of this situation is continuous addressing access

with more than 294 kHz in I2C.

With I2C single write mode, BD71815AGW write the register after 3 or 4 RTC crystal clock time when stop

condition is happened.

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14. Interrupt Handling

The system is informed about important events through interrupts. Enabled interrupt events are signaled to the

processor by driving the INTB pin low.

Each interrupt can be disabled by setting the corresponding enable bit to 0.

Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until

cleared. Each interrupt can be cleared by writing “1” to the appropriate bit in the Interrupt Status register; this will

also cause the INTB pin to go high. If there are multiple interrupt bits, the INTB pin will remain low until all are

cleared. If a new interrupt occurs while the processor clears an existing interrupt bit, the INTB pin will remain low.

The IC powers up with all interrupts disabled, so the processor must initially poll the device to determine if any

interrupts are active. Alternatively, the processor can enable the interrupt bits of interest.

Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the

debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in

the Interrupt summary. Due to the asynchronous nature of the debounce timer, the effective debounce time can

vary slightly.

Table 11. Interrupt summary

Register Map

Enable Status/Clear

Address bit Address bit

Register Map

Debounce

Interval

(3 times match)

Debounce

Interval

(3 times match)

Enable

Status/Clear

Address

Interrupt Event

Address

90

91

92

93

94

95

96

bit

4

1

0

7

6

5

4

3

2

1

0

2

1

0

5

4

3

2

1

0

7

6

5

4

3

2

1

0

2

1

0

bit

4

1

0

7

6

5

4

3

2

1

0

2

1

0

5

4

3

2

1

0

7

6

5

4

3

2

1

0

2

1

0

LED_SCP

LED_OCP

LED_OVP

8B

8C

8D

8E

8F

90

7

6

5

4

3

2

1

0

5

4

3

2

1

6

1

0

7

6

3

2

1

0

7

6

5

4

3

2

0

7

6

5

98

99

9A

9B

9C

9D

7

6

5

4

3

2

1

0

5

4

3

2

1

6

1

0

7

6

3

2

1

0

7

6

5

4

3

2

0

7

6

5

1kHz

4kHz

1kHz

RTC

4kHz

128Hz

none

1kHz

RTC

BAT_RMV

TMP_OUT_DET

TMP_OUT_RES

VBAT_OV_DET

VBAT_OV_RES

VBAT_LO_DET

VBAT_LO_RES

VBAT_SHT_DET

VBAT_SHT_RES

DBAT_DET

VBAT_MON_DET

VBAT_MON_RES

CC_MON3_DET

CC_MON2_DET

CC_MON1DET

OCUR3_DET

OCUR3_RES

OCUR2_DET

OCUR2_RES

OCUR1_DET

OCUR1_RES

VF_DET

9D

9E

9F

A0

A1

A2

A3

128Hz

1Hz

BUCK5FAULT

BUCK4FAULT

BUCK3FAULT

BUCK2FAULT

BUCK1FAULT

DCIN_OV_DET

DCIN_OV_RES

DCIN_CLPS_IN

DCIN_CLPS_OUT

DCIN_RMV

128Hz

1Hz

WDOGB

1Hz

DCIN_MON_DET

DCIN_MON_RES

VSYS_MON_DET

VSYS_MON_RES

VSYS_LO_DET

VSYS_LO_RES

VSYS_UV_DET

VSYS_UV_RES

CHG_TRNS

4kHz

1Hz

VF_RES

VF125_DET

VF125_RES

OVTMP_DET

OVTMP_RES

LOTMP_DET

LOTMP_RES

ALM2

1Hz

TMP_TRNS

128Hz

1Hz

BAT_MNT_IN

BAT_MNT_OUT

CHG_WDT_EXP

EXTEMP_TOUT

BTA_ILIM

TH_DET

TH_RMV

BAT_DET

RTC

128Hz

1Hz

128Hz

ALM1

ALM0

128Hz

Note1: 1 kHz of this table means 1.024 kHz, and 4 kHz of this table means 4.096 kHz.

INTB

BD71815AGW

INT_UPDATE(reg)

Interrupt Enable

Reset

Event Source

3 times

match

D

Q

:

Interrupt

Status

Sampling clock

=Debounce interval

INT_STAT

(Addr=97h)

:

Figure 23 Interrupt Block Diagram

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Absolute Maximum Ratings (Ta=25°C)

Parameter

Symbol

Rating

30

Unit

V

Maximum Supply Voltage 1

DCIN

VDCIN_MAX

VIN_MAX

PVIN_MAX

VINL_MAX

VBAT_MAX

Maximum Supply Voltage 2

VIN, PVIN1,2,3,4,5,6

VINL1, VINL2, VBAT

6

V

Maximum Supply Voltage 3

DVDD

VDVDD_MAX

4.5

30

V

Maximum Input Voltage 1

VO6, LX6

VO6IN_MAX

LX6IN_MAX

Maximum Input Voltage 2

FB1,2,3,4,5,6, LX1,2,3,4,5, HX6,

VO1,2,3,4,5,VOLPSR, DVREFIN,

VODVREF, CLK32KOUT,

POR, INTB, READY, VSYS,

PGATE, CHGLED, GPO1,

PWRON, STANDBY, RESETINB,

WDOGB, LDO4VEN, LDO5VSEL,

SDA, SCL, XIN, XOUT,

VMAXIN_MAX

6

V

TS, BATTP, BATTM

Maximum Input Voltage 3

SNVSC

VSNVSCIN_MAX

VCHGREF_MAX

4.5

V

Maximum Input Voltage 4

CHGREF

VSNVSCIN_MAX+ 0.3

Operating Temperature Range

Topr

Tstg

-40 to +85

℃

Storage Temperature Range

-55 to +125

Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over

the absolute maximum ratings.

Thermal Resistance^{(Note 1)}

Parameter

Symbol

Thermal Resistance (Typ)

69.0

Unit

UCSP55M4C(BD71815AGW)

Junction to Ambient

θ_JA

°C/W

(Note 1)Based on Rohm’s standard board

Recommended Operating Conditions

Parameter

Symbol

Limits

Unit

V

Input Voltage Range 1

DCIN

VDCIN

3.5 to 28

Input Voltage Range 2^(Note2)

VIN, PVIN1,2,3,4

VIN

PVIN

2.9 to 5.5

V

Input Voltage Range 3

VINL1, VINL2

VINL1

VINL2

1.8 to 5.5

1.5 to 3.4

V

Input Voltage Range 4

DVDD

VDVDD

(Note2) It is necessary to supply the same voltage to VIN, and PVIN1,2,3,4

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TSZ22111・15・001

BD71815AGW

Electrical Characteristics

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

Symbol

Unit

Condition

Min

Max

Quiescent Circuit Current

RTC, Coulomb Counter,

VBAT Circuit Current 1

(SNVS Mode)

IQVB1

IQVB2

-

20

50

70

μA

and LDO_SNVS are ON

DCINOK=L, DVDD=0V

RTC, Coulomb Counter,

LDO_SNVS, LDO_LPSR,

and LDO1 are ON

VBAT Circuit Current 2

(LPSR Mode)

150

DCINOK=L, DVDD=0V

RTC, Coulomb Counter,

BUCK2,3,4 (Auto Mode),

LDO_SNVS, LDO_LPSR,

and LDO1,2,3 are ON

VBAT Circuit Current 3

(SUSPEND Mode)

IQVB3

-

150

200

μA

DCINOK=L, DVDD=0V

RTC, Coulomb Counter,

BUCK1,2,3,4,5 (PWMfixMode),

LDO_SNVS, LDO_LPSR, LDO_DVREF

and LDO1,2,4,5 are ON

DCINOK=L, DVDD=0V

VBAT Circuit Current 4

(RUN Mode)

IQVB4

-

45

-

70

1

mA

DVDD Circuit Current

IQDVDD

μA

Voltage Detector – VIN Under Voltage

VIN sweep down

SNVS to Coin state

VIN sweep up

Detect Voltage

UVLOVIN

2.4

2.7

2.5

2.8

2.6

2.9

V

Release Voltage

RUVLOVIN

Coin to SNVS state

Voltage Detector – SNVS Under Voltage

VIN sweep down

Coin to Shutdown state

VIN sweep up

Detect Voltage

UVLOSNVS

2.0

2.2

2.4

V

Release Voltage

RUVLOSNVS

2.15

2.35

2.55

Shutdown to Coin state

GPO1

Output L Level

VOL_GPO

IOFF_GPO

-

0.4

1

V

I_IN= 1mA

Output Off Leak current

-1

0

μA

VIN=VGPO=5.5V

Digital pin characteristics - Input1 (PWRON, STANDBY, WDOGB, LDO5_VSEL, LDO4_EN)

Input "H" level

Input "L" level

VIH1

VIL1

1.44

-

V

0.4

STANDBY, WDOGB, LDO4_VEN,

LDO5_VSEL

RPD1

-

1.5

-

MΩ

Pull Down Resistance

Digital pin characteristics – Input2 (RESETINB)

RESETINB

VIH2

2.1

-

0.9

-

V

SNVS*0.7V

SNVS*0.3V

Input "H" level

RESETINB

Input "L" level

VIL2

-

RESETINB

Pull Up Resistance

RPU2

10

kΩ

Digital pin characteristics – Input3 (SCL, SDA)

SCL,SDA

Input "H" level

SCL,SDA

Input "L" level

SCL,SDA

Input leak current

DVDD

x0.7

DVDD

+ 0.3

DVDD

x0.3

VIH3

VIL3

IIC3

-

V

-0.3

-1

0

1

μA

Digital pin characteristics - Output (SDA, POR, INTB,READY)

SDA

VOL1

VOL2

-

0.4

1

V

IOL=6mA

Output "L" level voltage

POR, INTB,READY

Output "L" level voltage

IOL=1mA

Output Off Leak current

IOFF_NO

-1

0

μA

VIN=VO=5.5V

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TSZ02201-0Q4Q0AB00610-1-2

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TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

BUCK1 – VDD_ ARM

Symbol

Unit

Condition

Min

Max

Initial value

Io = 200mA, PWMMode

Output Voltage

VOSW1

VORSW1

IOSW1

1.084

1.100

-

1.117

V

Programmable

Output Voltage Range

0.8

2

800

20

-

25mVstep

Output Current

Load Stability

-

mA

mV

%

ΔVLSW1

ηSW11

-

10

84

88

6

Io=1mA~800mA

VIN =PVIN=3.6V, Io = 1mA, Vo = 1.1V

Inductor Rdc=40mΩ

VIN=PVIN = 3.6V, Io = 200mA, Vo = 1.1V

Inductor Rdc=40mΩ

VIN=4.0V, Vo = 1.1V

PWMmode, Io = 0mA

-

Efficiency

ηSW12

-

%

Oscillating Frequency

Turn-on Time

FOSW1

-

MHz

usec

Ω

TONSW1

RDISSW1

LBUCK1

CBUCK1

-

500

-

Discharge Resistance

Output Inductance

-

600

0.47

10

0.22

4.7

1.0

100

μH

μF

Ta = -40℃～85℃

with BUCK's DC bias

Output Capacitance

BUCK2 – VDD_ SOC

Initial value

Io = 200mA, PWMMode

Output Voltage

VOSW2

VORSW2

IOSW2

0.985

1.000

-

1.015

V

Programmable

Output Voltage Range

0.8

2

1000

20

-

25mVstep

Output Current

Load Stability

-

mA

mV

%

ΔVLSW2

ηSW21

-

10

84

88

6

Io=1mA~800mA

VIN =PVIN=3.6V, Io = 1mA, Vo = 1.0V

Inductor Rdc=40mΩ

VIN=PVIN = 3.6V, Io = 200mA, Vo = 1.0V

Inductor Rdc=40mΩ

VIN=4.0V, Vo = 1.0V

PWMmode, Io = 0mA

-

Efficiency

ηSW22

-

%

Oscillating Frequency

Turn-on Time

FOSW2

-

MHz

usec

Ω

TONSW2

RDISSW2

LBUCK2

CBUCK2

-

500

-

Discharge Resistance

Output Inductance

-

600

0.47

10

0.22

4.7

1.0

100

μH

μF

Ta = -40℃～85℃

with BUCK's DC bias

Output Capacitance

BUCK3 – NVCC_1P8, VDDA_1P8

Initial value

Io = 200mA, PWMMode

Output Voltage

VOSW3

VORSW3

IOSW3

1.773

1.800

-

1.827

2.7

500

20

-

V

Programmable

Output Voltage Range

1.2

50mVstep

Output Current

Load Stability

-

mA

mV

%

ΔVLSW3

ηSW31

-

10

84

88

6

Io=1mA~800mA

VIN =PVIN=3.6V, Io = 1mA, Vo = 1.8V

Inductor Rdc=40mΩ

VIN=PVIN = 3.6V, Io = 200mA, Vo = 1.8V

Inductor Rdc=40mΩ

VIN=4.0V, Vo = 1.8V

PWMmode, Io = 0mA

-

Efficiency

ηSW32

-

%

Oscillating Frequency

Turn-on Time

FOSW3

-

MHz

usec

Ω

TONSW3

RDISSW3

LBUCK3

CBUCK3

-

500

-

Discharge Resistance

Output Inductance

Output Capacitance

-

600

0.47

10

0.22

4.7

1.0

100

μH

μF

Ta = -40℃～85℃

with BUCK's DC bias

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TSZ02201-0Q4Q0AB00610-1-2

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TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

BUCK4 – NVCC_DRAM

Output Voltage

Symbol

Unit

Condition

Min

Max

Initial value

VOSW4

VORSW4

IOSW4

1.182

1.200

-

1.218

1.85

1000

20

V

Io = 200mA, PWMMode

Programmable

Output Voltage Range

1.1

25mVstep

Output Current

Load Stability

-

mA

mV

%

ΔVLSW4

ηSW41

-

10

84

88

6

Io=1mA~800mA

VIN =PVIN=3.6V, Io = 1mA, Vo = 1.2V

Inductor Rdc=40mΩ

VIN=PVIN = 3.6V, Io = 200mA, Vo = 1.2V

Inductor Rdc=40mΩ

VIN=4.0V, Vo = 1.2V

PWMmode, Io = 0mA

-

Efficiency

ηSW42

-

%

Oscillating Frequency

Turn-on Time

FOSW4

-

MHz

usec

Ω

TONSW4

RDISSW4

LBUCK4

CBUCK4

-

500

-

Discharge Resistance

Output Inductance

-

600

0.47

10

0.22

4.7

1.0

100

μH

μF

Ta = -40℃～85℃

with BUCK's DC bias

Output Capacitance

BUCK5 – Peripheral

Initial value

Io = 200mA, PWMMode

Output Voltage

VOSW5

VORSW5

IOSW5

3.251

3.300

-

3.350

3.3

1000

20

-

V

Programmable

Output Voltage Range

1.8

50mVstep

Output Current

Load Stability

-

mA

mV

%

ΔVLSW5

ηSW51

-

10

92

94

6

Io=1mA~800mA

VIN =PVIN=3.6V, Io = 1mA, Vo = 3.3V

Inductor Rdc=40mΩ

VIN=PVIN = 3.6V, Io = 200mA, Vo = 3.3V

Inductor Rdc=40mΩ

VIN=4.0V, Vo = 3.3V

PWMmode, Io = 0mA

-

Efficiency

ηSW52

-

%

Oscillating Frequency

Turn-on Time

FOSW5

-

MHz

usec

Ω

TONSW5

RDISSW5

LBUCK5

CBUCK5

-

500

-

Discharge Resistance

Output Inductance

Output Capacitance

-

600

0.47

10

0.22

4.7

1.0

100

μH

μF

Ta = -40℃～85℃

with BUCK's DC bias

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TSZ02201-0Q4Q0AB00610-1-2

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TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

LDO1 - NVCC_GPIO2

Symbol

Unit

Condition

Min

Max

Initial value

Io=50mA

Output Voltage

VOL1

VORL1

IOL1

3.250

3.300

3.350

V

Programmable

Output Voltage Range

0.8

-

3.3

50mVstep

Output Current

-

100

mA

V

Io=50mA

Dropout Voltage

VODPL1

ΔVIL1

-

0.04

2

-

5

20

-

VINL1=3.2V(Vo=3.3Vsetting)

VIN =PVIN=3.5~4.5V, Io=50mA

Input Voltage Stability

Load Stability

-

mV

Ω

ΔVLL1

RDISL1

RRL1

-

10

600

60

1

Io=1mA~ 100mA

Discharge Resistance

Ripple rejection ratio

-

VIN=PVIN=4.2V, VR=-20dBV, fR=120Hz,

Io=50mA, Vo=1.2V, BW=20Hz～20kHz

Ta=-40～85C,

-

dB

μF

Output Capacitor

COL1

0.47

-

with LDO's DC bias

LDO2 - NVCC_3P3

Initial value

Io=50mA

Output Voltage

VOL2

VORL2

IOL2

3.250

3.300

3.350

V

Programmable

Output Voltage Range

0.8

-

3.3

50mVstep

Output Current

-

100

mA

V

Io=50mA

VINL1=3.2V(Vo=3.3Vsetting)

Dropout Voltage

VODPL2

ΔVIL2

-

0.04

2

-

5

20

-

Input Voltage Stability

Load Stability

-

mV

Ω

VIN =PVIN=3.5~4.5V, Io=50mA

Io=1mA~ 100mA

ΔVLL2

RDISL2

RRL2

-

10

600

60

1

Discharge Resistance

Ripple rejection ratio

-

VIN=PVIN=4.2V, VR=-20dBV, fR=120Hz,

Io=50mA, Vo=1.2V, BW=20Hz～20kHz

Ta=-40～85C,

-

dB

μF

Output Capacitor

COL2

0.47

-

with LDO's DC bias

LDO3 - VDDA_USB1,2_3P3

Initial value

Io=50mA

Output Voltage

VOL3

VORL3

IOL3

3.250

3.300

3.350

V

Programmable

Output Voltage Range

0.8

-

3.3

50

-

50mVstep

Output Current

-

mA

V

Io=50mA

VINL1=3.2V(Vo=3.3Vsetting)

Dropout Voltage

VODPL3

ΔVIL3

-

0.08

2

Input Voltage Stability

Load Stability

-

5

mV

Ω

VIN =PVIN=3.5~4.5V, Io=50mA

Io=1mA~ 50mA

ΔVLL3

RDISL3

RRL3

-

10

600

60

1

20

-

Discharge Resistance

Ripple rejection ratio

Output Capacitor

-

VIN=PVIN=4.2V, VR=-20dBV, fR=120Hz,

Io=50mA, Vo=1.2V, BW=20Hz～20kHz

Ta=-40～85C,

-

dB

μF

COL3

0.47

-

with LDO's DC bias

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TSZ02201-0Q4Q0AB00610-1-2

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36/103

TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

LDO4 - SD Card / eMMC

Output Voltage

Symbol

Unit

Condition

Min

Max

VOL4L

VORL4

IOL4

3.250

3.300

-

3.350

V

Io=50mA

Programmable

Output Voltage Range

0.8

3.3

50mVstep

Output Current

-

400

mA

V

Io=50mA

Dropout Voltage

VODPL4

ΔVIL4

-

0.03

2

-

5

20

-

VINL2=3.2V(Vo=3.3Vsetting)

Input Voltage Stability

Load Stability

-

mV

Ω

VIN =PVIN=3.5~4.5V, Io=50mA

ΔVLL4

RDISL4

RRL4

10

600

60

2.2

Io=1mA~ 400mA

Discharge Resistance

Ripple rejection ratio

-

VIN=PVIN=4.2V, VR=-20dBV, fR=120Hz,

Io=50mA, Vo=1.2V, BW=20Hz～20kHz

Ta=-40～85C,

-

dB

μF

Output Capacitor

COL4

1.0

-

with LDO's DC bias

LDO5 - SD Card / eMMC Interface

LDO5VSEL=L

Io=50mA

LDO5VSEL=H

Io=50mA

VOL5L

VOL5H

VORL5

IOL5

3.250

3.300

1.800

-

3.350

V

Output Voltage

1.773

1.827

Programmable

Output Voltage Range

0.8

3.3

V

50mVstep

Output Current

-

250

mA

V

Io=50mA

VINL2=3.2V(Vo=3.3Vsetting)

Dropout Voltage

VODPL5

ΔVIL5

-

0.04

2

-

5

20

-

Input Voltage Stability

Load Stability

-

mV

Ω

VIN =PVIN=3.5~4.5V, Io=50mA

Io=1mA~ 250mA

ΔVLL5

RDISL5

RRL5

-

10

Discharge Resistance

Ripple rejection ratio

-

600

60

VIN=PVIN=4.2V, VR=-20dBV, fR=120Hz,

Io=50mA, Vo=1.2V, BW=20Hz～20kHz

Ta=-40～85C,

-

dB

μF

Output Capacitor

COL5

0.47

1

-

with LDO's DC bias

LDO_SNVS - SNVS

Output Voltage

VOL6

IOL6

2.94

3.00

-

3.06

25

5

V

Io=10mA

Output Current

-

mA

mV

Ω

VIN= PVIN=3.5~4.5V,

Io=10mA

Input Voltage Stability

Load Stability

ΔVIL6

ΔVLL6

RDISL6

COL6

-

2

-

10

600

1

20

-

Io=1mA~ 25mA

Discharge Resistance

Ta=-40～85C,

with LDO's DC bias

Output Capacitor

0.47

-

μF

LDO_LPSR - LPSR, NVCC_GPO1

Output Voltage

VOL7

IOL7

1.773

1.800

1.827

V

Io=50mA

Output Current

-

2

100

mA

mV

Ω

VIN= PVIN=3.5~4.5V,

Io=50mA

Input Voltage Stability

Load Stability

ΔVIL7

ΔVLL7

RDISL7

COL7

-

5

20

-

10

600

1

Io=1mA~ 100mA

Discharge Resistance

Output Capacitor

Ta=-40～85C,

with LDO's DC bias

0.47

-

μF

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TSZ02201-0Q4Q0AB00610-1-2

3.Mar.2017 Rev.002

37/103

TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

LDO_DVREF- DDR_VREF

Output Voltage

Symbol

Unit

Condition

Min

Max

DVREFIN DVREFIN DVREFIN

VOL8

IOL8

V

Io=5mA

x0.49

x0.50

x0.51

Output Current

-

10

mA

mV

Ω

VIN= PVIN=3.5~4.5V,

Io=5mA

Input Voltage Stability

Load Stability

ΔVIL8

ΔVLL8

RDISL8

COL8

-

2

10

600

1

5

20

-

Io=1mA~ 10mA

Discharge Resistance

Ta=-40～85C,

Output Capacitor

0.47

-

μF

with LDO's DC bias

RTC

Input Clock Frequency

RTCLKIN

RTCLKD

STBTIME

STPDET

-

32.768

-

kHz

ppm

Output Clock FrequencyDrift

Oscillator Stabilization Time

−100

-

100

1000

150

(Note1)

-

msec

μsec

Within 3% of target frequency

Oscillator Stop Detection

RTC Output Buffer (CLK32KOUT)

Output Frequency

Output DutyCycle

Output L Level Voltage

RTCLK

RTCDTY

VOL32K

IOFF32K

-

30

-

32.768

-

70

0.4

1

KHz

%

With external crystal

I_IN= 1mA

50

-

V

VIN=VCLK32KOUT=5.5V

Open drain output OFF mode

Output Off Leak current

-1

0

μA

RTC Calibration Characteristics

Calibration Range

Step Size

RTCCR

RTCCSTP

RTCCCI

−126

-

2

126

ppm

sec

-

Correction Interval

30

Li-ion Battery Charger – OVP

DCIN UVLO release voltage

DCIN UVLO hysteresis range

DCIN OVP detection voltage

DCIN OVP hysteresis range

VSYS Output Voltage

RUVLODCIN

HUVLODCIN

OVPDCIN

HOVPDCIN

VOVSYS

3.7

100

6.3

100

4.55

-

3.8

150

6.5

150

4.75

5

3.9

200

6.7

200

4.95

10

V

mV

V

DCIN rising

DCIN falling

DCIN rising

mV

V

DCIN=5.0Vinput

Voltage Output turn-on time

DCIN leakage current in OVP state

TDCIN_ON

ILDCIN

msec

mA

-

2

DCIN < 28V

(Note1) Frequency stability over temperature depends on the characteristics of the crystal unit which is expressed as a quadratic function. Recommended crystal unit is FC-135(Seiko Epson).

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TSZ02201-0Q4Q0AB00610-1-2

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38/103

TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V, DCIN=5.0V)

Target Spec.

Parameter

Symbol

Unit

Condition

Min

Typ

Max

Li-ion Battery Charger

100mAstep

Internal MOS mode

100mAstep

External MOS mode

Ichg=500mA

VBAT=3.6V

IBATR_INT

IBATR_EXT

100

-

500

2000

-

mA

%

Fast Charging current range

IBATCHG

_ACC

Fast Charging current accuracy

Pre Charging current

±10

100

-

Initial value

VBAT=3.3V

IBATPRE

IBATPRER

IBATTRI

70

50

5

130

375

15

mA

V

Pre Charging current range

Trickle Charging current

Initial value

VBAT=3.0V

10

-

TricKle Charging Current range

IBATTRKR

VPRE_LOW

VPRE_LOWR

VPRE_HIGH

VPRE_HIGHR

VCHG

2.5

2.9

2.1

3.2

2.1

4.18

3.72

4.15

4.2

10

-

25

10mAstep

Transition Voltage from Trickle

Charging to Pre Charging

Transition Voltage range from Trickle

Charging to Pre Charging

Transition Voltage from Pre Charging

to Fast Charging

Transition Voltage range from Pre

Charging to Fast Charging

Initial value

VBAT rising

3.0

-

3.1

3.6

3.4

3.6

4.22

4.34

4.35

4.6

200

-

V

VBAT rising, 100mVstep

Initial value

VBAT rising

3.3

-

V

VBAT rising, 100mVstep

Initial value

Battery Charging voltage

4.2

-

V

Battery Charging voltage range

Battery OVP detection

VCHGR

V

20mVstep

VBOVP

4.25

-

V

Initial value

Battery OVP detection range

Charging termination current range

VBOVPR

V

50mVstep

ICHGTRMR

-

mA

%

Charging termination current

accuracy

Enter Supplement mode voltage

threshold

Exit supplement mode

voltage threshold （Hysteresis）

ON-state resistance between

SYSTEM and VBAT

Battery Error Detection Time

(Pre Charge)

ICHGTRM

_ACC

±5

60

40

150

129

641

129

15

0.5

1.5

0.1

58

2

Ichg_term=50mAsetting

VBAT-VSYS voltage

ΔVBS

ΔVBSTH

20

-

100

-

mV

mΩ

min

sec

Hz

V

RON_VBAT

TPRE

80

116

577

116

13

0.4

1.4

-

200

142

705

142

17

Battery Error Detection Time

(Fast Charge)

Battery Error Detection Time

(High Temperature protection)

TFAST

THTPRO

Over 58°C

Charging termination delay time

TTOPOFF

TCHGLED

VBATSHT

HSVBATSHT

VTH_HOT

VTH_COLD

TBAT_ACC

VTS_DIS

CHGLED output toggling

frequency

0.6

1.6

-

At Temp Error1, 2, or 5

Battery short-circuit detection voltage

Battery short-circuit detection

hysteresis range

V

Battery temperature threshold HOT

Battery temperature threshold COLD

-

°C

V

-

Battery temperature

measurement accuracy

-2

-

2

TS threshold disable voltage

Battery Open detection voltage

0.06

1.25

0.1

1.39

0.17

1.53

VTS_BATOPN

V

Measure TS voltage

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TSZ02201-0Q4Q0AB00610-1-2

3.Mar.2017 Rev.002

39/103

TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

Symbol

Unit

Condition

Min

Max

White LED Boost Converter-Switching Regurator

LED Output Current range

LED Output Current accuracy

Inducor Current limit

Boost Over Voltage limit

Switching Frequency

Turn-on Time

ILEDR

ILED_ACC

ILEDLIM

VLEDOV

fSW_LED

TONLED

LLED

0.01

-20

-

0

25

20

mA

%

ILED=10mA

900

26

-

1200

28

mA

V

24

20

-

800

500

4.7

-

kHz

usec

μH

μF

-

Output Inductance

1.0

0.22

2.2

0.47

Ta = -40℃～85℃

Output Capacitance

CLED

with BOOST DC bias

Coulomb counter

Resolution

CCRES

CCFCLK

-

15

-

bit

kHz

sec

mV

mA

A

Sign + 14-bits

xtal

Operating Clock Frequency

Integration Period

32.768

CCTCONV

CCVAIN

-

1

-

Analog Input Voltage Range

−30

-

30

-

Least Significant Bit of

ΔΣ-ADC output

CCLSB

0.33

Sense resister 30mΩ

Current Measurement Range

DC Offset current after calibration

Offset current over temperature

CCIAIN

−1.0

-3.6

-4

-

0

-

1.0

3.6

4

Sense resister 30mΩ

Ta=+25°C

Sense resister 30mΩ

Offset current variation from Ta=0°C to 60°C

CCINAIN rante

CCOFSCALIB

CCOFSCALBT

CCLIN

mA

LSB

Integral Non-Linearity(note1)

Endpoint Method

12-bit SAR ADC

Resolution

SAR_RES

SAR_FCLK

SAR_TCONV

SAR_VAIN1

SAR_VAIN2

SAR_VAIN3

SAR_DNL

-

400

40

-

12

-

bit

kHz

μsec

V

Operating Clock Frequency

Conversion Period

-

16 clocks

VBAT input

TS input

Analog Input Voltage Range 1

Analog Input Voltage Range 2

Analog Input Voltage Range 3

Differential Non-Linearity

Integral Non-Linearity

0.6

0.2

-30

-

5.6

1.2

30

-

V

-

mV

LSB

BATTP input

TS input

±3

±6

SAR_INL

-

TS input

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TSZ02201-0Q4Q0AB00610-1-2

3.Mar.2017 Rev.002

40/103

TSZ22111・15・001

BD71815AGW

(Unless otherwise specified, Ta=+25℃, VIN =PVIN=VINL=3.6V, DVDD=1.8V)

Target Spec.

Typ

Parameter

I2C Bus Interface

Symbol

Unit

Condition

Min

Max

I2C_CLK clock frequency

f_SCLH

t_HD;STA

t_LOW

0

160

60

160

0

-

400

kHz

nsec

pF

Hold time START condition

LOW period of I2C_CLK clock

HIGH period of I2C_CLK clock

-

t_HIGH

-

Set-up time for a repeated START

condition

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

C_b

Data hold time

70

-

Data set-up time

10

160

-

Set-up time for STOP condition

Capacitive load for each bus line

-

100

10

-

Pulse width of spikes that are

suppressed bythe input filter *

t_SP

0

ns

Bus Free Time

t_BUFF

1.3

us

Sr

P

t_rDA

70%

SDA

30%

t_SU;STO

t_SU;STA

t_HD;STA

t_HD;DAT

t_SU;DAT

70%

SCL

30%

t_fCL

t_LOW

t_rCL

t_LOW

t_rCL1

t_HIGH

Figure 24. I2C AC Timing – High Speed Mode

t_BUFF

SDA

t_SU:STO

SCL

P

S

Figure 25. I2C AC Timing – Bus Free Time

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TSZ02201-0Q4Q0AB00610-1-2

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41/103

TSZ22111・15・001

BD71815AGW

Register Map

OTP

(note 4)

ADRS.

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

Register Name

R/W INIT

D7

D6

D5

D4

D3

D2

DEVICEID[3:0]

WDOGB_PWROFF INHIBIT_0(note1)

PWRON_DBNC[1:0]

D1

D0

R,

R/W

DEVICE

41h I2C_UNEMPTY

LSIVER [2:0]

NA

x

PWRCTRL

R/W 22h INHIBIT_0(note1)

STBY_INV

INHIBIT_0(note1) LPSR_MODE

BUCK1_PWM_FIX BUCK1_SNVS_ON BUCK1_RUN_ON BUCK1_LPSR_ON

BUCK1_MODE

BUCK2_MODE

BUCK3_MODE

BUCK4_MODE

BUCK5_MODE

BUCK1_VOLT_H

BUCK1_VOLT_L

BUCK2_VOLT_H

BUCK2_VOLT_L

BUCK3_VOLT

BUCK4_VOLT

BUCK5_VOLT

LED_CTRL

LED_DIMM

LDO_MODE1

LDO_MODE2

LDO_MODE3

LDO_MODE4

LDO1_VOLT

LDO2_VOLT

LDO3_VOLT

LDO4_VOLT

LDO5_VOLT_H

LDO5_VOLT_L

BUCK_PD_DIS

LDO_PD_DIS

GPO

R/W 05h

BUCK1_RAMPRATE[1:0]

BUCK2_RAMPRATE[1:0]

-

BUCK1_LP_ON

BUCK2_LP_ON

BUCK3_LP_ON

BUCK4_LP_ON

BUCK5_LP_ON

x

BUCK2_PWM_FIX BUCK2_SNVS_ON BUCK2_RUN_ON BUCK2_LPSR_ON

x

BUCK3_PWM_FIX BUCK3_SNVS_ON BUCK3_RUN_ON BUCK3_LPSR_ON

-

x

BUCK4_PWM_FIX BUCK4_SNVS_ON BUCK4_RUN_ON BUCK4_LPSR_ON

-

x

BUCK5_PWM_FIX BUCK5_SNVS_ON BUCK5_RUN_ON BUCK5_LPSR_ON

-

x

BUCK1_STBY_DVS

R/W 8Ch BUCK1_DVSSEL

R/W 08h

R/W 88h BUCK2_DVSSEL

BUCK1_H[5:0]

BUCK1_L[5:0]

BUCK2_H[5:0]

BUCK2_L[5:0]

BUCK3[4:0]

x

-

x

BUCK2_STBY_DVS

x

R/W 08h

R/W 0Ch

R/W 04h

R/W 1Eh

R/W 00h

-

x

-

x

BUCK4[4:0]

x

BUCK5[4:0]

x

CHGDONE_LE

-

LED_RUN_ON LED_LPSR_ON LED_LP_ON

LED_DIMM[5:0]

LDO4_REG_MODE LDO3_REG_MODE

x

D_EN

NA

x

R/W 74h LDO1_SNVS_ON LDO1_RUN_ON LDO1_LPSR_ON LDO1_LP_ON

-

INHIBIT_0(note1)

R/W F5h LDO3_SNVS_ON LDO3_RUN_ON LDO3_LPSR_ON LDO3_LP_ON LDO2_SNVS_ON LDO2_RUN_ON LDO2_LPSR_ON LDO2_LP_ON

R/W 57h LDO5_SNVS_ON LDO5_RUN_ON LDO5_LPSR_ON LDO5_LP_ON LDO4_SNVS_ON LDO4_RUN_ON LDO4_LPSR_ON LDO4_LP_ON

x

LDO_LPSR_SNVS_ON LDO_LPSR_RUN_ON LDO_LPSR_LPSR_ON

DVREF_SNVS_ON DVREF_RUN_ON DVREF_LPSR_ON

LDO_LPSR_LP_ON

R/W 57h

R/W 32h

R/W 14h

R/W 32h

R/W 00h

DVREF_LP_ON

x

-

LDO1[5:0]

LDO2[5:0]

x

-

x

-

LDO3[5:0]

x

-

LDO4[5:0]

NA

x

-

LDO5_H[5:0]

LDO5_L[5:0]

-

BUCK5_PD_DIS BUCK4_PD_DIS BUCK3_PD_DIS BUCK2_PD_DIS BUCK1_PD_DIS

LDO5_PD_DIS LDO4_PD_DIS LDO3_PD_DIS LDO2_PD_DIS LDO1_PD_DIS

READY_FORCE_LOW

LDO_LPSR_PD_DIS

DVREF_PD_DIS

R/W 03h

R,

-

INHIBIT_0(note1) GPO1_MODE

-

INHIBIT_1(note2) GPO1_OUT

OUT32K

01h OTP_STATUS

-

S20

-

S10

-

S4

OUT32K_MODE OUT32K_EN

R/W

SEC

R/W XXh

R/W 0Xh

R/W XXh

R/W 00h

-

S40

S8

S2

M2

S1

M1

NA

MIN

-

M40

M20

H20/PA

-

M10

M8

M4

HOUR

12/24

-

H10

H8

H4

H2

H1

WEEK

-

W4

W2

W1

DAY

-

D20

D10

D8

D4

D2

D1

MONTH

-

MO10

Y10

MO8

Y8

MO4

Y4

MO2

Y2

MO1

Y1

YEAR

Y80

Y40

Y20

ALM0_SEC

ALM0_MIN

-

A0S40

A0S20

A0M20

A0H20/PA

-

A0S10

A0M10

A0H10

-

A0S8

A0M8

A0H8

-

A0S4

A0M4

A0H4

A0W4

A0D4

A0MO4

A0Y4

A0S2

A0M2

A0H2

A0W2

A0D2

A0MO2

A0Y2

A0S1

A0M1

A0H1

A0W1

A0D1

A0MO1

A0Y1

-

A0M40

ALM0_HOUR

ALM0_WEEK

ALM0_DAY

ALM0_MONTH

ALM0_YEAR

A0_12/24

-

A0D20

-

A0D10

A0MO10

A0Y10

A0D8

A0MO8

A0Y8

-

A0Y80

A0Y40

A0Y20

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42/103

TSZ22111・15・001

BD71815AGW

Register Map (continued)

OTP

(note 4)

ADRS.

Register Name

ALM1_SEC

ALM1_MIN

R/W INIT

R/W 00h

D7

D6

D5

A1S20

A1M20

A1H20/PA

-

D4

A1S10

A1M10

A1H10

-

D3

D2

A1S4

D1

D0

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

-

A1S40

A1S8

A1S2

A1S1

NA

x

-

A1M40

A1M8

A1M4

A1H4

A1M2

A1H2

A1M1

ALM1_HOUR

ALM1_WEEK

ALM1_DAY

ALM1_MONTH

ALM1_YEAR

ALM0_MASK

ALM1_MASK

ALM2

A1_12/24

-

A1H8

A1H1

-

A1W4

A1D4

A1W2

A1D2

A1W1

A1D1

-

A1D20

-

A1D10

A1MO10

A1Y10

A0_DAY

A1_DAY

-

A1D8

-

A1MO8

A1MO4

A1Y4

A1MO2

A1Y2

A1MO1

A1Y1

A1Y80

A1Y40

A0_YEAR

A1_YEAR

-

A1Y20

A0_MON

A1_MON

-

A1Y8

R/W 00h A0_ONESEC

R/W 00h A1_ONESEC

A0_WEEK

A0_HOUR

A1_HOUR

-

A0_MIN

A1_MIN

A0_SEC

A1_SEC

A1_WEEK

R/W 00h

R/W 01h

R/W 00h

-

ALM2[1:0]

TRIM

DEV

TRIM[6:0]

CONF

-

XSTB

PON

-

SYS_INIT

CHGRST

CHG_STATE

CHG_LAST_STATE

BAT_STAT

R

XXh

0Xh

XXh

0Xh

XXh

CHG_STATE[6:0]

CHG_LAST_STATE[6:0]

-

BAT_DET

BAT_DET_DONE

VBAT_OV

LOW_BAT

VBAT_SHORT

DCIN_CLPS_DET

VSYS_LO

-

DBAT_DET

DCIN_DET

DCIN_STAT

VSYS_STAT

CHG_STAT

CHG_WDT_STAT

BAT_TEMP

IGNORE_0

-

DCIN_OV

IGNORE(note3)

-

VSYS_UVN

VRECHG_DET

CHGWDTS[7:0]

-

BAT_TEMP[2:0]

IGNORE(note3) IGNORE(note3) IGNORE(note3) IGNORE(note3) IGNORE(note3) IGNORE(note3)

INHIBIT_0

R/W E6h INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_0(note1) INHIBIT_0(note1) INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_0(note1)

DCIN_CLPS

VSYS_REG

VSYS_MAX

VSYS_MIN

R/W 36h

R/W 0Bh

R/W 33h

R/W 30h

R/W 6Fh

DCIN_CLPS[11:4]

x

-

VSYS_REG[4:0]

x

-

VSYS_MAX[12:6]

x

-

VSYS_MIN[12:6]

AUTO_RECHG

x

CHG_SET1

CHG_SET2

CHG_WDT_PRE

CHG_WDT_FST

CHG_IPRE

WDT_DIS

WDT_AUTO

AUTO_FST

FST_TRG

BTMP_EN

-

COLD_ERR_EN

CHG_EN

NA

x

R/W 98h VF_TREG_EN EXTMOS_EN REBATDET_TRG BATDET_EN INHIBIT_1(note2)

TIM_CNT_SEL[1:0]

R/W 1Eh

R/W 26h

R/W 44h

R/W 12h

R/W 05h

WDT_PRE[7:0]

WDT_FST[10:3]

x

ITRI[3:0]

IPRE[3:0]

IFST[4:0]

IFST_TERM[3:0]

VPRE_LO[3:0]

VBAT_CHG1[4:0]

x

CHG_IFST

-

x

CHG_IFST_TERM

CHG_VPRE

CHG_VBAT_1

CHG_VBAT_2

CHG_VBAT_3

CHG_LED_1

VF_TH

-

x

R/W C9h VPRE_HI[3:0]

x

R/W 18h

R/W 13h

R/W 10h

R/W 03h

R/W 00h

R/W 14h

R/W 42h

R/W 01h

-

x

VBAT_CHG2[4:0]

VBAT_CHG3[4:0]

x

CHG_LED_BTA

_MASK

-

TERR[2:0]

x

VF_TH[7:0]

x

BAT_SET_1

BAT_SET_2

BAT_SET_3

ALM_VBAT_TH_U

VBAT_HI[3:0]

VBAT_LO[3:0]

x

VBAT_OVP[3:0]

-

VBAT_MNT[2:0]

x

-

VBAT_DONE[2:0]

-

TIM_DBP[2:0]

-

x

-

VBAT_TH[12]

x

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43/103

TSZ22111・15・001

BD71815AGW

Register Map (continued)

OTP

(note 4)

ADRS.

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

Register Name

ALM_VBAT_TH_L

ALM_DCIN_TH

ALM_VSYS_TH

VM_IBAT_U

R/W INIT

R/W FFh

R/W 0Fh

D7

D6

D5

D4

VBAT_TH[11:4]

DCIN_TH[11:4]

D3

D2

D1

D0

x

R/W FFh VSYS_TH[12:5]

IBAT_DIR

x

R

00h

-

IBAT[11:8]

NA

x

VM_IBAT_L

IBAT[7:0]

VM_VBAT_U

-

VBAT[12:8]

VM_VBAT_L

VBAT[7:0]

BTMP[7:0]

VTH[7:0]

VM_BTMP

VM_VTH

VM_DCIN_U

-

DCIN[11:8]

VM_DCIN_L

DCIN[7:0]

VF[7:0]

(reserved)

-

VM_VF

IBAT_OC_PRE_DIR

VM_OCI_PRE_U

VM_OCI_PRE_L

VM_OCV_PRE_U

VM_OCV_PRE_L

VM_OCI_PST_U

VM_OCI_PST_L

VM_OCV_PST_U

VM_OCV_PST_L

VM_SA_VBAT_U

VM_SA_VBAT_L

VM_SA_IBAT_U

VM_SA_IBAT_L

CC_CTRL

IBAT_OC_PRE[11:8]

IBAT_OC_PRE[7:0]

-

VBAT_OC_PRE[12:8]

VBAT_OC_PRE[7:0]

IBAT_OC_PST_DIR

-

IBAT_OC_PST[11:8]

IBAT_OC_PST[7:0]

-

VBAT_OC_PST[12:8]

VBAT_OC_PST[7:0]

VBAT_SA[12:8]

VBAT_SA[7:0]

00h IBAT_SA_DIR

00h

-

IBAT_SA[11:8]

IBAT_SA[7:0]

R/W 40h

CCNTRST

-

CCNTENB

-

CC_CALIB

-

72h CC_BATCAP1_TH_U R/W 00h

73h CC_BATCAP1_TH_L R/W 7Eh

74h CC_BATCAP2_TH_U R/W 00h

75h CC_BATCAP2_TH_L R/W 3Fh

76h CC_BATCAP3_TH_U R/W 00h

77h CC_BATCAP3_TH_L R/W 1Fh

CC_BATCAP1_TH[11:8]

CC_BATCAP2_TH[11:8]

CC_BATCAP3_TH[11:8]

CC_BATCAP1_TH[7:0]

x

-

x

CC_BATCAP2_TH[7:0]

x

-

x

CC_BATCAP3_TH[7:0]

x

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

80h

81h

82h

83h

CC_STAT

R

00h

-

CC_MON3

CC_MON2

CC_MON1

NA

x

CC_CCNTD_3

CC_CCNTD_2

CC_CCNTD_1

CC_CCNTD_0

CC_CURCD_U

CC_CURCD_L

R/W 00h

CCNTD[27:24]

CCNTD[23:16]

CCNTD[15:8]

CCNTD[7:0]

R

00h

CURDIR

-

CURCD[13:8]

CURCD[7:0]

VM_OCUR_THR_1 R/W 7Dh

VM_OCUR_DUR_1 R/W 64h

VM_OCUR_THR_2 R/W 5Eh

VM_OCUR_DUR_2 R/W 8Ch

VM_OCUR_THR_3 R/W 4Eh

OCURTHR1[12:5]

OCURDUR1[7:0]

OCURTHR2[12:5]

OCURDUR2[7:0]

OCURTHR3[12:5]

x

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TSZ22111・15・001

BD71815AGW

Register Map (continued)

OTP

(note 4)

ADRS.

Register Name

VM_OCUR_DUR_3 R/W A5h

VM_OCUR_MON 0Xh

R/W INIT

D7

D6

D5

D4

D3

D2

D1

D0

84h

OCURDUR3[7:0]

x

85h

R

-

OCUR3

OCUR2

OCUR1

NA

x

86h VM_BTMP_OV_THR R/W 8Ch

87h VM_BTMP_OV_DUR R/W 28h

OVBTMPTHR[7:0]

OVBTMPDUR[7:0]

LOBTMPTHR[7:0]

LOBTMPDUR[7:0]

x

88h

89h VM_BTMP_LO_DUR R/W 28h

0Xh

VM_BTMP_LO_THR R/W C8h

x

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

A1h

A2h

A3h

A4h

VM_BTMP_MON

INT_EN_01

INT_EN_02

INT_EN_03

INT_EN_04

INT_EN_05

INT_EN_06

INT_EN_07

INT_EN_08

INT_EN_09

INT_EN_10

INT_EN_11

INT_EN_12

INT_STAT

R

-

OVBTMP

LOBTMP

NA

R/W 00h

LED_SCP

LED_OCP

-

LED_OVP

BUCK5FAULT BUCK4FAULT BUCK3FAULT BUCK2FAULT BUCK1FAULT

DCIN_CLPS_OUT

-

DCIN_OV_DET DCIN_OV_RES DCIN_CLPS_IN

DCIN_RMV

-

WDOGB

INHIBIT_0(note1) INHIBIT_0(note1) INHIBIT_0(note1) INHIBIT_0(note1) DCIN_MON_DET DCIN_MON_RES

VSYS_LO_DET VSYS_LO_RES VSYS_UV_DET VSYS_UV_RES

BAT_MNT_IN BAT_MNT_OUT CHG_WDT_EXP EXTEMP_TOUT

INHIBIT_0(note1)

BAT_DET BAT_RMV TMP_OUT_DET TMP_OUT_RES

R/W 00h VSYS_MON_DET VSYS_MON_RES

-

R/W 00h

CHG_TRNS

TH_DET

TMP_TRNS

TH_RMV

-

R/W 00h VBAT_OV_DET VBAT_OV_RES VBAT_LO_DET VBAT_LO_RES VBAT_SHT_DET VBAT_SHT_RES DBAT_DET

-

R/W 00h

-

VBAT_MON_DET VBAT_MON_RES

CC_MON3_DET CC_MON2_DET CC_MON1_DET

-

OCUR3_DET

OCUR3_RES

VF125_RES

-

OCUR2_DET

OVTMP_DET

-

OCUR2_RES

OVTMP_RES

ALM2

OCUR1_DET

LOTMP_DET

ALM1

OCUR1_RES

LOTMP_RES

ALM0

VF_DET

VF_RES

-

VF125_DET

-

R

00h

BUCK_AST

DCIN_AST

LED_OCP

-

VSYS_AST

CHG_AST

BAT_AST

BMON_AST

TMPALE

ALM_AST

R/W

C

INT_STAT_01

INT_STAT_02

INT_STAT_03

INT_STAT_04

INT_STAT_05

INT_STAT_06

INT_STAT_07

INT_STAT_08

INT_STAT_09

INT_STAT_10

INT_STAT_11

INT_STAT_12

INT_UPDATE

-

LED_SCP

LED_OVP

BUCK5FAULT BUCK4FAULT BUCK3FAULT BUCK2FAULT BUCK1FAULT

R/W

C

DCIN_CLPS_OUT

-

DCIN_OV_DET DCIN_OV_RES DCIN_CLPS_IN

DCIN_RMV

-

R/W

C

INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_1(note2)

& IGNORE(note3) & IGNORE(note3) & IGNORE(note3) & IGNORE(note3)

WDOGB

DCIN_MON_DET DCIN_MON_RES

R/W

C

00h VSYS_MON_DET VSYS_MON_RES

-

VSYS_LO_DET VSYS_LO_RES VSYS_UVDET VSYS_UV_RES

INHIBIT_1(note2)

R/W

C

00h

CHG_TRNS

TH_DET

TMP_TRNS

TH_RMV

BAT_MNT_IN BAT_MNT_OUT CHG_WDT_EXP EXTEMP_TOUT

-

& IGNORE(note3)

R/W

C

BAT_DET

BAT_RMV

-

TMP_OUT_DET TMP_OUT_RES

R/W

C

00h VBAT_OV_DET VBAT_OV_RES VBAT_LO_DET VBAT_LO_RES VBAT_SHT_DET VBAT_SHT_RES DBAT_DET

-

R/W

C

00h

-

VBAT_MON_DET VBAT_MON_RES

CC_MON3_DET CC_MON2_DET CC_MON1_DET

R/W

C

-

R/W

C

-

OCUR3_DET

OCUR3_RES

OCUR2_DET

OCUR2_RES

OCUR1_DET

OCUR1_RES

LOTMP_RES

ALM0

R/W

C

VF_DET

VF_RES

VF125_DET

VF125_RES

OVTMP_DET

OVTMP_RES

LOTMP_DET

R/W

C

-

ALM2

ALM1

R/W

C

-

INT_UPDATE

-

A5h-

AFh

-

B0h

B1h

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

RESERVE_0

RESERVE_1

RESERVE_2

RESERVE_3

RESERVE_4

RESERVE_5

RESERVE_6

RESERVE_7

RESERVE_8

RESERVE_9

R/W 00h

RESERVE_0[7:0]

RESERVE_1[7:0]

RESERVE_2[7:0]

RESERVE_3[7:0]

RESERVE_4[7:0]

RESERVE_5[7:0]

RESERVE_6[7:0]

RESERVE_7[7:0]

RESERVE_8[7:0]

RESERVE_9[7:0]

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TSZ02201-0Q4Q0AB00610-1-2

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BD71815AGW

Register Map (continued)

OTP

(note 4)

ADRS.

Register Name

R/W INIT

D7

D6

D5

D4

D3

D2

D1

D0

BAh-

BFh

-

00h

0Fh

FFh

8Fh

FFh

00h

1Fh

FFh

00h

-

NA

C0h

C1h

C2h

C3h

VM_VSYS_U

VM_VSYS_L

VM_SA_VSYS_U

VM_SA_VSYS_L

-

R

-

VSYS[12:8]

VSYS[7:0]

-

VSYS_SA[12:8]

VSYS_SA[7:0]

C4h-

CFh

-

IBAT_SA_MIN_DIR

D0h VM_SA_IBAT_MIN_U

D1h VM_SA_IBAT_MIN_L

D2h VM_SA_IBAT_MAX_U

D3h VM_SA_IBAT_MAX_L

D4h VM_SA_VBAT_MIN_U

D5h VM_SA_VBAT_MIN_L

R

IBAT_SA_MIN[11:8]

IBAT_SA_MIN[7:0]

IBAT_SA_MAX_DIR

-

IBAT_SA_MAX[11:8]

IBAT_SA_MAX[7:0]

-

VBAT_SA_MIN[12:8]

VBAT_SA_MIN[7:0]

VBAT_SA_MAX[7:0]

VSYS_SA_MIN[7:0]

VSYS_SA_MAX[7:0]

VM_SA_VBAT_MAX_

D6h

D7h

D8h

VBAT_SA_MAX[12:8]

VSYS_SA_MIN[12:8]

VSYS_SA_MAX[12:8]

U

VM_SA_VBAT_MAX_

L

VM_SA_VSYS_MIN_

U

D9h VM_SA_VSYS_MIN_L

VM_SA_VSYS_MAX_

DAh

U

VM_SA_VSYS_MAX_

DBh

L

VM_SA_MINMAX_CL R/W

VSYS_SA_MAX_CLR VSYS_SA_MIN_CLR IBAT_SA_MAX_CLR

VBAT_SA_MAX_CLR VBAT_SA_MIN_CLR

IBAT_SA_MIN_CLR

-

DCh

-

R

-

C

-

DDh-

DFh

-

E0h

E1h

E2h

E3h

E4h

E5h

E6h

E7h

E8h

E9h

EAh

EBh

ECh

REX_CCNTD_3

REX_CCNTD_2

REX_CCNTD_1

REX_CCNTD_0

REX_SA_VBAT_U

REX_SA_VBAT_L

REX_CTRL_1

REX_CTRL_2

FULL_CCNTD_3

FULL_CCNTD_2

FULL_CCNTD_1

FULL_CCNTD_0

FULL_CTRL

R

REX_CCNTD[27:24]

REX_CCNTD[23:16]

REX_CCNTD[15:8]

REX_CCNTD[7:0]

-

REX_VBAT_SA[12:8]

REX_VBAT_SA[7:0]

REX_PMU_STA

TE_MASK

R/W 00h

REX_CLR

REX_EN

REX_DUR[1:0]

REX_CURCD_TH[7:0]

-

R

00h

FULL_CCNTD[27:24]

FULL_CCNTD[23:16]

FULL_CCNTD[15:8]

FULL_CCNTD[7:0]

R/W

C

-

FULL_CLR

-

EDh-

Efh

-

F0h

F1h

CCNTD_CHG_3

CCNTD_CHG_2

-

R/W 09h

R/W 0Ah

CHG_CCNTD[31:24]

CHG_CCNTD[23:16]

BAh-

FFh

-

00h

-

(note1) Please always write "0" to the INHIBIT-0 register when in use.

(note2) Please always write "1" to the INHIBIT-1 register when in use.

(note3) Please always ignore the read data.

(note4) Legend of the “OTP" Column: “NA“=Not OTP target, “x”=OTP target

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BD71815AGW

Address 00h: DEVICE Register (R, R/W)

Address

(Index)

Register Name

DEVICE

R/W

R, R/W I2C_UNEMPTY

41h

Bit7

Bit6

1

Bit5

LSIVER [2:0]

0

Bit4

0

Bit3

0

Bit2

Bit1

0

Bit0

1

DEVICEID[3:0]

00h

Initial Value

0

Bit 7 :

I2C_UNEMPTY [Read only]

0: The buffer passed to RTC from I2C is empty.

1: The buffer passed to RTC from I2C is not empty.

Bit 6-4 : LSIVER [2:0]

LSI Version

Device ID

Bit 3-0 : DEVICE ID[3:0]

Address 01h: PWRCTRL Register (R/W)

Address

(Index)

Register Name

PWRCTRL

R/W

32h

Bit7

Bit6

STBY_INV

0

Bit5

Bit4

LPSR_MODE

1

Bit3

Bit2

Bit1

Bit0

WDOGB_PWROFF

INHIBIT_0(note1)

0

INHIBIT_1(note2)

1

PWRON_DBNC[1:0]

INHIBIT_0(note1)

0

01h

Initial Value

0

1

Bit 7 :

Bit 6 :

INHIBIT_0(note1)

For ROHM factory only

STBY_INV

STANDBY pin polarity setting

0: STANDBY pin HIGH active

1: STANDBY pin LOW active

Bit 5 :

Bit 4 :

INHIBIT_1(note1)

For ROHM factory only

LPSR_MODE

0: Change from RUN state to SNVS state when PWRON H -> L.

1: Change from RUN state to LPSR state when PWRON H -> L.

Bit 3-2 : PWRON_DBNC[1:0]

PWRON hardware debounce time setting

PWRON_DBNC[1:0]

Time (ms)

00

01

10

11

0

31

125

750

Bit 1 :

WDOGB_PWROFF

0: Warm Reset

Select the reset mode triggered by assertion of WDOGB pin.

When WDOGB is asserted to L, Warm Reset event occurs.

POR is asserted to low for 1ms.

1: Cold Reset

When WDOGB is asserted to L, Cold Reset event occurs.

All voltage rails will be initialized and then re-boot.

And the all OTP configurable registers will be initialized.

Bit 0 :

INHIBIT_0(note1)

For ROHM factory only

Address 02h: BUCK1_MODE Register (R/W)

Address

(Index)

Register Name

BUCK1_MODE

Initial Value

R/W

05h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

BUCK1_PWM_ BUCK1_SNVS BUCK1_RUN_ BUCK1_LPSR BUCK1_LP_O

BUCK1_RAMPRATE[1:0]

-

FIX

_ON

ON

_ON

N

02h

0

1

0

1

Bit 7-6 : BUCK1_RAMPRATE[1:0]

00: 10.00mV/usec

BUCK1RAMPRATE[1:0]ꢀBUCK1 DVS ramp rate setting

01: 5.00mV/usec

10: 2.50mV/usec

11: 1.25mV/usec

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

BUCK1_PWM_FIX

0: BUCK1 operates in auto mode.

1: BUCK1 operates in PWM mode.

Cleared BUCK1_PWM_FIX bit to 0, when BUCK1 OCP failure is detected.

BUCK1_SNVS_ON

0: BUCK1 is OFF at SNVS state.

1: BUCK1 is ON at SNVS state.

Cleared BUCK1_SNVS_ON bit to 0, when BUCK1 OCP failure is detected.

BUCK1_RUN_ON

0: BUCK1 is OFF at RUN state.

1: BUCK1 is ON at RUN state.

Cleared BUCK1_RUN_ON bit to 0, when BUCK1 OCP failure is detected.

BUCK1_LPSR_ON

0: BUCK1 is OFF at LPSR state.

1: BUCK1 is ON at LPSR state.

Cleared BUCK1_LPSR_ON bit to 0, when BUCK1 OCP failure is detected.

BUCK1_LP_ON

0: BUCK1 is OFF at SUSPEND state.

1: BUCK1 is ON at SUSPEND state.

Cleared BUCK1_LP_ON bit to 0, when BUCK1 OCP failure is detected.

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BD71815AGW

Address 03h: BUCK2_MODE Register (R/W)

Address

(Index)

Register Name

BUCK2_MODE

Initial Value

R/W

05h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

BUCK2_PWM_ BUCK2_SNVS BUCK2_RUN_ BUCK2_LPSR BUCK2_LP_O

BUCK2_RAMPRATE[1:0]

-

FIX

0

_ON

0

ON

1

_ON

0

N

1

03h

0

Bit 7-6 : BUCK2_RAMPRATE[1:0]

00: 10.00mV/usec

BUCK2RAMPRATE[1:0] BUCK2 DVS ramp rate setting

01: 5.00mV/usec

10: 2.50mV/usec

11: 1.25mV/usec

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

BUCK2_PWM_FIX

0: BUCK2 operates in auto mode.

1: BUCK2 operates in PWM mode.

Cleared BUCK2_PWM_FIX bit to 0, when BUCK2 OCP failure is detected.

BUCK2_SNVS_ON

0: BUCK2 is OFF at SNVS state.

1: BUCK2 is ON at SNVS state.

Cleared BUCK2_SNVS_ON bit to 0, when BUCK2 OCP failure is detected.

BUCK2_RUN_ON

0: BUCK2 is OFF at RUN state.

1: BUCK2 is ON at RUN state.

Cleared BUCK2_RUN_ON bit to 0, when BUCK2 OCP failure is detected.

BUCK2_LPSR_ON

0: BUCK2 is OFF at LPSR state.

1: BUCK2 is ON at LPSR state.

Cleared BUCK2_LPSR_ON bit to 0, when BUCK2 OCP failure is detected.

BUCK2_LP_ON

0: BUCK2 is OFF at SUSPEND state.

1: BUCK2 is ON at SUSPEND state.

Cleared BUCK2_LP_ON bit to 0, when BUCK2 OCP failure is detected.

Address 04h: BUCK3_MODE Register (R/W)

Address

(Index)

Register Name

BUCK3_MODE

Initial Value

R/W

05h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

BUCK3_PWM_ BUCK3_SNVS BUCK3_RUN_ BUCK3_LPSR BUCK3_LP_O

-

FIX

_ON

ON

_ON

N

04h

0

1

0

1

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

BUCK3_PWM_FIX

0: BUCK3 operates in auto mode.

1: BUCK3 operates in PWM mode.

Cleared BUCK3_PWM_FIX bit to 0, when BUCK3 OCP failure is detected.

BUCK3_SNVS_ON

0: BUCK3 is OFF at SNVS state.

1: BUCK3 is ON at SNVS state.

Cleared BUCK3_SNVS_ON bit to 0, when BUCK3 OCP failure is detected.

BUCK3_RUN_ON

0: BUCK3 is OFF at RUN state.

1: BUCK3 is ON at RUN state.

Cleared BUCK3_RUN_ON bit to 0, when BUCK3 OCP failure is detected.

BUCK3_LPSR_ON

0: BUCK3 is OFF at LPSR state.

1: BUCK3 is ON at LPSR state.

Cleared BUCK3_LPSR_ON bit to 0, when BUCK3 OCP failure is detected.

BUCK3_LP_ON

0: BUCK3 is OFF at SUSPEND state.

1: BUCK3 is ON at SUSPEND state.

Cleared BUCK3_LP_ON bit to 0, when BUCK3 OCP failure is detected.

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BD71815AGW

Address 05h: BUCK4_MODE Register (R/W)

Address

(Index)

Register Name

BUCK4_MODE

Initial Value

R/W

05h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

BUCK4_PWM_ BUCK4_SNVS BUCK4_RUN_ BUCK4_LPSR BUCK4_LP_O

-

FIX

0

_ON

0

ON

1

_ON

0

N

1

05h

0

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

BUCK4_PWM_FIX

0: BUCK4 operates in auto mode.

1: BUCK4 operates in PWM mode.

Cleared BUCK4_PWM_FIX bit to 0, when BUCK4 OCP failure is detected.

BUCK4_SNVS_ON

0: BUCK4 is OFF at SNVS state.

1: BUCK4 is ON at SNVS state.

Cleared BUCK4_SNVS_ON bit to 0, when BUCK4 OCP failure is detected.

BUCK4_RUN_ON

0: BUCK4 is OFF at RUN state.

1: BUCK4 is ON at RUN state.

Cleared BUCK4_RUN_ON bit to 0, when BUCK4 OCP failure is detected.

BUCK4_LPSR_ON

0: BUCK4 is OFF at LPSR state.

1: BUCK4 is ON at LPSR state.

Cleared BUCK4_LPSR_ON bit to 0, when BUCK4 OCP failure is detected.

BUCK4_LP_ON

0: BUCK4 is OFF at SUSPEND state.

1: BUCK4 is ON at SUSPEND state.

Cleared BUCK4_LP_ON bit to 0, when BUCK4 OCP failure is detected.

Address 06h: BUCK5_MODE Register (R/W)

Address

(Index)

Register Name

BUCK5_MODE

Initial Value

R/W

05h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

BUCK5_PWM_ BUCK5_SNVS BUCK5_RUN_ BUCK5_LPSR BUCK5_LP_O

-

FIX

_ON

ON

_ON

N

06h

0

1

0

1

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

BUCK5_PWM_FIX

0: BUCK5 operates in auto mode.

1: BUCK5 operates in PWM mode.

Cleared BUCK5_PWM_FIX bit to 0, when BUCK5 OCP failure is detected.

BUCK5_SNVS_ON

0: BUCK5 is OFF at SNVS state.

1: BUCK5 is ON at SNVS state.

Cleared BUCK5_SNVS_ON bit to 0, when BUCK5 OCP failure is detected.

BUCK5_RUN_ON

0: BUCK5 is OFF at RUN state.

1: BUCK5 is ON at RUN state.

Cleared BUCK5_RUN_ON bit to 0, when BUCK5 OCP failure is detected.

BUCK5_LPSR_ON

0: BUCK5 is OFF at LPSR state.

1: BUCK5 is ON at LPSR state.

Cleared BUCK5_LPSR_ON bit to 0, when BUCK5 OCP failure is detected.

BUCK5_LP_ON

0: BUCK5 is OFF at SUSPEND state.

1: BUCK5 is ON at SUSPEND state.

Cleared BUCK5_LP_ON bit to 0, when BUCK5 OCP failure is detected.

Address 07h: BUCK1_VOLT_H Register (R/W)

Address

(Index)

Register Name

BUCK1_VOLT_H

Initial Value

R/W

8Ch

Bit7

Bit6

Bit5

0

Bit4

0

Bit3

Bit2

1

Bit1

0

Bit0

0

BUCK1_DVSS BUCK1_STBY

BUCK1_H[5:0]

EL

1

_DVS

0

07h

1

Bit 7 :

Bit 6 :

BUCK1_DVSSEL

0: Use BUCK1_L bits setting for BUCK1 output voltage.

1: Use BUCK1_H bits setting for BUCK1 output voltage.

Select BUCK1 output voltage

BUCK1_STBY_DVS

0 : DVS fucntion for BUCK1 is handled according to BUCK1_DVSSEL bit.

1 : DVS fucntion for BUCK1 is handled according to Power State: RUN/CLEAN=BUCK1_H voltage setting, SUSPEND/LPSR=BUCK1_L voltage setting.

Select the DVS control event

Bit 5-0 : BUCK1_H[5:0]

Sets the BUCK1 output voltage.

See Table 4 for all possible configurations.

Address 08h: BUCK1_VOLT_L Register (R/W)

Address

(Index)

Register Name

BUCK1_VOLT_L

Initial Value

R/W

08h

Bit7

Bit6

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

BUCK1_L[5:0]

-

08h

0

1

Bit 5-0 : BUCK1_L[5:0]

Sets the BUCK1 output voltage.

See Table 4 for all possible configurations.

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BD71815AGW

Address 09h: BUCK2_VOLT_H Register (R/W)

Address

(Index)

Register Name

BUCK2_VOLT_H

Initial Value

R/W

88h

Bit7

Bit6

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

BUCK2_DVSS BUCK2_STBY

BUCK2_H[5:0]

EL

1

_DVS

0

09h

1

Bit 7 :

Bit 6 :

BUCK2_DVSSEL

0: Use BUCK2_L bits setting for BUCK2 output voltage.

1: Use BUCK2_H bits setting for BUCK2 output voltage.

Select BUCK2 output voltage

BUCK2_STBY_DVS

0 : DVS fucntion for BUCK2 is handled according to BUCK2_DVSSEL bit.

1 : DVS fucntion for BUCK2 is handled according to Power State: RUN/CLEAN=BUCK2_H voltage setting, SUSPEND/LPSR=BUCK2_L voltage setting.

Select the DVS control event

Bit 5-0 : BUCK2_H[5:0]

Sets the BUCK2 output voltage.

See Table 4 for all possible configurations.

Address 0Ah: BUCK2_VOLT_L Register (R/W)

Address

(Index)

Register Name

BUCK2_VOLT_L

Initial Value

R/W

08h

Bit7

Bit6

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

BUCK2_L[5:0]

-

0Ah

0

1

Bit 5-0 : BUCK2_L[5:0]

Sets the BUCK2 output voltage.

See Table 4 for all possible configurations.

Address 0Bh: BUCK3_VOLT Register (R/W)

Address

(Index)

Register Name

BUCK3_VOLT

Initial Value

R/W

0Ch

Bit7

Bit6

Bit5

Bit4

0

Bit3

1

Bit2

BUCK3[4:0]

1

Bit1

0

Bit0

0

-

0Bh

0

Bit 5-0 : BUCK3[4:0]

Sets the BUCK3 output voltage.

See Table 4 for all possible configurations.

Address 0Ch: BUCK4_VOLT Register (R/W)

Address

(Index)

Register Name

BUCK4_VOLT

Initial Value

R/W

04h

Bit7

Bit6

Bit5

Bit4

0

Bit3

0

Bit2

BUCK4[4:0]

1

Bit1

0

Bit0

0

-

0Ch

0

Bit 5-0 : BUCK4[4:0]

Sets the BUCK4 output voltage.

See Table 4 for all possible configurations.

Address 0Dh: BUCK5_VOLT Register (R/W)

Address

(Index)

Register Name

BUCK5_VOLT

Initial Value

R/W

1Eh

Bit7

Bit6

Bit5

Bit4

1

Bit3

1

Bit2

BUCK5[4:0]

1

Bit1

1

Bit0

0

-

0Dh

0

Bit 5-0 : BUCK5[4:0]

Sets the BUCK5 output voltage.

See Table 4 for all possible configurations.

Address 0Eh: LED_CTRL Register (R/W)

Address

(Index)

Register Name

LED_CTRL

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LED_LP_ON

0

CHGDONE_LE

D_EN

LED_LPSR_O

N

-

LED_RUN_ON

0

0Eh

Initial Value

0

Bit4 :

CHGDONE_LED_EN

0: Disable

Select the LED (Shared with READY output pin) control mode with charge completion status

Not automatically indicate charge competion status, but can be controlled by READY_FORCE_LOW bit.

1: Enable

Automatically indicate charge completion status , READY output goes L. But READY_FORCE_LOW bit control is prioritized.

Bit2 :

Bit1 :

Bit0 :

LED_RUN_ON

0: White LED boost converter is OFF at RUN state.

1: White LED boost converter is ON at RUN state.

LED_LPSR_ON

0: White LED boost converter is OFF at LPSR state.

1: White LED boost converter is ON at LPSR state.

LED_LP_ON

0: White LED boost converter is OFF at SUSPEND state.

1: White LED boost converter is ON at SUSPEND state.

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Address 0Fh: LED_DIMM Register (R/W)

Address

(Index)

Register Name

LED_DIMM

R/W

00h

Bit7

Bit6

Bit5

0

Bit4

0

Bit3

Bit2

0

Bit1

0

Bit0

0

LED_DIMM[5:0]

-

0Fh

Initial Value

0

Bit 5-0 : LED_DIMM[5:0]

Select White LED boost converter dimming

LED_DIMM[5:0]

LED current

10 uA

00h

01h

20 uA

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

30 uA

50 uA

70 uA

100 uA

200 uA

300 uA

500 uA

700 uA

1 mA

2 mA

3 mA

4 mA

5 mA

6 mA

7 mA

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

8 mA

9 mA

10 mA

11 mA

12 mA

13 mA

14 mA

15 mA

16 mA

17 mA

18 mA

19 mA

20 mA

21 mA

22 mA

23 mA

24 mA

25 mA

1F

20h

21h

22h

23～3Fh

don't use

Address 10h: LDO_MODE1 Register (R/W)

Address

(Index)

Register Name

LDO_MODE1

Initial Value

R/W

74h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LDO1_SNVS_ LDO1_RUN_O LDO1_LPSR_

LDO4_REG_M LDO3_REG_M

INHIBIT_0(note1)

0

LDO1_LP_ON

1

-

ON

N

ON

ODE

10h

0

1

0

1

0

Bit 7 :

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 0 :

LDO1_SNVS_ON

0: LDO1 is OFF at SNVS state.

1: LDO1 is ON at SNVS state.

LDO1_RUN_ON

0: LDO1 is OFF at RUN state.

1: LDO1 is ON at RUN state.

LDO1_LPSR_ON

0: LDO1 is OFF at LPSR state.

1: LDO1 is ON at LPSR state.

LDO1_LP_ON

0: LDO1 is OFF at SUSPEND state.

1: LDO1 is ON at SUSPEND state.

LDO4_REG_MODE

0: LDO4 is controlled via external pin (LDO4VEN).

1: LDO4 is controlled via register.

LDO3_REG_MODE

0: LDO3 starts when DCIN is supplied.

1: LDO3 is controlled via register.

INHIBIT_0(note1)

For ROHM factory only

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Address 11h: LDO_MODE2 Register (R/W)

Address

(Index)

Register Name

LDO_MODE2

Initial Value

R/W

F5h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LDO3_SNVS_ LDO3_RUN_O LDO3_LPSR_

LDO2_SNVS_ LDO2_RUN_O LDO2_LPSR_

LDO3_LP_ON

1

LDO2_LP_ON

1

ON

1

N

1

ON

1

ON

0

N

1

ON

0

11h

Bit 7 :

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

LDO3_SNVS_ON

0: LDO3 is OFF at SNVS state.

1: LDO3 is ON at SNVS state.

LDO3_RUN_ON

0: LDO3 is OFF at RUN state.

1: LDO3 is ON at RUN state.

LDO3_LPSR_ON

0: LDO3 is OFF at LPSR state.

1: LDO3 is ON at LPSR state.

LDO3_LP_ON

0: LDO3 is OFF at SUSPEND state.

1: LDO3 is ON at SUSPEND state.

LDO2_SNVS_ON

0: LDO2 is OFF at SNVS state.

1: LDO2 is ON at SNVS state.

LDO2_RUN_ON

0: LDO2 is OFF at RUN state.

1: LDO2 is ON at RUN state.

LDO2_LPSR_ON

0: LDO2 is OFF at LPSR state.

1: LDO2 is ON at LPSR state.

LDO2_LP_ON

0: LDO2 is OFF at SUSPEND state.

1: LDO2 is ON at SUSPEND state.

Address 12h: LDO_MODE3 Register (R/W)

Address

(Index)

Register Name

LDO_MODE3

Initial Value

R/W

57h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LDO5_SNVS_ LDO5_RUN_O LDO5_LPSR_

LDO4_SNVS_ LDO4_RUN_O LDO4_LPSR_

LDO5_LP_ON

1

LDO4_LP_ON

1

ON

N

ON

N

ON

12h

0

1

0

1

Bit 7 :

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

LDO5_SNVS_ON

0: LDO5 is OFF at SNVS state.

1: LDO5 is ON at SNVS state.

LDO5_RUN_ON

0: LDO5 is OFF at RUN state.

1: LDO5 is ON at RUN state.

LDO5_LPSR_ON

0: LDO5 is OFF at LPSR state.

1: LDO5 is ON at LPSR state.

LDO5_LP_ON

0: LDO5 is OFF at SUSPEND state.

1: LDO5 is ON at SUSPEND state.

LDO4_SNVS_ON

0: LDO4 is OFF at SNVS state.

1: LDO4 is ON at SNVS state.

LDO4_RUN_ON

0: LDO4 is OFF at RUN state.

1: LDO4 is ON at RUN state.

LDO4_LPSR_ON

0: LDO4 is OFF at LPSR state.

1: LDO4 is ON at LPSR state.

LDO4_LP_ON

0: LDO4 is OFF at SUSPEND state.

1: LDO4 is ON at SUSPEND state.

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Address 13h: LDO_MODE4 Register (R/W)

Address

(Index)

Register Name

LDO_MODE4

Initial Value

R/W

57h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DVREF_SNVS DVREF_RUN_ DVREF_LPSR DVREF_LP_O LDO_LPSR_S LDO_LPSR_R LDO_LPSR_L LDO_LPSR_L

_ON

0

ON

1

_ON

0

N

1

NVS_ON

0

UN_ON

1

PSR_ON

1

P_ON

1

13h

Bit 7 :

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

DVREF_SNVS_ON

0: DVREF is OFF at SNVS state.

1: DVREF is ON at SNVS state.

DVREF_RUN_ON

0: DVREF is OFF at RUN state.

1: DVREF is ON at RUN state.

DVREF_LPSR_ON

0: DVREF is OFF at LPSR state.

1: DVREF is ON at LPSR state.

DVREF_LP_ON

0: DVREF is OFF at SUSPEND state.

1: DVREF is ON at SUSPEND state.

LDO_LPSR_SNVS_ON

0: LDO_LPSR is OFF at SNVS state.

1: LDO_LPSR is ON at SNVS state.

LDO_LPSR_RUN_ON

0: LDO_LPSR is OFF at RUN state.

1: LDO_LPSR is ON at RUN state.

LDO_LPSR_LPSR_ON

0: LDO_LPSR is OFF at LPSR state.

1: LDO_LPSR is ON at LPSR state.

LDO_LPSR_LP_ON

0: LDO_LPSR is OFF at SUSPEND state.

1: LDO_LPSR is ON at SUSPEND state.

Address 14h: LDO1_VOLT Register (R/W)

Address

(Index)

Register Name

LDO1_VOLT

Initial Value

R/W

32h

Bit7

Bit6

Bit5

1

Bit4

1

Bit3

Bit2

0

Bit1

1

Bit0

0

LDO1[5:0]

-

14h

0

Bit5-0 : LDO1[5:0]

Sets the LDO1 output voltage.

See Table 4 for all possible configurations.

Address 15h: LDO2_VOLT Register (R/W)

Address

(Index)

Register Name

LDO2_VOLT

Initial Value

R/W

32h

Bit7

Bit6

Bit5

1

Bit4

1

Bit3

0

Bit2

Bit1

1

Bit0

0

LDO2[5:0]

-

15h

0

Bit5-0 : LDO2[5:0]

Sets the LDO2 output voltage.

See Table 4 for all possible configurations.

Address 16h: LDO3_VOLT Register (R/W)

Address

(Index)

Register Name

LDO3_VOLT

Initial Value

R/W

32h

Bit7

Bit6

Bit5

1

Bit4

1

Bit3

0

Bit2

0

Bit1

1

Bit0

0

LDO3[5:0]

-

16h

0

Bit5-0 : LDO3[5:0]

Sets the LDO3 output voltage.

See Table 4 for all possible configurations.

Address 17h: LDO4_VOLT Register (R/W)

Address

(Index)

Register Name

LDO4_VOLT

Initial Value

R/W

32h

Bit7

Bit6

Bit5

1

Bit4

1

Bit3

0

Bit2

0

Bit1

1

Bit0

0

LDO4[5:0]

-

17h

0

Bit5-0 : LDO4[5:0]

Sets the LDO4 output voltage.

See Table 4 for all possible configurations.

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Address 18h: LDO5_VOLT_H Register (R/W)

Address

(Index)

Register Name

LDO5_VOLT_H

Initial Value

R/W

14h

Bit7

Bit6

Bit5

0

Bit4

1

Bit3

Bit2

1

Bit1

0

Bit0

0

LDO5_H[5:0]

-

18h

0

Bit5-0 : LDO5_H[5:0]

LDO5 output voltage

See the description of LDO5_VOLT_L register below.

Address 19h: LDO5_VOLT_L Register (R/W)

Address

(Index)

Register Name

LDO5_VOLT_L

Initial Value

R/W

32h

Bit7

Bit6

Bit5

1

Bit4

1

Bit3

0

Bit2

0

Bit1

1

Bit0

0

LDO5_L[5:0]

-

19h

0

Bit5-0 : LDO5_L[5:0]

LDO5 output voltage

If LDO5VSEL = L, LDO5 output voltage corresponds to the setting of LDO5_L bits.

If LDO5VSEL = H, LDO5 output voltage corresponds to the setting of LDO5_H bits.

Address 1Ah: BUCK_PD_DIS Register (R/W)

Address

(Index)

Register Name

BUCK_PD_DIS

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

BUCK5_PD_DI BUCK4_PD_DI BUCK3_PD_DI BUCK2_PD_DI BUCK1_PD_DI

-

S

1Ah

0

Bit4 :

BUCK5_PD_DIS

0: Discharge for BUCK5 turn off is enabled.

1: Discharge for BUCK5 turn off is disabled.

Bit3 :

Bit2 :

Bit1 :

Bit0 :

BUCK4_PD_DIS

0: Discharge for BUCK4 turn off is enabled.

1: Discharge for BUCK4 turn off is disabled.

BUCK3_PD_DIS

0: Discharge for BUCK3 turn off is enabled.

1: Discharge for BUCK3 turn off is disabled.

BUCK2_PD_DIS

0: Discharge for BUCK2 turn off is enabled.

1: Discharge for BUCK2 turn off is disabled.

BUCK1_PD_DIS

0: Discharge for BUCK1 turn off is enabled.

1: Discharge for BUCK1 turn off is disabled.

Address 1Bh: LDO_PD_DIS Register (R/W)

Address

(Index)

Register Name

LDO_PD_DIS

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DVREF_PD_DI LDO_LPSR_P

-

LDO5_PD_DIS LDO4_PD_DIS LDO3_PD_DIS LDO2_PD_DIS LDO1_PD_DIS

S

D_DIS

1Bh

0

Bit 6 :

Bit 5 :

Bit 4 :

Bit 3 :

Bit 2 :

Bit 1 :

Bit 0 :

DVREF_PD_DIS

0: Discharge for DVREF turn off is enabled

1: Discharge for DVREF turn off is disabled.

LDO_LPSR_PD_DIS

0: Discharge for LDO_LPSR turn off is enabled

1: Discharge for LDO_LPSR turn off is disabled.

LDO5_PD_DIS

0: Discharge for LDO5 turn off is enabled

1: Discharge for LDO5 turn off is disabled.

LDO4_PD_DIS

0: Discharge for LDO4 turn off is enabled

1: Discharge for LDO4 turn off is disabled.

LDO3_PD_DIS

0: Discharge for LDO3 turn off is enabled

1: Discharge for LDO3 turn off is disabled.

LDO2_PD_DIS

0: Discharge for LDO2 turn off is enabled

1: Discharge for LDO2 turn off is disabled.

LDO1_PD_DIS

0: Discharge for LDO1 turn off is enabled

1: Discharge for LDO1 turn off is disabled.

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Address 1Ch: GPO Register (R/W)

Address

(Index)

Register Name

GPO

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

GPO1_OUT

1

READY_FORC

E_LOW

INHIBIT_0(note1)

0

INHIBIT_1(note2)

1

R/W

03h

-

GPO1_MODE

0

-

1Ch

Initial Value

0

Bit 5 :

Bit 4 :

INHIBIT_0 (note1)

For ROHM factory only

GPO1_MODE

0: Open drain output mode

1: CMOS output mode

GPO1 Output mode setting

Bit 2 :

READY_FORCE_LOW

0: Normal

Force READY pin to be L output

READY pin be controlled as per Power State, Power Sequence, DVS and PWRON push status.

1: Low

Bit １ :

INHIBIT_1 (note2)

For ROHM factory only

GPO1 Output setting

Bit 0 :

GPO1_OUT

0: Low

1: Hi-Z [Open drain output mode] / High [CMOS output mode]

Address 1Dh: OUT32K Register (R,R/W)

Address

(Index)

Register Name

OUT32K

R/W

R,R/W OTP_STATUS

01h

OTP test status [Read only]

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

OUT32K_EN

1

OUT32K_MOD

E

-

1Dh

Initial Value

0

Bit 7 :

Bit 1 :

Bit 0 :

OTP_STATUS

0: Already stored sample

1: Not stored sample

OUT32K_MODE

0: Open drain output mode

1: CMOS output mode

CLK32KOUT output mode setting

CLK32KOUT clock output enable

OUT32K_EN

0: Disable [Hi-Z at Open drain mode, H at CMOS mode]

1: Enable

Address 1Eh: SEC Register (R/W)

Address

(Index)

Register Name

SEC

R/W

Bit7

Bit6

S40

x

Bit5

S20

x

Bit4

S10

x

Bit3

S8

x

Bit2

S4

x

Bit1

S2

x

Bit0

S1

x

R/W

XXh

-

1Eh

Initial Value

0

Bit 6-0 : S1 to S40 Second Counter.

The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00.Configured in BCD（Binary-Coded Decimal)

Any writing to the second counter resets divider units of less than 1 second.

RTC calendar and time information (address from 1Eh to 24h) should be read in accordance with continuous manner,

so stop condition should not be inserted during reading these registers.

Address 1Fh: MIN Register (R/W)

Address

(Index)

Register Name

MIN

R/W

XXh

Bit7

Bit6

M40

x

Bit5

M20

x

Bit4

M10

x

Bit3

M8

x

Bit2

M4

x

Bit1

M2

x

Bit0

M1

x

-

1Fh

Initial Value

0

Bit 6-0 : M1 to M40 Minute Counter.

The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00.Configured in BCD（Binary-Coded Decimal)

RTC calendar and time information (address from 1Eh to 24h) should be read in accordance with continuous manner,

so stop condition should not be inserted during reading these registers.

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Address 20h: HOUR Register (R/W)

Address

(Index)

Register Name

HOUR

R/W

XXh

Bit7

12/24

0

Bit6

Bit5

H20/PA

x

Bit4

H10

x

Bit3

H8

x

Bit2

H4

x

Bit1

H2

x

Bit0

H1

x

-

20h

Initial Value

0

Bit 7 :

12/24 Selects whether 12-hour clock or 24-hour clock is used.

0: 12hour clock

1: 24hour clock

Bit 5-0 : H20 to H1 Hour Counter.

The hour digits' range are as shown in this table and are carried to the day-of-month and day-of-week digits in transition

from PM11 to AM12 or from 23 to 00. Configured in BCD（Binary-Coded Decimal)

RTC calendar and time information (address from 1Eh to 24h) should be read in accordance with continuous manner,

so stop condition should not be inserted during reading these registers.

24-hour clock 12-hour clock 24-hour clock 12-hour clock

0

1

12(AM12)

01(AM1)

02(AM2)

03(AM3)

04(AM4)

05(AM5)

06(AM6)

07(AM7)

08(AM8)

09(AM9)

10(AM10)

11(AM11)

12

13

14

15

16

17

18

19

20

21

22

23

32(PM12)

21(PM1)

22(PM2)

23(PM3)

24(PM4)

25(PM5)

26(PM6)

27(PM7)

28(PM8)

29(PM9)

30(PM10)

31(PM11)

2

3

4

5

6

7

8

9

10

11

Address 21h: WEEK Register (R/W)

Address

(Index)

Register Name

WEEK

R/W

0Xh

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

W4

x

Bit1

W2

x

Bit0

W1

x

-

21h

Initial Value

0

Bit 2-0 : W4 to W1 Day-of-week Counter.

The day-of-week counter is incremented by 1 when the hour digits are carried to the day-of-month digits. Configured in BCD（Binary-Coded Decimal)

Correspondences between days of the week and the day-of-week digit are user-definable.

(Ex. Sunday = 0, 0, 0)

The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.

RTC calendar and time information (address from 1Eh to 24h) should be read in accordance with continuous manner,

so stop condition should not be inserted during reading these registers.

Address 22h: DAY Register (R/W)

Address

(Index)

Register Name

DAY

R/W

S/W

XXh

Bit7

Bit6

Bit5

D20

x

Bit4

D10

x

Bit3

D8

x

Bit2

D4

x

Bit1

D2

x

Bit0

D1

x

-

22h

Initial Value

0

Bit 5-0 : D20 to D1 Day-of-month Counter

The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October, and December,

from 1 to 30 for April, June, September, and November, from 1 to 29 for February in leap years, from 1 to 28 for February in ordinary years.

The day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. Configured in BCD（Binary-Coded Decimal)

RTC calendar and time information (address from 1Eh to 24h) should be read in accordance with continuous manner,

so stop condition should not be inserted during reading these registers.

Address 23h: MONTH Register (R/W)

Address

(Index)

Register Name

MONTH

R/W

XXh

Bit7

Bit6

Bit5

Bit4

MO10

x

Bit3

MO8

x

Bit2

MO4

x

Bit1

MO2

x

Bit0

MO1

x

-

23h

Initial Value

0

Bit 4-0 : MO10 to MO1 Month Counter.

The month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. Configured in BCD（Binary-Coded Decimal)

RTC calendar and time information (address from 1Eh to 24h) should be read in accordance with continuous manner,

so stop condition should not be inserted during reading these registers.

Address 24h: YEAR Register (R/W)

Address

(Index)

Register Name

YEAR

R/W

XXh

Bit7

Y80

x

Bit6

Y40

x

Bit5

Y20

x

Bit4

Y10

x

Bit3

Y8

x

Bit2

Y4

x

Bit1

Y2

x

Bit0

Y1

x

24h

Initial Value

Bit 7-0 : Y80 to Y1 Year Counter.

The year digits (Y80 to Y1) range from 00 to 99 and are carried to the 19/20 digits in reversion from 99 to 00.

00, 04, 08, ..., 92 and 96 in leap years. Configured in BCD（Binary-Coded Decimal)

RTC calendar and time information (address from 1Eh to 24h) should be read in accordance with continuous manner,

so stop condition should not be inserted during reading these registers.

Address 25h: ALM0_SEC Register (R/W)

Address

(Index)

Register Name

ALM0_SEC

Initial Value

R/W

00h

Bit7

Bit6

A0S40

0

Bit5

A0S20

0

Bit4

A0S10

0

Bit3

A0S8

0

Bit2

A0S4

0

Bit1

A0S2

0

Bit0

A0S1

0

-

25h

0

Bit 6-0 : A0S40 to A0S1 Alarm0 Second threshold value.Configured in BCD（Binary-Coded Decimal)

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Address 26h: ALM0_MIN Register (R/W)

Address

(Index)

Register Name

ALM0_MIN

R/W

00h

Bit7

Bit6

A0M40

0

Bit5

A0M20

0

Bit4

A0M10

0

Bit3

A0M8

0

Bit2

A0M4

0

Bit1

A0M2

0

Bit0

A0M1

0

-

26h

Initial Value

0

Bit 6-0 : A0M40 to A0M1 Alarm0 Minute threshold value.Configured in BCD（Binary-Coded Decimal)

Address 27h: ALM0_HOUR Register (R/W)

Address

(Index)

Register Name

ALM0_HOUR

Initial Value

R/W

00h

Bit7

A0_12/24

0

Bit6

Bit5

A0H20/PA

0

Bit4

A0H10

0

Bit3

A0H8

0

Bit2

A0H4

0

Bit1

A0H2

0

Bit0

A0H1

0

-

27h

0

Bit 7 :

A0_12/24 12hour clock / 24hour clock select bit.

Bit 5-0 : A0H20/PA, A0H40 to A0H1 Alarm0 Hour threshold value.Configured in BCD（Binary-Coded Decimal)

Address 28h: ALM0_WEEK Register (R/W)

Address

(Index)

Register Name

ALM0_WEEK

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

A0W4

0

Bit1

A0W2

0

Bit0

A0W1

0

-

28h

0

Bit 2-0 : : A0W4 to A0W1 Alarm0 day of the Week threshold value.Configured in BCD（Binary-Coded Decimal)

Address 29h: ALM0_DAY Register (R/W)

Address

(Index)

Register Name

ALM0_DAY

Initial Value

R/W

00h

Bit7

Bit6

Bit5

A0D20

0

Bit4

A0D10

0

Bit3

A0D8

0

Bit2

A0D4

0

Bit1

A0D2

0

Bit0

A0D1

0

-

29h

0

Bit 5-0 : A0D20 to A0D1 Alarm0 Day threshold value.Configured in BCD（Binary-Coded Decimal)

Address 2Ah: ALM0_MONTH Register (R/W)

Address

(Index)

Register Name

ALM0_MONTH

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

A0MO10

0

Bit3

A0MO8

0

Bit2

A0MO4

0

Bit1

A0MO2

0

Bit0

A0MO1

0

-

2Ah

0

Bit 4-0 : A0MO10 to A0MO1 Alarm0 Month threshold value.Configured in BCD（Binary-Coded Decimal)

Address 2Bh: ALM0_YEAR Register (R/W)

Address

(Index)

Register Name

ALM0_YEAR

Initial Value

R/W

00h

Bit7

A0Y80

0

Bit6

A0Y40

0

Bit5

A0Y20

0

Bit4

A0Y10

0

Bit3

A0Y8

0

Bit2

A0Y4

0

Bit1

A0Y2

0

Bit0

A0Y1

0

2Bh

Bit 7-0 : A0Y80 to A0Y1 Alarm0 Year threshold value

Address 2Ch: ALM1_SEC Register (R/W)

Address

(Index)

Register Name

ALM1_SEC

Initial Value

R/W

00h

Bit7

Bit6

A1S40

0

Bit5

A1S20

0

Bit4

A1S10

0

Bit3

A1S8

0

Bit2

A1S4

0

Bit1

A1S2

0

Bit0

A1S1

0

-

2Ch

0

Bit 6-0 : A1S40 to A1S1 Alarm1 Second threshold value.Configured in BCD（Binary-Coded Decimal)

Address 2Dh: ALM1_MIN Register (R/W)

Address

(Index)

Register Name

ALM1_MIN

R/W

00h

Bit7

Bit6

A1M40

0

Bit5

A1M20

0

Bit4

A1M10

0

Bit3

A1M8

0

Bit2

A1M4

0

Bit1

A1M2

0

Bit0

A1M1

0

-

2Dh

Initial Value

0

Bit 6-0 : A1M80 to A1M1 Alarm1 Minute threshold value.Configured in BCD（Binary-Coded Decimal)

Address 2Eh: ALM1_HOUR Register (R/W)

Address

(Index)

Register Name

ALM1_HOUR

Initial Value

R/W

00h

Bit7

A1_12/24

0

Bit6

Bit5

A1H20/PA

0

Bit4

A1H10

0

Bit3

A1H8

0

Bit2

A1H4

0

Bit1

A1H2

0

Bit0

A1H1

0

-

2Eh

0

Bit 7 :

A1_12/24, 12hour clock / 24hour clock select bit.

Bit 5-0 : A1H20/PA, A1H10 to A1H1 Alarm1 Hour threshold value.Configured in BCD（Binary-Coded Decimal)

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Address 2Fh: ALM1_WEEK Register (R/W)

Address

(Index)

Register Name

ALM1_WEEK

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

A1W4

0

Bit1

A1W2

0

Bit0

A1W1

0

-

2Fh

0

Bit 2-0 : : A1W4 to A1W1 Alarm1 day of the Week threshold value.Configured in BCD（Binary-Coded Decimal)

Address 30h: ALM1_DAY Register (R/W)

Address

(Index)

Register Name

ALM1_DAY

Initial Value

R/W

00h

Bit7

Bit6

Bit5

A1D20

0

Bit4

A1D10

0

Bit3

A1D8

0

Bit2

A1D4

0

Bit1

A1D2

0

Bit0

A1D1

0

-

30h

0

Bit 5-0 : A1D20 to A1D1 Alarm1 Day threshold value.Configured in BCD（Binary-Coded Decimal)

Address 31h: ALM1_MONTH Register (R/W)

Address

(Index)

Register Name

ALM1_MONTH

Initial Value

R/W

00h

Bit7

Bit6

Bit5

Bit4

A1MO10

0

Bit3

A1MO8

0

Bit2

A1MO4

0

Bit1

A1MO2

0

Bit0

A1MO1

0

-

31h

0

Bit 4-0 : A1MO10 to A1MO1 Alarm1 Month threshold value.Configured in BCD（Binary-Coded Decimal)

Address 32h: ALM1_YEAR Register (R/W)

Address

(Index)

Register Name

ALM1_YEAR

Initial Value

R/W

00h

Bit7

A1Y80

0

Bit6

A1Y40

0

Bit5

A1Y20

0

Bit4

A1Y10

0

Bit3

A1Y8

0

Bit2

A1Y4

0

Bit1

A1Y2

0

Bit0

A1Y1

0

32h

Bit 7-0 : A1Y80 to A1Y1 Alarm1 Year threshold value.Configured in BCD（Binary-Coded Decimal)

Address 33h: ALM0_MASK Register (R/W)

Address

(Index)

Register Name

ALM0_MASK

Initial Value

R/W

R/W A0_ONESEC

00h

Bit7

Bit6

A0_YEAR

0

Bit5

A0_MON

0

Bit4

A0_DAY

0

Bit3

A0_WEEK

0

Bit2

A0_HOUR

0

Bit1

A0_MIN

0

Bit0

A0_SEC

0

33h

0

Bit 7 :

A0_ONESEC Alarm0 interrupt occurs once every second. (Synchronized with second counter increment)

0: Disable

1: Enable

When A0_ONESEC is set to "1", regardless of any other setting in the ALM0_MASK register and the contents of

the respective ALM0_SEC to ALM0_YEAR registers.

Bit 6-0 : A0_YEAR to A0_SEC Alarm0 interrupt threshold mask bit.

0: Mask

1: Not masked

Address 34h: ALM1_MASK Register (R/W)

Address

(Index)

Register Name

ALM1_MASK

Initial Value

R/W

R/W A1_ONESEC

00h

Bit7

Bit6

A1_YEAR

0

Bit5

A1_MON

0

Bit4

A1_DAY

0

Bit3

A1_WEEK

0

Bit2

A1_HOUR

0

Bit1

A1_MIN

0

Bit0

A1_SEC

0

34h

0

Bit 7 :

A1_ONESEC Alarm1 interrupt occur once every second. (Synchronized with second counter increment)

0: Disable

1: Enable

When A1_ONESEC is set to "1", regardless of any other setting in the ALM1_MASK register and the contents of

the respective ALM1_SEC to ALM1_YEAR registers.

Bit 6-0 : A1_YEAR to A1_SEC Alarm1 interrupt threshold mask bit.

0: Mask

1: Not masked

Address 35h: ALM2 Register (R/W)

Address

(Index)

Register Name

ALM2

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0

ALM2[1:0]

-

35h

Initial Value

0

Bit 1-0 : ALM2[1:0]

00: OFF (Initial State)

01: Once per 1 second (Synchronized with second counter increment)

10: Once per minute (at 00 seconds of every minute)

11: Once per hour (at 00 minutes, and 00 seconds of every hour)

Invalidate Alarm2 when changing the value of clock and calendar.

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Address 36h: TRIM Register (R/W)

Address

(Index)

Register Name

TRIM

R/W

Bit7

DEV

0

Bit6

0

Bit5

0

Bit4

0

Bit3

TRIM[6:0]

0

Bit2

0

Bit1

0

Bit0

0

R/W

00h

36h

Initial Value

Bit 7 :

DEV

When DEV is set to '0', the Oscillation Adjustment Circuit operates at 00, 30 seconds.

When DEV is set to '1', the Oscillation Adjustment Circuit operates at 00 seconds only.

Bit 6-0 : TRIM[6:0]

The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of the settings of

the Oscillation Adjustment Register at the timing set by DEV.

The Oscillation Adjustment Circuit will not operate with the same timing (00, or 30 seconds ) as the timing of

writing to the Oscillation Adjustment Register.

The TRIM 6 : bit setting of '0' causes an increment of (TRIM[5:0]-1) x 2 of time counts.

The TRIM 6 : bit setting of '1' causes a decrement of (invert(TRIM[5:0])+1) x 2 of time counts.

The TRIM 6-0 : bit setting of "x00000x" causes neither an increment nor decrement of time counts.

Address 37h: CONF Register (R/W)

Address

(Index)

Register Name

CONF

R/W

01h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

XSTB

0

Bit0

PON

1

-

37h

Initial Value

0

Bit 1 :

XSTB

Oscillator Stop Flag

0: RTC clock has been stopped.

1: RTC clock is normallyOscillator operating normally.

The XSTB bit is used to check the status of the Real Time Clock (RTC). This bit accepts R/W for "1" and "0".

If "1" is written to this bit, the XSTB bit will change value to "0" when the RTC is stopped.

Bit 0 :

PON

Power-on-reset Flag.

0: Normal condition.

1: Power-on-reset detected

The PON bit is used to check for a power-on-reset condition. Only "0" values may be written to this bit.

A power-on-reset condition is detected when the supply voltage rises above the SNVS undervoltage lockout (UVLO) value.

When a power-on-reset condition is detected, the PON bit is set to "1".

When the PON bit is set to "0", SNVS UVLO operates in intermittent monitoring mode.

Address 38h: SYS_INIT Register (R/W)

Address

(Index)

Register Name

SYS_INIT

R/W

00h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

CHGRST

0

Bit0

-

38h

Initial Value

0

Bit 1(W) :CHGRST

Writing "0" releases reset operation.

Writing "1" resets Battery Charger States. Charger state is returned to SUSPEND state, and timers of charger are reset.

Bit 1(R) : CHGRST

Reset status for CHGRST

0: Reset released

1: Reset asserted

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Address 39h: CHG_STATE Register (R)

Address

(Index)

Register Name

CHG_STATE

Initial Value

R/W

R

Bit7

Bit6

x

Bit5

x

Bit4

x

Bit3

Bit2

x

Bit1

x

Bit0

x

CHG_STATE[6:0]

x

-

39h

XXh

0

Bit 6-0 : CHG_STATE[6:0]

The current state of the battery charger. Table below shows the details of the register values.

Address 3Ah: CHG_LAST_STATE Register (R)

Address

(Index)

Register Name

CHG_LAST_STATE

Initial Value

R/W

R

Bit7

Bit6

x

Bit5

x

Bit4

x

Bit3

Bit2

x

Bit1

x

Bit0

x

CHG_LAST_STATE[6:0]

x

-

3Ah

XXh

0

Bit 6-0 : CHG_LAST_STATE[6:0]

The previous state of the battery charger. Table shows the details of the register values.

CHG_STATE[6:0]

State

Description

CHG_LAST_STATE[6:0]

00h

01h

02h

03h

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

20h

21h

22h

23h

24h

30h

31h

32h

7Fh

others

SUSPEND

TRICKLE CHARGE

PRE CHARGE

FAST CHARGE

BATDET

Suspend charging

Trickle charging (Pre-conditioning)

Pre-charging

Fast Charging

Battery detection

TOP OFF

Termination Current reached

DONE

Charging finished

Temp Err 1

Temp Err 2

Temp Err 3

Temp Err 4

Temp Err 5

TSD 1

Out of standard temperature while in PRE CHARGE State

Out of standard temperature while in FAST CHARGE or TOP OFF State

Out of standard temperature while in DONE State

Out of standard temperature while in SUSPEND State

Out of standard temperature while in PRE CHARGE State

Thermal Shut Down while in PRE CHARGE State

Thermal Shut Down while in FAST CHARGE State

Thermal Shut Down while in TOP OFF State

( > 135℃)

TSD 2

TSD 3

( > 135℃)

TSD 4

Thermal Shut Down while in DONE State

TSD 5

Thermal Shut Down while in TRICKLE CHARGE State ( > 135℃)

VSYS < VBAT while in FAST CHARGE State

VSYS < VBAT while in TOP OFF State

VSYS < VBAT after TOP OFF State (DONE)

Battery Error

BATT ASSIST 1

BATT ASSIST 2

BATT ASSIST 3

Batt Error

(reserved)

-

Address 3Bh: BAT_STAT Register (R)

Address

(Index)

Register Name

BAT_STAT

R/W

R

Bit7

Bit6

Bit5

BAT_DET

x

Bit4

Bit3

VBAT_OV

x

Bit2

LOW_BAT

x

Bit1

Bit0

BAT_DET_DO

NE

-

VBAT_SHORT DBAT_DET

3Bh

Initial Value

XXh

0

x

Bit 5 :

Bit 4 :

Bit 3 :

BAT_DET

Battery detection result

0：Battery removed or no battery detected

1：Battery present

BAT_DET_DONE

0：Detection running

1：Detection finished

Battery detection status

VBAT_OV

VBAT over-voltage Status

0：VBAT ≦ VBAT_OVP - 150mV (Hysteresis)

1：VBAT ≧ VBAT_OVP

For example, VBAT_OV might be detected when the battery is removed while Fast charging.

Bit 2 :

Bit 1 :

Bit 0 :

LOW_BAT

0：VBAT > VBAT_LO

1：VBAT ≦VBAT_LO

Battery low-voltage Status

VBAT_SHORT

0：VBAT ≧ 1.6V (Hysteresis)

1：VBAT ≦ 1.5V

Battery short-circuit detection status

Dead Battery detection status

DBAT_DET

0：Not detected

1：Detected

If VBAT is below VBAT_LO until the timer is expired, the battery is assumed as a weak or dead battery.

The timer expiration time is set by TIM_DBP register.

Address 3Ch: DCIN_STAT Register (R)

Address

(Index)

Register Name

DCIN_STAT

Initial Value

R/W

R

Bit7

Bit6

Bit5

Bit4

Bit3

DCIN_OV

x

Bit2

Bit1

Bit0

DCIN_DET

x

IGNORE(note3 DCIN_CLPS_D

-

)

ET

3Ch

0Xh

0

x

Bit 3 :

DCIN_OV

0：Normal voltage

1：DCIN > 6.5V

DCIN over-voltage status

Bit 2 :

Bit 1 :

IGNORE (note3)

For ROHM factory only

DCIN_CLPS_DET

0：Normal operation

1：Anti-collapse

DCIN anti-collapse status

Bit 0 :

DCIN_DET

0：Not detected or low level

DCIN detection status

1：DCIN detected (over UVLO level)

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Address 3Dh: VSYS_STAT Register (R)

Address

(Index)

Register Name

VSYS_STAT

Initial Value

R/W

R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

VSYS_LO

x

Bit0

VSYS_UVN

x

-

3Dh

0Xh

0

Bit 1 :

Bit 0 :

VSYS_LO

VSYS low voltage detection status. The threshold voltage is configurable by VSYS_MIN and VSYS_MAX.

The higher voltage of among VSYS(Addr.C0h-C1h) and VSYS_SA(Addr.C2h-C3h) are used for VSYS voltage.

VSYS UVLO detection status

0：VSYS ≦ VSYS_MIN

1：VSYS ≧ VSYS_MAX

VSYS_UVN

0：Low voltage

1：Normal voltage

Address 3Eh: CHG_STAT Register (R)

Address

(Index)

Register Name

CHG_STAT

Initial Value

R/W

R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

-

VRECHG_DET

x

3Eh

0Xh

0

Bit 0 :

VRECHG_DET

Re-charge voltage detection status voltage.

0：VBAT > VBAT_MNT

1：VBAT ≦ VBAT_MNT

Address 3Fh: CHG_WDT_STAT Register (R)

Address

(Index)

Register Name

CHG_WDT_STAT

Initial Value

R/W

R

Bit7

Bit6

x

Bit5

x

Bit4

Bit3

x

Bit2

x

Bit1

x

Bit0

x

CHGWDTS[7:0]

3Fh

XXh

x

Bit 7-0 : CHGWDTS[7:0]

Actual watch-dog timer counter value for Pre-charging & Tricle-Charging or Fast Charging & Top Off.

PCHG(or TCHG) : (CHGWDTS -1) X (64/60) min.

FCHG(or TOFF)

FCHG(or TOFF) COLD1 condition

:

(CHGWDTS * 8 -240) * (64/60/2) min.

(CHGWDTS * 8 -3) * (64/60) min.

:

Address 40h: BAT_TEMP Register (R)

Address

(Index)

Register Name

BAT_TEMP

Initial Value

R/W

R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

x

Bit1

Bit0

x

BAT_TEMP[2:0]

x

-

40h

0Xh

0

The temperature thresholds have hysteresis. Table lists the temperature threshold values.

BAT_TEMP[2:0] Temperature Range

Description

0h

1h

2h

3h

4h

5h

6h

7h

Room Temp

HOT1

T2 < Tbat < T3

T3 < Tbat < T5

T5 < Tbat < T4

T4 < Tbat

HOT2

HOT3

COLD1

T1 < Tbat < T2

Tbat < T1

COLD2

Temp. Disable

BatteryOpen

Disable thermal control (No Thermistor)

TS port is open

No. Description

Default Value

2 deg.

Note

1

2

3

4

5

6

7

8

9

Lower threshold of T1

T1 in JEITAprofile

T2 in JEITAprofile

T3 in JEITAprofile

T4 in JEITAprofile

Between T3 and T4

Upper threshold of T1

Lower threshold of T2

Upper threshold of T2

Lower threshold of T3

Upper threshold of T3

Lower threshold of T4

Upper threshold of T4

Lower threshold of T5

5 deg.

10 deg.

13 deg.

42 deg.

45 deg.

55 deg.

58 deg.

47 deg.

50 deg.

10 Upper threshold of T5

Measured/Preset Battery Temperature. -55 to 200 deg. Celsius, 1-degree steps.

Degree Celsius = 200 - BTMP[7:0](address 5Fh)

Address 41h: IGNORE_0 Register (R)

Address

(Index)

Register Name

IGNORE_0

R/W

R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

-

IGNORE(note3) IGNORE(note3) IGNORE(note3) IGNORE(note3) IGNORE(note3) IGNORE(note3)

41h

Initial Value

XXh

0

x

Bit 5-0 : IGNORE(note3)

For ROHM factory only

Address 42h: INHIBIT_0 Register (R/W)

Address

(Index)

Register Name

INHIBIT_0

R/W

E6h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_0(note1) INHIBIT_0(note1) INHIBIT_1(note2) INHIBIT_1(note2) INHIBIT_1(note2)

42h

Initial Value

1

0

1

0

Bit 7-0 : INHIBIT_0/1(note1/2)

For ROHM factory only

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Address 43h: DCIN_CLPS Register (R/W)

Address

(Index)

Register Name

DCIN_CLPS

Initial Value

R/W

36h

Bit7

0

Bit6

0

Bit5

1

Bit4

Bit3

0

Bit2

1

Bit1

1

Bit0

0

DCIN_CLPS[11:4]

43h

1

Bit 7-0 : DCIN_CLPS[11:4]

DCIN Anti-collapse entry voltage threshold 0.0V to 20.4V range, 80 mV steps.

When DCINOK = L, Anti-collapse detection is invalid.

When DCIN < DCIN_CLPS is detected, the charger decreases the input current restriction value.

DCIN_CLPS voltage must be set higher than VBAT_CHG1, VBAT_CHG2, and VBAT_CHG3.

If DCIN_CLPS set lower than these value, can't detect removing DCIN.

Address 44h: VSYS_REG Register (R/W)

Address

(Index)

Register Name

VSYS_REG

Initial Value

R/W

0Bh

Bit7

Bit6

Bit5

Bit4

Bit3

1

Bit2

Bit1

1

Bit0

1

VSYS_REG[4:0]

0

-

44h

0

Bit 7-0 : VSYS_REG[4:0]

VSYS regulation voltage setting. 4.2V to 5.25V range, 50mV step.

VSYS_REG

00h

VSYS Voltage

4.20V

4.25V

4.30V

4.35V

4.40V

4.45V

4.50V

4.55V

4.60V

4.65V

4.70V

4.75V

4.80V

4.85V

4.90V

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

4.95V

5.00V

5.05V

5.10V

13h

14h

15h

5.15V

5.20V

5.25V

Address 45h: VSYS_MAX Register (R/W)

Address

(Index)

Register Name

VSYS_MAX

Initial Value

R/W

33h

Bit7

Bit6

0

Bit5

Bit4

1

Bit3

Bit2

0

Bit1

1

Bit0

1

VSYS_MAX[12:6]

0

-

45h

0

1

Bit 6-0 : VSYS_MAX[12:6]

VSYS voltage rising detection threshold. 0.0V to 8.128V range, 64mV steps.

Address 46h: VSYS_MIN Register (R/W)

Address

(Index)

Register Name

VSYS_MIN

R/W

30h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

VSYS_MIN[12:6]

0

-

46h

Initial Value

0

1

Bit 6-0 : VSYS_MIN[12:6]

VSYS voltage falling detection threshold. 0.0V to 8.128V range, 64mV steps.

VSYS_MAX

VSYS Voltage

VSYS_MIN

08h-28h

29h

0.512V- 2.56 V

2.624V

2Ah

2.688V

2Bh

2.752V

2Ch

2Dh

2Eh

2.816V

2.880V

2.944V

2Fh

3.008V

30h

3.072V

31h

3.136V

32h

3.200V

33h

3.264V

34h

3.328V

35h

3.392V

36h

3.456V

37h

3.520V

38h-6Dh

3.584V- 6.976V

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Address 47h: CHG_SET1 Register (R/W)

Address

(Index)

Register Name

CHG_SET1

Initial Value

R/W

6Fh

Bit7

WDT_DIS

0

Bit6

WDT_AUTO

1

Bit5

AUTO_FST

1

Bit4

FST_TRG

0

Bit3

Bit2

BTMP_EN

1

Bit1

Bit0

CHG_EN

1

COLD_ERR_E

N

AUTO_RECHG

1

47h

1

Bit 7 :

Bit 6 :

Bit 5

WDT_DIS

0 : Normal operation

1 : Disable

Disable Charger Watch Dog Timer(WDT). This control is valid for watch dog timer of Trickle-charging, Pre-charging, Fast-charging and Top

When WDT_DIS = "0", the charger will stop charging when the WDT expired, indicating an error has occurred.

When WDT_DIS = "1", the Host should handle any error by its software.

WDT_AUTO

0 : Manual setting

1 : Auto setting

WDT setting mode

In auto setting mode, the WDT expiration time is set to 128 minutes for Pre-charging and 640 minites for Fast-charging.

In manual setting mode, the WDT expiration time is set by the register WDT_PRE for Pre-charging and the register WDT_FST for Fast-charging.

AUTO_FST

0 : Manual control

1 : Auto control

Fast charging transition mode

When VBAT > VPRE_HI is detected at Pre-charging, the charger goes to Fast Charging.

In the Manual control mode, the Host should write FST_TRG = "1" to move the charger to Fast Charging.

Bit 4

Bit 3

FST_TRG

0 : No action

Trigger Fast Charging

1 : Trigger to Fast Charging at Pre-Charge state with AUTO_FST='0'

The positive edge of FST_TRG is needed for the trigger.

AUTO_RECHG

0 : Manual control

1 : Auto control

Automatic re-charging mode

In the auto control mode, the charger will re-start charging when the maintenance voltage is detected

(VBAT < VBAT_MNT).

While in manual control mode, VBAT_MNT can be detected but re-charging should be triggered by the software.

Bit 2

Bit 1

Bit 0

BTMP_EN

0 : Disable

1 : Enable

Charging voltage is reduced by battery temperature.

COLD_ERR_EN

0 : Disable

1 : Enable

Slow down the watch-dog timer counter in COLD1 condition.

Count down every 4.27min.

Count down every 8.53min.

CHG_EN

0 : Disable

1 : Enable

Enabling charger operation.

Address 48h: CHG_SET2 Register (R/W)

Address

(Index)

Register Name

CHG_SET2

Initial Value

R/W

R/W VF_TREG_EN EXTMOS_EN

98h

Thermal shutdown for charger

Bit7

Bit6

Bit5

Bit4

BATDET_EN

1

Bit3

Bit2

Bit1

Bit0

REBATDET_T

RG

INHIBIT_1(note2)

1

TIM_CNT_SEL[1:0]

-

48h

1

0

Bit7 :

VF_TREG_EN

0 : Disable

1 : Enable

Bit6 :

Bit5 :

Bit4 :

Bit3 :

EXTMOS_EN

0 :ꢀCharger uses Internal MOSFET.

1 :ꢀCharger uses External MOSFET.

Select Internal/External MOSFET. Change this register after CHG_EN is set to '0' (charge disable)

REBATDET

Trigger for re-trial of Battery detection

When REBATDET_TRG bit is set to 1, battery detection trial will start.

REBATDET_TRG needs to be set 1 again after set to 0 for next battery detection.

BATDET_EN

0 : Disable

1 : Enable

Enable Battery detection

INHIBIT_1(note2)

For ROHM factory only

Bit1-0 : TIME_CNT_SEL[1:0]

Transition Timer Setting from the Suspend State to the Trickle state.

Timer Setting

TIM_CNT_SEL[2:0]

(CLK32K Cycle)

0h

1h

2h

3h

1600 (48.8ms)

3200 (97.7ms)

4800 (146.5ms)

6400 (195.3ms)

Address 49h: CHG_WDT_PRE Register (R/W)

Address

(Index)

Register Name

CHG_WDT_PRE

Initial Value

R/W

1Eh

Bit7

Bit6

0

Bit5

0

Bit4

Bit3

1

Bit2

1

Bit1

1

Bit0

0

WDT_PRE[7:0]

49h

0

1

Bit7-0 : WDT_PRE[7:0]

Watch Dog Timer setting for Pre-charging 0 to 271 minutes range, 64-sec steps.

This register is effective only when '0' is written to WDT_AUTO(address 47h Bit6).

PCHG(or TCHG) : (WDT_PRE -1) * (64/60) min.

It can be invalid with WDT_PRE set to '1' and expire immediately with WDT_PRE set to '0'.

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Address 4Ah: CHG_WDT_FST Register (R/W)

Address

(Index)

Register Name

CHG_WDT_FST

Initial Value

R/W

26h

Bit7

Bit6

0

Bit5

1

Bit4

Bit3

0

Bit2

1

Bit1

1

Bit0

0

WDT_FST[10:3]

4Ah

0

Bit7-0 : WDT_FST[10:3]

Watch Dog Timer setting for Fast Charging 8.5 to 2176 minutes range, 512-sec steps.

This register is effective only when '0' is written to WDT_AUTO(address 42h Bit6).

FCHG(or TOFF)

FCHG(or TOFF) COLD1 condition

:

(WDT_FST * 8 -240) * (64/60/2) min.

(WDT_FST * 8 -3) X (64/60) min.

:

The timer can be invalid with WDT_FST set to '0'.

In case of COLD1 condition, it can expire immediately with WDT_FST set to '30' or less.

Address 4Bh: CHG_IPRE Register (R/W)

Address

(Index)

Register Name

CHG_IPRE

R/W

44h

Bit7

Bit6

Bit5

Bit4

Bit3

0

Bit2

1

Bit1

0

Bit0

0

ITRI[3:0]

IPRE[3:0]

4Bh

Initial Value

0

1

0

Bit 7-4 : ITRI[3:0]

Bit 3-0 : IPRE[3:0]

Trickle charge current setting 5.0 mA to 25 mA range, 2.5 mA steps.

Pre-charging current setting 50 mA to 375 mA range, 50 mA steps.

ITRI

0h

1h

2h

3h

4h

5h

Trickle charging current

0.0 mA

IPRE

0h

Pre-charging current

0 mA

2.5 mA

1h

25 mA

5.0 mA

2h

50 mA

7.5 mA

3h

75 mA

10.0 mA

4h

100 mA

12.5 mA

5h

125 mA

6h

7h

8h

9h

15.0 mA

17.5 mA

20.0 mA

22.5 mA

6h

7h

8h

9h

150 mA

175 mA

200 mA

225 mA

Ah

25.0 mA

Ah

Bh

Ch

Dh

Eh

Fh

250 mA

275 mA

300 mA

325 mA

350 mA

375 mA

Bh-Fh

(reserved)

Address 4Ch: CHG_IFST Register (R/W)

Address

(Index)

Register Name

CHG_IFST

R/W

12h

Bit7

Bit6

Bit5

Bit4

Bit3

0

Bit2

Bit1

1

Bit0

0

IFST[4:0]

0

-

4Ch

Initial Value

0

1

Bit 4-0 : IFST[4:0]

Battery Charging Current for Fast Charge 100 mA to 2000 mA range, 100 mA steps.

Fast charging Current

External MOSFET

(RSENS=10mohm)

External MOSFET

(RSENS=30mohm)

IFST

Internal MOSFET

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h-1Fｈ

0 mA

25 mA

0 mA

33.3 mA

66.7 mA

100 mA

133 mA

167 mA

200 mA

233 mA

267 mA

300 mA

333 mA

367 mA

400 mA

433 mA

467 mA

500 mA

533 mA

567 mA

600 mA

633 mA

667 mA

(reserved)

100 mA

50 mA

200 mA

75 mA

300 mA

100 mA

125 mA

150 mA

175 mA

200 mA

225 mA

250 mA

275 mA

300 mA

325 mA

350 mA

375 mA

400 mA

425 mA

450 mA

475 mA

500 mA

(reserved)

400 mA

500 mA

600 mA

700 mA

800 mA

900 mA

1000 mA

1100 mA

1200 mA

1300 mA

1400 mA

1500 mA

1600 mA

1700 mA

1800 mA

1900 mA

2000 mA

(reserved)

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Address 4Dh: CHG_IFST_TERM Register (R/W)

Address

(Index)

Register Name

CHG_IFST_TERM

Initial Value

R/W

05h

Bit7

Bit6

Bit5

Bit4

Bit3

0

Bit2

Bit1

0

Bit0

1

IFST_TERM[3:0]

-

4Dh

0

1

Bit3-0 : IFST_TERM[3:0]

Charging Termination Current for Fast Charge 10 mA to 200 mA range.

Termination Current

IFST_TERM

RSEN=10mohm

0 mA

RSEN=30mohm

0 mA

0h

1h

10 mA

3.33 mA

6.67 mA

10.0 mA

13.3 mA

16.7 mA

33.3 mA

50.0 mA

66.7 mA

(reserved)

2h

20 mA

3h

30 mA

4h

40 mA

5h

50 mA

6h

100 mA

150 mA

200 mA

(reserved)

7h

8h

9h-Fｈ

Address 4Eh: CHG_VPRE Register (R/W)

Address

(Index)

Register Name

CHG_VPRE

Initial Value

R/W

C9h

Bit7

1

Bit6

Bit5

0

Bit4

0

Bit3

1

Bit2

0

Bit1

Bit0

1

VPRE_HI[3:0]

VPRE_LO[3:0]

4Eh

1

0

Bit7-4 : VPRE_HI[3:0]

Bit3-0 : VPRE_LO[3:0]

Upper threshold of Pre-charging voltage 2.1V to 3.6V range, 0.1V steps.

Lower threshold of Pre-charging voltage 2.1V to 3.6V range, 0.1V steps.

VPRE_LO is also the upper threshold of Trickle Charging voltage.

VPRE_HI

VPRE_LO

Setting Voltage

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

2.1 V

2.2 V

2.3 V

2.4 V

2.5 V

2.6 V

2.7 V

2.8 V

2.9 V

3.0 V

3.1 V

3.2 V

3.3 V

3.4 V

3.5 V

3.6 V

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Address 4Fh: CHG_VBAT_1 Register (R/W)

Address

(Index)

Register Name

CHG_VBAT_1

Initial Value

R/W

18h

Bit7

Bit6

Bit5

Bit4

1

Bit3

1

Bit2

Bit1

0

Bit0

0

VBAT_CHG1[4:0]

0

-

4Fh

0

Bit4-0 : VBAT_CHG1[4:0]

Fast Charging Voltage for the temperature range ROOM.

3.72V to 4.34V range, 20mV step

VBAT_CHGx

00h

Setting Voltage

3.72 V

3.74 V

3.76 V

3.78 V

3.80 V

~

01h

02h

03h

04h

~

1Dh

1Eh

4.30 V

4.32 V

4.34 V

1Fh

Address 50h: CHG_VBAT_2 Register (R/W)

Address

(Index)

Register Name

CHG_VBAT_2

Initial Value

R/W

13h

Bit7

Bit6

Bit5

Bit4

1

Bit3

0

Bit2

Bit1

1

Bit0

1

VBAT_CHG2[4:0]

0

-

50h

0

Bit4-0 : VBAT_CHG2[4:0]

Fast Charging Voltage for the temperature range HOT1.

3.72V to 4.34V range, 20mV step

Address 51h: CHG_VBAT_3 Register (R/W)

Address

(Index)

Register Name

CHG_VBAT_3

Initial Value

R/W

10h

Bit7

Bit6

Bit5

Bit4

1

Bit3

0

Bit2

Bit1

0

Bit0

0

VBAT_CHG3[4:0]

0

-

51h

0

Bit4-0 : VBAT_CHG3[4:0]

Fast Charging Voltage for the temperature range HOT2 and COLD1.

3.72V to 4.34V range, 20mV step

Charging

Voltage

Charging

Voltage

BTMP_EN = ‘0’(address47h Bit2)

BTMP_EN = ‘1’(address47h Bit2)

VBAT_CHG1

VBAT_CHG2

VBAT_CHG3

VBAT_CHG1

VBAT_CHG2

VBAT_CHG3

T1

T2

T3

T5 T4

T1

T2

T3

Temperrature of Battery Pack

T5 T4

Temperrature of Battery Pack

Address 52h: CHG_LED_1 Register (R/W)

Address

(Index)

Register Name

CHG_LED_1

Initial Value

R/W

03h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

0

Bit1

Bit0

1

CHG_LED_BT

A_MASK

TERR[2:0]

1

-

52h

0

Bit4 :

CHGLED mask control for Battery Assist 1&2.

CHG_LED_BTA_MASK

0 : Lighting

1 : Not lighting

Bit2-0 :

CHGLED lighting setting for the battery charging temperature error indication.

TERR[2:0]

LED Lighting

TERR

for Error Indication

0h

1h

2h

3h

4h

5h

6h

7h

Always ON

Blinking at 0.125 Hz

Blinking at 0.25 Hz

Blinking at 0.5 Hz

Blinking at 1 Hz

Blinking at 4 Hz

Blinking at 8 Hz

Light OFF

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Address 53h: VF_TH Register (R/W)

Address

(Index)

Register Name

VF_TH

R/W

00h

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

VF_TH[7:0]

53h

Initial Value

Bit7-0 : VF_TH[7:0]

Vf Voltage threshold for monitor. 0.100V to 1.395V range, 1.3V/256 steps.

Address 54h: BAT_SET_1 Register (R/W)

Address

(Index)

Register Name

BAT_SET_1

Initial Value

R/W

00h

Bit7

Bit6

Bit5

0

Bit4

Bit3

0

Bit2

Bit1

0

Bit0

0

VBAT_HI[3:0]

VBAT_LO[3:0]

54h

0

Bit7-4 : VBAT_HI[3:0]

Bit3-0 : VBAT_LO[3:0]

Battery voltage threshold for VBAT rising 3.00V to 3.60V range, 50 mV steps.

Battery voltage threshold for VBAT falling 2.50V to 3.10V range, 50 mV steps.

VBAT_LO is also the lower threshold of dead battery detection.

VBAT_HI

0h

Setting Voltage

3.00 V

3.05 V

3.10 V

3.15 V

3.20 V

3.25 V

3.30 V

3.35 V

3.40 V

3.45 V

3.50 V

3.55 V

3.60 V

3.65 V

3.70 V

3.75 V

VBAT_LO

0h

Setting Voltage

2.50 V

2.55 V

2.60 V

2.65 V

2.70 V

2.75 V

2.80 V

2.85 V

2.90 V

2.95 V

3.00 V

3.05 V

3.10 V

3.15 V

3.20 V

3.25 V

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

Bh

Ch

Dh

Eh

Fh

Address 55h: BAT_SET_2 Register (R/W)

Address

(Index)

Register Name

BAT_SET_2

Initial Value

R/W

14h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

1

Bit1

Bit0

0

VBAT_OVP[3:0]

VBAT_MNT[2:0]

0

-

55h

0

1

0

Bit7-4 : VBAT_OVP[3:0]

Bit2-0 : VBAT_MNT[2:0]

Battery over-voltage detection threshold. 4.20V to 4.60V range, 50 mV steps.

Battery voltage maintenance threshold.

The charger starts re-charging when VBAT ≦ VBAT_MNT.

VBAT_OVP Setting Voltage

VBAT_MNT

Setting Voltage

0h

1h

4.20 V

4.25 V

4.30 V

4.35 V

4.40 V

4.45 V

4.50 V

4.55 V

4.60 V

(reserved)

0h

1h

2h

3h

4h

5h

6h

7h

VBAT_CHG1/2/3 - 0.35V

VBAT_CHG1/2/3 - 0.30V

VBAT_CHG1/2/3 - 0.25V

VBAT_CHG1/2/3 - 0.20V

VBAT_CHG1/2/3 - 0.15V

VBAT_CHG1/2/3 - 0.10V

VBAT_CHG1/2/3 - 0.05V

VBAT_CHG1/2/3 - 0.00V

2h

3h

4h

5h

6h

7h

8h

9h - Fh

Address 56h: BAT_SET_3 Register (R/W)

Address

(Index)

Register Name

BAT_SET_3

Initial Value

R/W

42h

Bit7

Bit6

1

Bit5

Bit4

Bit3

Bit2

0

Bit1

TIM_DBP[2:0]

1

Bit0

0

VBAT_DONE[2:0]

0

-

56h

0

Bit2-0 : VBAT_DONE[2:0]

Bit2-0 : TIM_DBP[2:0]

Charging Termination Battery voltage threshold for Fast Charge.

The charger accepts VBAT > VBAT_DONE as one of the condition for end of Fast Charge.

Dead Battery Provisioning timer setting

Refer to the description for DBAT_DET bit.

VBAT_DONE

Setting Voltage

TIM_DBP

DBP Timer Setting

0h

1h

2h

3h

4h

5h

6h

7h

VBAT_CHG1/2/3 - 0.112V

VBAT_CHG1/2/3 - 0.096V

VBAT_CHG1/2/3 - 0.080V

VBAT_CHG1/2/3 - 0.064V

VBAT_CHG1/2/3 - 0.048V

VBAT_CHG1/2/3 - 0.032V

VBAT_CHG1/2/3 - 0.016V

VBAT_CHG1/2/3 - 0.000V

0h

1h

2h

3h

4h

5h

6h

7h

12 min

32 min

45 min

64 min

128 min

5 min

1 min

0 min

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Address 57h: ALM_VBAT_TH_U Register (R/W)

Address

(Index)

Register Name

ALM_VBAT_TH_U

Initial Value

R/W

01h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

VBAT_TH[12]

1

-

57h

0

Address 58h: ALM_VBAT_TH_L Register (R/W)

Address

(Index)

Register Name

ALM_VBAT_TH_L

Initial Value

R/W

FFh

Bit7

Bit6

1

Bit5

1

Bit4

Bit3

1

Bit2

1

Bit1

1

Bit0

1

VBAT_TH[11:4]

58h

1

VBAT_TH[12:0]

Battery Voltage Alarm Threshold.

Setting Range is from 0.000V to 8.176V, 16mV steps. It will be compared with VM_VBAT[12:4] (concatenated VM_VBAT_U[12:8] and VM_V


型号：	BD71815AGW
厂家：	ROHM
描述：	BD71815AGW凭借罗姆出众的模拟设计技术实现了“i.MX 7Solo/7Dual”处理器驱动的很好的电源系统。它不仅拥有与以往产品同等的功率转换效率（82%以上），还成功将待机时的电流消耗减少了16％※1，这是在应用中实现低功耗的关键。此外，还内置了30V耐压的带输入过电压保护功能（OVP）的Li-ion电池充电器和LED驱动器（6灯）。由于开关频率高速化（6MHz）实现的外接线圈的小型化、搭载功能的优化、以及采用WL-CSP的小型封装（16mm²：面积比以往减少75％）的应用，使得包含外接零件在内的贴装面积大幅度减少。内置库仑计数器，采用搭载罗姆独创算法的参考软件，实现了高精度电池余量监视。本产品对移动设备所追求的“低功耗”、“小型化”、“高精度”做出了很大贡献。※1 Buck converter部每个信道的消耗电流电池开关驱动驱动器计数器
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BD71815AGW [ROHM]

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