BD71850MWV [ROHM]
BD71850MWV是运用罗姆此前积累的处理器用电源技术，集成了i.MX 8M Nano Family处理器所需的电源和功能的PMIC。内置适用于i.MX 8M Nano Family的电源ON/OFF时序器，不仅可以实现小型化，还容易进行应用设计，有助于大幅削减开发周期。集成了控制逻辑、降压DC/DC转换器（Buck Converter）6ch、LDO6ch，只需1枚芯片，即可向处理器，以及应用所需的DDR存储器供电。而且内置SDXC卡用1.8V/3.3V开关、32.768kHz晶体振荡器的缓存、各种保护功能（各电源系统的输出短路、输出过电压、输出过电流和热关断）。配备高功率转换效率为95%的降压DC/DC转换器，可在1节Li-Ion电池到USB的大输入电压范围（2.7V~5.5V）内工作，是适合i.MX 8M Nano Famil适用领域的PMIC。;
| 型号： | BD71850MWV |
| 厂家： | 
ROHM |
| 描述： | BD71850MWV是运用罗姆此前积累的处理器用电源技术，集成了i.MX 8M Nano Family处理器所需的电源和功能的PMIC。内置适用于i.MX 8M Nano Family的电源ON/OFF时序器，不仅可以实现小型化，还容易进行应用设计，有助于大幅削减开发周期。集成了控制逻辑、降压DC/DC转换器（Buck Converter）6ch、LDO6ch，只需1枚芯片，即可向处理器，以及应用所需的DDR存储器供电。而且内置SDXC卡用1.8V/3.3V开关、32.768kHz晶体振荡器的缓存、各种保护功能（各电源系统的输出短路、输出过电压、输出过电流和热关断）。配备高功率转换效率为95%的降压DC/DC转换器，可在1节Li-Ion电池到USB的大输入电压范围（2.7V~5.5V）内工作，是适合i.MX 8M Nano Famil适用领域的PMIC。 电池 开关 双倍数据速率 集成电源管理电路 存储 振荡器 晶体振荡器 转换器 |
| 文件： | 总119页 (文件大小：1988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Power Management Integrated Circuit
BD71850MWV
General Description
Key Specifications
BD71850MWV is a programmable Power Management
IC (PMIC) for powering single-core, dual-core, and
quad-core SoC’s such as NXP-i.MX 8M Nano. It is
optimized for low BOM cost and compact solution
footprint. It integrates 6 Buck regulators and 6 LDO’s to
provide all the power rails required by the SoC and the
commonly used peripherals.
Input Voltage Range (VSYS):
SNVS State Current:
SUSPEND State Current:
IDLE State Current:
RUN State Current:
Operating Temperature Range:
2.7 V to 5.5 V
30 μA(Typ)
115 μA(Typ)
125 μA(Typ)
125 μA(Typ)
-40 °C to +105 °C
QFN package and pinout support low cost Type 3
(non-HDI) PCB. Programmable power sequencing
and output voltages, flexible power state control for
easier system design and supports a wide variety of
processors and system implementations.
Applications
Streaming Media Boxes and Dongles
AV Receivers and Wireless Sound Bars
Industrial HMI, SBC, IPC and Panel Computer
Package
UQFN56BV7070
W(Typ) x D(Typ) x H(Max)
7.00 mm x 7.00 mm x 1.00 mm
Features
6 Buck Regulators
2.0 MHz Switching Frequency.
(BUCK1, BUCK2, BUCK5, BUCK7, and BUCK8).
1.5MHz Switching Frequency. (BUCK6)
Target Efficiency: 83% to 95%.
Output Current & Voltage.
BUCK1: 3.0 A, 0.7 V to 1.3 V/10 mV step, DVS
BUCK2: 3.0 A, 0.7 V to 1.3 V/10 mV step, DVS
BUCK5: 3.0 A, 0.70 V to 1.35 V/8steps, DVS
BUCK6: 3.0 A, 2.6 V to 3.3 V/100 mV step
BUCK7: 1.5 A, 1.605 V to 1.995 V/8steps
BUCK8: 3.0 A, 0.8 V to 1.4 V/10 mV step
6ch Linear Regulators (6 LDOs)
LDO1: 10 mA, 3.0 V to 3.3 V, 1.6 V to 1.9 V
LDO2: 10 mA, 0.9 V, 0.8 V
LDO3: 300 mA, 1.8 V to 3.3 V
LDO4: 250 mA, 0.9 V to 1.8 V
LDO5: 300 mA, 0.8 V to 3.3 V
LDO6: 300 mA, 0.9 V to 1.8 V
Power Mux Switch
1.8V Input: 500 mΩ(Max)
3.3V Input: 500 mΩ(Max)
32.768 kHz Crystal Oscillator Driver
Power Button Detector
Protection and Monitoring: Soft Start, Power Rails Fault
Detection, UVLO, OVP and TSD
OTP Configurable Power Sequencing
OTP and Software Programmable Output Voltage,
Ramp rates.
Hardware Signaling with SoC for Transition into or out
of Low Power States
Interfaces:
I2C: 100 kHz/400 kHz, 1 MHz
Power-on Reset Output: POR_B, RTC_RESET_B,
Watchdog Reset Input: WDOG_B:
Power State Control:
PMIC_STBY_REQ, PMIC_ON_REQ, PWRON_B
Interrupt to SoC: IRQ_B
Type3 PCB Applicable
Product structure : Silicon integrated circuit. This product has no designed protection against radioactive rays
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Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Package
W(Typ) x D(Typ) x H(Max) ................................................................................................................1
1. Introduction.............................................................................................................................................................................7
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
1.8.
Terminology....................................................................................................................................................................7
System Power Map & Typical Application Circuit ...........................................................................................................8
Pin Configuration..........................................................................................................................................................10
Pin Description.............................................................................................................................................................11
I/O Equivalence Circuit.................................................................................................................................................12
Power Rail....................................................................................................................................................................13
Register Map................................................................................................................................................................14
ESD..............................................................................................................................................................................16
2. Operating Conditions............................................................................................................................................................17
2.1.
2.2.
2.3.
2.4.
2.5.
Absolute Maximum Ratings (Ta=25 ˚C)........................................................................................................................17
Thermal Resistance .....................................................................................................................................................17
Recommended Operating Conditions ..........................................................................................................................18
Current Consumption...................................................................................................................................................18
Power Reference and Detectors (UVLO).....................................................................................................................19
3. Power State Control .............................................................................................................................................................20
3.1.
3.1.1.
Power Control Signals..................................................................................................................................................20
PWRON_B...........................................................................................................................................................21
PMIC_ON_REQ...................................................................................................................................................21
PMIC_STBY_REQ...............................................................................................................................................21
WDOG_B.............................................................................................................................................................21
RTC_RESET_B...................................................................................................................................................22
POR_B.................................................................................................................................................................22
Power States................................................................................................................................................................23
Power State Diagram...........................................................................................................................................23
Power State Register...........................................................................................................................................24
Power State Definition .........................................................................................................................................26
Power State Control Events.................................................................................................................................27
3.1.2.
3.1.3.
3.1.4.
3.1.5.
3.1.6.
3.2.
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.2.4.1.
3.2.4.2.
3.2.5.
3.2.5.1.
Reset Event.................................................................................................................................................27
Emergency Shutdown Event .......................................................................................................................29
Power State Transitions.......................................................................................................................................29
OFF to READY............................................................................................................................................29
READY to SNVS .........................................................................................................................................30
SNVS to RUN..............................................................................................................................................33
RUN to IDLE................................................................................................................................................35
IDLE to RUN................................................................................................................................................35
RUN to SUSPEND ......................................................................................................................................35
SUSPEND to RUN ......................................................................................................................................35
IDLE to SUSPEND......................................................................................................................................36
Emergency Shutdown .................................................................................................................................36
VR Fault ......................................................................................................................................................37
EMG to OFF................................................................................................................................................41
EMG to READY...........................................................................................................................................42
EMG_STAY Condition .................................................................................................................................43
Warm Reset.................................................................................................................................................43
PWROFF.....................................................................................................................................................44
PWROFF to READY....................................................................................................................................46
PWROFF to SNVS......................................................................................................................................46
PWRON_B Functionality .............................................................................................................................46
3.2.5.2.
3.2.5.3.
3.2.5.4.
3.2.5.5.
3.2.5.6.
3.2.5.7.
3.2.5.8.
3.2.5.9.
3.2.5.10.
3.2.5.11.
3.2.5.12.
3.2.5.13.
3.2.5.14.
3.2.5.15.
3.2.5.16.
3.2.5.17.
3.2.5.18.
3.3.
3.3.1.
Power Sequence..........................................................................................................................................................48
Power ON Sequence...........................................................................................................................................48
Power OFF Sequence .........................................................................................................................................50
RUN to IDLE........................................................................................................................................................54
IDLE to RUN........................................................................................................................................................55
RUN to SUSPEND...............................................................................................................................................56
SUSPEND to RUN...............................................................................................................................................57
IDLE to SUSPEND ..............................................................................................................................................58
Emergency Shutdown..........................................................................................................................................59
Warm Reset.........................................................................................................................................................60
3.3.2.
3.3.3.
3.3.4.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.3.9.
3.3.10.
Reset Source Indicators.......................................................................................................................................61
4. I2C and Interrupt ..................................................................................................................................................................62
4.1.
4.1.1.
4.1.2.
I2C Bus Interface .........................................................................................................................................................62
I2C Bus Interface Overview .................................................................................................................................62
I2C Bus Interface Electrical Characteristics.........................................................................................................63
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BD71850MWV
4.1.3.
4.1.4.
4.2.
4.2.1.
Device Addressing...............................................................................................................................................65
Write / Read Operation ........................................................................................................................................66
Interrupt........................................................................................................................................................................67
Interrupt Overview ...............................................................................................................................................67
5. Power Rails ..........................................................................................................................................................................70
5.1.
5.2.
Output Voltage Range..................................................................................................................................................70
Details of Buck .............................................................................................................................................................72
BUCK1.................................................................................................................................................................72
5.2.1.
5.2.1.1.
5.2.1.2.
5.2.1.3.
5.2.2.
BUCK1 Block Diagram ................................................................................................................................72
BUCK1 Electrical Characteristics ................................................................................................................73
BUCK1 Control............................................................................................................................................74
BUCK2.................................................................................................................................................................76
BUCK2 Block Diagram ................................................................................................................................76
BUCK2 Electrical Characteristics ................................................................................................................77
BUCK2 Control............................................................................................................................................78
BUCK5.................................................................................................................................................................80
BUCK5 Block Diagram ................................................................................................................................80
BUCK5 Electrical Characteristics ................................................................................................................81
BUCK5 Control............................................................................................................................................82
BUCK6.................................................................................................................................................................83
BUCK6 Block Diagram ................................................................................................................................83
BUCK6 Electrical Characteristics ................................................................................................................84
BUCK6 Control............................................................................................................................................85
BUCK7.................................................................................................................................................................86
BUCK7 Block Diagram ................................................................................................................................86
BUCK7 Electrical Characteristics ................................................................................................................87
BUCK7 Control............................................................................................................................................88
BUCK8.................................................................................................................................................................89
BUCK8 Block Diagram ................................................................................................................................89
BUCK8 Electrical Characteristics ................................................................................................................90
BUCK8 Control............................................................................................................................................91
5.2.2.1.
5.2.2.2.
5.2.2.3.
5.2.3.
5.2.3.1.
5.2.3.2.
5.2.3.3.
5.2.4.
5.2.4.1.
5.2.4.2.
5.2.4.3.
5.2.5.
5.2.5.1.
5.2.5.2.
5.2.5.3.
5.2.6.
5.2.6.1.
5.2.6.2.
5.2.6.3.
5.3.
5.3.1.
5.3.1.1.
5.3.1.2.
5.3.1.3.
5.3.2.
Details of LDO..............................................................................................................................................................92
LDO1 ...................................................................................................................................................................92
LDO1 Block Diagram...................................................................................................................................92
LDO1 Electrical Characteristics...................................................................................................................93
LDO1 Control ..............................................................................................................................................94
LDO2 ...................................................................................................................................................................95
LDO2 Block Diagram...................................................................................................................................95
LDO2 Electrical Characteristics...................................................................................................................96
LDO2 Control ..............................................................................................................................................96
LDO3 ...................................................................................................................................................................97
LDO3 Block Diagram...................................................................................................................................97
LDO3 Electrical Characteristics...................................................................................................................98
LDO3 Control ..............................................................................................................................................99
LDO4 .................................................................................................................................................................100
LDO4 Block Diagram.................................................................................................................................100
LDO4 Electrical Characteristics.................................................................................................................101
LDO4 Control ............................................................................................................................................102
LDO5 .................................................................................................................................................................103
LDO5 Block Diagram.................................................................................................................................103
LDO5 Electrical Characteristics.................................................................................................................104
LDO5 Control ............................................................................................................................................105
LDO6 .................................................................................................................................................................106
LDO6 Block Diagram.................................................................................................................................106
LDO6 Electrical Characteristics.................................................................................................................107
LDO6 Control ............................................................................................................................................108
5.3.2.1.
5.3.2.2.
5.3.2.3.
5.3.3.
5.3.3.1.
5.3.3.2.
5.3.3.3.
5.3.4.
5.3.4.1.
5.3.4.2.
5.3.4.3.
5.3.5.
5.3.5.1.
5.3.5.2.
5.3.5.3.
5.3.6.
5.3.6.1.
5.3.6.2.
5.3.6.3.
5.4.
5.4.1.
5.4.2.
MUXSW .....................................................................................................................................................................109
MUXSW Block Diagram.....................................................................................................................................109
MUXSW Electrical Characteristics.....................................................................................................................110
6. 32.768 kHz Crystal Oscillator Driver................................................................................................................................... 111
6.1.
6.2.
32.768 kHz Crystal Oscillator Driver Block Diagram .................................................................................................. 111
32.768 kHz Crystal Oscillator Driver Electrical Characteristics .................................................................................. 111
7. Operational Notes ..............................................................................................................................................................112
8. Ordering Information...........................................................................................................................................................114
9. Marking Diagram................................................................................................................................................................114
10.
11.
Physical Dimension and Packing Information ................................................................................................................115
Revision History .............................................................................................................................................................116
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Figure
Figure 1-1. System Power Map ...............................................................................................................................................8
Figure 1-2. Typical Applications Circuit....................................................................................................................................9
Figure 1-3. Pin Configuration (TOP VIEW)............................................................................................................................10
Figure 1-4. I/O Equivalence Circuit 1.....................................................................................................................................12
Figure 2-1. Power Reference and Detectors Block Diagram .................................................................................................19
Figure 3-1. Power Control Signals of BD71850MWV ............................................................................................................20
Figure 3-2. Power State Transition ........................................................................................................................................23
Figure 3-3. Power Sub State Definition..................................................................................................................................25
Figure 3-4. VSYS Condition for moving to SNVS ..................................................................................................................30
Figure 3-5. PMIC_ON_REQ Condition for moving to SNVS..................................................................................................30
Figure 3-6. PWRON_B Short Push Condition for moving to SNVS .......................................................................................31
Figure 3-7. PWRON_B Long Push Condition for moving to SNVS........................................................................................31
Figure 3-8. Cold Reset Condition for moving to SNVS..........................................................................................................31
Figure 3-9. VSYS Condition for moving to RUN ....................................................................................................................33
Figure 3-10. PMIC_ON_REQ Condition for moving to RUN..................................................................................................33
Figure 3-11. PWRON_B Short Push Condition for moving to RUN .......................................................................................34
Figure 3-12. PWRON_B Long Push Condition for moving to RUN........................................................................................34
Figure 3-13. Cold Reset Condition for moving to RUN ..........................................................................................................34
Figure 3-14. Example of VR Fault and Recovery Sequence (RCVLMT[3:0] = 2) ..................................................................41
Figure 3-15. EMG to OFF Power State Transition.................................................................................................................41
Figure 3-16. EMG to READY Power State Transition (VSYS_UVLO) ...................................................................................42
Figure 3-17. EMG to READY Power State Transition (Die Temperature) ..............................................................................42
Figure 3-18. Warm Reset by WDOG_B.................................................................................................................................43
Figure 3-19. Cold Reset Duration Time set by PONT[3:0].....................................................................................................45
Figure 3-20. Power Button Block Diagram.............................................................................................................................46
Figure 3-21. Power ON Sequence.........................................................................................................................................48
Figure 3-22. Power OFF Sequence (To SNVS).....................................................................................................................50
Figure 3-23. Power OFF Sequence (To READY) ..................................................................................................................52
Figure 3-24. RUN to IDLE......................................................................................................................................................54
Figure 3-25. IDLE to RUN......................................................................................................................................................55
Figure 3-26. RUN to SUSPEND ............................................................................................................................................56
Figure 3-27. SUSPEND to RUN ............................................................................................................................................57
Figure 3-28. IDLE to SUSPEND............................................................................................................................................58
Figure 3-29. Emergency Shutdown .......................................................................................................................................59
Figure 3-30. Warm Reset (SWRESET) .................................................................................................................................60
Figure 3-31. Warm Reset (WDOG_B) ...................................................................................................................................60
Figure 3-32. Warm Reset (PWRON_B Long Push)...............................................................................................................60
Figure 4-1. I2C (Slave) Block Diagram ..................................................................................................................................62
Figure 4-2. I2C Bus Interface AC Timing ...............................................................................................................................64
Figure 4-3. I2C Device Addressing........................................................................................................................................65
Figure 4-4. I2C Write / Read Operation .................................................................................................................................66
Figure 4-5. IRQ_B Architecture Block Diagram .....................................................................................................................67
Figure 5-1. BUCK1 Block Diagram........................................................................................................................................72
Figure 5-2. BUCK2 Block Diagram........................................................................................................................................76
Figure 5-3. BUCK5 Block Diagram........................................................................................................................................80
Figure 5-4. BUCK6 Block Diagram........................................................................................................................................83
Figure 5-5. BUCK7 Block Diagram........................................................................................................................................86
Figure 5-6. BUCK8 Block Diagram........................................................................................................................................89
Figure 5-7. LDO1 Block Diagram...........................................................................................................................................92
Figure 5-8. LDO2 Block Diagram...........................................................................................................................................95
Figure 5-9. LDO3 Block Diagram...........................................................................................................................................97
Figure 5-10. LDO3 Voltage Source Switching .......................................................................................................................99
Figure 5-11. LDO4 Block Diagram.......................................................................................................................................100
Figure 5-12. LDO4 Voltage Source Switching .....................................................................................................................102
Figure 5-13. LDO5 Block Diagram.......................................................................................................................................103
Figure 5-14. LDO6 Block Diagram.......................................................................................................................................106
Figure 5-15. MUXSW Block Diagram ..................................................................................................................................109
Figure 5-16. MUXSW Sequence .........................................................................................................................................110
Figure 6-1. 32.768 kHz Crystal Oscillator Driver Block Diagram ......................................................................................... 111
Figure 9-1. Marking Diagram...............................................................................................................................................114
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Table
Table 1-1. Acronyms, Conventions and Terminology ...............................................................................................................7
Table 1-2. Pin Description......................................................................................................................................................11
Table 1-3. Power Rails and Output Signals ...........................................................................................................................13
Table 1-4. Register Map.........................................................................................................................................................14
Table 1-5. REV - Revision Register .......................................................................................................................................14
Table 1-6. REGLOCK - Lock Register ...................................................................................................................................15
Table 1-7. OTPVER – OTP Version Register.........................................................................................................................15
Table 1-8. ESD ......................................................................................................................................................................16
Table 2-1. Absolute Maximum Ratings...................................................................................................................................17
Table 2-2. Thermal Resistance (Note 1).....................................................................................................................................17
Table 2-3. Recommended Operating Conditions...................................................................................................................18
Table 2-4. Current Consumption............................................................................................................................................18
Table 2-5. Power Reference and Detectors Electrical Characteristics...................................................................................19
Table 3-1. PWRON_B Electrical Characteristics....................................................................................................................21
Table 3-2. PMIC_ON_REQ Electrical Characteristics............................................................................................................21
Table 3-3. PMIC_STBY_REQ Electrical Characteristics........................................................................................................21
Table 3-4. WDOG_B Electrical Characteristics......................................................................................................................21
Table 3-5. RTC_RESET_B Electrical Characteristics ............................................................................................................22
Table 3-6. POR_B Electrical Characteristics..........................................................................................................................22
Table 3-7. POW_STATE – Power State Register...................................................................................................................24
Table 3-8. Voltage Rails ON/OFF for Respective Power State ..............................................................................................27
Table 3-9. Setting of Cold or Warm Reset Selection..............................................................................................................28
Table 3-10. SWRESET - Software Reset Register ................................................................................................................28
Table 3-11. PWRCTRL0 - Power Control 0 Register .............................................................................................................28
Table 3-12. Conditions from OFF to READY state.................................................................................................................29
Table 3-13. Conditions from READY to SNVS.......................................................................................................................30
Table 3-14. TRANS_COND0 - Transition Condition Select 0 Register ..................................................................................32
Table 3-15. Conditions from SNVS to RUN ...........................................................................................................................33
Table 3-16. Conditions from RUN to IDLE .............................................................................................................................35
Table 3-17. PWRCTRL1 - Power Control 1 Register.............................................................................................................35
Table 3-18. Conditions from IDLE to RUN .............................................................................................................................35
Table 3-19. Conditions from RUN to SUSPEND....................................................................................................................35
Table 3-20. Conditions from SUSPEND to RUN....................................................................................................................35
Table 3-21. Conditions from IDLE to SUSPEND....................................................................................................................36
Table 3-22. Conditions from SNVS, RUN, IDLE, SUSPEND, PWROFF to EMG...................................................................36
Table 3-23. VR FAULT threshold and monitoring condition....................................................................................................37
Table 3-24. VRFAULTEN - VR FAULT ON/OFF Register: Debugging Purpose.....................................................................38
Table 3-25. MVRFLTMASK0 - VR FAULT Mask 0 Register...................................................................................................38
Table 3-26. MVRFLTMASK1 - VR FAULT Mask 1 Register...................................................................................................39
Table 3-27. MVRFLTMASK2 - VR FAULT Mask 2 Register...................................................................................................39
Table 3-28. RCVCFG - Recovery Configuration Register......................................................................................................40
Table 3-29. RCVNUM - Recovery Number Register..............................................................................................................40
Table 3-30. Conditions from EMG to OFF..............................................................................................................................41
Table 3-31. Conditions from EMG to READY ........................................................................................................................42
Table 3-32. Conditions for Stay at EMG.................................................................................................................................43
Table 3-33. Conditions from RUN, IDLE, SUSPEND to PWROFF ........................................................................................44
Table 3-34. TRANS_COND1 - Transition Condition Select 1 Register ..................................................................................44
Table 3-35. VR Summary After Power OFF Sequence..........................................................................................................45
Table 3-36. PWRONCONFIG0 - PWRON_B Configuration 0 Register..................................................................................46
Table 3-37. PWRONCONFIG1 - PWRON_B Configuration 1 Register..................................................................................47
Table 3-38. Power ON Sequence Timing Specification..........................................................................................................49
Table 3-39. Power OFF Sequence Timing Specification (To SNVS)......................................................................................51
Table 3-40. Power OFF Sequence Timing Specification (To READY) ...................................................................................53
Table 3-41. RUN to IDLE Timing Specification ......................................................................................................................54
Table 3-42. IDLE to RUN Timing Specification ......................................................................................................................55
Table 3-43. RUN to SUSPEND Timing Specification.............................................................................................................56
Table 3-44. SUSPEND to RUN Timing Specification .............................................................................................................57
Table 3-45. IDLE to SUSPEND Timing Specification.............................................................................................................58
Table 3-46. Emergency Shutdown Timing Specification ........................................................................................................59
Table 3-47. Warm Reset (SWRESET) Timing Specification ..................................................................................................60
Table 3-48. Warm Reset (WDOG_B) Timing Specification ....................................................................................................60
Table 3-49. Warm Reset (PWRON_B Long Push) Timing Specification................................................................................60
Table 3-50. RESETSRC - Reset Source Indicator Register...................................................................................................61
Table 4-1. I2C Bus Interface DC Electrical Characteristics....................................................................................................63
Table 4-2. I2C Bus Interface AC Timing - Fast Mode.............................................................................................................64
Table 4-3. I2C_DEV - I2C Device Address Indicator Register ...............................................................................................65
Table 4-4. Interrupt Event ......................................................................................................................................................67
Table 4-5. IRQ_B Electrical Characteristics...........................................................................................................................67
Table 4-6. IRQ - Interrupt Register.........................................................................................................................................68
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Table 4-7. MIRQ – IRQ Mask Register ..................................................................................................................................68
Table 4-8. IN_MON - Input Port Monitor Register..................................................................................................................69
Table 5-1. Output Voltage Range1.........................................................................................................................................70
Table 5-2. Output Voltage Range2.........................................................................................................................................71
Table 5-3. BUCK1 Electrical Characteristics..........................................................................................................................73
Table 5-4. BUCK1_CTRL - BUCK1 Control Register.............................................................................................................74
Table 5-5. BUCK1_VOLT_RUN - BUCK1 Voltage (RUN) Register........................................................................................74
Table 5-6. BUCK1_VOLT_IDLE - BUCK1 Voltage (IDLE) Register .......................................................................................75
Table 5-7. BUCK1_VOLT_SUSP - BUCK1 Voltage (SUSPEND) Register ............................................................................75
Table 5-8. BUCK2 Electrical Characteristics..........................................................................................................................77
Table 5-9. BUCK2_CTRL - BUCK2 Control Register.............................................................................................................78
Table 5-10. BUCK2_VOLT_RUN - BUCK2 Voltage (RUN) Register......................................................................................78
Table 5-11. BUCK2_VOLT_IDLE - BUCK2 Voltage (IDLE) Register......................................................................................79
Table 5-12. BUCK5 Electrical Characteristics........................................................................................................................81
Table 5-13. BUCK5_CTRL - BUCK5 Control Register...........................................................................................................82
Table 5-14. BUCK5_VOLT - BUCK5 Voltage Register...........................................................................................................82
Table 5-15. BUCK6 Electrical Characteristics........................................................................................................................84
Table 5-16. BUCK6_CTRL - BUCK6 Control Register...........................................................................................................85
Table 5-17. BUCK6_VOLT - BUCK6 Voltage Register...........................................................................................................85
Table 5-18. BUCK7 Electrical Characteristics........................................................................................................................87
Table 5-19. BUCK7_CTRL - BUCK7 Control Register...........................................................................................................88
Table 5-20. BUCK7_VOLT - BUCK7 Voltage Register...........................................................................................................88
Table 5-21. BUCK8 Electrical Characteristics........................................................................................................................90
Table 5-22. BUCK8_CTRL - BUCK8 Control Register...........................................................................................................91
Table 5-23. BUCK8_VOLT - BUCK8 Voltage Register...........................................................................................................91
Table 5-24. LDO1 Electrical Characteristics ..........................................................................................................................93
Table 5-25. LDO1_VOLT - LDO1 Voltage Register................................................................................................................94
Table 5-26. LDO2 Electrical Characteristics ..........................................................................................................................96
Table 5-27. LDO2_VOLT - LDO2 Voltage Register................................................................................................................96
Table 5-28. LDO3 Electrical Characteristics ..........................................................................................................................98
Table 5-29. LDO3_VOLT - LDO3 Voltage Register................................................................................................................99
Table 5-30. LDO4 Electrical Characteristics ........................................................................................................................101
Table 5-31. LDO4_VOLT - LDO4 Voltage Register..............................................................................................................102
Table 5-32. LDO5 Electrical Characteristics ........................................................................................................................104
Table 5-33. LDO5_VOLT - LDO5 Voltage Register..............................................................................................................105
Table 5-34. LDO6 Electrical Characteristics ........................................................................................................................107
Table 5-35. LDO6_VOLT - LDO6 Voltage Register..............................................................................................................108
Table 5-36. MUXSW Electrical Characteristics....................................................................................................................110
Table 5-37. SD_VSELECT Electrical Characteristics...........................................................................................................110
Table 5-38. MUXSW Sequence Timing................................................................................................................................110
Table 5-39. MUXSW_EN - MUXSW Enable Register..........................................................................................................110
Table 6-1. C32K_OUT Control Register............................................................................................................................... 111
Table 6-2. 32.768 kHz Crystal Oscillator Driver Electrical Characteristics ........................................................................... 111
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1. Introduction
1.1. Terminology
Table 1-1. Acronyms, Conventions and Terminology
Term
BOM Bill Of Materials
Definition
DAC
DVS
FET
I2C
Digital to Analog Converter
Dynamic Voltage Scaling
Field Effect Transistor
Inter-Integrated Circuit
IRQ
LDO
NTC
Interrupt Request
Low Drop-Out regulator
Negative Temperature Coefficient. (a type of thermistor)
OCP Over Current Protection
OTP
OVP
One Time Programmable memory
Over Voltage Protection
PFM Pulse-FrequencyModulation
POR Power On Reset
PWM Pulse-Width Modulation
SMPS Switched Mode Power Supply
SoC
UVLO Under Voltage-LockOut
VR Voltage Regulator
System-On-a-Chip
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1.2. System Power Map & Typical Application Circuit
i.MX8M Nano
BD71850MWV
BUCK1 – DVS
3.0 A, 0.7 V to 1.3 V
/10 mV step
0.8 V/0.9 V
VDD_SOC
VDDA_0V8
PHY_0V8
VSYS(5V)
VDD_DRAM
VDD_GPU
BUCK2 – DVS
3.0 A, 0.7 V to 1.3 V
/10 mV step
0.8 V/0.9 V/ 1.0V
VDD_ARM
I2C I/F
PWRON_B
PMIC_STBY_REQ
PMIC_ON_REQ
HOST
I/F
WDOG_B
RTC_RESET_B
POR_B
BUCK5 - DVS
3.0 A, 0.70 V to 1.35 V
/ 8steps
OFF
IRQ_B
BUCK8
3.0 A, 0.8 V to 1.4 V
/10 mV step
1.10 V/1.20 V/1.35 V
SD_VSELECT
C32K_OUT
NVCC_DRAM
LDO1
1.8V
10 mA, 3.0 V to 3.3 V
/1.6 V to 1.9 V
NVCC_SNVS
VDD_SNVS
LDO2
10 mA,
0.8V
0.9 V/0.8 V
XIN
32kHz
Crystal
Driver
XOUT
BUCK6
3.0 A, 2.6 V to 3.3 V
/0.1 V step
3.3V
NVCC_3V3
LDO3
300 mA,
1.8 V to 3.3 V
VDDA_1V8
VDDA_DRAM
1.8V
OFF
LDO5
300 mA,
0.8 V to 3.3 V
BUCK7
1.5 A, 1.605 V to
1.995 V/ 8steps
1.8V
OFF
NVCC_1V8
LDO4
250 mA,
0.9 V to 1.8 V
LDO6
300 mA,
0.9 V to 1.8 V
VDD_PHY_1V2
(MIPI)
1.2V
1.8V
3.3V
1.8V/3.3V(SD CARD)
150mA MUXSW
Figure 1-1. System Power Map
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1.2. System Power Map & Typical Application Circuit - continued
BD71850MWV
VDD_V1P5
BUCK1
VDD_V1P5
VSYS
VSYS
(VDD_SOC
VDDA_0V8
PHY_0V8
VDD_DRAM
VDD_GPU)
VDD_V1P5
BUCK1_VIN
BUCK1_LX
VSYS
VDD_V1P5
VREF
BUCK1
VREF
Voltage
Reference
INTLDO1P5
AGND
Buck Converter
DVS 0.7 V to 1.3 V / 3.0 A
Internal
Power On Reset
PGND
BUCK1_FB
UVLO
TSD
VDD_V1P5
VSYS
VSYS
BUCK2_VIN
BUCK2_LX
Connect to the VSYS pin when not use the
Power Button Function
VREF
VDD_V1P5
BUCK2
(VDD_ARM)
VSYS
BUCK2
CLOCK Generator
Buck Converter
DVS 0.7 V to 1.3 V / 3.0 A
PWRON_B
OTP
PGND
BUCK2_FB
Power ON Key
VDD_V1P5
XIN
32.768 kHz
Crystal Oscillator Driver
XOUT
VDD_V1P5
DVDD,VSYS
C32K_OUT
NVCC_SNVS
NVCC_SNVS
DVDD
SCL
I2C Slave Interface
SDA
NVCC_SNVS
POR_B
IRQ_B
SOC
RTC_RESET_B
Power Controll
PMIC_ON_REQ
PMIC_STBY_REQ
SD_VSELECT
VDD_V1P5
VSYS
WDOG_B
Register
VSYS
Sequencer
BUCK5_VIN
BUCK5_LX
VREF
VSYS
VDD_V1P5
VREF
VSYS
BUCK5
VSYS
BUCK5
(Note 1)
Buck Converter
DVS 0.7 V to 1.35 V / 3.0 A
LDO1
LDO1
(NVCC_SNVS)
3.0 V to 3.3 V, 1.6 V
to 1.9 V / 10 mA
LDO1_VOUT
LDO2_VOUT
PGND
LDO2
BUCK5_FB
LDO2
(VDD_SNVS)
0.9 V, 0.8V / 10 mA
VDD_V1P5
VSYS
VSYS
VSYS
VSYS
BUCK6_VIN
BUCK6_LX
VREF
BUCK6
(NVCC_3V3)
VSYS/VIN_1P8
VDD_V1P5
BUCK6
BUCK7
VSYS
VIN_1P8_1
Buck Converter
2.6 V to 3.3 V / 3.0 A
LDO4
PGND
0.9 V to1.8 V
/ 250 mA
BUCK6_FB
VREF
VSYS
LDO6
0.9 V to 1.8 V
/ 300 mA
VDD_V1P5
VSYS
LDO4
BUCK7_VIN
BUCK7_LX
LDO4_VOUT
(Note 1)
VREF
BUCK7
(NVCC_1V8)
LDO6
(VDD_PHY_1V2)
BUCK7
LDO6_VOUT
VIN_1P8_2
VSYS
VDD_V1P5
Buck Converter
1.605 V to 1.995 V / 1.5 A
BUCK7
MUXSW
PGND
BUCK7_FB
1.8 V / 500 mΩ (Max)
3.3 V / 500 mΩ (Max)
LOADSW
(NVCC_SD2)
MUXSW_VOUT
VIN_3P3
VSYS/VIN_3P3
VDD_V1P5
BUCK6
VSYS
VDD_V1P5
VSYS
BUCK8_VIN
BUCK8_LX
VREF
BUCK8
(NVCC_DRAM)
VREF
BUCK8
VSYS
LDO3
1.8 V to 3.3 V
/ 300 mA
Buck Converter
0.8 V to 1.4 V / 3.0 A
LDO3
LDO5
0.8 V to 3.3 V
/ 300 mA
(VDDA_1V8&VDDA_DRAM)
PGND
BUCK8_FB
LDO3_VOUT
LDO5_VOUT
LDO5
(Note 1)
PGND
PGND (EXP-PAD)
(Note 1) Output components of BUCK5, LDO4 and LDO5 can be removed because their default settings of OTP are OFF. Other power rails output components
cannot be removed. If they are removed, VR fault would be detected and PMIC would be shut down.
Figure 1-2. Typical Applications Circuit
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1.3. Pin Configuration
EXP-PAD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VIN_1P8_1 43
LDO6_VOUT 44
SD_VSELECT 45
BUCK6_FB 46
BUCK6_VIN 47
BUCK6_VIN 48
BUCK6_LX 49
BUCK6_LX 50
BUCK7_LX 51
BUCK7_LX 52
BUCK7_VIN 53
BUCK7_FB 54
MUXSW_VOUT 55
VIN_1P8_2 56
28 DVDD
27 SDA
26 SCL
25 POR_B
24 BUCK2_FB
23 BUCK2_VIN
22 BUCK2_LX
21 BUCK2_LX
20 BUCK1_LX
19 BUCK1_LX
18 BUCK1_VIN
17 BUCK1_FB
16 PMIC_STBY_REQ
15 PMIC_ON_REQ
EXP-PAD
(PGND)
1Pin Mark
2
1
3
4
5
6
7
8
9
10
11
12
13
14
EXP-PAD
Figure 1-3. Pin Configuration (TOP VIEW)
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1.4. Pin Description
Table 1-2. Pin Description
PWR
/GND
PWR
Voltage
Level
VSYS
Terminal
Equivalent pull-up/down
Internal
Pin# Block Name
Pin Name
Dir
Pin Description
18
19
BUCK1_VIN
BUCK1_LX
BUCK1_LX
BUCK1_FB
BUCK2_VIN
BUCK2_LX
BUCK2_LX
BUCK2_FB
BUCK5_VIN
BUCK5_VIN
BUCK5_LX
BUCK5_LX
BUCK5_FB
BUCK6_VIN
BUCK6_VIN
BUCK6_LX
BUCK6_LX
BUCK6_FB
BUCK7_VIN
BUCK7_LX
BUCK7_LX
BUCK7_FB
BUCK8_VIN
BUCK8_LX
BUCK8_LX
BUCK8_FB
VSYS
I
O
O
I
BUCK1 switcher input supply
BUCK1 switch node connection
BUCK1 switch node connection
BUCK1 feedback sense
BUCK2 switcher input supply
BUCK2 switch node connection
BUCK2 switch node connection
BUCK2 feedback sense
BUCK5 switcher input supply
BUCK5 switcher input supply
BUCK5 switch node connection
BUCK5 switch node connection
BUCK5 feedback sense
BUCK6 switcher input supply
BUCK6 switcher input supply
BUCK6 switch node connection
BUCK6 switch node connection
BUCK6 feedback sense
BUCK7 switcher input supply
BUCK7 switch node connection
BUCK7 switch node connection
BUCK7 feedback sense
BUCK8 switcher input supply
BUCK8 switch node connection
BUCK8 switch node connection
BUCK8 feedback sense
LDO1, LDO2 input supply
LDO1 output
LDO2 output
LDO4, LDO6 input supply
LDO4 input supply
LDO4 output
LDO6 output
LDO3,MUXSW input supply
LDO3,LDO5 input supply
LDO3 output
LDO5 output
LDO3,MUXSW input supply
MUXSW input supply
LOADSW output
Internal LDO for PMIC
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
D2_1
H1_1
H1_1
H1_1
D2_1
G1_1
G1_1
G1_1
G1_2,G3_1
G1_1,G3_1
G3_1
G1_2
G3_2
G1_1,G3_2
G3_2
G1_1
F2_1
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
-
-
-
VSYS
VSYS
BUCK1
VSYS
VSYS
VSYS
BUCK2
VSYS
VSYS
VSYS
VSYS
BUCK5
VSYS
VSYS
VSYS
VSYS
BUCK6
VSYS
VSYS
VSYS
BUCK7
VSYS
VSYS
VSYS
BUCK8
VSYS
LDO1
LDO2
BUCK7
VSYS
LDO4
LDO6
BUCK6
VSYS
LDO3
LDO5
BUCK6
BUCK7
LOADSW
BUCK1
20
17
23
21
I
PWR
-
-
-
PWR
PWR
-
-
O
O
I
I
I
O
O
I
I
I
BUCK2
22
24
31
32
33
34
30
47
48
49
50
46
53
51
52
54
37
35
36
38
9
BUCK5
BUCK6
-
PWR
PWR
-
-
O
O
I
-
I
PWR
-
-
-
PWR
-
-
-
PWR
-
-
PWR
PWR
-
O
O
I
BUCK7
BUCK8
I
O
O
I
I
LDO1
LDO2
10
8
LDO1_VOUT
LDO2_VOUT
VIN_1P8_1
VSYS
LDO4_VOUT
LDO6_VOUT
VIN_3P3
O
O
I
43
41
42
44
7
5
6
4
1
56
55
11
12
14
13
28
26
27
29
39
25
3
LDO4
LDO6
I
O
O
I
-
PWR
PWR
-
LDO3
LDO5
VSYS
I
LDO3_VOUT
LDO5_VOUT
VIN_3P3
VIN_1P8_2
MUXSW_VOUT
INTLDO1P5
AGND
O
O
I
-
PWR
PWR
-
PWR INTLDO1P5
GND
MUXSW
REF
I
F2_1
F2_1
G1_3
Z1_1
E1_1
O
O
I
I
O
I
AGND
0V
INTLDO1P5
INTLDO1P5
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
Crystal
Oscillator
XIN
XOUT
DVDD
SCL
32.768kHz crystal input
32.768kHz crystal output
Interface input supply
-
-
E1_1
Z1_1
A1_1
A3_1
C1_1
C1_1
C1_1
C1_1
C1_1
A6_1
C1_1
C1_1
A6_1
PWR
I2C CLOCK
No(Note 1)
No(Note 1)
No
I
-
-
-
-
-
-
-
-
-
-
-
I2C DATA
SDA
C32K_OUT
IRQ_B
POR_B
RTC_RESET_B
WDOG_B
PMIC_ON_REQ
PMIC_STBY_REQ
SD_VSELECT
PWRON_B
I /O
O
O
O
O
I
I
I
I
I
32.768kHz clock output
No(Note 1)
No(Note 1)
No(Note 1)
No
No
No
Interrupt signal to processor(Open Drain)
Power on reset output(Open Drain)
Power OK signal for LDO1,2(Open Drain)
Watchdog input from processor
Power on/off control Input
Interface
2
DVDD
VSYS
DVDD
DVDD
15
16
45
40
Standby input signal
Voltage select for SD
No
No
Power Button
VSYS
Power Ground. Connect the center EXP-PAD in the Figure 1-3
to the GND plane of PCB. The EXP-PADs on the 4-corner have
the same potential as the center EXP-PAD. The EXP-PADs on GND
the 4-coner are recommended to be soldered to PCB (GND or
open).
EXP-PAD
(PGND)
-
-
-
0V
Z1_1
No
(Note 1) Need to pull-up external resistance to DVDD
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1.5. I/O Equivalence Circuit
VDD
VDD
VDD
A1_1)
A3_1)
A6_1)
VDD=DVDD
GND=AGND
VDD=DVDD
GND=AGND
VDD=VSYS
GND
GND GND
GND GND
GND
GND
(A1_1)
(A3_1)
(A6_1)
E1_1)
VDD=INTLDO1P5
GND=AGND
VDD
C1_1)
VDD=DVDD
GND=AGND
D2_1)
GND=AGND
VDD
VDD
XOUT
XIN
GND GND
GND
AGND
GND
VDD
GND
GND
GND
(C1_1)
(D2_1)
(E1_1)
VDD1
F2_1)
G3_1)
G1_1)
IN1
IN1=VIN_3P3
IN2=VIN_1P8_2
OUT
VDD1=VSYS
VDD2=VIN_1P8_1
GND=AGND
OUT=LDO4
G3_2)
VDD=VSYS
GND=AGND
OUT=LDO1,LDO2,
LDO5
GND
=MUXSW_VOUT
VDD2
G1_2)
VDD1=VSYS
VDD2=VIN_3P3
GND=AGND
OUT=LDO3
VDD=VIN_1P8_1
GND=AGND
OUT=LDO6
G1_3)
VDD=VSYS
GND=AGND
OUT=INTLDO1P5
GND
GND
IN2
OUT
OUT
GND
OUT
GND
GND
GND
GND
GND
AGND
GND
AGND
(F2_1)
(G1_1,2,3)
(G3_1,2)
H1_1)
BUCK1_VIN, BUCK2_VIN,
BUCK5_VIN to BUCK8_VIN
VDD
LX
VDD=BUCK1_VIN,
BUCK2_VIN,
BUCK5_VIN
to BUCK8_VIN
LX =BUCK1_LX,
BUCK2_LX,
DVDD
INTLDO1P5
VSYS
PGND
AGND
BUCK5_LX
to BUCK8_LX
GND=PGND
GND
(H1_1)
(Z1_1)
Figure 1-4. I/O Equivalence Circuit 1
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1.6. Power Rail
Table 1-3. Power Rails and Output Signals
Output Voltage
Output Voltage
Adjustable
Range [V]
Sequence
Order
Rail/Signal
Name
Input
Rail
Function
Type
Initial
Value [V]
DVS
IOMAX [A]
3.0 to 3.3,1.6 to 1.9
(100 mVstep)
1
2
3
4
NVCC_SNVS
VDD_SNVS
LDO1
LDO2
Source LDO VSYS
Source LDO VSYS
1.8
0.8
-
-
-
-
-
0.01
0.9, 0.8
0.01
RTC_RESET_B
32K_OUT
RTC_RESET_B
C32K_OUT
Open drain
CMOS
-
-
-
-
-
DVDD
-
VDD_SOC,
VDDA_0V8,
PHY_0V8,
VDD_DRAM,
VDD_GPU
0.7 to 1.3
(10 mVstep)
5
BUCK1
SMPS
VSYS
VSYS
0.8
DVS
3.0
0.7 to 1.3
(10 mVstep)
1.8 to 3.3
6
6
VDD_ARM
BUCK2
LDO3
SMPS
0.9
1.8
DVS
-
3.0
0.3
VDDA_1V8,
VDDA_DRAM
VSYS/
BUCK6
Source LDO
(100 mVstep)
1.605,1.695,1.755,
1.800,1.845,1.905,
1.950,1.995
7
NVCC_1V8
BUCK7
SMPS
VSYS
1.8
-
1.5
0.8 to 1.4
(10 mVstep)
2.6 to 3.3
8
9
NVCC_DRAM
BUCK8
BUCK6
MUXSW
LDO6
SMPS
SMPS
VSYS
VSYS
1.1
3.3
-
3.0
3.0
0.15
0.3
-
NVCC_3V3
-
(100mVstep)
BUCK6/
BUCK7
9
NVCC_SD2
MUXSwitch
3.3/1.8
1.2
-
-
0.9 to 1.8
(100 mVstep)
10
11
-
VDD_PHY_1V2
Source LDO BUCK7
-
POR_B
POR_B
BUCK5
LDO4
Open drain
SMPS
-
-
-
-
0.70,0.80,0.90,1.00
1.05,1.10,1.20,1.35
0.9 to 1.8
(100 mVstep)
0.8 to 3.3
-
-
-
VSYS
0.9
DVS
3.0
0.25
0.3
VSYS/
BUCK7
-
Source LDO
0.9
-
-
-
LDO5
Source LDO VSYS
3.3
(100 mVstep)
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1.7. Register Map
Table 1-4. Register Map
Write
Access
Lock
Reset
Condition
(Note 1)
Initial
Value
(Hex)
Address
(Hex)
Access
(R, W, R/W)
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
OTP
(Note 2)
00
01
02
03
04
05
06
07
08
NA
UVLO
UVLO
UVLO
UVLO
READY
READY
-
REV
SWRESET
I2C_DEV
PWRCTRL0
PWRCTRL1
BUCK1_CTRL
BUCK2_CTRL
-
MAJREV[3:0]
MINREV[3:0]
SWRESET_SEL[1:0]
A1
04
03
A2
00
40
40
-
R
R/W
R
No
No
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SWRESET
-
-
-
-
-
-
-
-
-
I2C_DEV_ADRS[1:0]
WDOGB_SEL[1:0]
Yes
Yes
Yes
Yes
Yes
-
-
DEBUG_STATE[1:0]
RELOAD_REG
-
R/W
R/W
R/W
R/W
-
PWRSEQ
-
-
-
-
-
-
-
-
-
IDLE_MODE
-
BUCK1_RAMPRATE[1:0]
BUCK2_RAMPRATE[1:0]
BUCK1_PWM_FIX
BUCK1_SEL
BUCK1_EN
VREG
VREG
-
BUCK2_PWM_FIX
BUCK2_SEL
BUCK2_EN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
09
0A
0B
0C
0D
0E
0F
10
READY
READY
READY
READY
READY
READY
READY
READY
BUCK5_CTRL
BUCK6_CTRL
-
-
-
-
-
-
-
-
BUCK5_PWM_FIX
-
-
-
-
BUCK5_SEL
BUCK6_SEL
BUCK7_SEL
BUCK8_SEL
BUCK5_EN
BUCK6_EN
BUCK7_EN
BUCK8_EN
02
00
00
00
0A
0A
0A
14
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
VREG
VREG
VREG
VREG
VREG
VREG
VREG
VREG
BUCK6_PWM_FIX
BUCK7_CTRL
BUCK7_PWM_FIX
BUCK8_CTRL
BUCK8_PWM_FIX
BUCK1_VOLT_RUN
BUCK1_VOLT_IDLE
BUCK1_VOLT_SUSP
BUCK2_VOLT_RUN
BUCK1_VOLT_RUN[6:0]
BUCK1_VOLT_IDLE[6:0]
BUCK1_VOLT_SUSP[6:0]
BUCK2_VOLT_RUN[6:0]
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
READY
-
BUCK2_VOLT_IDLE
-
-
-
-
BUCK2_VOLT_IDLE[6:0]
0A
-
R/W
-
Yes
-
VREG
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
READY
READY
READY
READY
READY
READY
READY
READY
READY
READY
-
BUCK5_VOLT
BUCK6_VOLT
BUCK7_VOLT
BUCK8_VOLT
LDO1_VOLT
LDO2_VOLT
LDO3_VOLT
LDO4_VOLT
LDO5_VOLT
LDO6_VOLT
-
BUCK5_VOLT_SEL[1:0]
-
BUCK5_VOLT[2:0]
02
03
03
1E
22
20
00
80
8F
03
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
VREG
VREG
VREG
VREG
VREG
VREG
VREG
VREG
VREG
VREG
-
-
-
-
BUCK6_VOLT_SEL
-
-
BUCK6_VOLT[1:0]
-
-
BUCK7_VOLT[2:0]
BUCK8_VOLT[6:0]
LDO1_SEL
LDO2_SEL
LDO3_SEL
LDO4_SEL
LDO5_SEL
LDO6_SEL
-
LDO1_EN
LDO2_EN
LDO3_EN
LDO4_EN
LDO5_EN
LDO6_EN
-
LDO1_VOLT_SEL
-
-
-
-
-
LDO1_VOLT[1:0]
LDO2_VOLT_SEL
-
-
-
-
-
LDO3_VOLT[3:0]
-
-
LDO4_VOLT[3:0]
LDO5_VOLT[3:0]
LDO6_VOLT[3:0]
-
LDO5_VOLT_SEL
-
-
-
-
-
-
-
-
C1_
C1_
C1_
C1_
C0_
C0_
C0_
C0_
1F
20
UVLO
UVLO
TRANS_COND0
TRANS_COND1
VSYS_3P0_
ONLY_EN
PMIC_ON_
REQ_EN
SHORT_
PUSH_EN
LONG_
PUSH_EN
VSYS_3P0_
ONLY_EN
PWRON_
POFF_TO_
READY
PMIC_ON_
REQ_EN
WDOG_
POFF_TO_
READY
SHORT_
LONG_
48
C0
R/W
R/W
Yes
Yes
PWRSEQ
PWRSEQ
PUSH_EN
SWRST_
POFF_TO_
READY
PUSH_EN
ON_REQ_
POFF_TO_
READY
PONT[3:0]
21
22
UVLO
UVLO
VRFAULTEN
-
-
-
-
-
-
-
VRFLTEN
MBUCK5_
VOUTOKL
MBUCK1_
VOUTOKL
MLDO1_
01
00
R/W
R/W
Yes
Yes
-
-
MBUCK8_
VOUTOKH
MBUCK8_
VOUTOKL
MBUCK7_
VOUTOKH
MBUCK7_
VOUTOKL
MBUCK6_
VOUTOKH
MBUCK2_
VOUTOKH
MLDO4_
VOUTOKL
MBUCK6_
VOUTOKL
MBUCK2_
VOUTOKL
MLDO3_
VOUTOKL
MBUCK5_
VOUTOKH
MBUCK1_
VOUTOKH
MLDO2_
VOUTOKL
MVRFLTMASK0
23
24
UVLO
UVLO
MVRFLTMASK1
MVRFLTMASK2
-
-
-
-
-
-
00
00
R/W
R/W
Yes
Yes
-
-
MLDO6_
VOUTOKL
MLDO5_
VOUTOKL
VOUTOKL
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
FF
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
READY
READY
READY
NA
RCVCFG
RCVNUM
RCVLMT[3:0]
RCVDT[3:0]
4C
00
16
00
00
7F
00
00
00
01
11
01
C3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Yes
No
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RCVNUM[3:0]
SHORTT[3:0]
LONGT[3:0]
PWRONCONFIG0
PWRONCONFIG1
RESETSRC
MIRQ
-
-
PBDBNCT[1:0]
Yes
Yes
No
-
-
-
-
RPWRON
RWDOG
MSWRST
SWRST
-
RSWRST
MPWRON_S
PWRON_S
-
RPMIC_ON_REQ
MPWRON_L
PWRON_L
-
RVSYS_2P7
RTEMP
ROCP
RVR_FAULT
MSTBY_REQ
-
-
-
MPWRON
MWDOG
MON_REQ
ON_REQ
No
IRQ
PWRON
WDOG
STBY_REQ
No
IN_MON
STAT_PWRON
STAT_WDOG
STAT_ON_REQ
STAT_STBY_REQ
No
POW_STATE
OUT32K
POW_ST[3:0]
-
-
-
-
-
-
-
-
POW_SUB[1:0]
R
No
-
-
-
-
-
-
-
-
-
-
VREG
-
-
-
-
OUT32K_EN
PWRSEQ
R/W
R/W
R/W
R
Yes
No
REGLOCK
MUXSW_EN
OTPVER
MUXSW_EN
Yes
Yes
OTPVER[7:0]
(Note 1) Reset Condition of each register is classified as follow s.
UVLO: When INTLDO1P5_UVLO=0, register values are reset to the default value.
READY: When Pow er State enters READY, register values are reset to the default value.
(Note 2) Regarding registes labeled in this column, its w rite access is disabled as follow s.
PWRSEQ: When PWRSEQ in REGLOCK register is set to 1, w rite access is disabled.
VREG: When VREG in REGLOCK register is set to 1, w rite access is disabled.
Table 1-5. REV - Revision Register
Register Name
REV
R/W
R
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0xA1
Address
0x00
MAJREV[3:0]
MINREV[3:0]
Bit
Name
Function
Initial
D[7:4]
MAJREV[3:0]
MINREV[3:0]
Major Revision
Minor Revision
1010
0001
D[3:0]
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1.7. Register Map – continued
Table 1-6. REGLOCK - Lock Register
Register Name
REGLOCK
R/W
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
-
D0
Initial
0x11
Address
0x2F
-
VREG
-
-
PWRSEQ
Bit
Name
Function
Initial
Write access to following 21 registers is controlled bythis bit.
0 = Enable the write access
1 = Disable the write access
BUCK1_CTRL, BUCK2_CTRL,
BUCK5_CTRL, BUCK6_CTRL, BUCK7_CTRL, BUCK8_CTRL
BUCK1_VOLT_RUN, BUCK1_VOLT_IDLE
VREG
1
D[4]
BUCK1_VOLT_SUSP, BUCK2_VOLT_RUN
BUCK2_VOLT_IDLE, BUCK5_VOLT, BUCK6_VOLT, BUCK7_VOLT
BUCK8_VOLT, LDO1_VOLT, LDO2_VOLT, LDO3_VOLT
LDO4_VOLT, LDO5_VOLT, LDO6_VOLT
Write access to following 3 registers is controlled bythis bit.
0 = Enable the write access
PWRSEQ
1 = Disable the write access
1
D[0]
PWRCTRL0, TRANS_COND0, TRANS_COND1
Table 1-7. OTPVER – OTP Version Register
Register Name
OTPVER
R/W
R
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0xC3
Address
0xFF
OTPVER[7:0]
Bit
Name
Function
Initial
0xC3
D[7:0]
OTP_VER[7:0]
OTP Version
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1.8. ESD
Table 1-8. ESD
Minimum
Parameter
Unit
Limit
±2000
±1000
Human BodyModel(HBM)
V
V
Charged Device Model(CDM)
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2. Operating Conditions
2.1. Absolute Maximum Ratings (Ta=25 ˚C)
Table 2-1. Absolute Maximum Ratings
Limit
Parameter
Symbol
Unit
V
Min
Max
+6.0
Voltage Range in PINs:
VSYS, BUCK1_VIN, BUCK2_VIN, BUCK5_VIN to BUCK8_VIN,
VIN_1P8_1, VIN_1P8_2, VIN_3P3, PWRON_B, PMIC_ON_REQ
Voltage Range in PIN:
VAMR_1
-0.3
VAMR_2
VAMR_3
VAMR_4
-0.3
-0.3
+4.5
+2.1
+7.0
V
V
V
DVDD
Voltage Range in PIN:
INTLDO1P5
Voltage Range in PINs:
-1.0(DC)
-2.0(10 ns)
BUCK1_LX, BUCK2_LX, BUCK5_LXto BUCK8_LX
Voltage Range in PINs:
SCL,SDA,IRQ_B,POR_B,WODG_B, RTC_RESET_B
PMIC_STBY_REQ,SD_VSELECT,C32K_OUT
Voltage Range in PINs:
VAMR_5
-0.3
+4.5
V
BUCK1_FB, BUCK2_FB, BUCK5_FB to BUCK8_FB,
LDO1_VOUT to LDO6_VOUT, MUXSW_VOUT
Voltage Range in PINs:
VAMR_6
-0.3
-0.3
+4.5
+2.1
V
V
VAMR_7
XIN, XOUT
Maximum Junction Temperature
Tjmax
Tstg
-
150
°C
°C
Storage Temperature Range
-55
+150
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
2.2. Thermal Resistance
Table 2-2. Thermal Resistance (Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
2s2p(Note 4)
1s(Note 3)
UQFN56BV7070
Junction to Ambient
28.1
6
θJA
ΨJT
76.8
6
°C/W
°C/W
Junction to Top Characterization Parameter(Note 2)
(Note 1) Based on JESD51-2A(Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
ꢀꢀꢀꢀꢀꢀꢀsurface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
114.3mm x76.2mm x1.57mmt
Single
Top
Copper Pattern
Thickness
Footprints and Traces
70μm
Thermal Via(Note 6)
Layer Number of
Measurement Board
Material
FR-4
Board Size
114.3mm x76.2mm x1.6mmt
2 Internal Layers
Pitch
Diameter
Φ0.30mm
4 Layers
1.20mm
Top
Copper Pattern
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Thickness
70μm
74.2mm x74.2mm
Footprints and Traces
70μm
74.2mm x74.2mm
35μm
(Note 5) This thermal via connects with the copper pattern of all layers.
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2.3. Recommended Operating Conditions
Table 2-3. Recommended Operating Conditions
Limit
Typ
Parameter
Voltage Range in PINs:
VSYS, BUCK1_VIN, BUCK2_VIN,
BUCK5_VIN to BUCK8_VIN(Note 1)
Voltage Range in PIN:
VIN_3P3(Note 2)
Voltage Range in PIN:
VIN_1P8_1(Note 3)
Voltage Range in PIN:
Symbol
Unit
V
Min
Max
5.50
VOPR_1
2.70
5.00
VOPR_2
VOPR_3
VOPR_4
VOPR_5
Topr
2.70
1.71
1.71
1.71
-40
3.30
1.80
1.80
1.80
+25
3.60
5.50
1.89
3.60
+105
V
V
V
VIN_1P8_2(Note 3)
Voltage Range in PIN:
DVDD
V
Operating Temperature
°C
(Note 1) It is necessary to supply the same voltage to the VSYS pin and the BUCK1_VIN, BUCK2_VIN, and BUCK5_VIN to BUCK8_VIN pins.
(Note 2) The VIN_3P3 pin is recommended to connect with BUCK6 outputs.
(Note 3) The VIN_1P8_1 pin and the VIN_1P8_2 pin are recommended to connect with BUCK7 outputs.
2.4. Current Consumption
Table 2-4. Current Consumption
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
VSYS Circuit Current 1
Symbol
Unit
Condition
Min
Typ
14
Max
23
READYState(Note 1)
SNVS State(Note 1)
IQ_VSYS1
IQ_VSYS2
IQ_VSYS3
IQ_VSYS4
IQ_VSYS5
IQ_DVDD1
-
-
-
-
-
-
μA
μA
μA
μA
μA
μA
VSYS Circuit Current 2
VSYS Circuit Current 3
VSYS Circuit Current 4
VSYS Circuit Current 5
DVDD Circuit Current 1
30
50
SUSPEND State(Note 1)
IDLE State(Note 1)
115
125
125
-
180
185
185
2
Run State(Note 1)
DVDD static current (OUT32K_EN=0)
DVDD oparation current (OUT32K_EN=1)
(Note 2)
DVDD Circuit Current 2
IQ_DVDD2
-
4
-
μA
(Note 1) When DVDD is connected with LDO1, total circuit current is the value that added VSYS and DVDD circuit current of this table.
(Note 2) This circuit current is affected by parasitic capacitance of the board.
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2.5. Power Reference and Detectors (UVLO)
VSYS
VDD_V1P5
Sequencer
VDD_V1P5
INTLDO1P5
Ref
+
-
VSYS
+
-
VSYS
INTLDO1P5_UVLO
+
-
VSYS_UVLO
VDD_V1P5
Thermal
Sensor
+
Debounce
Alert Temp Detect
-
Figure 2-1. Power Reference and Detectors Block Diagram
Table 2-5. Power Reference and Detectors Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Limit
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
Voltage Detector - VSYS under voltage(VSYS_UVLO)
Release Voltage
Detect Voltage
VUVLORL
VUVLODT
VUVLOHYS
2.65
2.65
-
3.00
2.70
0.3
3.35
2.75
-
V
V
V
VSYS=Sweep up
VSYS =Sweep down
Hysteresis Voltage
Voltage Detector - INTLDO1P5 under voltage(INTLDO1P5_UVLO)
Release Voltage
Detect Voltage
V
-
-
1.39
1.35
-
-
V
V
VSYS=Sweep up
INTUVLORL
V
VSYS =Sweep down
INTUVLODT
PMIC Die Critical Temperature Detector (Thermal Shutdown factor)
Detect Temperature
Power Reference
TCTD
-
150
-
°C
Die Temperature=Sweep up
This output voltage is for internal
use only.
INTLDO1P5 Output Voltage
VLDO15
-
1.5
1.0
-
V
COUTꢀCapacitor
CO_LDO15
0.5
5.0
μF
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3. Power State Control
3.1. Power Control Signals
VSYS
[Internal Logic Circuit]
Enable signal for
PWRON_B
VSYS
PWRON_B
VR
(BUCK1,BUCK2,
BUCK5 to BUCK8)
(LDO1 to LDO6)
VSYS
PMIC_ON_REQ
POR_B
DVDD
PMIC_STBY_REQ
GND
GND
RTC_RESET_B
WDOG_B
Figure 3-1. Power Control Signals of BD71850MWV
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3.1.1. PWRON_B
PWRON_B is an active-low input for triggering the system to power on or off. Normally, PWRON_B is connected to a
power button.
Table 3-1. PWRON_B Electrical Characteristics
(Unless otherwise specified, Ta= +25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Unit
Condition
Condition
Condition
Condition
Min
1.44
-
Typ
Max
-
Input "H" Level
V
-
-
V
V
IH_PWRON
Input "L" Level
V
0.40
IL_PWRON
3.1.2. PMIC_ON_REQ
PMIC_ON_REQ is an active-high input for going to RUN state.
Table 3-2. PMIC_ON_REQ Electrical Characteristics
(Unless otherwise specified, Ta= +25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Unit
Min
1.44
-
Typ
Max
-
Input "H" Level
V
-
-
V
V
IH_ONREQ
Input "L" Level
V
0.40
IL_ONREQ
3.1.3. PMIC_STBY_REQ
PMIC_STBY_REQ is an active-high input for going to SUSPEND state.
Table 3-3. PMIC_STBY_REQ Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Input "H" Level
V
DVDD x0.75
-
-
-
-
V
V
IH_STBYREQ
Input "L" Level
V
DVDD x0.25
IL_STBYREQ
3.1.4. WDOG_B
WDOG_B is an active-low input for triggering Cold Reset or Warm Reset.
Table 3-4. WDOG_B Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Input "H" Level
V
DVDD x0.75
-
-
-
-
V
V
IH_WDOG
Input "L" Level
V
DVDD x0.25
IL_WDOG
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3.1.5. RTC_RESET_B
RTC_RESET_B is an active-low output for RTC.
Table 3-5. RTC_RESET_B Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Unit
Condition
Min
-
Typ
Max
DVDD x0.2
+1
Output "L" Level Voltage
Output Off Leak Current
VOL_RTCRESET
IOLK_RTCRESET
-
-
V
IOL=3 mASink
-1
μA
3.1.6. POR_B
POR_B is an active-low output for the reset of SoC.
Table 3-6. POR_B Electrical Characteristics
(Unless otherwise specified, Ta= +25 °C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Unit
Condition
Min
-
Typ
Max
DVDD x0.2
+1
Output "L" Level Voltage
Output Off Leak Current
VOL_POR
IOLK_POR
-
-
V
IOL=3 mASink
-1
μA
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3.2. Power States
3.2.1. Power State Diagram
BD71850MWV has eight power states or modes: OFF, READY, SNVS, RUN, IDLE, SUSPEND, PWROFF and EMG.
Figure 3-2 shows the state transition diagram along with the conditions to enter and exit each state.
READY_TO_SNVS Condition is described in 3.2.5.2. This condition is configurable by TRANS_COND0 registers.
SNVS_TO_RUN Condition is described in 3.2.5.3. This condition is configurable by TRANS_COND0 registers.
BD71850MWV has Thermal Shutdown, OCP, VR Fault, and VSYS_UVLO=0 as Emergency Shutdown events.
Emergency Shutdown Condition is described in 3.2.5.9. EMG_TO_READY Condition is described in 3.2.5.12.
EMG_STAY Condition is described in 3.2.5.13.
BD71850MWV has WDOG_B, SWRESET, and PWRON_B long detection as Cold Reset events. COLD_RESET
Condition is described in 3.2.4.1. After cold reset events or PMIC_ON_REQ=0, BD71850MWV is configurable that it
returns to READY or SNVS state. POFF_TO_READY Condition is described in 3.2.5.16. POFF_TO_SNVS Condition
is described in 3.2.5.17. Concerning VSYS_UVLO and INTLDO1P5_UVLO, please refer to 2.5.
Any
state
OFF
INTLDO1P5_UVLO = 0
INTLDO1P5_UVLO = 0
VSYS_UVLO = 1
VSYS_UVLO = 0
READY
EMG_TO_READY
Condition
POFF_TO_READY Condition
(Defaultsetting:Not available)
(All Emergencyshutdown
events are not met,
or VR fault recovery attempt.)
EMG_STAY
Condition
READY_TO_SNVS
Condition
(Defaultsetting:VSYS_UVLO =1)
(VSYS_UVLO=0, Thermal
shutdown(T>130˚C),
or VR fault recovery failed.)
POFF_TO_SNVS Condition
(Defaultsetting:PMIC_ON_REQ=0,
SWRESET=1, WDOG_B=0, or
PWRON_B long push)
PWROFF
EMG
SNVS
EmergencyShutdown
Condition
COLD_RESETCondition
or PMIC_ON_REQ = 0
EmergencyShutdown
SNVS_TO_RUN
Condition
Condition
(Defaultsetting:PMIC_ON_REQ=1)
PMIC_STBY_REQ = 1
PMIC_ON_REQ = 1
IDLE
SUSPEND
(reg) IDLE_MODE = 1
PMIC_STBY_REQ = 1
PMIC_ON_REQ = 1
PMIC_STBY_REQ = 0
(reg) IDLE_MODE = 0
PMIC_ON_REQ = 1
RUN
EmergencyShutdown Condition
COLD_RESETCondition:
WDOG_B = 0
SWRESET = 1
PWRON_B long push
COLD_RESETCondition
or PMIC_ON_REQ = 0
EmergencyShutdown Condition:
Thermal Shutdown(T>150˚C)
OCP, VR Fault, VSYS_UVLO=0
Figure 3-2. Power State Transition
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3.2.2. Power State Register
The POW_STATE register shows current power state and power sub state in Table 3-7. The power sub state definition
is illustrated in Figure 3-3.
Table 3-7. POW_STATE – Power State Register
Register Name
POW_STATE
R/W
R
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x2D
POW_ST[3:0]
POW_SUB[1:0]
-
-
Bit
Name
Function
This bit field shows current power state.
Initial
0000
0x0 = OFF
0x2 = SNVS
0x9 = IDLE
0x1 = READY
0x8 = RUN
0xA= SUSPEND
POW_ST[3:0]
D[7:4]
0xB = PWROFF 0xC = EMG
This bit field shows current power sub state.
00 = Stable
01 = Up
POW_SUB[1:0]
00
D[1:0]
10 = Down
11 = Counting Cold Reset duration time (set byPONT[3:0])
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3.2.2. Power State Register – continued
Stable
OFF
(0x0)
Any
state
Down
Down
Up
Down
Stable
READY
(0x1)
Down
Down
Up
Stable
Stable
Stable
PWROFF
(0xB)
EMG
(0xC)
Up
SNVS
(0x2)
Down
Down
Down
Up
Stable
Stable
Down
IDLE
(0x9)
SUSPEND
(0xA)
Down
Up
Down
Stable
Up
RUN
(0x8)
Down
Down
Figure 3-3. Power Sub State Definition
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3.2.3. Power State Definition
(a) OFF state
BD71850MWV is in OFF state when INTLDO1P5_UVLO is detected. If INTLDO1P5_UVLO is 0, the data in all
registers are reset to their default values.
To exit this state, VSYS voltage must exceed 3.0 V (VSYS_UVLO = 1)
(b) READY state
In this state, VSYS voltage is over 3.0V. When power state transitions from OFF state to READY state, OTP data will
only be loaded to registers with "Yes" in "OTP" column of Register Map (Table 1-4). When power state transitions
from PWROFF or EMG state to READY state, OTP data will only be loaded to registers with reset condition during
READY state and "Yes" condition in "OTP" column. This OTP loading can be skipped depending on the value of
RELOAD_REG in PWRCTRL0 register.
(c) SNVS state
If READY_TO_SNVS condition is satisfied, the power state changes to SNVS state. In this state, LDO1(NVCC_SNVS)
and LDO2(VDD_SNVS) are turned on as shown in Table 3-8.
(d) RUN state
If SNVS_TO_RUN condition is satisfied, the power state changes to RUN state. In this state, the VR’s shown in Table
3-8 are turned ON.
The voltage of BUCK1(VDD_SOC, VDDA_0V8, PHY_0V8) depends on BUCK1_VOLT_RUN register.
The voltage of BUCK2(VDD_ARM) depends on BUCK2_VOLT_RUN register.
(e) IDLE state
If IDLE_MODE in PWRCTRL1 register is set to 1, the power state changes to IDLE state. The voltage of
BUCK1(VDD_SOC, VDDA_0V8, PHY_0V8) depends on BUCK1_VOLT_IDLE register. The voltage of
BUCK2(VDD_ARM) depends on BUCK2_VOLT_IDLE register.
(f) SUSPEND state
If PMIC_STBY_REQ is set to 1, the power state changes to SUSPEND state. The voltage of BUCK1(VDD_SOC,
VDDA_0V8, PHY_0V8) depends on BUCK1_VOLT_SUSP register.
(g) EMG state
If Emergency Shutdown Condition is satisfied, the power state changes to EMG state. In this state, all VR’s are OFF.
(h) PWROFF state
If COLD_RESET Condition is satisfied or PMIC_ON_REQ is reset to 0, the power state changes to PWROFF state. In
this state, all VR’s except LDO1(NVCC_SNVS) and LDO2(VDD_SNVS) are OFF. The next state of PWROFF is either
READY or SNVS. TRANS_COND1[3:0] values decide which power state to go.
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3.2.3. Power State Definition – continued
Table 3-8. Voltage Rails ON/OFF for Respective Power State
Power State
SNVS(Note) SUSPEND(Note) IDLE(Note)
VR No.
Function
Rail Name
RUN(Note)
ON
OFF
OFF
OFF
READY
OFF
PWROFF
ON/OFF
ON/OFF
EMG
OFF
OFF
VR1
VR2
NVCC_SNVS
VDD_SNVS
LDO1
LDO2
ON
ON
ON
ON
ON
ON
OFF
ON
VDD_SOC,
VDDA_0V8,
PHY_0V8,
VR3
BUCK1
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VDD_DRAM,
VDD_GPU
VR4
VR5
VR6
VDD_ARM
BUCK2
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VR7
-
BUCK5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDA_1V8,
VDDA_DRAM
VR8
LDO3
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
VR9
VR10
VR11
VR12
VR13
VR14
VR15
VR16
-
LDO4
BUCK6
BUCK7
BUCK8
LDO5
LDO6
-
OFF
OFF
OFF
OFF
OFF
OFF
-
OFF
OFF
OFF
OFF
OFF
OFF
-
OFF
OFF
OFF
OFF
OFF
OFF
-
OFF
ON
ON
ON
OFF
ON
-
OFF
ON
ON
ON
OFF
ON
-
OFF
ON
ON
ON
OFF
ON
-
OFF
OFF
OFF
OFF
OFF
OFF
-
OFF
OFF
OFF
OFF
OFF
OFF
-
NVCC_3V3
NVCC_1V8
NVCC_DRAM
-
VDD_PHY_1V2
-
NVCC_SD2
MUXSW
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
(Note) ON/OFF setting of each VR at SNVS/SUSPEND/IDLE/RUN state can be configured by OTP.
3.2.4. Power State Control Events
3.2.4.1.
Reset Event
BD71850MWV has Cold and Warm resets.
Cold reset initiates POR_B asserted to L and power rails are turned off. Then, the power state changes to
either READY state or SNVS state. Next, the power state returns to RUN state automatically.
Warm reset initiates POR_B asserted to L for 1 ms. It does not affect the on/off status of all power rails.
Warm reset does not initiate the power state transition.
BD71850MWV has three reset sources as follows.
• PWRON_B terminal is set H to L. (PWRON_B Long Push reset)
• WDOG_B terminal is set H to L. (WDOG_B reset)
• SWRESET in SWRESET register is set 0 to 1 (Software reset)
The cold or warm reset selection setting is shown in Table 3-9.
The details of the two registers related to the setting are shown in Table 3-10 and Table 3-11.
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3.2.4.1. Reset Event – continued
Table 3-9. Setting of Cold or Warm Reset Selection
Reset Source
Register Name
Register Bit Name
Value
10 (default)
11
Cold/Warm Reset or No Reset
Cold reset
PWRON_B
Long Push
PWRCTRL0
DEBUG_STATE[1:0]
Warm reset
00 or 01
10 (default)
11
No reset action
Cold reset
WDOG_B
Software
PWRCTRL0
SWRESET
WDOGB_SEL[1:0]
Warm reset
00 or 01
10 (default)
11
No reset action
Cold reset
SWRESET_SEL[1:0]
Warm reset
00 or 01
No reset action
Table 3-10. SWRESET - Software Reset Register
Register Name
SWRESET
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x04
Address
0x01
SWRESET_SEL[1:0]
-
-
-
-
SWRESET
Bit
Name
Function
Initial
10
Select Cold reset, Warm reset or No reset action when SWRESET bit ( D[0]) is set
to 1.
00 = No reset action
01 = No reset action
10 = Cold reset
11 = Warm reset
D[2:1]
SWRESET_SEL[1:0]
0 – No action
1 – Initiates Cold Reset or Warm Reset in accordance with SWRESET_SEL bit.
Writing 1 to SWRESET bit, then SWRESET bit is automatically cleared to 0 when
Cold Reset or Warm Reset operation is completed.
Writing 1 to SWRESET bit can be done when Power State = RUN, IDLE and
SUSPEND.
SWRESET
0
D[0]
Table 3-11. PWRCTRL0 - Power Control 0 Register
Register Name
PWRCTRL0
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0xA2
Address
0x03
RELOAD_
REG
DEBUG_STATE[1:0]
Name
WDOGB_SEL[1:0]
-
-
-
Bit
Function
Initial
10
Select Cold reset, Warm reset or No reset action when PWRON_B long push is
detected.
00 = No reset action
01 = No reset action
10 = Cold reset
11 = Warm reset
D[7:6]
DEBUG_STATE[1:0]
Select OTP configurable registers initialization when the power state goes through
READYstate.
0 = No initialization
D[5]
RELOAD_REG
1
1= Reload OTP registers and set to initial value
Select Cold reset, Warm reset or No reset action when WDOG_B is asserted to 0.
00 = No reset action
01 = No reset action
10 = Cold reset
WDOGB_SEL[1:0]
10
D[1:0]
11 = Warm reset
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3.2.4.2.
Emergency Shutdown Event
There are four Emergency Shutdown Events as follows:
• Thermal Shutdown (Thermal Protection)
If the die temperature surpasses 150ºC, the thermal protection circuit will shut down all VR’s to avoid
damage. This detection is not valid at OFF, READY and SNVS state.
• OCP
If the OCP is triggered in any VR’s, all VR’s are turned off.
• VR Fault
If the voltage of VR is not within the regular range, all VR’s are turned off.
• VSYS_UVLO = 0
If the VSYS_UVLO = 0, Emergency Shutdown sequence is initiated.
3.2.5. Power State Transitions
3.2.5.1.
OFF to READY
Table 3-12 shows the conditions for exiting OFF state. “VSYS_UVLO = 1” is necessary.
Table 3-12. Conditions from OFF to READY state
Conditions
(All must be satisfied per Event Trigger)
Event Trigger
Next State
Notes
1) VSYS Voltage Up
from 0 Vor 2.7 V
VSYS_UVLO = 1
(VSYS > 3.0 V)
VSYS Insertion or
VSYS recoveryfrom 2.7 V
READY
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3.2.5.2.
READY to SNVS
There are six event triggers for shifting from READY to SNVS as shown in Table 3-13. The event trigger of
VSYS_UVLO, PMIC_ON_REQ, PWRON_B Short Push, and PWRON_B Long Push are configurable to be
valid or invalid by TRANS_COND0 registers. VSYS_UVLO condition is valid with default setting.
Table 3-13. Conditions from READY to SNVS
Conditions
(All must be satisfied per Event Trigger)
Event Trigger
1) VSYS_UVLO
Next State
SNVS
Notes
No other event is necessary.
Valid with default setting
VSYS_UVLO = 1
VSYS_UVLO = 1 and
PMIC_ON_REQ = 1
2) PMIC_ON_REQ
SNVS
Invalid with default setting
Invalid with default setting
Invalid with default setting
3) PWRON_B Short
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Short Push Detection
SNVS
4) PWRON_B Long
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Long Push Detection
SNVS
5) Cold Reset
Sequence
VSYS_UVLO = 1 and
Cold_Reset_flag = 1
On the wayback to RUN state
in Cold Reset sequence
SNVS
6) VR Fault Recovery
Attempt
VSYS_UVLO = 1 and
VR Fault Recovery
SNVS
1) VSYS_UVLO
The power state shifts to SNVS if VSYS_UVLO = 1 as shown in Figure 3-4. No other conditions are
necessary.
3.0 V
VSYS
0 V
VSYS_UVLO
Power State
OFF
READY
SNVS
Figure 3-4. VSYS Condition for moving to SNVS
2) PMIC_ON_REQ
The power state shifts to SNVS if PMIC_ON_REQ = 1 as shown in Figure 3-5.
3.0 V
VSYS
0V
VSYS_UVLO
PMIC_ON_REQ
Power State
OFF
READY
SNVS
Figure 3-5. PMIC_ON_REQ Condition for moving to SNVS
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3.2.5.2.
READY to SNVS – continued
3) PWRON_B Short Push
The power state shifts to SNVS if PWRON_B Short Push is detected as shown in Figure 3-6.
3.0 V
VSYS
0 V
VSYS_UVLO
PWRON_B
Short Push is detected.
Power State
OFF
READY
SNVS
Figure 3-6. PWRON_B Short Push Condition for moving to SNVS
4) PWRON_B Long Push
The power state shifts to SNVS if PWRON_B Long Push is detected as shown in Figure 3-7.
3.0 V
VSYS
0 V
VSYS_UVLO
PWRON_B
Long Push is detected.
Power State
OFF
READY
SNVS
Figure 3-7. PWRON_B Long Push Condition for moving to SNVS
5) Cold Reset
The power state shifts to SNVS if Cold_Reset_flag = 1 as shown in Figure 3-8.
High
VSYS_UVLO
Cold Reset
Event occurs
Cold_Reset_flag
(PMIC Internal Signal)
Power State
RUN
PWROFF
READY
SNVS
Figure 3-8. Cold Reset Condition for moving to SNVS
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3.2.5.2.
READY to SNVS – continued
6) VR Fault Recovery Attempt
Please see 3.2.5.10.
It is possible to use each four event triggers such as:
VSYS_UVLO,
PMIC_ON_REQ,
PWRON_B Short Push and
PWRON_B Long Push
These triggers are configurable to use them respectively by D[3:0] in TRANS_COND0 register as shown
in Table 3-14.
Table 3-14. TRANS_COND0 - Transition Condition Select 0 Register
Register Name
TRANS_COND0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x48
Address
0x1F
C1_
C1_
C1_
SHORT_
PUSH_EN
C1_
LONG_
PUSH_EN
C0_
C0_
C0_
SHORT_
PUSH_EN
C0_
LONG_
PUSH_EN
R/W VSYS_3P0_ PMIC_ON_
VSYS_3P0_ PMIC_ON_
ONLY_EN REQ_EN
ONLY_EN
REQ_EN
Bit
Name
Function
Initial
0
Select onlyVSYS_UVLO = 1 as SNVS ==> RUN transition condition or not
0 = VSYS_UVLO = 1 is not used as the condition
C1_VSYS_3P0_ONLY_EN
C1_PMIC_ON_REQ_EN
C1_SHORT_PUSH_EN
C1_LONG_PUSH_EN
C0_VSYS_3P0_ONLY_EN
C0_PMIC_ON_REQ_EN
C0_SHORT_PUSH_EN
C0_LONG_PUSH_EN
D[7]
1 = VSYS_UVLO = 1 is used as the condition
Select PMIC_ON_REQ as SNVS ==> RUN transition condition or not
0 = PMIC_ON_REQ is not used as the condition
1 = PMIC_ON_REQ is used as the condition
1
0
0
1
0
0
0
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Select PWRON_B Short Push as SNVS ==> RUN transition condition or not
0 = PWRON_B Short Push is not used as the condition
1 = PWRON_B Short Push is used as the condition
Select PWRON_B Long Push as SNVS ==> RUN transition condition or not
0 = PWRON_B Long Push is not used as the condition
1 = PWRON_B Long Push is used as the condition
Select onlyVSYS_UVLO = 1 as READY==> SNVS transition condition or not
0 = VSYS_UVLO = 1 is not used as the condition
1 = VSYS_UVLO = 1 is used as the condition
Select PMIC_ON_REQ as READY==> SNVS transition condition or not
0 = PMIC_ON_REQ is not used as the condition
1 = PMIC_ON_REQ is used as the condition
Select PWRON_B Short Push as READY==> SNVS transition condition or not
0 = PWRON_B Short Push is not used as the condition
1 = PWRON_B Short Push is used as the condition
Select PWRON_B Long Push as READY==> SNVS transition condition or not
0 = PWRON_B Long Push is not used as the condition
1 = PWRON_B Long Push is used as the condition
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3.2.5.3.
SNVS to RUN
There are six event triggers for shifting from SNVS to RUN as shown in Table 3-15. The event trigger of
VSYS_UVLO=1 PMIC_ON_REQ, PWRON_B Short Push, and PWRON_B Long Push are configurable to
be valid or invalid by TRANS_COND0 registers. PMIC_ON_REQ condition is valid with default setting.
Table 3-15. Conditions from SNVS to RUN
Conditions(Note)
(All must be satisfied per Event Trigger)
Event Trigger
1) VSYS_UVLO
Next State
RUN
Notes
No other event is necessary.
Invalid with default setting
VSYS_UVLO = 1
VSYS_UVLO = 1 and
PMIC_ON_REQ = 1
2) PMIC_ON_REQ
RUN
Valid with default setting
Invalid with default setting
Invalid with default setting
3) PWRON_B Short
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Short Push Detection
RUN
4) PWRON_B Long
Push
VSYS_UVLO = 1 and
PWRON_B = 0 ==> Long Push Detection
RUN
5) Cold Reset
Sequence
VSYS_UVLO = 1 and
Cold_Reset_flag = 1
On the wayback to RUN state
in Cold Reset sequence
RUN
6) VR Fault Recovery
Attempt
VSYS_UVLO = 1 and
VR Fault Recovery
RUN
(Note) Die Temperature must be less than 150 ºC.
1) VSYS_UVLO
The power state shifts to RUN if VSYS_UVLO = 1 as shown in Figure 3-9. No other condition is required.
VSYS_UVLO
Power State
OFF
READY
SNVS
RUN
Figure 3-9. VSYS Condition for moving to RUN
2) PMIC_ON_REQ
The power state shifts to RUN if PMIC_ON_REQ = 1 as shown in Figure 3-10.
VSYS_UVLO
PMIC_ON_REQ
Power State
OFF
READY
SNVS
RUN
Figure 3-10. PMIC_ON_REQ Condition for moving to RUN
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3.2.5.3.
SNVS to RUN – continued
3) PWRON_B Short Push
VSYS_UVLO
PWRON_B
Short Push is detected.
Power State
OFF
READY
SNVS
RUN
Figure 3-11. PWRON_B Short Push Condition for moving to RUN
4) PWRON_B Long Push
The power state shifts to RUN if PWRON_B Long Push is detected as shown in Figure 3-12.
VSYS_UVLO
PWRON_B
Long Push is detected.
Power State
OFF
READY
SNVS
RUN
Figure 3-12. PWRON_B Long Push Condition for moving to RUN
5) Cold Reset
The power state shifts to RUN if Cold_Reset_flag = 1 as shown in Figure 3-13.
High
VSYS_UVLO
Cold Reset
Event occurs
Cold_Reset_flag
(PMIC Internal Signal)
Power State
RUN
PWROFF
READY
SNVS
RUN
Figure 3-13. Cold Reset Condition for moving to RUN
6) VR Fault Recovery Attempt
Please see 3.2.5.10.
It is possible to use each four event triggers such as:
VSYS_UVLO,
PMIC_ON_REQ,
PWRON_B Short Push and
PWRON_B Long Push
These triggers are configurable to use them respectively by D[7:4] in TRANS_COND0 register as shown in
Table 3-14.
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3.2.5.4.
RUN to IDLE
Table 3-16 shows the conditions for shifting from RUN to IDLE. The details of PWRCTRL1 register were
described in Table 3-17.
Table 3-16. Conditions from RUN to IDLE
Conditions(Note)
Event Trigger
Next State
IDLE
Notes
(All must be satisfied)
PMIC_STBY_REQ = 0
PMIC_ON_REQ = 1
Set IDLE_MODE
(PWRCTRL1
register) = 1
Register Write Operation
Set (reg) IDLE_MODE = 1
(Note) Die Temperature must be less than 150 ºC. VSYS_UVLO = 1.
Table 3-17. PWRCTRL1 - Power Control 1 Register
Register Name
PWRCTRL1
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
-
D0
Initial
0x00
Address
0x04
IDLE_
MODE
-
-
-
-
-
Bit
Name
Function
Control power state transition between RUN and IDLE
0 = Exit IDLE and back to RUN, or indicates power state = except IDLE
1 = Enter IDLE from RUN, or indicates power state = IDLE
Initial
0
IDLE_MODE
D[0]
Note : this bit automaticallyreturns to 0 when power state enters PWROFF,
EMG and SUSPEND.
3.2.5.5.
IDLE to RUN
Table 3-18 shows the conditions for shifting from IDLE to RUN.
Table 3-18. Conditions from IDLE to RUN
Conditions(Note)
(All must be satisfied)
PMIC_STBY_REQ = 0
Event Trigger
Next State
Notes
Set IDLE_MODE
(PWRCTRL1
register) = 0
RUN
PMIC_ON_REQ = 1
Set (reg) IDLE_MODE = 0
Register Write Operation
(Note) Die Temperature must be less than 150 ºC. VSYS_UVLO = 1.
3.2.5.6.
RUN to SUSPEND
Table 3-19 shows the conditions for shifting from RUN to SUSPEND.
Table 3-19. Conditions from RUN to SUSPEND
Conditions(Note)
(All must be satisfied)
Event Trigger
Next State
Notes
PMIC_STBY_REQ = 1
SUSPEND
PMIC_STBY_REQ
PMIC_ON_REQ = 1
(Note) Die Temperature must be less than 150 ºC. VSYS_UVLO = 1.
3.2.5.7.
SUSPEND to RUN
Table 3-20 shows the conditions for shifting from SUSPEND to RUN.
Table 3-20. Conditions from SUSPEND to RUN
Conditions(Note)
(All must be satisfied)
Event Trigger
Next State
Notes
PMIC_STBY_REQ = 0
RUN
PMIC_STBY_REQ
PMIC_ON_REQ = 1
(Note) Die Temperature must be less than 150 ºC. VSYS_UVLO = 1.
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BD71850MWV
3.2.5.8.
IDLE to SUSPEND
Table 3-21 shows the conditions for shifting from IDLE to SUSPEND. IDLE_MODE in PWRCTRL1 register
automatically returns to 0.
Table 3-21. Conditions from IDLE to SUSPEND
Conditions(Note)
(All must be satisfied)
PMIC_STBY_REQ = 1
PMIC_ON_REQ = 1
Event Trigger
Next State
SUSPEND
Notes
PMIC_STBY_REQ
(Note) Die Temperature must be less than 150 ºC. VSYS_UVLO = 1.
3.2.5.9.
Emergency Shutdown
There are four Emergency Shutdown events which are:
Thermal Shutdown (Thermal Protection)
OCP
VR Fault
VSYS_UVLO = 0 as shown in Table 3-22.
Table 3-22. Conditions from SNVS, RUN, IDLE, SUSPEND, PWROFF to EMG
Conditions
(All must be satisfied per Event Trigger)
Event Trigger
Next State
Notes
Thermal Protection
This protection is invalid at OFF,
READY, and SNVS state
1) Thermal Shutdown
Die Temperature > 150 ºC
EMG
2) OCP
AnyVR's OCP
AnyVR's out of the target voltage
VSYS_UVLO = 0
EMG
EMG
EMG
3) VR Fault
4) VSYS_UVLO = 0
The detail of VR Fault is described in 3.2.5.10.
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3.2.5.10. VR Fault
BD71850MWV has VR fault detection function which monitors all relevant VR’s of the system. The system
is shut down when a monitored voltage rail goes out of the target voltage. Once the system has shut down,
the system tries to boot up several times which is determined by RCVLMT[3:0] in RCVCFG register.
Table 3-23 shows the VR fault threshold and monitoring conditions. Even if one of output rails which are
described “Y” in Table 3-23 are not used, output inductors and capacitors are needed. If they are not
connected, PMIC would be shut down because of VR fault detection.
Table 3-23. VR FAULT threshold and monitoring condition
SNVS
SUSPEND
Voltage
IDLE
RUN
Voltage
Target
Range
Voltage
Target
Range
Voltage
Target
Range
VR No.
Function
Rail Name
Monitor
Y/N
Monitor
Y/N
Monitor
Y/N
Monitor
Y/N
Target
Range
80% <
LDO1
80% <
LDO1
80% <
LDO1
80% <
LDO1
VR1
VR2
NVCC_SNVS
VDD_SNVS
LDO1
LDO2
BUCK1
BUCK2
-
Y
Y
N
N
-
Y
Y
Y
N
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
80% <
LDO2
80% <
LDO2
80% <
LDO2
80% <
LDO2
VDD_SOC,
VDDA_0V8,
PHY_0V8
80% <
BUCK1
< 130%
80% <
BUCK1
< 130%
80% <
BUCK1
< 130%
VR3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80% <
BUCK2
< 130%
80% <
BUCK2
< 130%
VR4
VDD_ARM
-
-
-
-
VR5
-
-
-
-
-
-
-
-
-
VR6
-
-
-
-
-
VR7
BUCK5
LDO3
LDO4
BUCK6
BUCK7
BUCK8
LDO5
LDO6
-
N
N
N
N
N
N
N
N
-
N
Y
N
Y
Y
Y
N
Y
-
N
Y
N
Y
Y
Y
N
Y
-
N
Y
N
Y
Y
Y
N
Y
-
VDDA_1V8,
VDDA_DRAM
80% <
LDO3
80% <
LDO3
80% <
LDO3
VR8
VR9
-
-
-
-
80% <
BUCK6
< 130%
80% <
BUCK6
< 130%
80% <
BUCK6
< 130%
VR10
VR11
VR12
VR13
VR14
VR15
VR16
NVCC_3V3
NVCC_1V8
NVCC_DRAM
-
80% <
BUCK7
< 130%
80% <
BUCK7
< 130%
80% <
BUCK7
< 130%
80% <
BUCK8
< 130%
80% <
BUCK8
< 130%
80% <
BUCK8
< 130%
-
-
-
80% <
LDO6
80% <
LDO6
80% <
LDO6
VDD_PHY_1V2
-
-
-
-
-
-
-
Not
available
Not
available
Not
available
Not
available
NVCC_SD
MUXSW
Y: VR output is monitored to trigger VR Fault Emergency Shutdown sequence.
N: Not monitored at default (If the VR is turned ON by changing the register setting, its output is monitored for the VR Fault event trigger)
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3.2.5.10. VR Fault – continued
BD71850MWV monitors each rail. If a monitored VR goes out of the target voltage in a certain time, the
system will shut down. When the system cannot shift to RUN state after Power ON sequence several times
which is defined by RCVLMT[3:0] in RCVCFG register, the system stays at EMG state until
INTLDO1P5_UVLO = 0.
If a VR is turned OFF by VR control registers (BUCK1, BUCK2, BUCK5 to BUCK8 and LDO1 to LDO6), VR
fault of that VR is masked.
BD71850MWV has VR individual masking registers as shown in Table 3-25, Table 3-26 and Table 3-27.
This masking function is used for mainly debugging in development phase.
Table 3-24. VRFAULTEN - VR FAULT ON/OFF Register: Debugging Purpose
Register Name
VRFAULTEN
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x01
Address
0x21
R/W
-
-
-
-
-
-
-
VRFLTEN
Bit
Name
Function
Initial
1
VR Fault enable bit
0 = VR Fault is disabled.
1 = VR Fault is enabled.
VRFLTEN
D[0]
This bit is used for debugging purpose.Please do not set 0x00 in normal
operation.
Table 3-25. MVRFLTMASK0 - VR FAULT Mask 0 Register
Register Name
MVRFLTMASK0
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x22
MBUCK8_
VOUTOKH
MBUCK8_
VOUTOKL
MBUCK7_
VOUTOKH
MBUCK7_
VOUTOKL
MBUCK6_
VOUTOKH
MBUCK6_
VOUTOKL
MBUCK5_
VOUTOKH
MBUCK5_
VOUTOKL
Bit
Name
Function
Initial
0
Masking bit of BUCK8 130% threshold for target voltage
0 = monitoring 130% threshold
MBUCK8_VOUTOKH
MBUCK8_VOUTOKL
MBUCK7_VOUTOKH
MBUCK7_VOUTOKL
MBUCK6_VOUTOKH
MBUCK6_VOUTOKL
MBUCK5_VOUTOKH
MBUCK5_VOUTOKL
D[7]
1 = masked 130% threshold
Masking bit of BUCK8 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
0
0
0
0
0
0
0
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Masking bit of BUCK7 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
Masking bit of BUCK7 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
Masking bit of BUCK6 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
Masking bit of BUCK6 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
Masking bit of BUCK5 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
Masking bit of BUCK5 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
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3.2.5.10. VR Fault – continued
Table 3-26. MVRFLTMASK1 - VR FAULT Mask 1 Register
Register Name
MVRFLTMASK1
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x23
MBUCK2_
VOUTOKH
MBUCK2_
VOUTOKL
MBUCK1_
VOUTOKH
MBUCK1_
VOUTOKL
-
-
-
Bit
Name
Function
Initial
0
Masking bit of BUCK2 130% threshold for target voltage
0 = monitoring 130% threshold
MBUCK2_VOUTOKH
MBUCK2_VOUTOKL
MBUCK1_VOUTOKH
MBUCK1_VOUTOKL
D[3]
1 = masked 130% threshold
Masking bit of BUCK2 80% threshold for target voltage
0 = monitoring 80% threshold
0
0
0
D[2]
D[1]
D[0]
1 = masked 80% threshold
Masking bit of BUCK1 130% threshold for target voltage
0 = monitoring 130% threshold
1 = masked 130% threshold
Masking bit of BUCK1 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
Table 3-27. MVRFLTMASK2 - VR FAULT Mask 2 Register
Register Name
MVRFLTMASK2
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x24
MLDO6_
MLDO5_
MLDO4_
MLDO3_
MLDO2_
MLDO1_
VOUTOKL
-
VOUTOKL
VOUTOKL
VOUTOKL
VOUTOKL
VOUTOKL
Bit
Name
Function
Initial
0
Masking bit of LDO6 80% threshold for target voltage
0 = monitoring 80% threshold
MLDO6_VOUTOKL
MLDO5_VOUTOKL
MLDO4_VOUTOKL
MLDO3_VOUTOKL
MLDO2_VOUTOKL
MLDO1_VOUTOKL
D[5]
1 = masked 80% threshold
Masking bit of LDO5 80% threshold for target voltage
0 = monitoring 80% threshold
0
0
0
0
0
D[4]
D[3]
D[2]
D[1]
D[0]
1 = masked 80% threshold
Masking bit of LDO4 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
Masking bit of LDO3 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
Masking bit of LDO2 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
Masking bit of LDO1 80% threshold for target voltage
0 = monitoring 80% threshold
1 = masked 80% threshold
Following a VR Fault and an Emergency Shutdown sequence, BD71850MWV stays in READY state for a
programmed time which is specified by RCVDT[3:0] of RCVCFG register. Power ON sequence is then
initiated once RCVDT[3:0] time has elapsed.
To prevent an infinite loop of VR Fault induced power cycles, BD71850MWV limits the number of attempts
to recover the system by RCVLMT[3:0] of RCVCFG register when these failures occur. Once
BD71850MWV has attempted to recover from a VR Fault for a number of times which is specified by
RCVLMT[3:0], the next VR Fault results in BD71850MWV staying in EMG state until INTLDO1P5_UVLO =
0.
The ability to reset RCVNUM register which tracks the number of VR Fault recovery attempts via I2C is
supported. This will allow the SoC to reset this count value when needed.
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3.2.5.10. VR Fault – continued
Table 3-28. RCVCFG - Recovery Configuration Register
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x4C
Address
0x25
RCVLMT[3:0]
RCVDT[3:0]
RCVCFG
R/W
Bit
Name
Function
Initial
The limit number of attempts to recover the system after a VR Fault occurred.
0000 = No recovery. BD71850MWV stays in EMG state until VSYS is triggered
again.
0001 = 1 time
RCVLMT[3:0]
0010 = 2 times
0011 = 3 times
0100 = 4 times
:
0100
D[7:4]
1110 = 14 times
1111 = No limit of attempts to recover
The duration time during which BD71850MWV stays in READY state after a VR
Fault event.
BD71850MWV remains in READY state for the duration programmed here then
BD71850MWV performs a Power ON sequence, if RCVLMT[3:0] is not 0x0 or 0xF
and RCVLMT[3:0] is not equal to RCVNUM[3:0] of RCVNUMregister.
0000 = 5 ms
0001 = 10 ms
0010 = 15 ms
0011 = 20 ms
0100 = 25 ms
0101 = 30 ms
0110 = 35 ms
0111 = 40 ms
1000 = 45 ms
1001 = 50 ms
1010 = 75 ms
1011 = 100 ms
1100 = 250 ms
1101 = 500 ms
1110 = 750 ms
1111 = 1500 ms
D[3:0]
RCVDT[3:0]
1100
Table 3-29. RCVNUM - Recovery Number Register
Register Name
RCVNUM
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x26
RCVNUM[3:0]
-
-
-
Bit
Name
Function
The number of attempts to recover the system after a VR Fault occurred.
Once BD71850MWV has attempted to recover from a power failure times which is
indicated in RCVLMT[3:0] in RCVCFG register, the next failure shall result in
BD71850MWVstaying in EMG state until VSYS is triggered again.
When SoC writes RCVNUM register via I2C, then RCVNUM[3:0] is cleared to 0000.
As a result, the tracking number of power failure recoveryattempts is reset.
Note : When RCVLMT[3:0] = 0xF (no limit of attempts to recover) and the number of
attempt is over 0xF, RCVNUM[3:0] value is fixed to 0xF.
Initial
0000
D[3:0]
RCVNUM[3:0]
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3.2.5.10. VR Fault – continued
Due to {RCVLMT == RCVNUM},
Power ON does not occur and
▽
VR Fault occurred
and shutdown.
▼
VR Fault occurred
and shutdown.
▼
VR Fault occurred
and shutdown.
▼
Power ON
▼
Power ON
▼
PMIC keeps EMG state
VRs
RCVLMT[3:0]
RCVNUM[3:0]
2
0
1
2
▲
RCVDT[3:0] Increment by PMIC
▲
RCVDT[3:0] Increment by PMIC
RCVDT[3:0]
RVR_FAULT
in RESETSRC
Register
0
1
0
1
0
1
▲
Set by PMIC
▲
▲
▲
▲
Cleared by SoCSet by PMIC
Cleared by SoCSet by PMIC
RUN
READY
SNVS, RUN
READY
SNVS, RUN
EMG
Power State
EMG
EMG
Figure 3-14. Example of VR Fault and Recovery Sequence (RCVLMT[3:0] = 2)
3.2.5.11. EMG to OFF
Table 3-30 shows the conditions for shifting from EMG to OFF. If INTLDO1P5_UVLO = 0 after entry to EMG,
the power state immediately goes to OFF as shown in Figure 3-15.
Table 3-30. Conditions from EMG to OFF
Conditions
(All must be satisfied per Event Trigger)
Event Trigger
Next State
Notes
VSYS Voltage Low
INTLDO1P5_UVLO = 0
OFF
2.7V
VSYS
0V
1.35V
INTLDO1P5
0V
VSYS_UVLO
INTLDO1P5_UVLO
Power State
RUN
EMG
OFF
0V
0V
All VRs
Emergency
Shutdown
0V
Figure 3-15. EMG to OFF Power State Transition
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3.2.5.12. EMG to READY
Table 3-31 shows the conditions for shifting from EMG to READY. Basically, the power state can exit EMG
when no emergency events are found as shown in Figure 3-14, Figure 3-16, and Figure 3-17.
Table 3-31. Conditions from EMG to READY
Conditions
(All must be satisfied per Event Trigger)
Event Trigger
Next State
READY
Notes
VSYS_UVLO = 1
Die Temperature < 150 ºC
No OCP
1) No Emergency
Event
No VR Fault
VSYS_UVLO = 1
2) VR Fault Recovery
Attempt
Die Temperature < 150 ºC
During VR Fault RecoveryAttempt
READY
VSYS_UVLO
Power State
All VRs
IDLE
EMG
0 V
READY
0 V
Emergency
Shutdown
0 V
Figure 3-16. EMG to READY Power State Transition (VSYS_UVLO)
more than 3.0 V
VSYS
150 ºC
Die Temperature
Power State
All VRs
IDLE
EMG
READY
0 V
0 V
Emergency
Shutdown
0 V
Figure 3-17. EMG to READY Power State Transition (Die Temperature)
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BD71850MWV
3.2.5.13. EMG_STAY Condition
Table 3-32 shows the conditions for staying at EMG. Basically, the power state stays at EMG when
emergency events are found as shown in Figure 3-14, Figure 3-16, and Figure 3-17.
Note: In case of 3) VR Fault Recovery Failure in Table 3-32; in order to exit EMG, VSYS voltage must be
less than 2.7V and then the power state goes to OFF.
Table 3-32. Conditions for Stay at EMG
Conditions
(All must be satisfied per Event Trigger)
Event Trigger
Next State
Notes
VSYS_UVLO = 0
1) VSYS < 2.7 V
EMG
INTLDO1P5_UVLO = 1
Die Temperature > 150 ºC
INTLDO1P5_UVLO = 1
2) Thermal Shutdown
EMG
EMG
Thermal Protection
VR Fault RecoveryAttempt Failed
INTLDO1P5_UVLO = 1
3) VR Fault Recovery
Failure
3.2.5.14. Warm Reset
Warm Reset is executed when the power state = RUN, IDLE and SUSPEND.
Warm Reset set POR_B = L for 1 ms as shown in Figure 3-18.
Please refer to the Table 3-9 for necessary register setting.
Power State
WDOG_B
RUN, IDLE or SUSPEND
POR_B
1 ms
Figure 3-18. Warm Reset by WDOG_B
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BD71850MWV
3.2.5.15. PWROFF
Table 3-33 shows the conditions for shifting from RUN, IDLE, SUSPEND to PWROFF.
When the power state is PWROFF, BD71850MWV runs Power OFF sequence and VR’s are turned OFF in
a defined sequential order.
In the end of the sequence, the on-off state of C32K_OUT, RTC_RESET_B, LDO2 and LDO1 depends on
the setting of TRANS_COND1 register as shown in Table 3-34. The summary is shown in Table 3-35.
Table 3-33. Conditions from RUN, IDLE, SUSPEND to PWROFF
Conditions
(All must be satisfied per Event Trigger)
Event Trigger
Next State
Notes
1) PWRON_B Long
Push
PWRON_B = 0 ==> Long Push Detection
PWROFF
COLD_RESET event
2) WDOG_B
WDOG_B = 0
Write 1 to SWRESET in SWRESET register
PMIC_ON_REQ = 0
PWROFF
PWROFF
PWROFF
COLD_RESET event
COLD_RESET event
3) Software Reset
4) PMIC_ON_REQ
(Note) Die Temperature must be less than 150 ºC. VSYS_UVLO = 1.
Table 3-34. TRANS_COND1 - Transition Condition Select 1 Register
Register Name
TRANS_COND1
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0xC0
Address
0x20
PWRON_
WDOG_
SWRST_
ON_REQ_
PONT[3:0]
POFF_TO_ POFF_TO_ POFF_TO_ POFF_TO_
READY READY READY READY
Bit
Name
Function
Initial
COLD RESET duration during which the BD71850MWV stays in READY or SNVS in
a COLD RESET event.
The BD71850MWV remains in READY or SNVS for the duration programmed here
then BD71850MWVperforms a Power ON sequence.
0000 = 5 ms
0001 = 10 ms
0010 = 15 ms
0011 = 20 ms
0100 = 25 ms
0101 = 30 ms
PONT[3:0]
0110 = 35 ms
1100
D[7:4]
0111 = 40 ms
1000 = 45 ms
1001 = 50 ms
1010 = 75 ms
1011 = 100 ms
1100 = 250 ms
1101 = 500 ms
1110 = 750 ms
1111 = 1500 ms
Set which power state to go after PWROFF triggered byPWRON_B Long Push
0 = to SNVS
1 = to READY
PWRON_
POFF_TO_READY
0
D[3]
Set which power state to go after PWROFF triggered byWDOG_B = 0
0 = to SNVS
1 = to READY
WDOG_
POFF_TO_READY
D[2]
D[1]
D[0]
0
0
0
Set which power state to go after PWROFF triggered bySoftware Reset
0 = to SNVS
1 = to READY
SWRST_
POFF_TO_READY
Set which power state to go after PWROFF triggered byPMIC_ON_REQ = 0
0 = to SNVS
1 = to READY
ON_REQ_
POFF_TO_READY
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3.2.5.15. PWROFF – continued
more than 3.0 V
VSYS
VRs
RUN/SNVS
(Power On Sequence)
PWROFF
(Power Off Sequence)
SNVS/
READY
SNVS/READY
(POW_SUB[1:0]=11)
Power State
PONT[3:0] in
TRANS_COND1 register
Figure 3-19. Cold Reset Duration Time set by PONT[3:0]
Table 3-35. VR Summary After Power OFF Sequence
PWRON_
WDOG_
SWRST_
ON_REQ_
C32K_
OUT
RTC_
RESET_B
PWROFF trigger
POFF_TO_ POFF_TO_ POFF_TO_ POFF_TO_
READY
LDO2
LDO1
READY
READY
READY
0
1
-
-
-
-
-
-
-
On
Off
On
Off
On
Off
On
Off
High
Low
High
Low
High
Low
High
Low
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
PWRON_B Long Push
WDOG_B = 0
0
1
-
-
-
-
-
-
-
0
1
-
-
Software Reset
-
-
-
-
-
0
1
PMIC_ON_REQ = 0
-
-
-
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3.2.5.16. PWROFF to READY
After the completion of Power OFF sequence, the power state goes READY if the POFF_TO_READY = 1.
This is in accordance with PWROFF trigger event in the TRANS_COND1 register.
3.2.5.17. PWROFF to SNVS
After the completion of Power OFF sequence, the power state goes SNVS if the POFF_TO_READY = 0.
This is in accordance with PWROFF trigger event in the TRANS_COND1 register.
3.2.5.18. PWRON_B Functionality
The system has a button that can be used for triggering the system to power on or off. PWRON_B is an
active-low input to BD71850MWV. Timer circuitry measures the length of time the button is pressed. Then
the timer detects short push and long push events.
VSYS
BD71850MWV
IRQ_B
IRQ
Control
Short Push
Long Push
PWRON_B
Debouncer
Edge
Detector
Timer
Power
State
Machine
Power Button
STAT_PWRON
IN_MON
PWRONCONFIG0
PBDBNCT
SHORTT
PWRONCONFIG1
LONGT
Figure 3-20. Power Button Block Diagram
Table 3-36. PWRONCONFIG0 - PWRON_B Configuration 0 Register
Register Name
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x16
Address
0x27
PBDBNCT[1:0]
SHORTT[3:0]
PWRONCONFIG0
-
-
Bit
Name
PBDBNCT[1:0]
Function
PWRON_B Input Pin Debounce Time
Initial
01
D[5:4]
00 = 10 ms 01 = 30 ms(default) 10 = 60 ms 11 = 100 ms
Short Push Timer :
0000 = 10 ms
0001 = 0.5 s
0010 = 1.0 s
0011 = 1.5 s
0100 = 2.0 s
0101 = 2.5 s
0110 = 3.0 s (default)
0111 = 3.5 s
1000 = 4.0 s
1001 = 4.5 s
1010 = 5.0 s
1011 = 5.5 s
1100 = 6.0 s
1101 = 6.5 s
1110 = 7.0 s
1111 = 7.5 s
SHORTT[3:0]
0110
D[3:0]
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3.2.5.18. PWRON_B Functionality – continued
Table 3-37. PWRONCONFIG1 - PWRON_B Configuration 1 Register
Register Name
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x28
LONGT[3:0]
PWRONCONFIG1
-
-
-
-
Bit
Name
Function
Initial
Long Push Timer :
0000 = 10 ms (default)
0001 = 1 s
0010 = 2 s
0011 = 3 s
0100 = 4 s
0101 = 5 s
0110 = 6 s
LONGT[3:0]
0111 = 7 s
0000
D[3:0]
1000 = 8 s
1001 = 9 s
1010 = 10 s
1011 = 11 s
1100 = 12 s
1101 = 13 s
1110 = 14 s
1111 = 15 s
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3.3. Power Sequence
3.3.1. Power ON Sequence
Figure 3-21 shows an example when TRANS_COND0 = 0x48, which are:
READY to SNVS condition: VSYS_UVLO = 1
SNVS to RUN condition: PMIC_ON_REQ
Power State
VSYS
OFF
READY
SNVS
RUN
3.0 V
0
V
INTLDO1P5
0
V
VSYS_UVLO
(PMIC Internal)
LDO1 (1.8 V)
(NVCC_SNVS)
t0
LDO2 (0.8 V)
(VDD_SNVS)
t1
RTC clock
(PMIC Internal)
Stop
RTC_RESET_B
(PMIC -> SOC)
t2
C32K_OUT
(PMIC -> SOC)
t3
Stop
PMIC_ON_REQ
(SOC -> PMIC)
PMIC internal ON
signal
Masked to L
Masked to L
t15
PMIC_STBY_REQ
(SOC -> PMIC)
L
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
t4
BUCK5 (0.9 V)
LDO4 (0.9 V)
OFF
OFF
t7
BUCK2 (0.9 V)
(VDD_ARM)
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t9
BUCK7 (1.8 V)
(NVCC_1V8)
t10
BUCK8 (1.1 V)
(NVCC_DRAM)
t11
BUCK6 (3.3 V)
(NVCC_3V3)
t12
LDO6 (1.2 V)
(VDD_PHY_1V2)
t13
POR_B
(PMIC -> SOC)
t14
WDOG_B
(SOC -> PMIC)
Masked to H
LDO5 is turned on by Software
LDO5 (3.3 V)
OFF
Figure 3-21. Power ON Sequence
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3.3.1. Power ON Sequence – continued
Table 3-38. Power ON Sequence Timing Specification
Symbol
Description
Min
0
Typ
20
Max
22
Unit
ms
ms
ms
μs
t0
t1
t2
t3
t4
VSYS = 3.0 Vto LDO1 Assert Delay
LDO1 Assert to LDO2 Assert Delay
0
2.0
10
2.4
LDO2 Assert to RTC_RESET_B De-assert Delay
RTC_RESET_B De-assert to C32K_OUT Output Delay
PMIC_ON_REQ Assert to BUCK1 Assert Delay
BUCK1 Assert to BUCK2 Assert Delay
BUCK1 Assert to LDO3 Assert Delay
0
12
0
40
90
0
0.20
12.49
ms
t7
0
4.0
4.8
ms
t9
LDO3 Assert to BUCK7 Assert Delay
0
0
0
0
0
0
2.0
2.0
2.0
2.0
20
2.4
2.4
2.4
2.4
22
ms
ms
ms
ms
ms
ms
t10
t11
t12
t13
t14
BUCK7 Assert to BUCK8 Assert Delay
BUCK8 Assert to BUCK6 Assert Delay
BUCK6 Assert to LDO6 Assert Delay
LDO6 Assert to POR_B De-assert Delay
POR_B De-assert to WDOG_B Internal Mask Disabled
10
12
POR_B De-assert to PMIC_STBY_REQ Internal Mask
Disabled
t15
0
10
12
ms
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3.3.2. Power OFF Sequence
Figure 3-22 shows an example when triggered by PMIC_ON_REQ when ON_REQ_POFF_TO_READY = 0 in
TRANS_COND1 register.
Power State
VSYS
RUN
PWROFF
SNVS
H
H
INTLDO1P5
VSYS_UVLO
(PMIC Internal)
RTC clock
(PMIC Internal)
PMIC_ON_REQ
(SOC -> PMIC)
PMIC_STBY_REQ
(SOC -> PMIC)
L
WDOG_B
(SOC -> PMIC)
Masked to H
POR_B
(PMIC -> SOC)
t0
LDO5 (3.3 V)
OFF
LDO6 (1.2 V)
(VDD_PHY_1V2)
t2
BUCK6 (3.3 V)
(NVCC_3V3)
t3
BUCK8 (1.1 V)
(NVCC_DRAM)
t4
BUCK7 (1.8 V)
(NVCC_1V8)
t5
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t6
BUCK2 (0.9 V)
(VDD_ARM)
t7
LDO4 (0.9 V)
OFF
OFF
BUCK5 (0.9 V)
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
t10
C32K_OUT
(PMIC -> SOC)
RTC_RESET_B
H
(PMIC -> SOC)
0.8 V
LDO2 (0.8 V)
(VDD_SNVS)
LDO1 (1.8 V)
1.8 V
(NVCC_SNVS)
Figure 3-22. Power OFF Sequence (To SNVS)
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3.3.2. Power OFF Sequence – continued
Table 3-39. Power OFF Sequence Timing Specification (To SNVS)
Symbol
Description
Min
0
Typ
120
40
Max
200
48
Unit
μs
t0
t2
PMIC_ON_REQ De-assert to POR_B Assert Delay
POR_B De-assert to LDO6 De-assert Delay
LDO6 De-assert to BUCK6 De-assert Delay
BUCK6 De-assert to BUCK8 De-assert Delay
BUCK8 De-assert to BUCK7 De-assert Delay
BUCK7 De-assert to LDO3 De-assert Delay
LDO3 De-assert to BUCK2 De-assert Delay
BUCK2 De-assert to BUCK1 De-assert Delay
0
ms
ms
ms
ms
ms
ms
ms
t3
0
10
12
t4
0
10
12
t5
0
10
12
t6
0
10
12
t7
0
10
12
t10
0
30
36
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3.3.2. Power OFF Sequence – continued
Figure 3-23 shows an example when triggered by PMIC_ON_REQ when ON_REQ_POFF_TO_READY = 1 in
TRANS_COND1 register.
Power State
VSYS
RUN
PWROFF
READY
H
H
INTLDO1P5
VSYS_UVLO
(PMIC Internal)
RTC clock
(PMIC Internal)
PMIC_ON_REQ
(SOC -> PMIC)
PMIC_STBY_REQ
(SOC -> PMIC)
L
WDOG_B
(SOC -> PMIC)
Masked to H
POR_B
(PMIC -> SOC)
t0
LDO5 (3.3 V)
OFF
LDO6 (1.2 V)
(VDD_PHY_1V2)
t2
BUCK6 (3.3 V)
(NVCC_3V3)
t3
BUCK8 (1.1 V)
(NVCC_DRAM)
t4
BUCK7 (1.8 V)
(NVCC_1V8)
t5
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t6
BUCK2 (0.9 V)
(VDD_ARM)
t7
LDO4 (0.9 V)
OFF
OFF
BUCK5 (0.9 V)
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
t11
t10
C32K_OUT
(PMIC -> SOC)
t12
RTC_RESET_B
(PMIC -> SOC)
H
t13
LDO2 (0.8 V)
(VDD_SNVS)
0.8 V
1.8 V
LDO1 (1.8 V)
(NVCC_SNVS)
t14
Figure 3-23. Power OFF Sequence (To READY)
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3.3.2. Power OFF Sequence – continued
Table 3-40. Power OFF Sequence Timing Specification (To READY)
Symbol
Description
Min
0
Typ
120
40
10
10
10
10
10
30
10
10
10
10
Max
200
48
12
12
12
12
12
36
12
12
12
12
Unit
μs
t0
t2
PMIC_ON_REQ De-assert to POR_B Assert Delay
POR_B De-assert to LDO6 De-assert Delay
LDO6 De-assert to BUCK6 De-assert Delay
BUCK6 De-assert to BUCK8 De-assert Delay
BUCK8 De-assert to BUCK7 De-assert Delay
BUCK7 De-assert to LDO3 De-assert Delay
LDO3 De-assert to BUCK2 De-assert Delay
BUCK2 De-assert to BUCK1 De-assert Delay
BUCK1 De-assert to C32K_OUT Output Stop Delay
C32K_OUT Output Stop to RTC_RESET_B Assert Delay
RTC_RESET_B Assert to LDO2 De-assert Delay
LDO2 De-assert to LDO1 De-assert Delay
0
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
t3
0
t4
0
t5
0
t6
0
t7
0
t10
t11
t12
t13
t14
0
0
0
0
0
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3.3.3. RUN to IDLE
Power State
RUN
IDLE
RTC clock
(PMIC Internal)
RTC_RESET_B
H
(PMIC -> SOC)
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
PMIC_STBY_REQ
(SOC -> PMIC)
L
WDOG_B
H
(SOC -> PMIC)
POR_B
H
(PMIC -> SOC)
I2C Interface
(SOC -> PMIC)
Write 1 to IDLE_MODE in
PWRCTRL1 register
LDO5 (3.3 V)
OFF
LDO6 (1.2 V)
1.2
V
(VDD_PHY_1V2)
3.3 V
BUCK6 (3.3 V)
(NVCC_3V3)
BUCK8 (1.1 V)
(NVCC_DRAM)
1.1
V
BUCK7 (1.8 V)
(NVCC_1V8)
1.8
1.8
V
V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t0
Voltage specified by BUCK2_VOLT_RUN[6:0]
Voltage specified by BUCK2_VOLT_IDLE[6:0]
0.9
V
BUCK2 (0.9 V)
(VDD_ARM)
LDO4 (0.9 V)
OFF
OFF
BUCK5 (0.9 V)
t1
Voltage specified by BUCK1_VOLT_IDLE[6:0]
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
0.8
0.8
1.8
V
V
V
LDO2 (0.8 V)
(VDD_SNVS)
LDO1 (1.8 V)
(NVCC_SNVS)
Figure 3-24. RUN to IDLE
Table 3-41. RUN to IDLE Timing Specification
Symbol
Description
Min
0
Typ
120
120
Max
200
200
Unit
μs
t0
t1
End of I2C Access to BUCK2 Voltage Change Start
BUCK2 to BUCK1 Voltage Change Delay
0
μs
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3.3.4. IDLE to RUN
Power State
IDLE
RUN
RTC clock
(PMIC Internal)
RTC_RESET_B
H
(PMIC -> SOC)
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
H
H
H
PMIC_STBY_REQ
(SOC -> PMIC)
WDOG_B
(SOC -> PMIC)
POR_B
(PMIC -> SOC)
I2C Interface
(SOC -> PMIC)
Write 0 to IDLE_MODE in
PWRCTRL1 register
LDO5 (3.3 V)
OFF
1.2
V
LDO6 (1.2 V)
(VDD_PHY_1V2)
BUCK6 (3.3 V)
(NVCC_3V3)
3.3 V
1.1
V
BUCK8 (1.1 V)
(NVCC_DRAM)
BUCK7 (1.8 V)
(NVCC_1V8)
1.8
1.8
V
V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t1
0.9V = Voltage specified by BUCK2_VOLT_RUN[6:0]
BUCK2 (0.9 V)
(VDD_ARM)
Voltage specified by BUCK2_VOLT_IDLE[6:0]
LDO4 (0.9 V)
OFF
OFF
BUCK5 (0.9 V)
t0
BUCK1 (0.8 V)
Voltage specified by BUCK1_VOLT_IDLE[6:0]
0.8V = Voltage specified by BUCK1_VOLT_RUN[6:0]
(VDD_SOC,VDDA_0V8,PHY_0V8)
LDO2 (0.8 V)
(VDD_SNVS)
0.8
1.8
V
V
LDO1 (1.8 V)
(NVCC_SNVS)
Figure 3-25. IDLE to RUN
Table 3-42. IDLE to RUN Timing Specification
Symbol
Description
Min
0
Typ
120
120
Max
200
200
Unit
μs
t0
t1
End of I2C Access to BUCK1 Voltage Change Start
BUCK1 to BUCK2 Voltage Change Delay
0
μs
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3.3.5. RUN to SUSPEND
Power State
RUN
SUSPEND
RTC clock
(PMIC Internal)
RTC_RESET_B
H
(PMIC -> SOC)
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
PMIC_STBY_REQ
(SOC -> PMIC)
H
WDOG_B
(SOC -> PMIC)
H
H
POR_B
(PMIC -> SOC)
LDO5 (3.3 V)
OFF
1.2
V
LDO6 (1.2 V)
(VDD_PHY_1V2)
3.3 V
1.1 V
1.8 V
BUCK6 (3.3 V)
(NVCC_3V3)
BUCK8 (1.1 V)
(NVCC_DRAM)
BUCK7 (1.8 V)
(NVCC_1V8)
1.8
0.9
V
V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
BUCK2 (0.9 V)
(VDD_ARM)
0 V (OFF)
t0
LDO4 (0.9 V)
OFF
OFF
BUCK5 (0.9 V)
0.8
0.8
1.8
V
V
V
Voltage specified by BUCK1_VOLT_SUSP[6:0]
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
t2
LDO2 (0.8 V)
(VDD_SNVS)
LDO1 (1.8 V)
(NVCC_SNVS)
Figure 3-26. RUN to SUSPEND
Table 3-43. RUN to SUSPEND Timing Specification
Symbol
Description
Min
0
Typ
120
20
Max
200
24
Unit
μs
t0
t2
PMIC_STBY_REQ High to BUCK2 De-assert Delay
BUCK2 to BUCK1 Voltage Change Delay
0
ms
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3.3.6. SUSPEND to RUN
Power State
SUSPEND
RUN
RTC clock
(PMIC Internal)
RTC_RESET_B
H
(PMIC -> SOC)
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
H
H
H
PMIC_STBY_REQ
(SOC -> PMIC)
WDOG_B
(SOC -> PMIC)
POR_B
(PMIC -> SOC)
LDO5 (3.3 V)
OFF
1.2
V
LDO6 (1.2 V)
(VDD_PHY_1V2)
3.3 V
1.1 V
1.8 V
BUCK6 (3.3 V)
(NVCC_3V3)
BUCK8 (1.1 V)
(NVCC_DRAM)
BUCK7 (1.8 V)
(NVCC_1V8)
1.8
V
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
BUCK2 (0.9 V)
0.9
V
t2
(VDD_ARM)
0 V (OFF)
LDO4 (0.9 V)
OFF
OFF
BUCK5 (0.9 V)
t0
BUCK1 (0.8 V)
Voltage specified by BUCK1_VOLT_RUN[6:0]
(VDD_SOC,VDDA_0V8,PHY_0V8)
Voltage specified by BUCK1_VOLT_SUSP[6:0]
0.8
V
LDO2 (0.8 V)
(VDD_SNVS)
1.8
V
LDO1 (1.8 V)
(NVCC_SNVS)
Figure 3-27. SUSPEND to RUN
Table 3-44. SUSPEND to RUN Timing Specification
Symbol
Description
Min
0
Typ
120
2.0
Max
200
2.4
Unit
μs
t0
t2
PMIC_STBY_REQ Low to BUCK1 Voltage Change Start
BUCK1 to BUCK2 Voltage Change Delay
0
ms
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3.3.7. IDLE to SUSPEND
Power State
IDLE
SUSPEND
RTC clock
(PMIC Internal)
RTC_RESET_B
H
(PMIC -> SOC)
C32K_OUT
(PMIC -> SOC)
PMIC_ON_REQ
(SOC -> PMIC)
H
L
PMIC_STBY_REQ
(SOC -> PMIC)
IDLE_MODE in
PWRCTRL1
Automatically return to 0 when exiting IDLE
(PMIC Internal)
WDOG_B
(SOC -> PMIC)
H
H
POR_B
(PMIC -> SOC)
LDO5 (3.3 V)
OFF
1.2
V
LDO6 (1.2 V)
(VDD_PHY_1V2)
3.3
V
V
V
V
BUCK6 (3.3 V)
(NVCC_3V3)
1.1
1.8
1.8
BUCK8 (1.1 V)
(NVCC_DRAM)
BUCK7 (1.8 V)
(NVCC_1V8)
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
t0
BUCK2 (0.9 V)
(VDD_ARM)
Voltage specified by BUCK2_VOLT_IDLE[6:0]
0
V (OFF)
LDO4 (0.9 V)
OFF
BUCK5 (0.9 V)
OFF
BUCK1 (0.8 V)
Voltage specified by BUCK1_VOLT_IDLE[6:0]
Voltage specified by BUCK1_VOLT_SUSP[6:0]
(VDD_SOC,VDDA_0V8,PHY_0V8)
t2
0.8 V
LDO2 (0.8 V)
(VDD_SNVS)
1.8
V
LDO1 (1.8 V)
(NVCC_SNVS)
Figure 3-28. IDLE to SUSPEND
Table 3-45. IDLE to SUSPEND Timing Specification
Symbol
Description
Min
0
Typ
120
20
Max
200
24
Unit
μs
t0
t2
PMIC_STBY_REQ High to BUCK2 De-assert Delay
BUCK2 to BUCK1 Voltage Change Delay
0
ms
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3.3.8. Emergency Shutdown
Power State
VSYS
Any State except OFF and READY
EMG
H
H
INTLDO1P5
VSYS_UVLO
(PMIC Internal)
RTC clock
(PMIC Internal)
RTC_RESET_B
H
(PMIC -> SOC)
C32K_OUT
(PMIC -> SOC)
Thermal Shutdown Event occurs.
Emergency
Event
When Power State = RUN, IDLE and SUSPEND
When Power State = SNVS
POR_B
(PMIC -> SOC)
t0
LDO5 (3.3 V)
LDO6 (1.2 V)
(VDD_PHY_1V2)
BUCK6 (3.3 V)
(NVCC_3V3)
BUCK8 (1.1 V)
(NVCC_DRAM)
BUCK7 (1.8 V)
(NVCC_1V8)
t1
LDO3 (1.8 V)
(VDDA_1V8,VDDA_DRAM)
BUCK2 (0.9 V)
(VDD_ARM)
LDO4 (0.9 V)
OFF
OFF
BUCK5 (0.9 V)
BUCK1 (0.8 V)
(VDD_SOC,VDDA_0V8,PHY_0V8)
LDO2 (0.8 V)
(VDD_SNVS)
LDO1 (1.8 V)
(NVCC_SNVS)
Figure 3-29. Emergency Shutdown
Table 3-46. Emergency Shutdown Timing Specification
Symbol
Description
Min
Typ
120
30
Max
200
35
Unit
μs
EmergencyEvent to POR_B Assert and
All VRs Except BUCK7 De-assert Delay
t0
t1
0
POR_B Assert to BUCK7 De-assert Delay
0
ms
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3.3.9. Warm Reset
I2C Write Access for SWRESET = 1
SDA D0 ACK
STOP
SCL
t1
POR_B
t0
Figure 3-30. Warm Reset (SWRESET)
Table 3-47. Warm Reset (SWRESET) Timing Specification
Symbol
Description
Min
-
Typ
-
Max
1.0
Unit
μs
t0
t1
SCL rising to POR_B assert delay
POR_B assert duration time
0.95
1.00
1.05
ms
t0
Including debouncetime = 100μs
WDOG_B
POR_B
t1
Figure 3-31. Warm Reset (WDOG_B)
Table 3-48. Warm Reset (WDOG_B) Timing Specification
Symbol
Description
Min
100
0.95
Typ
110
1.00
Max
120
1.05
Unit
μs
t0
t1
WDOG_B falling to POR_B assert delay
POR_B assert duration time
ms
t0
PWRON_B
t1
Figure 3-32. Warm Reset (PWRON_B Long Push)
Table 3-49. Warm Reset (PWRON_B Long Push) Timing Specification
POR_B
Symbol
Description
Min
Typ
Max
Unit
PBDBNCT[1:0] in
PWRONCONFIG0
+ LONGT[3:0] in
PWRONCONFIG1
-50
PBDBNCT[1:0] in
PWRONCONFIG0
+ LONGT[3:0] in
PWRONCONFIG1
+50
PBDBNCT[1:0] in
PWRONCONFIG0
+ LONGT[3:0] in
PWRONCONFIG1
t0
PWRON_B falling to POR_B assert delay
POR_B assert duration time
ms
ms
t1
0.95
1.00
1.05
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3.3.10.Reset Source Indicators
The BD71850MWV has RESETSRC register which is intended to store the cause of a shutdown or reset, the firmware
reads this data on the next startup. Depending on the cause of a shutdown or reset, the only bit of RESETSRC register
is 1.
Table 3-50. RESETSRC - Reset Source Indicator Register
Register Name
RESETSRC
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x29
RPMIC_ON_
REQ
RPWRON
RWDOG
RSWRST
RVSYS_2P7
RTEMP
ROCP
RVR_FAULT
Bit
Name
Function
Initial
0
0 = Default
D[7]
RPWRON
1 = Previous shutdown was due to the PWRON_B Long Push Cold Reset
(Write-1-clear bit)
0 = Default
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
RWDOG
1 = Previous shutdown was due to the WDOG_B Cold Reset
(Write-1-clear bit)
0
0
0
0
0
0
0
0 = Default
RSWRST
1 = Previous shutdown was due to the Software Cold Reset
(Write-1-clear bit)
0 = Default
RPMIC_ON_REQ
RVSYS_2P7
RTEMP
1 = Previous shutdown was due to the PMIC_ON_REQ = 0
(Write-1-clear bit)
0 = Default
1 = Previous shutdown was due to the EmergencyVSYS < 2.7V
(Write-1-clear bit)
0 = Default
1 = Previous shutdown was due to the EmergencyThermal Shutdown
(Write-1-clear bit)
0 = Default
ROCP
1 = Previous shutdown was due to the EmergencyOCP
(Write-1-clear bit)
0 = Default
RVR_FAULT
1 = Previous shutdown was due to the EmergencyVR Fault
(Write-1-clear bit)
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4. I2C and Interrupt
4.1. I2C Bus Interface
4.1.1. I2C Bus Interface Overview
I2C access is not permitted when the power state = READY.
DVDD
DVDD
[Internal Logic Circuit]
I2C slave controller
DVDD
DVDD
SCL
SDA
Spike Filter
Spike Filter
GND
Figure 4-1. I2C (Slave) Block Diagram
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4.1.2. I2C Bus Interface Electrical Characteristics
Table 4-1. I2C Bus Interface DC Electrical Characteristics
(Unless otherwise specified, Ta=+25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Typ
Parameter
Symbol
Unit
Condition
Min
Max
Digital pin characteristics – Input (SCL)
SCL
Input "H" Level
SCL
Input "L" Level
SCL
Input Hysteresis
SCL
Input Leak Current(Input=0 V)
SCL
Input Leak Current(Input=5.5 V)
DVDD
x0.7
DVDD
+ 0.3
DVDD
x0.3
V
-
-
-
-
-
V
V
IH_SCL
V
-0.3
0.1
-1
IL_SCL
V
-
V
IHYS_SCL
IOFF1_SCL
+1
+1
μA
μA
IOFF2_SCL
-1
Digital pin characteristics – Input (SDA)
SDA
Input "H" Level
SDA
Input "L" Level
SDA
Input Hysteresis
SDA
Input Leak Current(Input=0 V)
SDA
Input Leak Current(Input=5.5 V)
DVDD
x0.7
DVDD
+ 0.3
DVDD
x0.3
V
-
-
-
-
-
V
V
IH_SDA
V
-0.3
0.1
-1
IL_SDA
V
-
V
IHYS_SDA
IOFF1_SDA
+1
+1
μA
μA
IOFF2_SDA
-1
Digital pin characteristics - Output (SDA)
SDA
VOL_SDA
-
-
-
-
0.4
+1
+1
V
IOL=6mA
Output "L" Level Voltage
Output Off Leak Current(Input=0
V)
Output Off Leak
Current(Input=5.5 V)
IOFF3_SDA
-1
-1
μA
μA
IOFF4_SDA
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4.1.2. I2C Bus Interface Electrical Characteristics – continued
Table 4-2. I2C Bus Interface AC Timing - Fast Mode
(Unless otherwise specified, Ta=+25°C, VSYS=5.0 V, DVDD=1.8 V)
Fast mode
Fast mode plus
Parameter
Symbol
Unit
Min
0
Typ
Max
Min
0
Typ
Max
I2C_CLK Clock Frequency
Hold Time START Condition
LOW Period of I2C_CLK Clock
fSCL
tHD_STA
tLOW
-
-
-
-
400
-
-
-
-
1000
kHz
μs
0.60
1.3
0.60
-
-
-
0.26
0.5
0.26
-
-
-
μs
HIGH Period of I2C_CLK Clock
Set-up Time for a Repeated START
Condition
tHIGH
μs
tSU_STA
0.60
-
-
0.26
-
-
μs
Data Hold Time
tHD_DAT
tSU_DAT
tSU_STO
tF
0
100
0.60
20
-
-
-
-
-
0
50
0.26
-
-
-
-
-
-
-
-
ns
ns
μs
ns
pF
Data Set-up Time
Set-up Time for STOP Condition
Fall Time of I2C_DATASignal
-
-
300
400
120
550
Capacitive Load for Each Bus Line
Pulse Width of Spikes that are
Suppressed bythe Input Filter
Bus Free Time
CB
-
-
-
-
tSP
0
50
0
-
50
ns
tBUF
1.3
-
-
-
-
0.5
-
-
-
-
μs
μs
μs
Data Valid Time
tVD_DAT
tVD_ACK
-
-
0.90
0.90
-
-
0.45
0.45
Data Valid Acknowledge Time
tF
tR
tSU_DAT
70%
30%
SDA
SCL
tF
tVD_DAT
70%
30%
tHD_DAT
tHD_STA
1 / fSCL
tLOW
tR
tHIGH
S
tBUF
70%
30%
SDA
SCL
tSU_STA
tHD_STA
tSU_STO
tSP
tVD_ACK
70%
30%
Sr
P
S
Figure 4-2. I2C Bus Interface AC Timing
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4.1.3. Device Addressing
Table 4-3. I2C_DEV - I2C Device Address Indicator Register
Register Name
I2C_DEV
R/W
R
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x03
Address
0x02
I2C_DEV_ADRS[1:0]
-
-
-
-
-
-
Bit
Name
Function
Initial
00 = I2C 7 bit Device Address = 0x48
01 = I2C 7 bit Device Address = 0x49
10 = I2C 7 bit Device Address = 0x4A
11 = I2C 7 bit Device Address = 0x4B
I2C_DEV_ADRS[1:0]
11
D[1:0]
I2C Device Address
Read / Write instruction bit
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
R / W
LSB
MSB
1
R / W
LSB
MSB
1
R / W
LSB
MSB
1
R / W
LSB
a
MSB
I2C Device Address is decided byOTP setting.
Figure 4-3. I2C Device Addressing
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4.1.4. Write / Read Operation
Write single register
7-bit Device
8-bit Data
(Reg. Address)
8-bit Data
(Write Data)
S
W
Ack
Ack
Ack
P
Address
Write multiple registers (Address Auto-Increment)
7-bit Device
Address
8-bit Data
(Reg. Address)
8-bit Data
(Write Data #1)
8-bit Data
(Write Data #1)
S
W
Ack
Ack
Ack
Ack
Ack
Ack
Ack
8-bit Data
(Write Data #2)
8-bit Data
(Write Data #3)
8-bit Data
(Write Data #N)
Ack
P
Read single register
7-bit Device
Address
8-bit Data
(Reg. Address)
7-bit Device
Address
8-bit Data
(Read Data)
S
W
Ack
Ack
Sr
R
Ack
NAck
P
Read multiple registers (Address Auto-Increment)
7-bit Device
Address
8-bit Data
(Reg. Address)
7-bit Device
Address
8-bit Data
(Read Data #1)
S
W
Ack
Ack
Ack
Sr
R
Ack
Ack
Ack
8-bit Data
(Read Data #2)
8-bit Data
(Read Data #3)
8-bit Data
(Read Data #N)
Ack
NAck
P
S
Start Condition
Sr Repeat Start Condition
P
Stop Condition
W
Write (= Low)
R
Read (= High)
Ack Acknowledge (= Low, driven by I2C Slave)
Ack Acknowledge (= Low, driven by I2C Master)
NAck Not Acknowledge (= High, driven by I2C Master)
Figure 4-4. I2C Write / Read Operation
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4.2. Interrupt
4.2.1. Interrupt Overview
Table 4-4. Interrupt Event
Definition
PWRON_B Pin Level Changed
IRQ Event
PWRON
PWRON_S
PWRON_L
WDOG
PWRON_B Short Push Detection
PWRON_B Long Push Detection
WDOG_B Pin Level Changed
SWRST
ON_REQ
STBY_REQ
Written 1 to SWRESET in SWRESET Register
PMIC_ON_REQ Pin Level Changed
PMIC_STBY_REQ Pin Level Changed
Write 1 Clear
Mask bit from
MIRQ register
IRQ_B
RN
D
Q
IRQ Event
CP
to IRQ register
Figure 4-5. IRQ_B Architecture Block Diagram
Table 4-5. IRQ_B Electrical Characteristics
(Unless otherwise specified, Ta=+25°C, VSYS=5.0 V, DVDD=1.8 V)
Limit
Parameter
Symbol
Unit
Condition
Min
-
Typ
Max
DVDD x0.2
+1
Output "L" Level Voltage
Output Off Leak Current
VOL_IRQB
IOLK_IRQB
-
-
V
IOL=3 mASink
-1
μA
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4.2.1. Interrupt Overview – continued
Table 4-6. IRQ - Interrupt Register
Register Name
IRQ
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x2B
SWRST
PWRON_S PWRON_L
PWRON
WDOG
ON_REQ STBY_REQ
Bit
Name
Function
Initial
0 = SWRESET in SWRESET register is not written 1
1 = SWRESET in SWRESET register is written 1
This bit is a write-1-to-clear bit.
SWRST
PWRON_S
PWRON_L
PWRON
0
0
0
0
0
0
0
D[6]
0 = PWRON_B Short Push not detected
1 = PWRON_B Short Push detected
This bit is a write-1-to-clear bit.
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0 = PWRON_B Long Push not detected
1 = PWRON_B Long Push detected
This bit is a write-1-to-clear bit.
0 = PWRON_B level change not generated
1 = PWRON_B level change generated
This bit is a write-1-to-clear bit.
0 = WDOG_B level change not generated
1 = WDOG_B level change generated
This bit is a write-1-to-clear bit.
WDOG
0 = PMIC_ON_REQ level change not generated
1 = PMIC_ON_REQ level change generated
This bit is a write-1-to-clear bit.
ON_REQ
STBY_REQ
0 = PMIC_STBY_REQ level change not generated
1 = PMIC_STBY_REQ level change generated
This bit is a write-1-to-clear bit.
Table 4-7. MIRQ – IRQ Mask Register
Register Name
MIRQ
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x7F
Address
0x2A
MPWRON_ MPWRON_
MSTBY_
REQ
MSWRST
MPWRON
MWDOG MON_REQ
S
L
Bit
Name
Function
Initial
1
0 = No Mask
1 = Mask Interrupt
D[6]
MSWRST
0 = No Mask
1 = Mask Interrupt
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
MPWRON_S
MPWRON_L
MPWRON
1
1
1
1
1
1
0 = No Mask
1 = Mask Interrupt
0 = No Mask
1 = Mask Interrupt
0 = No Mask
1 = Mask Interrupt
MWDOG
0 = No Mask
1 = Mask Interrupt
MON_REQ
MSTBY_REQ
0 = No Mask
1 = Mask Interrupt
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4.2.1. Interrupt Overview – continued
Table 4-8. IN_MON - Input Port Monitor Register
Register Name
IN_MON
R/W
R
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x2C
STAT_
STAT_
WDOG
STAT_
ON_REQ STBY_REQ
STAT_
-
-
-
PWRON
Bit
Name
Function
Initial
0 = PWRON_B level is 0
1 = PWRON_B level is 1
D[3]
STAT_PWRON
STAT_WDOG
0
0
0
0
0 = WDOG_B level is 0
1 = WDOG_B level is 1
D[2]
D[1]
D[0]
0 = PMIC_ON_REQ level is 0
1 = PMIC_ON_REQ level is 1
STAT_ON_REQ
STAT_STBY_REQ
0 = PMIC_STBY_REQ level is 0
1 = PMIC_STBY_REQ level is 1
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5. Power Rails
5.1. Output Voltage Range
Table 5-1. Output Voltage Range1
Data
[Hex]
BUCK1 BUCK2
-
-
BUCK5 BUCK6 BUCK7 BUCK8 LDO1 LDO2 LDO3 LDO4 LDO5 LDO6
-
1.80
0.90
00
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.70
0.80
3.00
3.10
3.20
1.605
1.695
1.755
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
3.00
3.10
3.20
3.30
0.90
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
0.90
1.00
1.10
(Note 1)
(Note 1)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
0.90
(Note 1)
3.30
(Note 1)
1.800
(Note 1)
1.20
(Note 1)
1.00
1.05
1.10
1.20
1.35
1.845
1.905
1.950
1.995
1.30
1.40
1.50
1.60
1.70
1.80
0.80
(Note 1)
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
3.30
(Note 1)
0.90
(Note 1)
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.10
(Note 1)
1.11
(Note 1) initial voltage(run mode)
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5.1. Output Voltage Range – continued
Table 5-2. Output Voltage Range2
Data
[Hex]
BUCK1 BUCK2
-
-
BUCK5 BUCK6 BUCK7 BUCK8 LDO1 LDO2 LDO3 LDO4 LDO5 LDO6
-
0.80
(Note 1)
20
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
1.32
1.33
1.34
1.35
1.36
1.37
1.38
1.39
1.40
1.60
1.70
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1.80
(Note 1)
1.90
(Note 1) initial voltage(run mode)
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5.2. Details of Buck
5.2.1. BUCK1
5.2.1.1.
BUCK1 Block Diagram
VSYS
INT LDO1P5
BUCK1_VIN
OCP
OSC
VREF
DAC
Voltage setting
BUCK1_LX
Switch
Control
LBK 1
-
-
Soft Start
COBK1
+
PGND
(EXP-PAD)
EN
BUCK1_FB
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-1. BUCK1 Block Diagram
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5.2.1.2.
BUCK1 Electrical Characteristics
Table 5-3. BUCK1 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Limit
Typ
Parameter
Output Voltage
Symbol
VO_BK1
Unit
V
Condition
Min
Max
Vo = 0.8 V
0.791
0.800
0.809
Io = 200 mA, PWM fix Mode
Programmable
Output Voltage Range
VORG_BK1
IQ_BK1
0.7
-
15
-
1.3
V
µA
mA
mA
%
10 mVstep
Vo = 0.8 V
Io = 0 mA, Auto mode
Quiescent Current
-
-
Maximum Output Current
Over Current Protection
IOMAX_BK1
IOCP_BK1
ΔVLDR_BK1
ηBK1_1mA
ηBK1_500mA
ηBK1_max
fSW_BK1
3000
-
Peak current of inductor(Note 1)
Io = 1 mAto Iomax, PWM fix Mode
Io = 1 mA, Vo = 0.8 V
4500
-
-
DC Output Voltage Load Regulation
-1
-
0
+1
80
84
70
2
-
%
Efficiency
-
-
%
Io = 500 mA, Vo = 0.8 V
Io = Iomax, Vo = 0.8 V
-
-
%
Oscillating Frequency
Start up Time
-
-
MHz
µs
Ω
PWM fix mode, Io = 0 mA
During EN to 90 % of nominal Voltage,
BUCK1_RAMPRATE_RUN[1:0] = 01
tST_BK1
-
144
100
80
500
Discharge Resistance
Low Side VR Fault Detect Level
RD_BK1
-
-
-
Vo = 0.8 V(FB = Sweep down)
VR fault detect level / Vo x 100
DVRFBK1_L
-
%
(VR fault release level - detect level) / Vo x
100
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
DVRFBK1_LHYS
DVRBK1_H
DVRFBK1_HHYS
LBK1
-
-
10
-
-
%
%
Vo = 0.8 V(FB = Sweep up)
Power good detect level / Vo x 100
130
(VR fault detect level - release level) / Vo x
100
High Side VR Fault Detect Hysteresis
Output Inductance
-
-
20
-
-
%
0.47
μH
(Note 2)
(Note 2)
Effective capacitance with BUCK's DC bias
Max value is limited by ramp rate.
<Output Max Capacitance>
ramp rate 1.25 mV, 2.5 mV, 5 mV: 100 µF
ramp rate 10 mV: 50 µF
Output Capacitance
COBK1
22
44
100
μF
(Note 1) For Buck- DCDC converters, (minimumOver Current Protection Current – ½ inductor ripple current) is the maximumoutput current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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5.2.1.3.
BUCK1 Control
Table 5-4. BUCK1_CTRL - BUCK1 Control Register
Register Name
BUCK1_CTRL
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x40
Address
0x05
BUCK1_RAMPRATE
[1:0]
BUCK1_
PWM_FIX
-
-
-
BUCK1_SEL BUCK1_EN
Bit
Name
Function
Initial
BUCK1 DVS ramp rate
00 = 10 mV/μs
01 = 5 mV/μs
10 = 2.5 mV/μs
11 = 1.25 mV/μs
BUCK1_RAMPRATE[1:0]
01
D[7:6]
Note : When BUCK1 voltage starts up from 0V,
the ramp rate is fixed 5mV/μs, regardless of the value of
BUCK1_RAMPRATE[1:0].
0 – AUTO PWM/PFMmode
VR adjusts the operating mode (PFM/PWM) automaticallybased on the load
current to maximize power efficiency.
1 – Forced PWMMode
BUCK1_PWM_FIX
BUCK1_SEL
0
0
D[3]
D[1]
VR operates in PWMmode only.
BUCK1 control select bit
0 = BUCK1 ON/OFF is controlled bystate machine.
1 = BUCK1 ON/OFF is controlled byD[0] on this register.
BUCK1 control bit with condition of D[1]
0 = BUCK1 OFF
1 = BUCK1 ON
BUCK1_EN
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[0]
When system is in SNVS, BUCK1_SEL = 1 and BUCK1_EN = 1, BUCK1
voltage is specified byBUCK1_VOLT_SUSP register.
Table 5-5. BUCK1_VOLT_RUN - BUCK1 Voltage (RUN) Register
Register Name
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x0A
Address
0x0D
BUCK1_VOLT_RUN
-
BUCK1_VOLT_RUN[6:0]
Function
Bit
Name
Initial
BUCK1 voltage when Power State = RUN
0x00 = 0.70 V
0x04 = 0.74 V
0x08 = 0.78 V
0x01 = 0.71 V
0x05 = 0.75 V
0x09 = 0.79 V
0x02 = 0.72 V
0x06 = 0.76 V
0x03 = 0.73 V
0x07 = 0.77 V
0x0A= 0.80V(initial)
0x0B = 0.81 V
0x0F = 0.85 V
0x13 = 0.89 V
0x15 = 0.91 V
0x19 = 0.95 V
0x1D = 0.99 V
0x21 = 1.03 V
0x25 = 1.07 V
0x29 = 1.11 V
0x2D = 1.15 V
0x31 = 1.19 V
0x35 = 1.23 V
0x39 = 1.27 V
0x0C = 0.82 V
0x0D = 0.83 V
0x11 = 0.87 V
0x0E = 0.84 V
0x12 = 0.88 V
0x10 = 0.86 V
0x14 = 0.90 V
0x16 = 0.92 V
0x1A= 0.96 V
0x1E = 1.00 V
0x22 = 1.04 V
0x26 = 1.08 V
0x2A= 1.12 V
0x2E = 1.16 V
0x32 = 1.20 V
0x36 = 1.24 V
0x3A= 1.28 V
0x17 = 0.93 V
0x1B = 0.97 V
0x1F = 1.01 V
0x23 = 1.05 V
0x27 = 1.09 V
0x2B = 1.13 V
0x2F = 1.17 V
0x33 = 1.21 V
0x37 = 1.25 V
0x3B = 1.29 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
D[6:0]
BUCK1_VOLT_RUN[6:0]
0001010
0x3D-0x7F = reserved
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5.2.1.3.
BUCK1 Control – continued
Table 5-6. BUCK1_VOLT_IDLE - BUCK1 Voltage (IDLE) Register
Register Name
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x0A
Address
0x0E
BUCK1_VOLT_IDLE
-
BUCK1_VOLT_IDLE[6:0]
Function
Bit
Name
Initial
BUCK1 voltage when Power State = IDLE
0x00 = 0.70 V
0x04 = 0.74 V
0x08 = 0.78 V
0x01 = 0.71 V
0x05 = 0.75 V
0x09 = 0.79 V
0x02 = 0.72 V
0x06 = 0.76 V
0x03 = 0.73 V
0x07 = 0.77 V
0x0A= 0.80 V(initial)
0x0B = 0.81 V
0x0F = 0.85 V
0x13 = 0.89 V
0x15 = 0.91 V
0x19 = 0.95 V
0x1D = 0.99 V
0x21 = 1.03 V
0x25 = 1.07 V
0x29 = 1.11 V
0x2D = 1.15 V
0x31 = 1.19 V
0x35 = 1.23 V
0x39 = 1.27 V
0x0C = 0.82 V
0x0D = 0.83 V
0x11 = 0.87 V
0x0E = 0.84 V
0x12 = 0.88 V
0x10 = 0.86 V
0x14 = 0.90 V
0x16 = 0.92 V
0x1A= 0.96 V
0x1E = 1.00 V
0x22 = 1.04 V
0x26 = 1.08 V
0x2A= 1.12 V
0x2E = 1.16 V
0x32 = 1.20 V
0x36 = 1.24 V
0x3A= 1.28 V
0x17 = 0.93 V
0x1B = 0.97 V
0x1F = 1.01 V
0x23 = 1.05 V
0x27 = 1.09 V
0x2B = 1.13 V
0x2F = 1.17 V
0x33 = 1.21 V
0x37 = 1.25 V
0x3B = 1.29 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
BUCK1_VOLT_IDLE[6:0]
0001010
D[6:0]
0x3D-0x7F = reserved
Table 5-7. BUCK1_VOLT_SUSP - BUCK1 Voltage (SUSPEND) Register
Register Name
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x0A
Address
0x0F
BUCK1_VOLT_SUSP
-
BUCK1_VOLT_SUSP[6:0]
Function
Bit
Name
Initial
BUCK1 voltage when Power State = SUSPEND
0x00 = 0.70 V
0x04 = 0.74 V
0x08 = 0.78 V
0x01 = 0.71 V
0x05 = 0.75 V
0x09 = 0.79 V
0x02 = 0.72 V
0x06 = 0.76 V
0x03 = 0.73 V
0x07 = 0.77 V
0x0A= 0.80V(initial)
0x0B = 0.81 V
0x0F = 0.85 V
0x13 = 0.89 V
0x15 = 0.91 V
0x19 = 0.95 V
0x1D = 0.99 V
0x21 = 1.03 V
0x25 = 1.07 V
0x29 = 1.11 V
0x2D = 1.15 V
0x31 = 1.19 V
0x35 = 1.23 V
0x39 = 1.27 V
0x0C = 0.82 V
0x0D = 0.83 V
0x11 = 0.87 V
0x0E = 0.84 V
0x12 = 0.88 V
0x10 = 0.86 V
0x14 = 0.90 V
0x16 = 0.92 V
0x1A= 0.96 V
0x1E = 1.00 V
0x22 = 1.04 V
0x26 = 1.08 V
0x2A= 1.12 V
0x2E = 1.16 V
0x32 = 1.20 V
0x36 = 1.24 V
0x3A= 1.28 V
0x17 = 0.93 V
0x1B = 0.97 V
0x1F = 1.01 V
0x23 = 1.05 V
0x27 = 1.09 V
0x2B = 1.13 V
0x2F = 1.17 V
0x33 = 1.21 V
0x37 = 1.25 V
0x3B = 1.29 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
BUCK1_VOLT_SUSP[6:0]
0001010
D[6:0]
0x3D-0x7F = reserved
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5.2.2. BUCK2
5.2.2.1.
BUCK2 Block Diagram
VSYS
INT LDO1P5
BUCK2_VIN
OCP
OSC
VREF
DAC
Voltage setting
BUCK2_LX
Switch
Control
LBK 2
-
-
Soft Start
COBK2
+
PGND
(EXP-PAD)
EN
BUCK2_FB
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-2. BUCK2 Block Diagram
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5.2.2.2.
BUCK2 Electrical Characteristics
Table 5-8. BUCK2 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Limit
Typ
Parameter
Output Voltage
Symbol
VO_BK2
Unit
V
Condition
Min
Max
0.91
Vo = 0.9 V
0.89
0.90
Io = 200 mA, PWM fix Mode
Programmable
Output Voltage Range
VORG_BK2
IQ_BK2
0.7
-
15
-
1.3
V
µA
mA
mA
%
10 mVstep
Vo = 0.9 V
Io = 0 mA, Auto mode
Quiescent Current
-
-
Maximum Output Current
Over Current Protection
IOMAX_BK2
IOCP_BK2
ΔVLDR_BK2
ηBK2_1mA
ηBK2_500mA
ηBK2_max
fSW_BK2
3000
-
Peak current of inductor(Note 1)
Io = 1 mAto Iomax, PWM fix Mode
Io = 1 mA, Vo = 0.9 V
4500
-
-
DC Output Voltage Load Regulation
-1
-
0
+1
79
84
71
2
-
%
Efficiency
-
-
%
Io = 500 mA, Vo = 0.9 V
Io = Iomax, Vo = 0.9 V
-
-
%
Oscillating Frequency
Start up Time
-
-
MHz
µs
Ω
PWM fix mode, Io = 0 mA
During EN to 90 % of nominal Voltage,
BUCK2_RAMPRATE_RUN[1:0] = 01
tST_BK2
-
162
100
80
500
Discharge Resistance
Low Side VR Fault Detect Level
RD_BK2
-
-
-
Vo = 0.9 V(FB = Sweep down)
VR fault detect level / Vo x 100
DVRFBK2_L
-
%
(VR fault release level - detect level) / Vo x
100
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
DVRFBK2_LHYS
DVRBK2_H
DVRFBK2_HHYS
LBK2
-
-
10
-
-
%
%
Vo = 0.9 V(FB = Sweep up)
Power good detect level / Vo x 100
130
(VR fault detect level - release level) / Vo x
100
High Side VR Fault Detect Hysteresis
Output Inductance
-
-
20
-
-
%
0.47
μH
(Note 2)
(Note 2)
Effective capacitance with BUCK's DC bias
Max value is limited by ramp rate.
<Output Max Capacitance>
ramp rate 1.25 mV, 2.5 mV, 5 mV: 100 µF
ramp rate 10 mV: 50 µF
Output Capacitance
COBK2
22
44
100
μF
(Note 1) For Buck- DCDC converters, (minimumOver Current Protection Current – ½ inductor ripple current) is the maximumoutput current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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5.2.2.3.
BUCK2 Control
Table 5-9. BUCK2_CTRL - BUCK2 Control Register
Register Name
BUCK2_CTRL
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x40
Address
0x06
BUCK2_
R/W BUCK2_RAMPRATE[1:0]
Name
-
-
-
BUCK2_SEL BUCK2_EN
PWM_FIX
Bit
Function
Initial
BUCK2 DVS ramp rate
00 = 10 mV/μs
01 = 5 mV/μs
10 = 2.5 mV/μs
11 = 1.25 mV/μs
D[7:6]
BUCK2_RAMPRATE[1:0]
01
Note : When BUCK2 voltage starts up from 0V,
the ramp rate is fixed 5mV/μs, regardless of the value of
BUCK2_RAMPRATE[1:0].
0 – AUTO PWM/PFMmode
VR adjusts the operating mode (PFM/PWM) automaticallybased on the load
current to maximize power efficiency.
1 – Forced PWMMode
BUCK2_PWM_FIX
BUCK2_SEL
0
0
D[3]
D[1]
VR operates in PWMmode only.
BUCK2 control select bit
0 = BUCK2 ON/OFF is controlled bystate machine.
1 = BUCK2 ON/OFF is controlled byD[0] on this register.
BUCK2 control bit with condition of D[1]
0 = BUCK2 OFF
1 = BUCK2 ON
BUCK2_EN
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
0
D[0]
When system is in SNVS or SUSPEND, BUCK2_SEL = 1 and BUCK2_EN = 1,
BUCK2 voltage is specified byBUCK2_VOLT_IDLE register.
Table 5-10. BUCK2_VOLT_RUN - BUCK2 Voltage (RUN) Register
Register Name
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x14
Address
0x10
BUCK2_VOLT_RUN[6:0]
Function
BUCK2_VOLT_RUN
-
Bit
Name
Initial
BUCK2 voltage when Power State = RUN
0x00 = 0.70 V
0x04 = 0.74 V
0x08 = 0.78 V
0x0C = 0.82 V
0x10 = 0.86 V
0x01 = 0.71 V
0x05 = 0.75 V
0x09 = 0.79 V
0x0D = 0.83 V
0x11 = 0.87 V
0x02 = 0.72 V
0x06 = 0.76 V
0x0A= 0.80 V
0x0E = 0.84 V
0x12 = 0.88 V
0x03 = 0.73 V
0x07 = 0.77 V
0x0B = 0.81 V
0x0F = 0.85 V
0x13 = 0.89 V
0x14 = 0.90 V(initial)
0x15 = 0.91 V
0x19 = 0.95 V
0x1D = 0.99 V
0x21 = 1.03 V
0x25 = 1.07 V
0x29 = 1.11 V
0x2D = 1.15 V
0x31 = 1.19 V
0x35 = 1.23 V
0x39 = 1.27 V
0x16 = 0.92 V
0x17 = 0.93 V
0x1B = 0.97 V
0x1F = 1.01 V
0x23 = 1.05 V
0x27 = 1.09 V
0x2B = 1.13 V
0x2F = 1.17 V
0x33 = 1.21 V
0x37 = 1.25 V
0x3B = 1.29 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
0x1A= 0.96 V
0x1E = 1.00 V
0x22 = 1.04 V
0x26 = 1.08 V
0x2A= 1.12 V
0x2E = 1.16 V
0x32 = 1.20 V
0x36 = 1.24 V
0x3A= 1.28 V
BUCK2_VOLT_RUN[6:0]
0010100
D[6:0]
0x3D-0x7F = reserved
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5.2.2.3.
BUCK2 Control – continued
Table 5-11. BUCK2_VOLT_IDLE - BUCK2 Voltage (IDLE) Register
Register Name
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x0A
Address
0x11
BUCK2_VOLT_IDLE[6:0]
Function
BUCK2_VOLT_IDLE
-
Bit
Name
Initial
BUCK2 voltage when Power State = IDLE
0x00 = 0.70 V
0x04 = 0.74 V
0x08 = 0.78 V
0x01 = 0.71 V
0x05 = 0.75 V
0x09 = 0.79 V
0x02 = 0.72 V
0x06 = 0.76 V
0x03 = 0.73 V
0x07 = 0.77 V
0x0A= 0.80V(initial)
0x0B = 0.81 V
0x0F = 0.85 V
0x13 = 0.89 V
0x15 = 0.91 V
0x19 = 0.95 V
0x1D = 0.99 V
0x21 = 1.03 V
0x25 = 1.07 V
0x29 = 1.11 V
0x2D = 1.15 V
0x31 = 1.19 V
0x35 = 1.23 V
0x39 = 1.27 V
0x0C = 0.82 V
0x0D = 0.83 V
0x11 = 0.87 V
0x0E = 0.84 V
0x12 = 0.88 V
0x10 = 0.86 V
0x14 = 0.90 V
0x16 = 0.92 V
0x1A= 0.96 V
0x1E = 1.00 V
0x22 = 1.04 V
0x26 = 1.08 V
0x2A= 1.12 V
0x2E = 1.16 V
0x32 = 1.20 V
0x36 = 1.24 V
0x3A= 1.28 V
0x17 = 0.93 V
0x1B = 0.97 V
0x1F = 1.01 V
0x23 = 1.05 V
0x27 = 1.09 V
0x2B = 1.13 V
0x2F = 1.17 V
0x33 = 1.21 V
0x37 = 1.25 V
0x3B = 1.29 V
0x18 = 0.94 V
0x1C = 0.98 V
0x20 = 1.02 V
0x24 = 1.06 V
0x28 = 1.10 V
0x2C = 1.14 V
0x30 = 1.18 V
0x34 = 1.22 V
0x38 = 1.26 V
0x3C = 1.30 V
BUCK2_VOLT_IDLE[6:0]
0001010
D[6:0]
0x3D-0x7F = reserved
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5.2.3. BUCK5
5.2.3.1.
BUCK5 Block Diagram
VSYS
INT LDO1P5
BUCK5_VIN
OCP
OSC
VREF
DAC
Voltage setting
BUCK5_LX
Switch
Control
LBK 5
-
-
Soft Start
COBK5
+
PGND
(EXP-PAD)
EN
BUCK5_FB
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-3. BUCK5 Block Diagram
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5.2.3.2.
BUCK5 Electrical Characteristics
Table 5-12. BUCK5 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Limit
Typ
Parameter
Output Voltage
Symbol
VO_BK5
Unit
V
Condition
Min
Max
0.91
Vo = 0.9 V
0.89
0.90
Io = 200 mA, PWMfixMode
Programmable
Output Voltage Range
0.70 V, 0.80 V, 0.90 V, 1.00 V,
1.05 V, 1.10 V, 1.20 V, 1.35 V
Vo = 0.9 V
VORG_BK5
IQ_BK5
0.70
-
15
-
1.35
V
µA
mA
mA
%
Quiescent Current
-
-
Io = 0 mA, Auto mode
Maximum Output Current
Over Current Protection
IOMAX_BK5
IOCP_BK5
ΔVLDR_BK5
ηBK5_1mA
ηBK5_500mA
ηBK5_max
fSW_BK5
3000
-
Peak current of inductor(Note 1)
Io = 1 mAto Iomax, PWMfixMode
Io = 1 mA, Vo = 0.9 V
4500
-
-
DC Output Voltage Load Regulation
-1
-
0
+1
79
84
71
2
-
%
Efficiency
-
-
%
Io = 500 mA, Vo = 0.9 V
-
-
%
Io = Iomax, Vo = 0.9 V
Oscillating Frequency
Start up Time
-
-
MHz
µs
Ω
PWMfixmode, Io = 0 mA
During EN to 90 % of nominal Voltage
tST_BK5
-
162
100
80
500
Discharge Resistance
Low Side VR Fault Detect Level
RD_BK5
-
-
-
Vo = 0.9 V(FB = Sweep down)
VR fault detect level / Vo x100
DVRFBK5_L
-
%
(VR fault release level - detect level) / Vo x
100
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
DVRFBK5_LHYS
DVRBK5_H
-
-
-
10
130
20
-
-
-
%
%
%
Vo = 0.9 V(FB = Sweep up)
Power good detect level / Vo x100
(VR fault detect level - release level) / Vo x
100
High Side VR Fault Detect Hysteresis
DVRFBK5_HHYS
Output Inductance
Output Capacitance
LBK5
-
0.47
44
-
μH
μF
(Note 2)
(Note 2)
COBK5
22
100
Effective capacitance with BUCK's DC bias
(Note 1) For Buck- DCDC converters, (minimumOver Current Protection Current – ½ inductor ripple current) is the maximumoutput current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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5.2.3.3.
BUCK5 Control
Table 5-13. BUCK5_CTRL - BUCK5 Control Register
Register Name
BUCK5_CTRL
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x02
Address
0x09
BUCK5_PW
M_FIX
-
-
-
-
BUCK5_SEL BUCK5_EN
Bit
Name
Function
Initial
0
0 – AUTO PWM/PFMmode
VR adjusts the operating mode (PFM/PWM) automaticallybased on the load
current to maximize power efficiency.
D[3]
BUCK5_PWM_FIX
1 – Forced PWMMode
VR operates in PWMmode only.
BUCK5 control select bit
BUCK5_SEL
BUCK5_EN
0 = BUCK5 ON/OFF is controlled bystate machine.
1 = BUCK5 ON/OFF is controlled byD[0] on this register.
1
0
D[1]
D[0]
BUCK5 control bit with condition of D[1]
0 = BUCK5 OFF
1 = BUCK5 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
Table 5-14. BUCK5_VOLT - BUCK5 Voltage Register
Register Name
BUCK5_VOLT
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x02
Address
0x14
BUCK5_
-
-
-
BUCK5_VOLT[2:0]
VOLT_SEL[1:0]
Name
Bit
Function
Initial
Select the BUCK5 voltage range set byD[2:0].
00 = 0.70 Vto 1.35 V 01 = 0.55 Vto 0.90 V
BUCK5_VOLT_SEL[1:0]
00
D[7:6]
10 = 0.675 Vto 1.325 V 11 = reserved
BUCK5 voltage
If D[7:6]=00
000 = 0.70 V 001 = 0.80 V 010 = 0.90 V(Initial) 011 = 1.00 V
100 = 1.05 V 101 = 1.10 V 110 = 1.20 V
If D[7:6]=01
000 = 0.55 V 001 = 0.60 V 010 = 0.65 V 011 = 0.70 V
100 = 0.75 V 101 = 0.80 V 110 = 0.85 V 111 = 0.90 V
If D[7:6]=10
111 = 1.35 V
D[2:0]
BUCK5_VOLT[2:0]
010
000 = 0.675 V 001 = 0.775 V 010 = 0.875 V 011 = 0.975 V
100 = 1.025 V 101 = 1.075 V 110 = 1.175 V 111 = 1.325 V
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5.2.4. BUCK6
5.2.4.1.
BUCK6 Block Diagram
VSYS
INT LDO1P5
BUCK6_VIN
OCP
OSC
VREF
DAC
Voltage setting
BUCK6_LX
Switch
Control
LBK 6
-
-
Soft Start
COBK6
+
PGND
(EXP-PAD)
EN
BUCK6_FB
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-4. BUCK6 Block Diagram
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5.2.4.2.
BUCK6 Electrical Characteristics
Table 5-15. BUCK6 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Limit
Typ
Parameter
Output Voltage
Symbol
VO_BK6
Unit
V
Condition
Min
Max
Vo=3.3 V
3.267
3.300
3.333
Io = 200 mA, PWMfixMode
Programmable
Output Voltage Range
VORG_BK6
IQ_BK6
2.6
-
9
3.3
V
µA
mA
mA
%
100 mVstep
Vo=3.3 V
Io=0 mA, Auto mode
Quiescent Current
-
-
Maximum Output Current
Over Current Protection
IOMAX_BK6
IOCP_BK6
ΔVLDR_BK6
ηBK6_1mA
ηBK6_500mA
ηBK6_max
fSW_BK6
3000
-
-
Peak current of inductor(Note 1)
Io=1 mAto Iomax, PWMfixMode
Io = 1 mA, Vo=3.3 V
4500
-
-
DC Output Voltage Load Regulation
-1
-
0
+1
93
95
88
1.5
240
100
80
-
%
Efficiency
-
-
%
Io = 500 mA, Vo=3.3 V
-
-
%
Io = Iomax, Vo=3.3 V
Oscillating Frequency
Start up Time
-
-
MHz
µs
Ω
PWMfixmode, Io = 0 mA
During EN to 90% of nominal Voltage
tST_BK6
-
500
Discharge Resistance
Low Side VR Fault Detect Level
RD_BK6
-
-
-
Vo = 3.3 V(FB = Sweep down)
VR fault detect level / Vo x100
DVRFBK6_L
-
%
(VR fault release level - detect level) / Vo x
100
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
DVRFBK6_LHYS
DVRBK6_H
-
-
-
10
130
20
-
-
-
%
%
%
Vo = 3.3 V(FB = Sweep up)
Power good detect level / Vo x100
(VR fault detect level - release level) / Vo x
100
High Side VR Fault Detect Hysteresis
DVRFBK6_HHYS
Output Inductance
Output Capacitance
LBK6
-
1
-
μH
μF
(Note 2)
(Note 2)
COBK6
15.4
44
100
Effective capacitance with BUCK's DC bias
(Note 1) For Buck- DCDC converters, (minimumOver Current Protection Current – ½ inductor ripple current) is the maximumoutput current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
Headroom for BUCK6
BUCK6 can’t maintain output voltage when the input voltage close to output voltage. The headroom voltage is
determined by output current and the impedance from VSYS to BUCK6 output including the inductor parasitic
impedance (DCR). The PMIC internal impedance from BUCK6_VIN to BUCK6_LX is 121 mΩ at the worst case.
Please calculate total impedance using this value, and secure enough headroom for VSYS according to the output
current and voltage.
(Example – ROHM Evaluation Board case)
Vo = 3.3V setting: VO
VSYS to BUCK6_VIN impedance of the EVB = 3 mΩ: RVIN
BUCK6_LX to inductor impedance of the EVB = 6 mΩ: RLX
Inductor parasitic impedance (DCR) = 45 mΩ: RIND
PMIC internal impedance from BUCK6_VIN to BUCK6_LX = 121 mΩ: RPMIC
Total impedance = 175 mΩ: RTOTAL=RVIN+RLX+RIND+RPMIC
Headroom = RTOTAL x Output Current
Output current
1.0 A
Required minimum VSYS voltage
3.475 V
3.650 V
3.825 V
2.0 A
3.0 A
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5.2.4.3.
BUCK6 Control
Table 5-16. BUCK6_CTRL - BUCK6 Control Register
Register Name
BUCK6_CTRL
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x0A
BUCK6_PW
M_FIX
-
-
-
-
BUCK6_SEL BUCK6_EN
Bit
Name
Function
Initial
0
0 – AUTO PWM/PFMmode
VR adjusts the operating mode (PFM/PWM) automaticallybased on the load
current to maximize power efficiency.
D[3]
BUCK6_PWM_FIX
1 – Forced PWMMode
VR operates in PWMmode only.
BUCK6 control select bit
BUCK6_SEL
BUCK6_EN
0 = BUCK6 ON/OFF is controlled bystate machine.
1 = BUCK6 ON/OFF is controlled byD[0] on this register.
0
0
D[1]
D[0]
BUCK6 control bit with condition of D[1]
0 = BUCK6 OFF
1 = BUCK6 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
Table 5-17. BUCK6_VOLT - BUCK6 Voltage Register
Register Name
BUCK6_VOLT
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x03
Address
0x15
BUCK6_
VOLT_SEL
-
-
-
-
BUCK6_VOLT[1:0]
Bit
Name
Function
Initial
0
Select the BUCK6 voltage range set byD[6].
0 =3.0 Vto 3.3 V 1 = 2.6 Vto 2.9 V
D[6]
BUCK6_VOLT_SEL
BUCK6_VOLT[1:0]
Note: Changing BUCK6 voltage value is not allowed when BUCK6 is still ON.
In the case where this register value is changed, BUCK6 should be turned
OFF.
BUCK6 voltage
If D[6]=0
00 = 3.0 V 01 = 3.1 V 10 = 3.2 V 11 = 3.3 V(Initial)
If D[6]=1
00 = 2.6 V 01 = 2.7 V 10 = 2.8 V 11 = 2.9 V
11
D[1:0]
Note: Changing BUCK6 voltage value is not allowed when BUCK6 is still ON.
In the case where this register value is changed, BUCK6 should be turned
OFF.
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5.2.5. BUCK7
5.2.5.1.
BUCK7 Block Diagram
VSYS
INT LDO1P5
BUCK7_VIN
OCP
OSC
VREF
DAC
Voltage setting
BUCK7_LX
Switch
Control
LBK 7
-
-
Soft Start
COBK7
+
PGND
(EXP-PAD)
EN
BUCK7_FB
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-5. BUCK7 Block Diagram
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5.2.5.2.
BUCK7 Electrical Characteristics
Table 5-18. BUCK7 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Limit
Typ
Parameter
Output Voltage
Symbol
VO_BK7
Unit
V
Condition
Min
Max
Vo = 1.8 V
1.782
1.800
1.818
Io = 200 mA, PWMfixMode
Programmable
Output Voltage Range
1.605 V, 1.695 V, 1.755 V, 1.800 V,
1.845 V, 1.905 V, 1.950 V, 1.995 V
Vo = 1.8 V
VORG_BK7
IQ_BK7
1.605
-
15
-
1.995
V
µA
mA
mA
%
Quiescent Current
-
-
Io = 0 mA, Auto mode
Maximum Output Current
Over Current Protection
IOMAX_BK7
IOCP_BK7
ΔVLDR_BK7
ηBK7_1mA
ηBK7_500mA
ηBK7_max
fSW_BK7
1500
-
Peak current of inductor(Note 1)
Io = 1 mAto Iomax, PWMfixMode
Io = 1 mA, Vo=1.8 V
3000
-
-
DC Output Voltage Load Regulation
-1
-
0
+1
85
89
85
2
-
%
Efficiency
-
-
%
Io = 500 mA, Vo=1.8 V
-
-
%
Io = Iomax, Vo=1.8 V
Oscillating Frequency
Start up Time
-
-
MHz
µs
Ω
PWMfixmode, Io = 0 mA
During EN to 90 % of nominal Voltage
tST_BK7
-
220
100
80
500
Discharge Resistance
Low Side VR Fault Detect Level
RD_BK7
-
-
-
Vo = 1.8 V(FB = Sweep down)
VR fault detect level / Vo x100
DVRFBK7_L
-
%
(VR fault release level - detect level) / Vo x
100
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
DVRFBK7_LHYS
DVRBK7_H
-
-
-
10
130
20
-
-
-
%
%
%
Vo = 1.8 V(FB = Sweep up)
Power good detect level / Vo x100
(VR fault detect level - release level) / Vo x
100
High Side VR Fault Detect Hysteresis
DVRFBK7_HHYS
Output Inductance
Output Capacitance
LBK7
-
0.47
22
-
μH
μF
(Note 2)
(Note 2)
COBK7
11
100
Effective capacitance with BUCK's DC bias
(Note 1) For Buck- DCDC converters, (minimumOver Current Protection Current – ½ inductor ripple current) is the maximumoutput current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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5.2.5.3.
BUCK7 Control
Table 5-19. BUCK7_CTRL - BUCK7 Control Register
Register Name
BUCK7_CTRL
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x0B
BUCK7_PW
M_FIX
-
-
-
-
BUCK7_SEL BUCK7_EN
Bit
Name
Function
Initial
0
0 – AUTO PWM/PFMmode
VR adjusts the operating mode (PFM/PWM) automaticallybased on the load
current to maximize power efficiency.
D[3]
BUCK7_PWM_FIX
1 – Forced PWMMode
VR operates in PWMmode only.
BUCK7 control select bit
BUCK7_SEL
BUCK7_EN
0 = BUCK7 ON/OFF is controlled bystate machine.
1 = BUCK7 ON/OFF is controlled byD[0] on this register.
0
0
D[1]
D[0]
BUCK7 control bit with condition of D[1]
0 = BUCK7 OFF
1 = BUCK7 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
Table 5-20. BUCK7_VOLT - BUCK7 Voltage Register
Register Name
BUCK7_VOLT
R/W
R/W
D7
-
D6
-
D5
-
D4
-
D3
-
D2
D1
D0
Initial
0x03
Address
0x16
BUCK7_VOLT[2:0]
Bit
Name
Function
Initial
BUCK7 voltage
000 = 1.605 V
001 = 1.695 V
010 = 1.755 V
011 = 1.800 V(Initial)
100 = 1.845 V
BUCK7_VOLT[2:0]
101 = 1.905 V
011
D[2:0]
110 = 1.950 V
111 = 1.995 V
Note: Changing BUCK7 voltage value is not allowed when BUCK7 is still ON.
In the case where this register value is changed, BUCK7 should be turned
OFF.
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5.2.6. BUCK8
5.2.6.1.
BUCK8 Block Diagram
VSYS
INT LDO1P5
BUCK8_VIN
OCP
OSC
VREF
DAC
Voltage setting
BUCK8_LX
Switch
Control
LBK 8
-
-
Soft Start
COBK8
+
PGND
(EXP-PAD)
EN
BUCK8_FB
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-6. BUCK8 Block Diagram
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5.2.6.2.
BUCK8 Electrical Characteristics
Table 5-21. BUCK8 Electrical Characteristics
(Unless otherwise specified, Ta=+25 °C, VSYS=5.0 V)
Limit
Typ
Parameter
Output Voltage
Symbol
VO_BK8
Unit
V
Condition
Min
Max
Vo = 1.1 V
1.089
1.100
1.111
Io = 200 mA, PWMfixMode
Programmable
Output Voltage Range
VORG_BK8
IQ_BK8
0.8
-
15
-
1.4
V
µA
mA
mA
%
10 mVstep
Vo = 1.1 V
Io = 0 mA, Auto mode
Quiescent Current
-
-
Maximum Output Current
Over Current Protection
IOMAX_BK8
IOCP_BK8
ΔVLDR_BK8
ηBK8_1mA
ηBK8_500mA
ηBK8_max
fSW_BK8
3000
-
Peak current of inductor (note 1)
Io = 1 mAto Iomax, PWMfixMode
Io = 1 mA, Vo=1.1 V
4500
-
-
DC Output Voltage Load Regulation
-1
-
0
+1
82
86
75
2
-
%
Efficiency
-
-
%
Io = 500 mA, Vo=1.1 V
-
-
%
Io = Iomax, Vo=1.1 V
Oscillating Frequency
Start up Time
-
-
MHz
µs
Ω
PWMfixmode, Io = 0 mA
During EN to 90 % of nominal Voltage
tST_BK8
-
200
100
80
500
Discharge Resistance
Low Side VR Fault Detect Level
RD_BK8
-
-
-
Vo = 1.1 V(FB = Sweep down)
VR fault detect level / Vo x100
DVRFBK8_L
-
%
(VR fault release level - detect level) / Vo x
100
Low Side VR Fault Detect Hysteresis
High Side VR Fault Detect Level
DVRFBK8_LHYS
DVRBK8_H
-
-
-
10
130
20
-
-
-
%
%
%
Vo = 1.1 V(FB = Sweep up)
Power good detect level / Vo x100
(VR fault detect level - release level) / Vo x
100
High Side VR Fault Detect Hysteresis
DVRFBK8_HHYS
Output Inductance
Output Capacitance
LBK8
-
0.47
44
-
μH
μF
(Note 2)
(Note 2)
COBK8
22
100
Effective capacitance with BUCK's DC bias
(Note 1) For Buck- DCDC converters, (minimumOver Current Protection Current – ½ inductor ripple current) is the maximumoutput current.
(Note 2) This part value range need to be guaranteed over the operating surrounding temperature.
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5.2.6.3.
BUCK8 Control
Table 5-22. BUCK8_CTRL - BUCK8 Control Register
Register Name
BUCK8_CTRL
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x0C
BUCK8_PW
M_FIX
-
-
-
-
BUCK8_SEL BUCK8_EN
Bit
Name
Function
Initial
0
0 – AUTO PWM/PFMmode
VR adjusts the operating mode (PFM/PWM) automaticallybased on the load
current to maximize power efficiency.
D[3]
BUCK8_PWM_FIX
1 – Forced PWMMode
VR operates in PWMmode only.
BUCK8 control select bit
BUCK8_SEL
BUCK8_EN
0 = BUCK8 ON/OFF is controlled bystate machine.
1 = BUCK8 ON/OFF is controlled byD[0] on this register.
0
0
D[1]
D[0]
BUCK8 control bit with condition of D[1]
0 = BUCK8 OFF
1 = BUCK8 ON
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
Table 5-23. BUCK8_VOLT - BUCK8 Voltage Register
Register Name
BUCK8_VOLT
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
Initial
0x1E
Address
0x17
BUCK8_VOLT[6:0]
Bit
Name
Function
Initial
BUCK8 voltage
0x00 = 0.80 V
0x04 = 0.84 V
0x08 = 0.88 V
0x0C = 0.92 V
0x10 = 0.96 V
0x14 = 1.00 V
0x18 = 1.04 V
0x1C = 1.08 V
0x01 = 0.81 V
0x05 = 0.85 V
0x09 = 0.89 V
0x0D = 0.93 V
0x11 = 0.97 V
0x15 = 1.01 V
0x19 = 1.05 V
0x1D = 1.09 V
0x02 = 0.82 V
0x06 = 0.86 V
0x0A= 0.90 V
0x0E = 0.94 V
0x12 = 0.98 V
0x16 = 1.02 V
0x1A= 1.06 V
0x03 = 0.83 V
0x07 = 0.87 V
0x0B = 0.91 V
0x0F = 0.95 V
0x13 = 0.99 V
0x17 = 1.03 V
0x1B = 1.07 V
0x1E = 1.10 V(initial)
D[6:0]
BUCK8_VOLT[6:0]
0011110
0x1F = 1.11 V
0x23 = 1.15 V
0x27 = 1.19 V
0x2B = 1.23 V
0x2F = 1.27 V
0x33 = 1.31 V
0x37 = 1.35 V
0x3B = 1.39 V
0x20 = 1.12 V
0x21 = 1.13 V
0x25 = 1.17 V
0x29 = 1.21 V
0x2D = 1.25 V
0x31 = 1.29 V
0x35 = 1.33 V
0x39 = 1.37 V
0x22 = 1.14 V
0x26 = 1.18 V
0x2A= 1.22 V
0x2E = 1.26 V
0x32 = 1.30 V
0x36 = 1.34 V
0x3A= 1.38 V
0x24 = 1.16 V
0x28 = 1.20 V
0x2C = 1.24 V
0x30 = 1.28 V
0x34 = 1.32 V
0x38 = 1.36 V
0x3C = 1.40 V
0x3D-0x7F = reserved
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5.3. Details of LDO
5.3.1. LDO1
5.3.1.1.
LDO1 Block Diagram
OCP
VSYS
VSYS
VREF
DAC
Voltage setting
-
-
Soft Start
+
LDO1_VOUT
COLDO1
EN
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-7. LDO1 Block Diagram
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5.3.1.2.
LDO1 Electrical Characteristics
Table 5-24. LDO1 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 1.8 Vsetting)
Limit
Parameter
Output Voltage
Symbol
Unit
Condition
Min
Typ
Max
VO=1.8 Vsetting
Io=1 mA
VO_LDO1
VORG_LDO1_1
VORG_LDO1_2
IOMAX_LDO1
IOCP_LDO1
IQ_LDO1
1.782
1.800
1.818
V
Output Voltage Range 1
Output Voltage Range 2
Maximum Output Current
Over Current Protection
Quiescent Current
1.600
-
-
1.900
V
100 mVstep
100 mVstep
3.000
3.300
V
10
-
-
mA
mA
µA
mV
µs
20
-
-
-
6
-
-
Io=0 mA
Io = Iomax
Dropout Voltage
ΔVODP_LDO1
tST_LDO1
-
40
440
10
2
VSYS=3.2 V, VO=3.3 Vsetting
Io=0 mA,
During EN to 90 % of nominal Voltage
Start up Time
-
1000
20
5
DC Output Voltage Load Regulation
DC Output Voltage Line Regulation
Discharge Resistance
VR Fault Detect Level
ΔVLDR_LDO1
ΔVLNR_LDO1
RDIS_LDO1
DVRFLDO1
-
mV
mV
Ω
Io=1 mAto Iomax
-
VSYS = 4.5 Vto 5.5 V, Io=Iomax
-
100
80
200
-
Output = Sweep down
Power good detect level / Vo x100
-
%
(VR fault release level - detect level) / Vo x
100
VR Fault Detect Hysteresis
Ripple Rejection Ratio
Output Capacitance
DVRFLDO1_HYS
-
-
10
60
1.0
-
-
%
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hzto 20 kHz
RRLDO1
dB
μF
(Note 1)
COLDO1
0.5
5.0
Effective capacitance with LDO's DC bias
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.1.3.
LDO1 Control
Table 5-25. LDO1_VOLT - LDO1 Voltage Register
Register Name
LDO1_VOLT
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x22
Address
0x18
LDO1_VOL
T_SEL
R/W LDO1_SEL LDO1_EN
Name
-
-
-
LDO1_VOLT[1:0]
Bit
Function
Initial
0
LDO1 control select bit
LDO1_SEL
LDO1_EN
0 = LDO1 ON/OFF is controlled bystate machine.
1 = LDO1 ON/OFF is controlled byD[6] on this register.
D[7]
LDO1 control bit with condition of D[7]
0 = LDO1 OFF
1 = LDO1 ON
0
1
D[6]
D[5]
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
Select the LDO1 voltage range set byD[1:0].
0 = 3.0 Vto 3.3 V
1 = 1.6 Vto 1.9 V
LDO1_VOLT_SEL
Note: Changing LDO1 voltage value is not allowed when LDO1 is still ON.
In the case where this register value is changed, LDO1 should be turned OFF.
LDO1 voltage
If D[5]=0,
00 = 3.0 V
01 = 3.1 V
10 = 3.2 V
11 = 3.3 V
If D[5]=1,
00 = 1.6 V
01 = 1.7 V
10 = 1.8 V(Initial)
11 = 1.9 V
D[1:0]
LDO1_VOLT[1:0]
10
Note: Changing LDO1 voltage value is not allowed when LDO1 is still ON.
In the case where this register value is changed, LDO1 should be turned OFF.
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5.3.2. LDO2
5.3.2.1.
LDO2 Block Diagram
OCP
VSYS
VSYS
VREF
DAC
Voltage setting
-
-
Soft Start
+
LDO2_VOUT
COLDO2
EN
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-8. LDO2 Block Diagram
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5.3.2.2.
LDO2 Electrical Characteristics
Table 5-26. LDO2 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 0.8 Vsetting)
Limit
Parameter
Output Voltage
Symbol
VO_LDO2
Unit
V
Condition
Min
Typ
Max
VO=0.8 Vsetting
Io=1 mA
0.785
0.800
0.815
Output Voltage Range
Maximum Output Current
Over Current Protection
Quiescent Current
VORG_LDO2
IOMAX_LDO2
IOCP_LDO2
IQ_LDO2
0.800
-
-
0.900
V
100 mVstep
10
-
mA
mA
µA
µs
20
-
-
-
-
6
Io = 0 mA
Io = 0 mA,
Start up Time
tST_LDO2
-
370
10
2
1000
20
5
During EN to 90 % of nominal Voltage
DC Output Voltage Load Regulation
DC Output Voltage Line Regulation
Discharge Resistance
VR Fault Detect Level
ΔVLDR_LDO2
ΔVLNR_LDO2
RDIS_LDO2
DVRFLDO2
-
mV
mV
Ω
Io = 1 mAto Iomax
-
VSYS = 4.5 Vto 5.5 V, Io = Iomax
-
100
80
200
-
Output = Sweep down
Power good detect level / Vo x100
-
%
(VR fault release level - detect level) / Vo x
100
VR Fault Detect Hysteresis
Ripple Rejection Ratio
Output Capacitance
DVRFLDO2_HYS
-
-
10
60
1.0
-
-
%
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hzto 20 kHz
RRLDO2
dB
μF
(Note 1)
COLDO2
0.5
5.0
Effective capacitance with LDO's DC bias
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
5.3.2.3.
LDO2 Control
Table 5-27. LDO2_VOLT - LDO2 Voltage Register
Register Name
LDO2_VOLT
R/W
D7
D6
D5
D4
D3
D2
D1
-
D0
-
Initial
0x20
Address
0x19
LDO2_VOL
T_SEL
R/W LDO2_SEL LDO2_EN
-
-
-
Bit
Name
Function
Initial
0
LDO2 control select bit
LDO2_SEL
LDO2_EN
0 = LDO2 ON/OFF is controlled bystate machine.
1 = LDO2 ON/OFF is controlled byD[6] on this register.
D[7]
LDO2 control bit with condition of D[7]
0 = LDO2 OFF
1 = LDO2 ON
0
1
D[6]
D[5]
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
Select the LDO2 voltage.
0 = 0.9V
1 = 0.8V(initial)
LDO2_VOLT_SEL
Note: Changing LDO2 voltage value is not allowed when LDO2 is still ON.
In the case where this register value is changed, LDO2 should be turned OFF.
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5.3.3. LDO3
5.3.3.1.
LDO3 Block Diagram
Note : Thesourceof LDO3 is VSYS whenBUCK6 is OFF.
Thesourceof LDO3 is VIN_3P3 when BUCK6 is ON.
Thechangingof the source is automatic.
VSYS
OCP
VSYS
BUCK6
VREF
VIN_3P3
DAC
Voltage setting
-
-
Soft Start
+
LDO3_VOUT
COLDO3
EN
Discharge
Resistor
EN
VR Controller
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-9. LDO3 Block Diagram
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5.3.3.2.
LDO3 Electrical Characteristics
Table 5-28. LDO3 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 1.8 Vsetting)
Limit
Parameter
Output Voltage
Symbol
VO_LDO3
Unit
V
Condition
Min
Typ
Max
VO=1.8 Vsetting
Io=1 mA
1.782
1.800
1.818
Output Voltage Range
Maximum Output Current
Over Current Protection
Quiescent Current
VORG_LDO3
IOMAX_LDO3
IOCP_LDO3
IQ_LDO3
1.800
-
-
3.300
V
100 mVstep
300
-
mA
mA
µA
mV
µs
390
-
-
-
-
-
-
-
-
-
9
-
-
Io = 0 mA
Io = Iomax
Dropout Voltage
ΔVODP_LDO3
tST_LDO3
450
310
10
2
VIN_3P3 = 1.7 V, VO = 1.8Vsetting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Start up Time
1000
20
5
DC Output Voltage Load Regulation
DC Output Voltage Line Regulation
Discharge Resistance
VR Fault Detect Level
ΔVLDR_LDO3
ΔVLNR_LDO3
RDIS_LDO3
DVRFLDO3
mV
mV
Ω
Io = 1 mAto Iomax
VSYS = 4.5 Vto 5.5 V, Io = 50 mA
100
80
200
-
Output = Sweep down
Power good detect level / Vo x100
%
(VR fault release level - detect level) / Vo x
100
VR Fault Detect Hysteresis
Ripple Rejection Ratio
Output Capacitance
DVRFLDO3_HYS
-
-
10
60
2.2
-
-
%
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hzto 20 kHz
RRLDO3
dB
μF
(Note 1)
COLDO3
1.1
22.0
Effective capacitance with LDO's DC bias
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.3.3.
LDO3 Control
Table 5-29. LDO3_VOLT - LDO3 Voltage Register
Register Name
LDO3_VOLT
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x00
Address
0x1A
R/W LDO3_SEL LDO3_EN
Name
-
-
LDO3_VOLT[3:0]
Bit
Function
Initial
0
LDO3 control select bit
LDO3_SEL
LDO3_EN
0 = LDO3 ON/OFF is controlled bystate machine.
1 = LDO3 ON/OFF is controlled byD[6] on this register.
D[7]
LDO3 control bit with condition of D[7]
0 = LDO3 OFF
1 = LDO3 ON
0
D[6]
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
LDO3 voltage
0x0 = 1.8 V(Initial)
0x1 = 1.9 V
0x2 = 2.0 V
0x3 = 2.1 V
0x4 = 2.2 V
0x5 = 2.3 V
0x6 = 2.4 V
0x7 = 2.5 V
0x8 = 2.6 V
0x9 = 2.7 V
0xA= 2.8 V
0xB = 2.9 V
0xC = 3.0 V
0xD = 3.1 V
0xE = 3.2 V
0xF = 3.3 V
LDO3_VOLT[3:0]
0000
D[3:0]
Note: Changing LDO3 voltage value is not allowed when LDO3 is still ON.
In the case where this register value is changed, LDO3 should be turned OFF.
It is recommended that the VIN_3P3 pin is connected to BUCK6. LDO3 power source is switched from the
VSYS pin to the VIN_3P3 pin after BUCK6 is turned on. On the other hand, LDO3 power source is switched
from the VIN_3P3 pin to the VSYS pin when BUCK6 is turned off. It takes 3 ms to complete this switching
operation. Therefore, actual BUCK6 turn-off is delayed as shown in Figure 5-10.
BUCK6_SEL
3 ms
BUCK6_EN
Low
BUCK6
0V
LDO3 Source
BUCK6
VSYS
Figure 5-10. LDO3 Voltage Source Switching
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5.3.4. LDO4
5.3.4.1.
LDO4 Block Diagram
Note : Thesourceof LDO4 is VSYS whenBUCK7 is OFF.
Thesourceof LDO4 is VIN_1P8_1 when BUCK7 is ON.
Thechangingof the source is automatic.
VSYS
OCP
VSYS
BUCK7
VREF
VIN_1P8_1
DAC
Voltage setting
-
-
Soft Start
+
LDO4_VOUT
COLDO4
EN
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-11. LDO4 Block Diagram
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5.3.4.2.
LDO4 Electrical Characteristics
Table 5-30. LDO4 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 0.9 Vsetting)
Limit
Parameter
Output Voltage
Symbol
VO_LDO4
Unit
V
Condition
Min
Typ
Max
VO=0.9 Vsetting
Io=1 mA
0.885
0.900
0.915
Output Voltage Range
Maximum Output Current
Over Current Protection
Quiescent Current
VORG_LDO4
IOMAX_LDO4
IOCP_LDO4
IQ_LDO4
0.900
-
-
1.800
V
100 mVstep
250
-
mA
mA
µA
mV
µs
325
-
-
-
-
-
-
-
-
-
9
-
-
Io = 0 mA
Io = Iomax
Dropout Voltage
ΔVODP_LDO4
tST_LDO4
450
400
10
2
VIN_V1P8_1 = 1.7 V, VO = 1.8 Vsetting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Start up Time
1000
20
5
DC Output Voltage Load Regulation
DC Output Voltage Line Regulation
Discharge Resistance
VR Fault Detect Level
ΔVLDR_LDO4
ΔVLNR_LDO4
RDIS_LDO4
DVRFLDO4
mV
mV
Ω
Io = 1 mAto Iomax
VSYS = 4.5 Vto 5.5 V, Io = 50 mA
100
80
200
-
Output = Sweep down
Power good detect level / Vo x100
%
(VR fault release level - detect level) / Vo x
100
VR Fault Detect Hysteresis
Ripple Rejection Ratio
Output Capacitance
DVRFLDO4_HYS
-
-
10
60
2.2
-
-
%
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hzto 20 kHz
RRLDO4
dB
μF
(Note 1)
COLDO4
1.1
22.0
Effective capacitance with LDO's DC bias
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.4.3.
LDO4 Control
Table 5-31. LDO4_VOLT - LDO4 Voltage Register
Register Name
LDO4_VOLT
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x80
Address
0x1B
R/W LDO4_SEL LDO4_EN
-
-
LDO4_VOLT[3:0]
Bit
Name
Function
Initial
1
LDO4 control select bit
LDO4_SEL
0 = LDO4 ON/OFF is controlled bystate machine.
D[7]
1 = LDO4 ON/OFF is controlled byD[6] on this register.
LDO4 control bit with condition of D[7]
0 = LDO4 OFF
LDO4_EN
1 = LDO4 ON
0
D[6]
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
LDO4 voltage
0x0 = 0.9 V(Initial)
0x1 = 1.0 V
0x2 = 1.1 V
0x3 = 1.2 V
0x4 = 1.3 V
0x5 = 1.4 V
0x6 = 1.5 V
0x7 = 1.6 V
0x8 = 1.7 V
0x9 = 1.8 V
0xA= 1.8 V
0xB = 1.8 V
0xC = 1.8 V
0xD= 1.8 V
0xE = 1.8 V
0xF = 1.8 V
LDO4_VOLT[3:0]
0000
D[3:0]
Note: Changing LDO4 voltage value is not allowed when LDO4 is still ON.
In the case where this register value is changed, LDO4 should be turned OFF.
It is recommended that the VIN_1P8_1 pin is connected to BUCK7. LDO4 power source is switched from
the VSYS pin to the VIN_1P8_1 pin after BUCK7 is turned on. On the other hand, LDO4 power source is
switched from the VIN_1P8_1 pin to the VSYS pin when BUCK7 is turned off. It takes 3 ms to complete this
switching operation. Therefore, actual BUCK7 turn-off is delayed as shown in Figure 5-12.
BUCK7_SEL
3 ms
BUCK7_EN
Low
BUCK7
0V
LDO4 Source
BUCK7
VSYS
Figure 5-12. LDO4 Voltage Source Switching
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5.3.5. LDO5
5.3.5.1.
LDO5 Block Diagram
OCP
VSYS
VSYS
VREF
DAC
Voltage setting
-
-
Soft Start
+
LDO5_VOUT
COLDO5
EN
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-13. LDO5 Block Diagram
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5.3.5.2.
LDO5 Electrical Characteristics
Table 5-32. LDO5 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 3.3 Vsetting)
Limit
Parameter
Output Voltage
Symbol
VO_LDO5
Unit
V
Condition
Min
Typ
Max
VO=3.3 Vsetting
Io=1 mA
3.267
3.300
3.333
Output Voltage Range
Maximum Output Current
Over Current Protection
Quiescent Current
VORG_LDO5
IOMAX_LDO5
IOCP_LDO5
IQ_LDO5
0.800
-
-
3.300
V
100 mVstep
300
-
mA
mA
µA
mV
µs
340
-
-
-
-
-
-
-
-
-
9
-
-
Io = 0 mA
Io = Iomax
Dropout Voltage
ΔVODP_LDO5
tST_LDO5
250
530
10
2
VSYS = 3.2 V, VO = 3.3 Vsetting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Start up Time
1000
20
5
DC Output Voltage Load Regulation
DC Output Voltage Line Regulation
Discharge Resistance
VR Fault Detect Level
ΔVLDR_LDO5
ΔVLNR_LDO5
RDIS_LDO5
DVRFLDO5
mV
mV
Ω
Io = 1 mAto Iomax
VSYS = 4.5 Vto 5.5 V, Io = 50 mA
100
80
200
-
Output = Sweep down
Power good detect level / Vo x100
%
(VR fault release level - detect level) / Vo x
100
VR Fault Detect Hysteresis
Ripple Rejection Ratio
Output Capacitance
DVRFLDO5_HYS
-
-
10
60
2.2
-
-
%
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hzto 20 kHz
RRLDO5
dB
μF
(Note 1)
COLDO5
1.1
22.0
Effective capacitance with LDO's DC bias
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.5.3.
LDO5 Control
Table 5-33. LDO5_VOLT - LDO5 Voltage Register
Register Name
LDO5_VOLT
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x8F
Address
0x1C
LDO5_VOL
T_SEL
R/W LDO5_SEL LDO5_EN
Name
-
LDO5_VOLT[3:0]
Bit
Function
Initial
1
LDO5 control select bit
D[7]
LDO5_SEL
0 = LDO5 ON/OFF is controlled bystate machine.
1 = LDO5 ON/OFF is controlled byD[6] on this register.
LDO5 control bit with condition of D[7]
0 = LDO5 OFF
D[6]
D[5]
LDO5_EN
1 = LDO5 ON
0
0
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
Select the LDO5 voltage range set byD[1:0].
0 = 1.8 Vto 3.3 V
1 = 0.8 Vto 2.3 V
LDO5_VOLT_SEL
Note: Changing LDO5 voltage value is not allowed when LDO5 is still ON.
In the case where this register value is changed, LDO5 should be turned OFF.
LDO5 voltage
if D[5]=0,
0x0 = 1.8 V 0x1 = 1.9 V 0x2 = 2.0 V 0x3 = 2.1 V
0x4 = 2.2 V 0x5 = 2.3 V 0x6 = 2.4 V 0x7 = 2.5 V
0x8 = 2.6 V 0x9 = 2.7 V 0xA= 2.8 V 0xB = 2.9 V
0xC = 3.0 V 0xD= 3.1 V 0xE = 3.2 V 0xF = 3.3 V(initial)
D[3:0]
LDO5_VOLT[3:0]
if D[5]=1,
1111
0x0 = 0.8 V 0x1 = 0.9 V 0x2 = 1.0 V 0x3 = 1.1 V
0x4 = 1.2 V 0x5 = 1.3 V 0x6 = 1.4 V 0x7 = 1.5 V
0x8 = 1.6 V 0x9 = 1.7 V 0xA= 1.8 V 0xB = 1.9 V
0xC = 2.0 V 0xD= 2.1 V 0xE = 2.2 V 0xF = 2.3 V
Note: Changing LDO5 voltage value is not allowed when LDO5 is still ON.
In the case where this register value is changed, LDO5 should be turned OFF.
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5.3.6. LDO6
5.3.6.1.
LDO6 Block Diagram
OCP
BUCK7(1.8V)
VIN_1P8_1
VREF
DAC
Voltage setting
-
-
Soft Start
+
LDO6_VOUT
COLDO6
EN
Discharge
Resistor
VR Controller
EN
GND
PGND
(EXP-PAD)
VR Fault
Detector
VR Fault Signal
Figure 5-14. LDO6 Block Diagram
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5.3.6.2.
LDO6 Electrical Characteristics
Table 5-34. LDO6 Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_1 = 1.8 V, Vo = 1.2 Vsetting)
Limit
Parameter
Output Voltage
Symbol
VO_LDO6
Unit
V
Condition
Min
Typ
Max
VO=1.2 Vsetting
Io=1 mA
1.185
1.200
1.215
Output Voltage Range
Maximum Output Current
Over Current Protection
Quiescent Current
VORG_LDO6
IOMAX_LDO6
IOCP_LDO6
IQ_LDO6
0.900
-
-
1.800
V
100 mVstep
300
-
mA
mA
µA
mV
µs
340
-
-
-
-
-
-
-
-
-
9
-
-
Io = 0 mA
Io = Iomax
Dropout Voltage
ΔVODP_LDO6
tST_LDO6
450
400
10
2
VIN_V1P8_1 = 1.7 V, VO = 1.8 Vsetting
Io = 0 mA,
During EN to 90 % of nominal Voltage
Start up Time
1000
20
5
DC Output Voltage Load Regulation
DC Output Voltage Line Regulation
Discharge Resistance
VR Fault Detect Level
ΔVLDR_LDO6
ΔVLNR_LDO6
RDIS_LDO6
DVRFLDO6
mV
mV
Ω
Io = 1 mAto Iomax
VSYS = 4.5 Vto 5.5 V, Io = 50 mA
100
80
200
-
Output = Sweep down
Power good detect level / Vo x100
%
(VR fault release level - detect level) / Vo x
100
VR Fault Detect Hysteresis
Ripple Rejection Ratio
Output Capacitance
DVRFLDO6_HYS
-
-
10
60
2.2
-
-
%
VSYS = 5.0 V, IO=Iomax/2
VR = -20 dBV, fR=100 Hz
BW=20 Hzto 20 kHz
RRLDO6
dB
μF
(Note 1)
COLDO6
1.1
22.0
Effective capacitance with LDO's DC bias
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
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5.3.6.3.
LDO6 Control
Table 5-35. LDO6_VOLT - LDO6 Voltage Register
Register Name
LDO6_VOLT
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x03
Address
0x1D
R/W LDO6_SEL LDO6_EN
Name
-
-
LDO6_VOLT[3:0]
Bit
Function
Initial
0
LDO6 control select bit
D[7]
LDO6_SEL
0 = LDO6 ON/OFF is controlled bystate machine.
1 = LDO6 ON/OFF is controlled byD[6] on this register.
LDO6 control bit with condition of D[7]
0 = LDO6 OFF
D[6]
LDO6_EN
1 = LDO6 ON
0
This bit returns to 0 at the beginning of PWROFF sequence or emergency
shutdown.
LDO6 voltage
0x0 = 0.9 V
0x1 = 1.0 V
0x2 = 1.1 V
0x3 = 1.2 V(initial)
0x4 = 1.3 V
0x5 = 1.4 V
0x6 = 1.5 V
0x7 = 1.6 V
0x8 = 1.7 V
0x9 = 1.8 V
0xA= 1.8 V
0xB = 1.8 V
0xC = 1.8 V
0xD= 1.8 V
0xE = 1.8 V
0xF = 1.8 V
LDO6_VOLT[3:0]
0011
D[3:0]
Note: Changing LDO6 voltage value is not allowed when LDO6 is still ON.
In the case where this register value is changed, LDO6 should be turned OFF.
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5.4. MUXSW
MUX Switch is for SD card power.
5.4.1. MUXSW Block Diagram
BUCK7
VIN_1P8_2
BUCK6
DVDD
VIN_3P3
SD_VSELECT
MUXSW_VOUT
MUX
Switch
Controller
COMUXSW
MUXSW_EN
DISCHARGE
RESISTOR
PGND
(EXP-PAD)
Figure 5-15. MUXSW Block Diagram
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5.4.2. MUXSW Electrical Characteristics
Table 5-36. MUXSW Electrical Characteristics
(Unless otherwise specified, Ta = +25 °C, VSYS = 5.0 V, VIN_3P3 = 3.3 V, VIN_1P8_2 = 1.8 V, Vo = 3.3 Vsetting)
Limit
Parameter
Symbol
Unit
V
Condition
Min
-
Typ
Max
-
VIN_3P3 Input Voltage
V
IN_3P3
3.300
Switch ON Resistance(3.3 Vmode)
VIN_1P8_2 Input Voltage
RON_3P3
-
-
500
-
mΩ
V
SD_VSELECT=0 V, VIN_3P3>3.2 V
V
IN_1P8
-
1.800
Switch ON Resistance(1.8 Vmode)
Maximum Output Current
RON_1P8
IOMAX_MUX
RDIS_MUX
-
150
-
-
-
500
-
mΩ
mA
Ω
SD_VSELECT=DVDD, VIN_1P8_2>1.7 V
VIN_1P8_2=0 V, VIN_3P3=0 V, IO=-10 mA
Discharge Resistance
30
50
(Note 1)
Output Capacitance
CO_MUX
11
22
33
μF
Effective capacitance with Output voltage
(Note 1) This part value range need to be guaranteed over the operating surrounding temperature.
Table 5-37. SD_VSELECT Electrical Characteristics
(Unless otherwise specified, Ta=25°C, DVDD=1.8 V)
Limit
Typ
Parameter
Input "H" Level
Input "L" Level
Symbol
Unit
Condition
Min
Max
-
DVDD
x0.75
V
IHSDV
-
-
V
V
DVDD
x0.25
V
ILSDV
-
t1
t2
SD_VSELECT
tf
tr
3.30 V
3.15 V
3.30 V
MUXSW_VOUT
1.89 V
1.80 V
Figure 5-16. MUXSW Sequence
Table 5-38. MUXSW Sequence Timing
Symbol
Description
SD_VSELCT High Time(Note 1)
SD_VSELCT Low Time(Note 1)
Min
2
Typ
Max
Unit
ms
ms
ms
ms
t1
t2
tf
-
-
-
-
2
Transition Time 3.3 Vto 1.8 V
1
1
-
-
-
-
tr
Transition Time 1.8 Vto 3.3 V
(Note 1) t1 and t2 need over 2ms.
Table 5-39. MUXSW_EN - MUXSW Enable Register
Register Name
MUXSW_EN
R/W
R/W
D7
-
D6
D5
D4
D3
D2
D1
D0
MUXSW_EN
Initial
0x01
Address
0x30
-
-
-
-
-
-
Bit
Name
Function
Initial
1
MUXSW control bit
0 = MUXSW OFF
1 = MUXSW ON
D[0]
MUXSW_EN
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6. 32.768 kHz Crystal Oscillator Driver
6.1. 32.768 kHz Crystal Oscillator Driver Block Diagram
INTLDO1P5
VDD_V1P5
VDD_V1P5
XOUT
32.768kHz
Crystal
CONTROLLER
Counter
XIN
Oscillator Driver
VDD_V1P5
DVDD
M
U
C32K_OUT
1/375
X
OUT32K_EN
divider
12MHz
Figure 6-1. 32.768 kHz Crystal Oscillator Driver Block Diagram
Table 6-1. C32K_OUT Control Register
Register Name
OUT32K
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Initial
0x01
Address
0x2E
-
-
-
-
-
-
-
OUT32K_EN
Bit
Name
OUT32K_EN
Function
Initial
1
0 = Disable (C32K_OUT is Low level)
1 = Enable
D[0]
At the beginning of power-on, the C32K_OUT pin output clock is generated from the 12 MHz internal oscillator; the clock
frequency is equal to 12 MHz / 375.
If an external 32.768 kHz crystal is present, the C32K_OUT pin output clock’s clock source is switched from the internal
oscillator to the crystal clock after 3000 crystal clock cycles, i.e., it is assumed that the crystal clock is stable by then.
6.2. 32.768 kHz Crystal Oscillator Driver Electrical Characteristics
Table 6-2. 32.768 kHz Crystal Oscillator Driver Electrical Characteristics
(Unless otherwise specified, Ta = +25°C, VSYS = 5.0 V, DVDD = 1.8 V)
Limit
Parameter
Output Frequency
Symbol
fRTCLK
Unit
kHz
Condition
With external crystal
Min
-
Typ
Max
-
32.768
Output DutyCycle
DRTCLK
VOH32K
VOL32K
40
50
-
60
-
%
V
DVDD
x0.8
Output H Level Voltage
IOH = -1 mA
IOL = 1 mA
Output L Level Voltage
-
-
0.4
V
(Note) The following 32.768 kHz crystal is recommended.
ST3215SB32768H5HPWAA (KYOCERA: CL=12.5pF)
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7. Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
6.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
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7.
Operational Notes – continued
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 7-1. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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BD71850MWV
8. Ordering Information
B D 7 1 8 5 0 M W V -
E2
Part Number
Package
Packaging and forming specification
MWV: UQFN56BV7070 E2: Embossed tape and reel
9. Marking Diagram
UQFN56BV7070 (TOP VIEW)
Part Number Marking
ROHM
LOT Number
BD71 850
Pin 1 Mark
Figure 9-1. Marking Diagram
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10. Physical Dimension and Packing Information
Package Name
UQFN56BV7070
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11. Revision History
Revision
Number
Date
Description
27.Sep.2019
16.Mar.2020
001
002
First Release
p.1,18 Changed maximum operating temperature to 105 °C.
p.73,77,81,84,87,90,93,96,98,101,104,107,110
Deleted temperature condition of parts. Added note about parts
temperature.
www.rohm.com
TSZ02201-0Q2Q0A500680-1-2
16.Mar.2020 Rev.002
© 2019 ROHM Co., Ltd. All rights reserved.
116/116
TSZ22111 • 15 • 001
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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