BD8LD650EFV-C (新产品) [ROHM]
BD8LD650EFV-C是一款适用于车载和工业设备的SPI输入8通道低边开关。该产品内置负载开路检测功能、输出接地故障检测功能、过电流保护功能、过热保护功能、有源钳位功能。;
| 型号： | BD8LD650EFV-C (新产品) |
| 厂家： | 
ROHM |
| 描述： | BD8LD650EFV-C是一款适用于车载和工业设备的SPI输入8通道低边开关。该产品内置负载开路检测功能、输出接地故障检测功能、过电流保护功能、过热保护功能、有源钳位功能。 开关 过电流保护 |
| 文件： | 总51页 (文件大小：1946K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Automotive IPD Series
8ch Low Side Switch
BD8LD650EFV-C
General Description
Key Specifications
BD8LD650EFV-C is an 8-channel SPI-input low side
switch for automotive and industrial application. It has
built-in open load detection function, short ground
detection function, over current protection function,
thermal shutdown function, and active clamp function.
◼ Input Voltage Range VDD:
◼ Input Voltage Range VDDIO:
◼ On State Resistance:
◼ Over Current Threshold Value:
◼ Active Clamp Energy:
4.0 V to 5.5 V
3.0 V to 5.5 V
650 mΩ (Typ)
0.5 A/1.0 A (Min)
125 mJ
◼ Operating Temperature Range Tj:-40 °C to +150 °C
Features
◼ AEC-Q100 Qualified(Note 1)
Package
W (Typ) x D (Typ) x H (Max)
6.5 mm x 6.4 mm x 1.0 mm
◼ Monolithic Power Management IC with Control Block
(CMOS) and a Power MOSFET Mounted on a Single
Chip
HTSSOP-B20
◼ Channel Control/error can be Detected by 16 bit SPI
Commands.
◼ Built-in Open Load Detection Function (OLD)
◼ Built-in Short Ground Detection Function (SGD)
◼ Built-in Over Current Protection Function (OCP)
◼ Built-in Thermal Shutdown Function(TSD)
◼ Built-in Active Clamp Function
◼ Built-in Synchro Mode
◼ Built-in Limp Home Mode
◼ Surface-mount HTSSOP-B20 Packaging
(Note 1) Grade1
HTSSOP-B20
Application
◼ Driving Resistive and Inductive Load
Typical Application Circuit
VDDIO
VDD
VBAT
CVDDIO
CVDD
VDDIO
VDD
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
I/O
Control Logic
RIDLE
RIN21
RIN43
RIN65
IDLE
IN21
IN43
IN65
UVLO
I/O
(IDLE, IN,
Limp Home)
Mode
Control
Control,
Diagnostic
and
protective
Functions
Limp
Home
OCP
TSD
MCU
Input
Register
RCSB
RSCLK
RSI
CSB
SCLK
SI
UVLO
OLD
OFD
SGD
SPI
Control
Active
Clamp
I/O
(SPI)
Gate
Driver
Diagnosis
Register
RSO
SO
COUT1 COUT2
COUT3
COUT4
COUT5
COUT6
COUT7
COUT8
GND
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
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BD8LD650EFV-C
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Application ......................................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Typical Application Circuit ...............................................................................................................................................................1
Contents .........................................................................................................................................................................................2
Pin Configuration ............................................................................................................................................................................3
Pin Descriptions..............................................................................................................................................................................3
Definition.........................................................................................................................................................................................4
Block Diagram ................................................................................................................................................................................4
Absolute Maximum Ratings ............................................................................................................................................................5
Thermal Resistance........................................................................................................................................................................6
Recommended Operating Conditions...........................................................................................................................................10
Electrical Characteristics...............................................................................................................................................................10
Typical Performance Curves.........................................................................................................................................................12
Measurement Circuit.....................................................................................................................................................................23
Timing Chart .................................................................................................................................................................................25
Synchro Mode...............................................................................................................................................................................27
Limp Home Mode .........................................................................................................................................................................28
SPI Specification...........................................................................................................................................................................29
Register Map ................................................................................................................................................................................33
Over Current Protection Function .................................................................................................................................................35
Thermal Shutdown Function.........................................................................................................................................................36
Open Load Detection (OLD) .........................................................................................................................................................37
Output Overhead Fault Detection Function (OFD)........................................................................................................................38
Short Ground Detection (SGD).....................................................................................................................................................39
Application Example .....................................................................................................................................................................41
Selection of Components Externally Connected...........................................................................................................................41
I/O Equivalence Circuits................................................................................................................................................................42
Operational Notes.........................................................................................................................................................................43
Ordering Information.....................................................................................................................................................................46
Marking Diagram ..........................................................................................................................................................................46
Physical Dimension and Packing Information...............................................................................................................................47
Revision History............................................................................................................................................................................48
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BD8LD650EFV-C
Pin Configuration
(TOP VIEW)
1
20
19
18
17
16
15
14
13
12
11
IDLE
CSB
VDDIO
VDD
2
3
SCLK
SI
IN21
4
IN43
5
SO
IN65
EXP-PAD
6
GND
OUT1
OUT2
OUT5
OUT6
GND
7
OUT3
OUT4
OUT7
OUT8
8
9
10
Pin Descriptions
Pin No.
Pin Name
IDLE
Function
Limp home mode control
1
2
3
4
This pin is connected to GND via an internal pull-down resistor.
SPI enable
CSB
SCLK
SI
This pin is connected to VDDIO via an internal pull-up resistor.
Serial clock input
This pin is connected to GND via an internal pull-down resistor.
Serial data input
This pin is connected to GND via an internal pull-down resistor.
5
6
SO
Serial data output
GND
GND
7
OUT1
OUT2
OUT5
OUT6
OUT8
OUT7
OUT4
OUT3
GND
ch1 output
ch2 output
ch5 output
ch6 output
ch8 output
ch7 output
ch4 output
ch3 output
GND
8
9
10
11
12
13
14
15
ch5, ch6 control(Note 1)
16
17
18
IN65
IN43
IN21
This pin is connected to GND via an internal pull-down resistor.
ch3, ch4 control(Note 1)
This pin is connected to GND via an internal pull-down resistor.
ch1, ch2 control(Note 1)
This pin is connected to GND via an internal pull-down resistor.
19
20
-
VDD
Analog power supply
VDDIO
Digital power supply
EXP-PAD
Be sure to connect EXP-PAD to GND.
(Note 1) Controlled channels can be changed by accessing DIRCTRL register from the SPI.
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BD8LD650EFV-C
Definition
IVDDIO
IVDD
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
IOUT6
IOUT7
VDDIO
VDD
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
VDDIO
VOUT1
VDD
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
IIDLE
ICSB
ISCLK
ISI
IDLE
CSB
SCLK
SI
VIDLE
VCSB
VSCLK
VSI
ISO
SO
VOUT7
VSO
IOUT8
IIN21
IIN43
IIN65
VOUT8
IN21
IN43
IN65
VIN21
VIN43
VIN65
GND
Block Diagram
VDDIO
VDD
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
I/O
Control Logic
IN21
IN43
UVLO
I/O
(IDLE, IN,
IN65
IDLE
Mode
Control
Limp Home)
Control,
Diagnostic
and
protective
Functions
Limp
Home
OCD
Input
Register
TSD
OLD
UVLO
CSB
SCLK
SI
SPI
Control
Active
Clamp
I/O
(SPI)
Gate
Driver
Diagnosis
Register
SO
GND
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BD8LD650EFV-C
Absolute Maximum Ratings (Tj = 25 °C)
Parameter
Symbol
Rating
Unit
VDDIO, VDD Power Supply Voltage
Output Voltage (Power MOS Output)
Output Current (Power MOS Output)
Output Voltage (SPI)
VDDIO, VDD
VOUT1-8
-0.3 to +7
-0.3 to (Internal Limit)(Note 1)
(Internal Limit)(Note 2)
-0.3 to +7
V
V
IOUT1-8
A
VSO
V
Input Voltage (IDLE)
VIDLE
-0.3 to +7
V
Input Voltage (SPI)
VCSB, VSCLK, VSI
VIN65, VIN43, VIN21
Tstg
-0.3 to +7
V
Input Voltage (IN65, IN43, IN21)
Storage Temperature Range
Maximum Junction Temperature
-0.3 to +7
V
-55 to +150
°C
°C
Tjmax
150
Active Clamp Energy (Single Pulse)
EAS1-8(25 °C)
EAS1-8(150 °C)
ES, AS1-8(25 °C)
ES, AS1-8(150 °C)
EAR(125 °C)
125
25
57
19
12
9
mJ
mJ
mJ
mJ
mJ
mJ
Tj(START) = 25 °C, IOUT1-8(START) = 0.4 A
Active Clamp Energy (Single Pulse)(Note 3)
Tj(START) = 150 °C, IOUT1-8(START) = 0.4 A
Active Clamp Energy (Single Pulse)
Tj(START) = 25 °C, IOUT1-8(START) = 0.8 A, Synchro Mode
Active Clamp Energy (Single Pulse)(Note 3)
Tj(START) = 150 °C, IOUT1-8(START) = 0.8 A, Synchro Mode
Active Clamp Energy (Repetitive)(Note 3)(Note 4)
Tj(START) = 125 °C, IOUT(START) = 0.2 A
Active Clamp Energy (Repetitive)(Note 3)(Note 4)
Tj(START) = 125 °C, IOUT(START) = 0.4 A, Synchro Mode
(Note 1) Limited by the active clamp function.
ES, AR(125 °C)
(Note 2) Limited by the over current protection function. The over current detection value can be adjusted in two levels.
(Note 3) Not 100 % are tested.
(Note 4) 2M cycles, All channel input.
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Caution 3: When IC is turned off with an inductive load, reverse energy has to be dissipated in the IC. This energy can be calculated by the following equation:
1
푉퐵퐴푇
퐸퐿 = ꢀ퐼푂푈푇(푆푇퐴푅푇)ꢁ × ꢂ1 −
2
ꢃ
푉퐵퐴푇 − 푉푂푈푇(퐶퐿)
Where:
L is the inductance of the inductive load.
IOUT(START) is the output current at the time of turning off.
VOUT(CL) is the output clamp voltage.
The IC integrates the active clamp function to internally absorb the reverse energy EL which is generated when the inductive load is turned off.
When the active clamp operates, the thermal shutdown function does not work. Decide a load so that the reverse energy EL is active clamp
energy EAS (Figure 1.), ES,AS (Figure 2.) or under when inductive load is used.
10000
1000
100
10
10000
1000
100
10
Tj = 25 °C
Tj = 25 °C
Tj = 150 °C
Tj = 150 °C
1
1
0.2
0.3
0.4
0.5
0.6
0.2
0.4
0.6
0.8
1.0
1.2
Output Current (Start): IOUT(START) [A]
Output Current (Start): IOUT(START) [A]
Figure 1. Active Clamp Energy (Single Pulse) vs
Output Current
Figure 2. Active Clamp Energy (Single Pulse)
Synchro Mode vs Output Current
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BD8LD650EFV-C
Thermal Resistance (Note 1)
Parameter
Symbol
Typ
Unit
Condition
HTSSOP-B20
96.6
35.1
24.5
°C/W
°C/W
°C/W
1s(Note 2)
2s(Note 3)
2s2p(Note 4)
Between Junction and Surroundings Temperature
Thermal Resistance
θJA
(Note 1) The thermal impedance is based on JESD51-2A(Still-Air) standard.
(Note 2) JESD51-3 standard FR4 114.3 mm x 76.2 mm x 1.57 mm 1-layer (1s)
(Top copper foil: ROHM recommended Footprint + wiring to measure, 2 oz. copper. )
(Note 3) JESD51-5 standard FR4 114.3 mm x 76.2 mm x 1.60 mm 2-layers (2s).
(Top copper foil: ROHM recommended Footprint + wiring to measure/
Copper foil area on the reverse side of PCB: 74.2 mm × 74.2 mm, copper (top & reverse side) 2 oz )
(Note 4) JESD51-5/-7 standard FR4 114.3 mm x 76.2 mm x 1.60 mm 4-layers (2s2p)
(Top copper foil: ROHM recommended Footprint + wiring to measure/
2 inner layers and copper foil area on the reverse side of PCB: 74.2 mm × 74.2 mm, copper (top & reverse side/inner layers) 2 oz./1 oz.)
■ PCB Layout 1 layer (1s)
100 mm2
Figure 3. PCB Layout 1 Layer (1s)
600 mm2
1200 mm2
Footprint
Dimension
Value
Board Finish Thickness
Board Dimension
1.57 mm ± 10 %
76.2 mm x 114.3 mm
FR4
Board Material
Copper Thickness (Top Layer)
Copper Foil Area Dimension
0.070 mm (Cu: 2 oz)
Footprint/100 mm2/600 mm2/1200 mm2
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BD8LD650EFV-C
Thermal Resistance – continued
■ PCB Layout 2 layers (2s)
Top Layer
Bottom Layer
Top Layer
Bottom Layer
Via
Isolation Clearance Diameter: ≥0.6 mm
Cross Section
Figure 4. PCB-layout 2-layer (2s)
Dimension
Value
1.60 mm ± 10 %
76.2 mm x 114.3 mm
FR4
Board Finish Thickness
Board Dimension
Board Material
Copper Thickness (Top/Bottom Layers)
Thermal Vias Separation/Diameter
0.070 mm (Cu +Plating)
1.2 mm/0.3 mm
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BD8LD650EFV-C
Thermal Resistance – continued
■ PCB Layout 4 layers (2s2p)
TOP Layer
Top Layer
2nd/Bottom Layers
3rd Layer
2nd Layer
3rd Layer
Bottom Layer
Via
Isolation Clearance Diameter: ≥0.6 mm
Cross Section
Figure 5. PCB-layout 4-layer (2s2p)
Dimension
Value
Board Finish Thickness
Board Dimension
1.60 mm ± 10 %
76.2 mm x 114.3 mm
FR4
Board Material
Copper Thickness (Top/Bottom Layers)
Copper Thickness (Inner Layers)
Thermal Vias Separation/Diameter
0.070 mm (Cu +Plating)
0.035 mm
1.2 mm/0.3 mm
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BD8LD650EFV-C
Thermal Resistance – continued
■ Transient Thermal Resistance (Single Pulse)
1000
100
10
1
1s footprint
2s
2s2p
0.1
0.0001 0.001 0.01
0.1
1
10
100 1000
Pulse Time [s]
Figure 6. Transient Thermal Resistance
■ Thermal Resistance (θJA vs Copper Foil area 1s)
120
100
80
60
40
20
0
0
200
400
600
800
1000
1200
Copper Fiol Area 1s [mm2]
Figure 7. Thermal Resistance
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BD8LD650EFV-C
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VDD Power Supply Voltage
VDDIO Power Supply Voltage
Operating Temperature
VDD
VDDIO
Topr
4.0
3.0
-40
5.0
5.0
5.5
5.5
V
V
+25
+150
°C
Electrical Characteristics
(Unless otherwise specified VDD = 4.0 V to 5.5 V, VDDIO = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C)
Parameter
[Power Supply]
Symbol
Min
Typ
Max
Unit
Conditions
VIDLE = 0 V
VIN21, VIN43, VIN65 = 0 V
VIDLE = 0 V
VIN21, VIN43, VIN65 = 0 V
VDD Standby Current
IVDDS
-
-
0
0
20
20
µA
µA
VDDIO Standby Current
IVDDIOS
VIDLE = 5 V
VDD Operating Current
IVDD
-
-
1.2
30
2.4
mA
µA
VIN21, VIN43, VIN65 = 5 V
OUTCTRLn[7:0] = FF(Note 1)
VIDLE = 5 V
VDDIO Operating Current
IVDDIO
150
VIN21, VIN43, VIN65 = 5 V
OUTCTRLn[7:0] = FF(Note 1)
VDD Power On Reset Voltage
VDDIO Power On Reset Voltage
VPORA
VPORD
-
-
-
-
4.0
2.7
V
V
[Input (IDLE, CSB, SCLK, SI, IN21, IN43, IN65)]
VDDIO
× 0.2
Low Level Input Voltage
VIL
0
-
V
VDDIO
× 0.7
0.25
High Level Input Voltage
Input Hysteresis Voltage
VIH
-
VDDIO
0.65
V
V
VHYS
0.45
VIDLE, VSCLK, VSI, VIN21, VIN43
VIN65 = 0 V
,
,
Low Level Input Current 1
(except CSB)
IIL1
-10
0
+10
µA
Low Level Input Current 2 (CSB)
High Level Input Current 1
(except CSB)
High Level Input Current 2 (CSB)
[Output (SO)]
IIL2
IIH1
IIH2
-100
25
-50
50
0
-25
100
+10
µA
µA
µA
VCSB = 0 V
VIDLE, VSCLK, VSI, VIN21, VIN43
VIN65 = 5 V
-10
VCSB = 5 V
Low Level Output Voltage
VOL
VOH
ISO
0
0.15
0.45
-
V
V
ISO = 1 mA
VDDIO
0.45
–
VDDIO
0.15
–
High Level Output Voltage
ISO = -1 mA
Serial Out Output Leakage Current
[Power MOS Output]
-5
0
+5
µA
VSO = 0 V / 5.5 V
VDD = 5 V
IOUT = 0.2 A, Tj = 25 °C
VDD = 5 V
IOUT = 0.2 A, Tj = 150 °C
-
-
650
800
mΩ
mΩ
Output On Resistance
RDS(ON)
1200
1500
-
-
0
1
µA
µA
V
VOUT = 30 V, Tj = 25 °C
VOUT = 30 V, Tj = 150 °C
IOUT = 1 mA, Output Off
Output Leakage Current
Output Clamp Voltage
IOUT(L)
VCL
0.15
41
2.00
45
37
(Note 1) Set by SPI control. Details are given in "Register Map". n represents the channel number.
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Electrical Characteristics – continued
(Unless otherwise specified, VDD = 4.0 V to 5.5 V, VDDIO = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C)
Parameter
[Power MOS Output]
Symbol
Min
Typ
Max
Unit
Conditions
Turn-On Time 1
Turn-Off Time 1
Turn-On Time 2
Turn-Off Time 2
Turn-On Time 3
Turn-Off Time 3
Slew Rate (On) 1
Slew Rate (Off) 1
Slew Rate (On) 2
Slew Rate (Off) 2
Slew Rate (On) 3
Slew Rate (Off) 3
tON1
tOFF1
-
-
-
-
50
50
µs
µs
RL = 60 Ω, VIDLE = 5 V, VBAT
=
12 V, SRCTRLn[1:0] = 00(Note 1)
tON2
-
-
200
200
25
µs
RL = 60 Ω, VIDLE = 5 V, VBAT
=
12 V, SRCTRLn[1:0] = 10(Note 1)
tOFF2
-
-
µs
tON3
-
-
µs
RL = 60 Ω, VIDLE = 5 V, VBAT
=
12 V, SRCTRLn[1:0] = 01(Note 1)
tOFF3
-
-
25
µs
SRON1
SROFF1
SRON2
SROFF2
SRON3
SROFF3
0.50
0.50
0.10
0.10
1.35
1.35
1.00
1.00
0.30
0.30
2.25
2.25
1.50
1.50
0.50
0.50
3.15
3.15
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
RL = 60 Ω, VIDLE = 5 V, VBAT
=
12 V, SRCTRLn[1:0] = 00(Note 1)
RL = 60 Ω, VIDLE = 5 V, VBAT
=
12 V, SRCTRLn[1:0] = 10(Note 1)
RL = 60 Ω, VIDLE = 5 V, VBAT
=
12 V, SRCTRLn[1:0] = 01(Note 1)
RL = 60 Ω, VIDLE = 5 V, VBAT
=
PWM Output Range
fPWM
-
-
5
kHz
12 V, SRCTRLn[1:0] = 00(Note 1)
[Over Current Protection Function]
Over Current Threshold Value 1
Over Current Threshold Value 2
Output Stop Time at OCP Detection
[Open Load Detection Function]
Open Load Detect Voltage
IOCP1
IOCP2
0.50
1.00
0.4
0.85
1.70
1.0
1.30
2.40
1.9
A
A
OCPCTRLn = '0'(Note 1)
OCPCTRLn = '1'(Note 1)
OCPCTRLn = '0' / '1'(Note 1)
tOCP_OFF
ms
DIAG_OLD/OFDn = '1'(Note 1)
Output Off
VOLD_DET
VOLD_REL
IOLD
1.2
1.6
15
2.2
2.6
40
3.2
3.6
90
V
V
Open Load Release Voltage
Output Sink Current
µA
VOUT = 12 V
[Output Overhead Fault Detection Function]
DIAG_OLD/OFDn = '1'(Note 1)
Output On
Output Overhead Detect Voltage
Output Overhead Release Voltage
[Short Ground Detection Function]
Short Ground Detect Voltage
Short Ground Release Voltage
Output Source Current
VOFD_DET
1.6
1.2
2.6
2.2
3.6
3.2
V
V
VOFD_REL
DIAG_SGDn = '1'(Note 1)
Output Off
VSGD_DET
VSGD_REL
ISGD
0.3
0.5
-40
1.0
1.4
-25
1.5
1.9
-10
V
V
µA
VOUT = 0 V
[Thermal Shutdown Function]
Detect Temperature(Note 2)
Hysteresis Temperature(Note 2)
TTSD_DET
TTSD_HYS
150
-
175
15
200
-
°C
°C
(Note 1) Set by SPI control. Details are given in "Register Map". n represents the channel number.
(Note 2) Not 100 % are tested.
Switching Time Measurement Waveform
Control by SPI
Control by IN21 / IN43/ IN65
SRON = (VBAT * 0.8) / TFALL
SROFF = (VBAT * 0.8) / TRISE
[V]
[V]
IN21 / IN43
IN65
CSB
for SPI
[t]
[t]
0
0
[V]
[V]
tONn
tOFFn
tONn
tOFFn
VBAT
VBAT*0.9
OUTn
VBAT
VBAT*0.9
OUTn
VBAT*0.1
VBAT*0.1
[t]
[t]
0
0
tFALLn
tRISEn
tFALLn
tRISEn
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BD8LD650EFV-C
Typical Performance Curves
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
20
15
10
5
20
15
10
5
0
0
0
1
2
3
4
5
6
7
-50
0
50
100
150
Power Supply Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 8. VDD Standby Current vs Power Supply Voltage
Figure 9. VDD Standby Current vs Junction Temperature
20
15
10
5
20
15
10
5
0
0
0
1
2
3
4
5
6
7
-50
0
50
100
150
Power Supply Voltage: VDDIO [V]
Junction Temperature: Tj [ºC]
Figure 10. VDDIO Standby Current vs Power Supply Voltage
Figure 11. VDDIO Standby Current vs Junction Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
2.4
2.0
1.6
1.2
0.8
0.4
0.0
2.4
2.0
1.6
1.2
0.8
0.4
0.0
Sweep
0
1
2
3
4
5
6
7
-50
0
50
100
150
Power Supply Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 12. VDD Operating Current vs Power Supply Voltage
Figure 13. VDD Operating Current vs Junction Temperature
150
150
120
90
60
30
0
120
Sweep
90
60
30
0
0
1
2
3
4
5
6
7
-50
0
50
100
150
Power Supply Voltage: VDDIO [V]
Junction Temperature: Tj [ºC]
Figure 14. VDDIO Operating Current vs Power Supply
Voltage
Figure 15. VDDIO Operating Current vs Junction
Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5
4
3
2
1
0
VPORA
VIH
VIL
VPORD
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 16. VDD/VDDIO Power On Reset Voltage vs Junction
Temperature
Figure 17. High/Low Level Input Voltage vs Junction
Temperature
0
100
80
IIH2
-20
-40
-60
60
IIH1
IIL2
40
20
-80
IIL1
-100
0
-50
-50
0
50
100
150
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 18. High/Low Level Input Current 1 vs Junction
Temperature
Figure 19. High/Low Level Input Current 2 vs Junction
Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
5.0
4.9
4.8
4.7
4.6
4.5
0.5
0.4
0.3
0.2
0.1
0.0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 20. SO Low Level Output Voltage vs Junction
Temperature
Figure 21. SO High Level Output Voltage vs Junction
Temperature
5
4
1.4
Tj = 25 °C
Tj = 150 °C
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3
2
1
0
-1
-2
-3
-4
-5
-50
0
50
100
150
3
4
5
6
Junction Temperature: Tj [ºC]
Power Supply Voltage: VDD [V]
Figure 22. Serial Out Output Leakage Current vs Junction
Temperature
Figure 23. Output On Resistance vs Power Supply Voltage
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
2.0
1.6
1.2
0.8
0.4
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Tj = 25 ºC
Tj = 150 ºC
0
4
8
12 16 20 24 28 32 36
Output Voltage: VOUT [V]
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Figure 24. Output On Resistance vs Junction Temperature
Figure 25. Output Leakage Current vs Output Voltage
2.0
1.6
1.2
0.8
0.4
0.0
45
43
41
39
37
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 26. Output Leakage Current vs Junction Temperature
Figure 27. Output Clamp Voltage vs Junction Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
50
40
30
20
10
0
50
40
30
20
10
0
tOFF1
tOFF1
tON1
tON1
3
4
5
6
-50
0
50
100
150
Power Supplay Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 28. Turn-On/Off Time 1 vs Power Supply Voltage
Figure 29. Turn-On/Off Time 1 vs Junction Temperature
1.5
1.3
1.5
1.3
SROFF1
SROFF1
SRON1
1.1
1.1
SRON1
0.9
0.9
0.7
0.5
0.7
0.5
3
4
5
6
-50
0
50
100
150
Power Supply Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 30. Slew Rate (On/Off) 1 vs Power Supply Voltage
Figure 31. Slew Rate (On/Off) 1 vs Junction Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
200
160
120
80
200
160
120
80
tOFF2
tON2
tOFF2
tON2
40
40
0
0
3
4
5
6
-50
0
50
100
150
Power Supply Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 32. Turn-On/Off Time 2 vs Power Supply Voltage
Figure 33. Turn-On/Off Time 2 vs Junction Temperature
0.5
0.5
0.4
0.4
SROFF2
SROFF2
0.3
0.3
SRON2
SRON2
0.2
0.1
0.2
0.1
3
4
5
6
-50
0
50
100
150
Power Supply Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 34. Slew Rate (On/Off) 2 vs Power Supply Voltage
Figure 35. Slew Rate (On/Off) 2 vs Junction Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
25
20
15
10
5
25
20
15
10
5
tOFF3
tOFF3
tON3
tON3
0
0
3
4
5
6
-50
0
50
100
150
Power Supply Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 36. Turn-On/Off Time 3 vs Power Supply Voltage
Figure 37. Turn-On/Off Time 3 vs Junction Temperature
3.2
2.8
3.2
2.8
2.4
2.4
SROFF3
SROFF3
SRON3
SRON3
2.0
2
1.6
1.2
1.6
1.2
3
4
5
6
-50
0
50
100
150
Power Suppy Voltage: VDD [V]
Junction Temperature: Tj [ºC]
Figure 38. Slew Rate (On/Off) 3 vs Power Supply Voltage
Figure 39. Slew Rate (On/Off) 3 vs Junction Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
2.4
2.0
1.6
1.2
0.8
0.4
0.0
1.9
1.6
1.3
1
IOCP2
IOCP1
0.7
0.4
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 40. Over Current Threshold Value 1,2 vs Junction
Temperature
Figure 41. Output Stop Time at OCP Detection vs Junction
Temperature
3.5
3.0
2.5
2.0
1.5
1.0
3.5
3.0
2.5
2.0
1.5
1.0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 42. Open Load Detect Voltage vs Junction
Temperature
Figure 43. Open Load Release Voltage vs Junction
Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
90
75
60
45
30
15
3.5
3.0
2.5
2.0
1.5
1.0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 44. Output Sink Current vs Junction Temperature
Figure 45. Output Overhead Detect Voltage vs Junction
Temperature
3.5
3.0
2.5
2.0
1.5
1.0
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 46. Output Overhead Release Voltage vs Junction
Temperature
Figure 47. Short Ground Detect Voltage vs Junction
Temperature
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BD8LD650EFV-C
Typical Performance Curves – continued
(Reference data) (Unless otherwise specified, VDD = 5 V, VDDIO = 5 V, Tj = 25 °C)
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-10
-15
-20
-25
-30
-35
-40
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature: Tj [ºC]
Junction Temperature: Tj [ºC]
Figure 48. Short Ground Release Voltage vs Junction
Temperature
Figure 49. Output Source Current vs Junction Temperature
200
190
180
170
160
150
3
4
5
6
Power Supply Voltage: VDD [V]
Figure 50. Thermal Shutdown Detect Temperature vs Power
Supply Voltage
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BD8LD650EFV-C
Measurement Circuit
VBAT
VDD
VDD
RL
VDD VDDIO OUTn
VDD VDDIO OUTn
IDLE
INxx
CSB
SCLK
SI
IDLE
INxx
0 V
VOUT
VDD
CSB
SCLK
SI
MCU
SO
SO
GND
GND
*ALL ch On
VSO
Figure 51. VDD Standby Current
VDDIO Standby Current
Figure 52. VDD Operating Current
VDDIO Operating Current
Low Level Input Current 1, 2
Output Leakage Current
VDD Power On Reset Voltage
VDDIO Power On Reset Voltage
Serial Out Output Leakage Current
Thermal Shutdown Detect Temperature
Thermal Shutdown Hysteresis Temperature
VDD
VDD
VDD VDDIO OUTn
VDD VDDIO OUTn
IDLE
INxx
IDLE
INxx
VDD
VDD
CSB
SCLK
SI
CSB
SCLK
SI
MCU
MCU
SO
SO
GND
GND
*ALL ch On/Off
Figure 53. Output On Resistance
Output Clamp Voltage
Figure 54. SO High/Low Level Output Voltage
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BD8LD650EFV-C
Measurement Circuit – continued
VBAT
VDD
VDD
RL
VDD VDDIO OUTn
VDD VDDIO OUTn
IDLE
INxx
IDLE
INxx
Monitor
VDD
VDD
CSB
SCLK
SI
CSB
SCLK
SI
MCU
MCU
SO
SO
GND
GND
*ALL ch On / Off
*ALL ch On / Off
Figure 55. Slew Rate (On/Off) 1, 2, 3
Turn-On/Off Time 1, 2, 3
Figure 56. Open Load Detect/Release Voltage
Output Sink Current
Output Overhead Detect/Release Voltage
Short Ground Detect/Release Voltage
Output Source Current
Over Current Threshold Value 1, 2
Output Stop Time at OCP Detection
VBAT
VDD
RL
VDD VDDIO OUTn
IDLE
INxx
CSB
SCLK
SI
VDD
SO
GND
Figure 57. Low Level Input Voltage
High Level Input Voltage
Input Hysteresis Voltage
High Level Input Current 1, 2
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BD8LD650EFV-C
Timing Chart
The following shows the sequence when H is input to the IDLE pin after the power is supplied.
“xx” denotes each input (21, 43, 65), and n denotes the channel number.
[V]
3.0 V (Max)
VDDIO
VDD
IDLE
CSB
[t]
0
[V]
4.0 V (Max)
[t]
[t]
0
[V]
tSETUP ≥ 0.1 µs
tSHUTDOWN ≥ 0.1 µs
When IDLE is set High, you can send command by SPI.
0
[V]
tSPI_START ≥ 10 µs
tSPI_END ≥ 0.1 µs
[t]
[t]
[t]
0
[V]
tINxx_ON ≥ 10 µs
tIDLE_OFF ≥ tOFFn_Max
INxx
0
[V]
tONn
tOFFn
VBAT
VBAT*0.9
OUTn
VBAT*0.1
0
(Supplement) About Each Symbol
tSETUP: Time from VDDIO and VDD reaches operating voltage until H can be input to IDLE.
tSPI_START: Time from H is input to IDLE until SPI communication is available.
tINxx_ON: Time from H is input to IDLE until control by INxx is available.
tSPI_END: Time from completion of SPI communication until L is input L to IDLE(Note 1)
tIDLE_OFF: Time from end of control by INxx until input L to IDLE.
.
tONn: Turn-On time
tOFFn: Turn-Off time
tOFFn_Max: Turn-Off Time (Max)
tSHUTDOWN: Time from input L to IDLE until VDDIO and VDD are turned off.
(Note 1) If using SPI control to turn off low side SW, wait tIDLE_OFF before inputting L to IDLE.
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BD8LD650EFV-C
Timing Chart – continued
The following shows the sequence when the VDDIO and IDLE pins are simultaneously turned on/off.
“xx” denotes each input (21, 43, 65), and n denotes the channel number.
[V]
3.0 V (Max)
VDDIO
VDD
[t]
0
[V]
4.0 V (Max)
[t]
[t]
0
[V]
IDLE
*short to
VDDIO
0
[V]
tSPI_START ≥ 10 µs
tSPI_END ≥ 0.1 µs
CSB
INxx
[t]
[t]
[t]
0
[V]
tINxx_ON ≥ 10 µs
tVDD_OFF ≥ tOFFn_Max
0
[V]
tONn
tOFFn
VBAT
VBAT*0.9
OUTn
VBAT*0.1
0
(Supplement) About Each Symbol
tSPI_START: Time from H is input to IDLE until SPI communication is available.
tINxx_ON: Time from VDD reaches operating voltage until control by INxx is available.
tSPI_END: Time from completion of SPI communication until lowering VDD(Note 1)
tVDD_OFF: Time from end of control by INxx until lowering VDD.
.
tONn: Turn-On time
tOFFn: Turn-Off time
tOFFn_Max: Turn-Off time (Max)
(Note 1) If using SPI control to turn off low side SW, wait tVDD_OFF before lowering VDD.
Inductive Load Operation
[V]
INxx
0
[t]
VCL
[V]
VOUT
VBAT
IOUT x RDS(ON)
[t]
[t]
0
[A]
VBAT
RL + RDS(ON)
IOUT
0
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BD8LD650EFV-C
Synchro Mode
Two adjacent output pins can be connected in parallel. Parallel connection is available by combining OUT1/OUT2, OUT3/OUT4,
OUT5/OUT6, OUT7/OUT8. The synchro mode can be set by SPI. For details, refer to "Register Map".
When controlling by IN21/IN43/IN65, channels connected in parallel are driven simultaneously.
All control by SPI is set from the odd number channel, and the even number channel setting is ignored. For example, to turn on
OUT1/OUT2, write "1" to OUTCTRL1 bit of OUTCTRL register. Writing to OUTCTRL2 bit is ignored.
Over current protection and thermal shutdown is active on each channel connected in parallel, and both channels are turned off
when protection is detected in either channel.
The detection of protection can be read from SPI by accessing DIAG_OUT4321 or DIAG_OUT8765 registers.
The error flag is output from the odd number channel and the error flag of the even number channel is fixed to "0". For example,
if over current protection is detected in OUT1/OUT2, "1" is output from DIAG_OCP1 bit of DIAG_OUT4321 register, and
DIAG_OCP2 bit outputs "0".
VDDIO
VDD
VBAT
CVDDIO
CVDD
VDDIO
VDD
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
I/O
Control Logic
RIDLE
RIN21
RIN43
RIN65
IDLE
IN21
IN43
IN65
UVLO
I/O
(IDLE, IN,
Limp Home)
Mode
Control
Control,
Diagnostic
and
protective
Functions
Limp
Home
OCD
TSD
MCU
Input
Register
RCSB
RSCLK
RSI
CSB
SCLK
SI
UVLO
OLD
OFD
SGD
SPI
Control
Active
Clamp
I/O
(SPI)
Gate
Driver
Diagnosis
Register
RSO
SO
COUT1
COUT2
COUT3
COUT4
GND
Caution: Differences in wire impedance between two neighboring outputs may affect characteristics such as turn-On/Off, slew rate, over current threshold value, and
active clamp energy. To avoid this, it is recommended to short output pin with near the IC as possible.
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BD8LD650EFV-C
Limp Home Mode
When IDLE is set to L, the IC enters Limp Home mode. This mode enables operation with low current consumption. Control by
SPI is not possible in this mode, but on/off control by IN21/IN43/IN65 is available. Controllable channels are limited to odd
number channels (1ch, 3ch, 5ch). When IDLE becomes L, the register is cleared and returns to the default setting.
The timing chart in Limp Home mode is shown below.
[V]
VDDIO
[t]
[t]
[t]
[t]
[t]
0
[V]
VDD
IDLE
INxx
0
[V]
0
[V]
tSETUP(Limp) ≥ 10 µs
tSHUTDOWN(Limp) ≥ tOFF_Max1,3.5
0
[V]
tON1,3,5
tOFF1,3,5
VBAT
VBAT*0.9
OUT1
OUT3
OUT5
VBAT*0.1
0
(Supplement) About Each Symbol
tSETUP(Limp): Time from VDDIO and VDD reaches operating voltage until control by INxx is available.
tON1,3,5: Turn-On time
tOFF1,3,5: Turn-Off time
tOFF_Max1,3,5: Turn-Off time (Max)
tSHUTDOWN(Limp): Time from all INxx is set to L until VDDIO and VDD are turned off.
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BD8LD650EFV-C
SPI Specification
SPI overview
When CSB = H
SO is High-Z.
When CSB = L
Outputs to SO at the rising edge of SCLK.
SI is loaded into the register at the falling edge of SCLK.
MSB
LSB
LSB
X
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
SO
SI
MSB
CSB
SCLK
SPI protocol
The SO response to SPI access is returned at the next SPI access as shown in the following figure.
SI
frame A
frame B
frame C
(previous
response)
response to
frame A
response to
frame B
SO
·Response when accessing with RE = 0 and with RE = 1
When accessing with RE = 0, respond “Standard diagnostic”.
When accessing with RE = 1, respond the value of the specified register.
SI
RE = 0
RE = 1 (register A)
(new command)
(previous
response)
Standard
diagnostic
register A
content
SO
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BD8LD650EFV-C
SPI Specification – continued
Serial Daisy Chain
Multiple devices can be connected in series as shown below.
For CSB signal and SCLK signal, connect a common signal. About SI / SO line, SO of Device 1 can be connected to SI of Device 2 as
shown below.
Device 1
SPI
Device 2
SPI
Device 7
SPI
Device 8
SPI
SI
SO
SI
SO
MO
CSB
SCLK
CSB
SCLK
CSB
SCLK
CSB
SCLK
MI
MCSB
MCLK
The timing chart when eight devices are connected is shown below.
X SO Device 8
SO Device 7
SO Device 2
SI Device 2
SO Device 1
SI Device 1
MI
MO
X SI Device 8
SI Device 7
MCSB
MCLK
OUTn
Parallel Connection
Multiple devices can be connected in parallel as shown below.
For SI signal, SCLK signal, and SO signal, connect a common signal. Separate signals are required for the CSB signal for each
device.
Device 1
SI
SCLK
CSB
SO
SPI
MCSB1
Device 2
SPI
SI
SCLK
CSB
SO
MO
MCLK
MCSB2
MI
The timing chart when two devices are connected is shown below.
SO Device 1
SO Device 2
SI Device 2
MI
SI Device 1
MO
MCSB1
MCSB2
MCLK
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BD8LD650EFV-C
SPI Specification – continued
SPI Timing chart
tCSB(lead)
tCSB(lag)
tCSB(td)
0.7VDD
0.2VDD
tSCLK(P)
CSB
tSCLK(su)
tSCLK(hd)
tSCLK(H)
tSCLK(L)
0.7VDD
0.2VDD
SCLK
tSI(su)
tSI(hd)
0.7VDD
0.2VDD
SI
Don't care
Hi-Z
SI
MSB
14
1
LSB
Don't care
tSO(td)
tSO(en)
tSO(dd)
tSO(dis)
0.7VDD
0.2VDD
Hi-Z
SO
x
SI
MSB
14
1
LSB
x
Parameter
Symbol
Min
Typ
Max
Unit
SCLK Frequency
SCLK Period
fSCLK
tSCLK(P)
tSCLK(H)
tSCLK(L)
tSCLK(su)
tSCLK(hd)
tCSB(lead)
tCSB(lag)
tCSB(td)
tSI(su)
0
200
50
50
50
50
250
250
250
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
SCLK High Time
SCLK Low Time
SCLK Setup Time
SCLK Hold Time
CSB Lead Time
CSB Lag Time
-
-
-
-
-
-
Transfer Delay Time
Data Setup Time
Data Hold Time
SPI Output Enable Time(Note 1)
SPI Output Disable Time(Note 1)
-
-
tSI(hd)
-
tSO(en)
200
250
100
200
tSO(dis)
tSO(dd)
-
SPI Output Data Delay Time(Note 1)(Note 2)
ERR Output Through Delay Time(Note 1)
-
tSO(td)
-
(Note 1) Not 100 % tested.
(Note 2) SO capacitance = 20 pF
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BD8LD650EFV-C
SPI Specification – continued
SI data structure
Bit[15]
RE
Bit[14]
WE
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
Bit[7]
Data
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Address
TEST
RE
0: SO outputs "Standard diagnostic" at the next SPI access.
1: SO outputs the register specified by Address at the next SPI access.
WE
0: Not Write.
1: Write.
TEST
Be sure to set 0.
Data
When WE = 1, various settings are enabled by writing '0' or '1' to Data.
For details, refer to "Register Map".
"Standard diagnostic" (when RE = 0 in the previous SPI access)
Initial Value 0x4000
Bit[15]
0
Bit[14]
INIT
Bit[13]
0
Bit[12]
0
Bit[11]
0
Bit[10]
TER
Bit[9]
0
Bit[8]
0
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
ERR8
ERR7
ERR6
ERR5
ERR4
ERR3
ERR2
ERR1
INIT
0: Normal (after power on or IDLE = 'L'->'H', from the second time SPI access).
1: After power on or IDLE = 'L'->'H', first time SPI access.
TER
0: Normal
1: SPI communication error
When High pulse input of SCLK is other than (16 times + 8 x m, m is an integer 0 or above) in the low level section of CSB, a
communication error is judged.
ERRn (n is the channel number)
0: Normal
1: The value is latched and output when over current protection or thermal shutdown of the corresponding channel is detected.
This bit is cleared by reading DIAG register (DIAG_OUT4321 or DIAG_OUT8765) of the channel on which protection is detected.
SO output data structure (when RE = 1 in the previous SPI access)
Bit[15]
1
Bit[14]
WE
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
Bit[7]
Data
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Address
ERRALL
WE, Address
Outputs WE and Address values that were set during the previous SPI access.
ERRALL
Outputs 1 when either over current protection or thermal shutdown of OUT is detected on at least one channel.
Data
Outputs the register value of Address that were set during the previous SPI access.
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BD8LD650EFV-C
Register Map
Address TEST
Bit[13:9] Bit[8]
Data
Register
Access
Register Name
Initial
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
OUTCTRL
SRCTRL0
R/W
R/W
R/W
R/W
R/W
R/W
RO
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x08
0x09
0x0A
0x0B
0x0C
0x1E
0
0
0
0
0
0
0
0
0
0
0
0
1
OUTCTRL8
OUTCTRL7
OUTCTRL6
OUTCTRL5
OUTCTRL4
OUTCTRL3
OUTCTRL2
OUTCTRL1
0x00
0x00
0x00
0x00
0x55
0x00
0x00
SRCTRL4[1:0]
SRCTRL8[1:0]
SRCTRL3[1:0]
SRCTRL7[1:0]
SRCTRL2[1:0]
SRCTRL6[1:0]
SRCTRL1[1:0]
SRCTRL5[1:0]
OCPCTRL2
SRCTRL1
OCPCTRL
OCPCTRL8
OCPCTRL7
OCPCTRL6
OCPCTRL5
OCPCTRL4
OCPCTRL3
DIRCTRL3
SYNC65
OCPCTRL1
DIRCTRL1
SYNC21
DIRCTRL
0
0
0
1
0
0
DIRCTRL6
DIRCTRL5
DIRCTRL4
SYNC87
0
DIRCTRL2
SYNC43
SYNC
0
0
0
0
STATUS_IN
DIAG_OLD/OFD
DIAG_SGD
DIAG_OUT4321
DIAG_OUT8765
HWCR
STATUS_IN65
STATUS_IN43
STATUS_IN21
R/W
R/W
RO
DIAG_OLD/OFD8 DIAG_OLD/OFD7 DIAG_OLD/OFD6 DIAG_OLD/OFD5 DIAG_OLD/OFD4 DIAG_OLD/OFD3 DIAG_OLD/OFD2 DIAG_OLD/OFD1 0x00
DIAG_SGD8
DIAG_SGD7
DIAG_TSD4
DIAG_TSD8
RST
DIAG_SGD6
DIAG_SGD5
DIAG_SGD4
DIAG_SGD3
DIAG_SGD2
DIAG_SGD1
DIAG_TSD1
DIAG_TSD5
0
0x00
0x00
0x00
0x00
0x00
DIAG_OCP4
DIAG_OCP3
DIAG_TSD3
DIAG_OCP2
DIAG_TSD2
DIAG_OCP1
RO
DIAG_OCP8
DIAG_OCP7
DIAG_TSD7
DIAG_OCP6
DIAG_TSD6
DIAG_OCP5
WO
WO
0
0
0
0
0
0
0
0
0
0
0
0
T_TESTMODE
0
TESTMODE
Register Name
OUTCTRL
Register Access
Read / Write
Address
0x00h
Explanation of Data
OUTCTRLn bit (n represents the channel number)
'0': OUTn off setting
'1': OUTn on setting
SRCTRLn[1:0] bit
'00': Slew Rate Setting 1.0 V/μs (Typ)
'01': Slew Rate Setting 2.25 V/μs (Typ)
'10': Slew Rate Setting 0.30 V/μs (Typ)
'11': Same setting as '00'
SRCTRL0
SRCTRL1
0x01h
0x02h
Read / Write
OCPCTRLn bit
OCPCTRL
DIRCTRL
SYNC
Read / Write
Read / Write
Read / Write
Read Only
0x03h
0x04h
0x05h
0x06h
'0': Over Current Threshold Value 1 0.85 A (Typ)
'1': Over Current Threshold Value 2 1.7 A (Typ)
DIRCTRLn bit
'0': IN control disabled
'1': IN control enabled
SYNC21/SYNC43/SYNC65/SYNC87 bit
'0': Synchro mode disabled
'1': Synchro mode enabled
STATUS_IN65/STATUS_IN43/STATUS_IN21 bit
'0': IN87/IN65/IN43/IN21 L input
'1': IN87/IN65/IN43/IN21 H input
DIAG_OLD/OFDn bit
STATUS_IN
'0': OLD/OFD disabled
'1': OLD/OFD enabled
OLD is enabled when OUTn is off. OFD is enabled when OUTn is
on. When SPI access is performed again, it automatically returns
to '0' (disabled).
Read OLD/OFD result by read access (RE = 1).
When OLD is active, the judgement is made as below.
'0': OLD detection
DIAG_OLD/OFD
Read / Write
0x08h
'1': Normal
When OFD is active, the judgement is made as below.
'0': Normal
'1': OFD detection
For details, refer to "Open Load Detection" and "Output Overhead
Fault Detection Function".
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BD8LD650EFV-C
Register Map – continued
Register Name
Register Access
Address
0x09h
Explanation of Data
DIAG_SGDn bit
'0': SGD disabled
'1': SGD enabled
This function is used when OUTn is off. When SPI access is
performed again, it automatically returns to '0' (disabled).
DIAG_SGD
Read / Write
Read SGD result by read access (RE = 1).
'0': SGD detection
'1': Normal
For details, refer to " Short Ground Detection".
Read the error flag of ch1/ch2/ch3/ch4.
DIAG_TSDn bit
'0': Normal
'1': TSD detection
DIAG_OUT4321
Read Only
0x0Ah
DIAG_OCPn bit
'0': Normal
'1': OCP detection
It automatically returns to '0' when DIAG_OUT4321 is accessed.
Read the error flag of ch5/ch6/ch7/ch8.
DIAG_TSDn bit
'0': Normal
'1': TSD detection
DIAG_OUT8765
Read Only
0x0Bh
DIAG_OCPn bit
'0': Normal
'1': OCP detection
It automatically returns to '0' when DIAG_OUT8765 is accessed.
RST
HWCR
Write Only
Write Only
0x0Ch
0x1Eh
'0': Normal
'1': Hardware reset (auto clear)
TESTMODE
'0': Normal
'1': Test Mode
T_TESTMODE
If IDLE is 5.6 V (Min) or more and "1" is written to this register, IC
enters test mode. For this reason, do not access to this register.
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BD8LD650EFV-C
Over Current Protection Function
Turns off the output when an over current error occurs in the output (A in the figure). The output returns to on when the output
stop time of 1 ms (Typ) has passed. However, if an over current error still continue at this time, the output will be turned off again
(B in the figure). When an over current error is improved, the output recovers after the output stop time from over current error is
lastly detected has passed (C in the figure).
If an over current error is detected, the internal over current detection flag outputs '1' (A' in the figure). This flag can be read from
SPI read access or from Standard diagnostic. When the flag is read by SPI read access, it is cleared by the next SPI access after
read access (D in the figure).
*n shows ch number [V]
OUT Enable(Note 1)
[t]
[t]
[t]
[t]
[t]
0
[V]
A
C
VBAT
OUTn
0
[A]
B
IOCP1
IOCP2
IOUTn
1 ms (Typ)
1 ms (Typ)
0
D
A'
DIAG_OCPn
'0'
'1'
'0'
in DIAG_OUT Register
DIAG_OUT
Read Access
Return
Response
[V]
CSB
for SPI
0
(Note 1) Output on/off control signal. This signal is controlled by IN65, IN43, IN21 or OUT_CTRL register.
When an over current error is detected in multiple channels, the output off time is measured starting from the channel that over
current error was detected lastly.
For example, if an over current error is detected in ch2 after an over current error is detected in ch1 before the output off time of
ch1 passes, the time tSHORT from ch1 detects an error until an error is detected in ch2 will be added to the output off time of ch1.
[A]
tSHORT
< 1 ms (Typ)
IOUT1
1 ms (Typ)
1 ms (Typ)
1 ms (Typ)
1 ms (Typ)
1 ms (Typ)
[t]
[t]
0
[A]
IOUT2
1 ms (Typ)
0
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BD8LD650EFV-C
Thermal Shutdown Function
Turns off the output when the junction temperature rises 175 °C (Typ) or above (A in the figure). After that, the output automatically
returns to on when the junction temperature falls 160 °C (Typ) or below (B in the figure).
When thermal shutdown is detected, the internal thermal shutdown flag outputs '1' (A in the figure). This flag can be read from SPI
read access or Standard diagnostic. When the flag is read by SPI read access, it is cleared by the next SPI access after read
access (C in the figure).
*n shows ch number [V]
OUT Enable(Note 1)
[t]
[t]
[t]
[t]
[t]
0
[V]
A
B
VBAT
OUTn
0
[°C]
TTSD_DET
TTSD_HYS
Tj
0
C
DIAG_TSDn
'0'
'1'
'0'
in DIAG_OUT Register
DIAG_TSD
Read Access
Return
Response
[V]
CSB
for SPI
0
(Note 1) Output on/off control signal. This signal is controlled by IN65, IN43, IN21 or OUT_CTRL register.
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BD8LD650EFV-C
Open Load Detection (OLD)
VBAT
RL
OUT
Power
MOS
DIAG_
OLD/OFDn
IOLD
SO
GND
When OLD is enabled, output sink current IOLD flows from OUT. The output voltage VOUT drops when the load RL increases, and
it is detected as OLD when it becomes VOLD_DET or less.
RL for detecting OLDs is given by the following equation:
푉퐵퐴푇 − 푉푂퐿퐷_퐷ꢅ푇
ꢄ퐿 ≥
퐼푂퐿퐷
VBAT: Battery voltage
VOLD_DET: Open load detection voltage 3.2 V (Max)
IOLD: Output sink current when OLD function is active 90 μA (Max)
When the output is off, OLD can be enabled and diagnosed by one SPI access of write and read access (RE = 1, WE = 1) to
DIAG_OLD/OFD register (B, F in the figure). Diagnostic is output to SO at the next SPI access (D, H in the figure).
At this time, OLD returns to inactive (D, H in the figure). When OUTn voltage is VOLD_DET or less, OLD is diagnosed as detected
and the error flag inside the IC outputs "0" (C in the figure). If OUTn voltage is VOLD_REL or more, OLD is diagnosed as undetected
and the error flag output '1' (G in the figure).
*n shows ch number
[V]
OUT Enable(Note 1)
[t]
[t]
[t]
[t]
[t]
0
[V]
DIAG_OLD/OFD
R/W Access
Return
Response
DIAG_OLD/OFD
R/W Access
Return
Response
CSB
for SPI
0
B
D
F
H
OLD Enable(Note 2)
'0'
'1'
'0'
'1'
'0'
A. Occur
E. Improve
"Open Load"
[V]
"Open Load"
VBAT
VOLD_REL
OUTn
Hi-Z
Hi-Z
VOLD_DET
0
C
G
OLD Error(Note 3)
'0'
(Detect)
'1'
'1'
'1'
'1'
(No Detect)
(Note 1) Output on/off control signal. This signal is controlled by IN65, IN43, IN21 or OUT_CTRL register.
(Note 2) Internal enable signal. High and Low indicates enabled and disabled, respectively. This signal is controlled by write access to DIAG_OLD/OFD register.
(Note 3) Internal error flag. High and Low indicates error undetected and detected, respectively. Also the flag outputs High during disable. This signal can be retrieved
to SO by read access to DIAG_OLD/OFD register.
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BD8LD650EFV-C
Output Overhead Fault Detection Function (OFD)
VBAT
RL
OUT
Power
MOS
DIAG_
OLD/OFDn
SO
GND
When the output is on, OFD can be enabled and diagnosed by one SPI access by write and read access (RE = 1, WE = 1) to
DIAG_OLD/OFD register (B, F in the figure). Diagnostic is output to SO at the next SPI access (D, H in the figure).
At this time, OFD returns to be inactive (D, H in the figure). When OUTn voltage is VOFD_DET or more, OFD is diagnosed as detected
and the error flag inside the IC outputs "1" (C in the figure). If OUTn voltage is VOFD_REL or less, OFD is diagnosed as undetected
and the error flag output '0' (G in the figure).
*n shows ch number
[V]
OUT Enable(Note 1)
[t]
[t]
[t]
[t]
[t]
0
[V]
DIAG_OLD/OFD
R/W Access
Return
Response
DIAG_OLD/OFD
R/W Access
Return
Response
CSB
for SPI
0
B
D
F
H
OFD Enable(Note 2)
'0'
'1'
'0'
'1'
'0'
A. Occur
E. Improve
[V]
"VDD Short"
"VDD Short"
VBAT
OUTn
VOFD_DET
VOFD_REL
0
C
G
OFD Error(Note 3)
'1'
(Detect)
'0'
'1'
'1'
'1'
(No Detect)
(Note 1) Output on/off control signal. High and Low indicates on and off, respectively. This signal is controlled by IN65, IN43, IN21 or OUT_CTRL register.
(Note 2) Internal enable signal. High and Low indicates enabled and disabled, respectively. This signal is controlled by write access to DIAG_OLD/OFD register.
(Note 3) Internal error flag. High and Low indicates error detected and undetected, respectively. Also the flag outputs High during disable. This signal can be retrieved
to SO by read access to DIAG_OLD/OFD register.
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BD8LD650EFV-C
Short Ground Detection (SGD)
VBAT
RL
ISGD
SW1
OUT
Power
MOS
RG
DIAG_
OLD/OFDn
SO
GND
·When normal load is connected (SW1 is on)
The output voltage VOUT is determined by the divided voltage between RL (normal load) and RG (OUT-GND impedance) and it is
detected as SGD when VOUT is VSGD_DET or less.
RG for detecting SGD is given roughly by the following equation.
푉
푆퐺퐷_퐷ꢅ푇
ꢄ퐺 ≤
∗ ꢄ퐿
푉퐵퐴푇 − 푉
푆퐺퐷_퐷ꢅ푇
VBAT: Battery voltage
VSGD_DET: Short ground detection voltage 0.3 V (Min)
·When the load is open (SW1 is off)
The output voltage VOUT is obtained from output source current ISGD that flows into RG and it is detected as SGD when VOUT is
VSGD_DET or less.
RG for detecting SGD is given by the following equation.
푉
푆퐺퐷_퐷ꢅ푇
ꢄ퐺 ≤
퐼푆퐺퐷
VSGD_DET: Short ground detection voltage 0.3 V (Min)
ISGD: Output source current when SGD function is active 40 μA (Max)
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BD8LD650EFV-C
Short Ground Detection (SGD) – continued
When the output is off, SGD can be enabled and diagnosed by one SPI access of write and read access (RE = 1, WE = 1) to
DIAG_SGD register (B, F in the figure). Diagnostic is output to SO at the next SPI access. At this time, SGD returns to be inactive
(D, H in the figure). When OUTn voltage is VSGD_DET or less, SGD is diagnosed as detected and the error flag inside the IC outputs
"0" (C in the figure). If OUTn voltage is VSGD_REL or more, SGD is diagnosed as undetected and the error flag output '1' (G in the
figure).
*n shows ch number
[V]
OUT Enable(Note 1)
[t]
[t]
[t]
[t]
[t]
0
[V]
DIAG_SGD
R/W Access
Return
Response
DIAG_SGD
R/W Access
Return
Response
CSB
for SPI
0
B
D
F
H
SGD Enable(Note 2)
'0'
'1'
'0'
'1'
'0'
A. Occur
"GND Short"
E. Improve
"GND Short"
[V]
VBAT
OUTn
VSGD_REL
VSGD_DET
0
C
G
SGD Error(Note 3)
'0'
(Detect)
'1'
'1'
'1'
'1'
(No Detect)
(Note 1) Output on/off control signal. This signal is controlled by IN65, IN43, IN21 or OUT_CTRL register.
(Note 2) Internal enable signal. High and Low indicates enabled and disabled, respectively. This signal is controlled by write access to DIAG_SGD register.
(Note 3) Internal error flag. High and Low indicates error undetected and detected, respectively. Also the flag outputs High during disable. This signal can be retrieved
to SO by read access to DIAG_SGD register.
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Application Example
VDDIO
VDD
VBAT
CVDDIO
CVDD
VDDIO
VDD
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
I/O
Control Logic
RIDLE
RIN21
RIN43
IDLE
IN21
IN43
UVLO
I/O
(IDLE, IN,
Limp Home)
Mode
Control
Control,
Diagnostic
and
protective
Functions
Limp
Home
OCD
TSD
MCU
Input
Register
RCSB
RSCLK
RSI
CSB
SCLK
SI
UVLO
OLD
OFD
SGD
SPI
Control
Active
Clamp
I/O
(SPI)
Gate
Driver
Diagnosis
Register
RSO
SO
COUT1 COUT2
COUT3
COUT4
COUT5
COUT6
COUT7
COUT8
GND
Selection of Components Externally Connected
Symbol
RIDLE
Value
1 kΩ
Purpose
Register for microcontroller protection against negative voltage surge
Register for microcontroller protection against negative voltage surge
Register for microcontroller protection against negative voltage surge
Capacitor for noise removal on the power supply line
RIN21, RIN43, RIN65
RCSB, RSCLK, RSI, RSO
CVDDIO, CVDD
COUT1 to COUT8
1 kΩ
1 kΩ
0.1 μF
0.1 μF
Capacitor for ESD surge and BCI protection
As a precaution in selecting a COUT, current flows from the capacitor when the switch is turned on. Depending on the capacitance,
over current protection may be detected. This current depends on the slew rate setting, over current protection setting, and VBAT
voltage. As a reference, capacitance that can be used with VBAT = 18 V without over current protection when the switch is turned
on is shown in the below table.
VBAT = 18 V
Over Current Protection Capacitance value that over current protection
Slew Rate setting
setting
is not detected (Max)
0.22 μF
OCPCTRLn = 0
OCPCTRLn = 1
OCPCTRLn = 0
OCPCTRLn = 1
OCPCTRLn = 0
OCPCTRLn = 1
SRCTRLn[1:0] = 00
SRCTRLn[1:0] = 01
SRCTRLn[1:0] = 10
0.22 μF
0.47 μF
0.83 μF
0.68 μF
1.5 μF
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BD8LD650EFV-C
I/O Equivalence Circuits
Pin No.
Pin Name
I/O Equivalence Circuit
VDDIO
100 kΩ
100 kΩ
IDLE
1
IDLE
GND
VDDIO
100 kΩ
1 kΩ
CSB
2
CSB
GND
VDDIO
SCLK
SI
IN65
IN43
IN21
SCLK
SI
IN65
IN43
IN21
1 kΩ
3, 4
16 to 18
100 kΩ
GND
VDDIO
50 Ω
SO
5
SO
GND
6, 15
GND
-
OUT1 to OUT8
7 to 14
OUT1 to OUT8
GND
19
20
VDD
-
-
VDDIO
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BD8LD650EFV-C
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
7. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
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Operational Notes – continued
10. Regarding the Input and Output Pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 58. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Function (TSD)
This IC has a built-in thermal shutdown function that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD function that will turn OFF power output pins. When the
Tj falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD function operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD function be used in a set design or for any purpose other than protecting the IC from
heat damage.
13. Over Current Protection Function (OCP)
This IC incorporates an integrated overcurrent protection function that is activated when the load is shorted. This
protection function is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection function.
14. Active Clamp Operation
The IC integrates the active clamp function to internally absorb the reverse energy EL which is generated when the
inductive load is turned off. When the active clamp operates, the thermal shutdown function does not work. Decide a
load so that the reverse energy EL is active clamp tolerance EAS (refer to Figure 1.), ES,AS (refer to Figure 2.) or under
when inductive load is used.
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BD8LD650EFV-C
Operational Notes – continued
15. Power Supply Steep Fluctuation
If the voltage of the power supply pin (VDD) falls sharply, the output pin (OUT) may temporarily turn off as shown in
Figure 55. If the power supply pin is expected to fall sharply, take measures such as inserting a capacitor between
the power supply pin and the ground pin so that it falls within the recommended usage range shown in Figure 56.
2.5
VDD[V]
2.0
Deprecated use range
VDD(FALL)
VDD
1.5
1.0
0.5
0.0
tVDD(FALL)
0
t
VOUT[V]
Recommended use range
≈ VBAT
VOUT
≈ 0 V
0
t
0
10
20
30
tVDD(FALL) [μs]
Figure 59. Output OFF operation when power supply
fluctuates sharply
Figure 60. Recommended use range
16. GND Pin Connection
Connect all ground pins to ground.
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BD8LD650EFV-C
Ordering Information
B D 8 L D 6
5
0 E F V
-
CE 2
8: 8ch
Package
Product Rank
L: low side switch
EFV: HTSSOP-B20
C: For Automotive
Packaging Specification
E2: Embossed tape and reel
Marking Diagram
HTSSOP-B20 (TOP VIEW)
Part Number Marking
LOT Number
8 L D 6 5 0
Pin 1 Mark
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BD8LD650EFV-C
Physical Dimension and Packing Information
Package Name
HTSSOP-B20
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BD8LD650EFV-C
Revision History
Date
Revision
001
Changes
26.Aug.2022
New Release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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