BD9G201EFJ-LB [ROHM]
本IC为可在电源电压4.5V～42V的范围内工作的内置高边FET的二极管整流型降压开关稳压器。通过电流模式控制实现了高速负载响应和简便的相位补偿设定。可用于小型二次电源，例如：可从12V、24V等电源输出3.3V/5V的降压电压。还具备与外部CLK同步的功能，可进行噪声管理。;
| 型号： | BD9G201EFJ-LB |
| 厂家： | 
ROHM |
| 描述： | 本IC为可在电源电压4.5V～42V的范围内工作的内置高边FET的二极管整流型降压开关稳压器。通过电流模式控制实现了高速负载响应和简便的相位补偿设定。可用于小型二次电源，例如：可从12V、24V等电源输出3.3V/5V的降压电压。还具备与外部CLK同步的功能，可进行噪声管理。 开关 二极管 稳压器 |
| 文件： | 总31页 (文件大小：1620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
4.5V to 42V Input Voltage Range 1.5A Output Current Integrated FET
1ch Buck Converter
BD9G201EFJ-LB BD9G201UEFJ-LB
General Description
Key Specifications
This is the product guarantees long time support in
Industrial market.
◼ Input Voltage range :
◼ Reference voltage precision
4.5V to 42V
(Ta= 25°C) ±1.5%
(Ta= -40°C to +105°C) ±2.0%
◼ Max Output Current : 1.5A(Max)
BD9G201(U)EFJ-LB is a buck converter with built-in
high side MOSFET. It has an input voltage range of
4.5V to 42V. Current mode architecture provides fast
transient response and a simple phase compensation
setup.
◼ Operating Temperature range :
-40°C to +105°C
Package W (Typ) x D (Typ) x H (Max)
HTSOP-J8ES
4.90mm x 6.00mm x 1.00mm
The IC is mainly used as a secondary side power
supply: for example, a step-down output of 3.3V/5V can
be produced from voltage power supply such as 12V or
24V. In addition, it has a synchronization function with
an external CLK that provides noise management.
Features
◼
Long Time Support Product for Industrial
Applications
◼
◼
◼
Integrated Nch MOSFET
Synchronizes to external clock 250kHz to 500kHz
ON/OFF Control through EN Terminal
(Standby current of 0µA)
◼
◼
Small package(HTSOP-J8ES)
LowDrop Out operation
HTSOP-J8ES
Applications
◼ Industrial distributed-power applications
Typical Application Circuit
0.1µF
5V/1.5A
L1: 22µH
LX
VOUT
VCC
VCC
COUT
: 47µF/16V
CVCC
: 10µF/50V
D1
BST
EN
GND
VC
R4
R5
EN
160kΩ
0.01μF
SYNC
FB
SYNC
4.7kΩ
30kΩ
Figure 1. Typical Application Circuit
〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays
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Pin Configuration
(TOP_VIEW)
LX 1
GND 2
VC 3
8 VCC
7 BST
6 EN
THERMAL
PAD
5 SYNC
FB 4
Figure 2. Pin Configuration
Pin Description
Pin No.
Pin Name
Description
1
2
3
4
5
6
7
8
-
LX
GND
Switching terminal
Ground terminal
VC
Error amplifier output terminal
Feedback input terminal
External clock input terminal
Enable terminal
FB
SYNC
EN
BST
Terminal for boot-strap capacitor
Power supply terminal
VCC
THERMAL PAD
PAD for heat dissipation. Always connect to GND.
Block Diagram
ON/OFF
EN
VCC
10μA
TSD
+
UVLO
REF
REG
OCP
CHG
-
1.8V
Current
Sense
ENUVLO
shutdown
BST
Current
Sense AMP
Nch FET SW
Error
FB
AMP
-
+
-
140mΩ
RꢀꢀQ
Sꢀꢀꢀ
0.8V
Σ
+
VOUT
+
LX
10Ω
Soft
Start
Maxduty
Logic
GND
Oscillator
SYNC
VC
Figure 3. Block Diagram
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Description of Blocks
1. REF
This block generates the reference voltage.
2. REG
Regulator for internal circuit power supply.
3. CHG
Regulator for bootstrap capacitor charging.
4. TSD
Thermal Shutdown Protection Circuit
When it detects the temperature exceeding Maximum Junction Temperature (Tj= 150°C), it turns off the output FET,
and resets SoftStart circuit. It has a hysteresis function. When the temperature is decreased, the chip automatically
returns to normal operation.
5. UVLO
Under Voltage Lock-Out Circuit
This prevents internal circuit error during increase and decrease of power supply voltage.
It monitors VCC terminal voltage. When VCC voltage becomes UVLO and below, it turns OFF output FET. SoftStart
circuit also resets during this time. This circuit has a hysteresis.
6. ENUVLO
If the voltage from this terminal is less than 0.3V, IC operation is OFF. If it is between 0.3V and 1.4V, internal REG
circuit turns ON. If it is greater than 1.8V(Typ), the IC is operational and a hysteresis generation current of 10 μA (Typ)
is sourced from the internal circuit. To turn off the IC, source current should be removed.
When the situation without a signal to control EN terminal at the time of startup is assumed, pull down EN terminal by
pull down resistor to prevent becoming the high impedance.
Arbitrary UVLO is possible by connecting EN terminal to a voltage divider from the input voltage.
7. ErrorAMP
This is an error amplifier circuit that detects the output signal, and outputs PWM control signal.
Internal reference voltage is set to 0.8V(Typ).
8. SoftStart
This is a circuit that gently raises the output voltage of the DC / DC converter to prevent in-rush current during start-up.
SoftStart Time is 8ms (Typ) when the IC operates with the 300 kHz (Typ) internal clock.
When the IC operates with an external clock, SoftStart Time is changed according to the oscillator frequency.
9. Oscillator
This is a oscillation circuit with an operating frequency fixed to 300 kHz(Typ).
By inputting external CLK to the SYNC terminal, synchronous operation of 250 kHz to 500 kHz can be achieved.
When used in self-running mode, please connect SYNC terminal to GND.
10. Current Sense AMP
This is a voltage - pulse width converter.
It compares the voltage depending on the current of FET SW through the sum of the error amplifier output voltage and
the slope ripple. The output then controls the width of the output pulse and outputs it to the driver.
11. Nch FET SW
It should be used within OCP threshold 2.0A(Min) including the output current and ripple current of the inductor.
12. OCP
The IC has a over current protection to protect the Nch FET from over current. When OCP is detected twice
sequentially, the device will stop certain period of time and restart automatically.
13. MaxDuty logic
When Nch FET SW continues being turned ON in continuous 8 cycles, the high side FET will be turned off forcibly.
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Absolute Maximum Ratings (Ta= 25°C)
Parameter
Symbol
Limit Rating
Unit
VCC-GND
VCC
VBST
VBST-LX
VEN
45
V
V
BST-GND
50
BST-LX
7
V
EN-GND
45
V
LX-GND
VLX
45
V
FB-GND
VFB
7
V
VC-GND
VVC
7
7
V
SYNC-GND
VSYNC
Topr
V
Operating Temperature range
Storage Temperature range
Maximum Junction Temperature
-40 to +105
-55 to +150
150
°C
°C
°C
Tstg
Tjmax
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an
open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in
case the IC is operated over the absolute maximum ratings
Thermal Resistance(Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
HTSOP-J8ES
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
206.4
21
45.2
13
°C/W
°C/W
ΨJT
(Note 1)Based on JESD51-2A(Still-Air)
(Note 2)The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3)Using a PCB board based on JESD51-3.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3mm x 76.2mm x 1.57mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70μm
(Note 4)Using a PCB board based on JESD51-7.
Thermal Via(Note 5)
Layer Number of
Material
Board Size
114.3mm x 76.2mm x 1.6mmt
2 Internal Layers
Measurement Board
Pitch
Diameter
4 Layers
FR-4
1.20mm
Φ0.30mm
Top
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
70μm
Footprints and Traces
70μm
74.2mm x 74.2mm
35μm
74.2mm x 74.2mm
(Note 5) This thermal via connects with the copper pattern of all layers..
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Recommended Operating Ratings (Ta= -40°C to +105°C)
Rating
Parameter
Power Supply Voltage
Symbol
Unit
Min
4.5(Note 6)
0.8 (Note 7)
-
Typ
Max
VCC
VOUT
IOUT
-
-
-
-
-
-
42
V
V
VCC (Note 8)
Output Voltage
Output Current
1.5
A
SYNC Terminal Input Frequency
Input Capacitance
Inductance
fSYNC
kHz
μF
μH
250
500
(Note 9)
CIN
2.2
-
-
L(Note 10)
11
(Note 6) Voltage more than 4.65V is necessary for IC start. The IC can operate to 4.5V after IC start.
(Note 7) Restricted by Min On Time 200ns(Max).
(Note 8) Upper limit restricted by MaxDuty.
(Note 9) The capacitance is selected in the range including temperature characteristics and bias voltage effect. Refer to P18.
(Note10) Restricted by output voltage setting. Refer to P17.
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Electrical Characteristics (Unless otherwise specified: Ta= 25°C, VCC= 12V, EN= 3V)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
Circuit Current
Standby Current
Ist
-
-
0
10
µA
VEN= 0V
Operating Current
Under Voltage Lock Out (UVLO)
Detect Voltage
Icc
1.2
2.4
mA
VFB= 1.2V
Vuv
VCC down sweep
3.65
50
4.00
200
4.35
300
V
Hysteresis Width
Oscillator
Vuvhy
mV
Oscillating Frequency
MaxDuty Cycle
fosc
270
300
330
kHz
%
Dmax
95.0
97.0
99.9
VSYNC= 0V
Error Amp
VFB
VFBT
IFB
0.788
0.784
-1.0
0.800
0.800
0
0.812
0.816
+1.0
V
V
Ta= 25°C
FB Threshold Voltage
Ta= -40°C to +105°C
VFB= 3.0V
FB terminal Input Current
FB terminal Leak Current
SoftStart Time
µA
µA
ms
Ileak
tsoft
-1.0
0
+1.0
VFB= 0V
5.6
8.0
10.4
VSYNC= 0V
Output Block
Nch FET ON Resistance(High-Side)
Nch FET ON Resistance(For Pre-charge)
Over Current Detect Threshold
RonH
RonL
Iocp
-
-
140
10
3
-
-
-
mΩ
Ω
2
A
CTL
EN Terminal Internal REG ON-Threshold
VENON
VENUV
IEN
0.3
1.65
9.0
-
1.4
1.95
11.0
V
V
EN Terminal UVLO Threshold
EN Terminal Source Current
1.80
10.0
µA
VEN= 3V
SYNC
SYNC Terminal Pulse Voltage High
VSYNCH
VSYNCL
ISYNC
2.0
-0.3
6
-
-
5.5
+0.8
24
V
V
SYNC Terminal Pulse Voltage Low
SYNC Terminal Input Current
12
µA
VSYNC= 3V
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Detailed Description
External CLK for SYNC Function
The SYNC terminal can be used to synchronize by input an external CLK signal(250kHz to 500kHz). To implement the
synchronization feature, connect a CLK to SYNC terminal. Input CLK signal amplitude must have transition lower than 0.8V
and higher than 2.0V on the SYNC terminal and have an ON and OFF time greater than 100ns. The rising edge of the LX
will be synchronized to the falling edge of SYNC terminal signal after 3 SYNC input pulse count. During the external CLK is
stop, the device transitions to self-running mode after 7 μs.
SYNC
Set the latch for
synchronization
_
SYNC LATCH
about
μs
LX
7
Figure 4. Frequency Synchronization Function Timing Chart
In the Case of not Using the Synchronization Function
Although the SYNC terminal is internally pulled down by a resistor, it is recommended to connect SYNC pin to ground if the
synchronization function is not in use.
SYNC
GND
Figure 5. Circuit Diagram of SYNC Pin Not in Use
SoftStart Time When using External CLK
The SoftStart Time is synchronized with a CLK.
If synchronization is used by SYNC terminal, the SoftStart Time is expressed by the equation below.
300
tSoft
=
8[ms]ꢀꢀ
fosc_ex
Where:
tsoft is the SoftStart time [ms],
fosc_ex is the external clock [kHz]
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Detailed Description - Continued
OCP Operation
The IC has built-in over current protection (OCP) for protecting the FET.
When OCP is detected twice sequentially, the IC is turned off, the IC turns on after certain period time stop.
In the case that the synchronization function is not used, it becomes 13ms at operating frequency 300 kHz.
When using synchronization function at the time of start up, latch stop time is determined by the external CLK frequency
through the following expression.
1
Tocp
=
4000ꢀ[ꢀms]
fosc_ex
Where:
Tocp is the Latch stop time [ms]
fosc_ex is the external CLK frequency [kHz]
VC voltage discharged
by OCP latch
OCP threshold
VC
VC voltage rising by
output connect to GND
force the High side FET OFF
by detecting OCP current
(pulse by pulse protection )
LX
output connect to GND
VOUT
OCP
set the OCP latch by detecting
the OCP current 2 times sequencially
OCP latch reset 13ms after
OCP_LATCH
Figure 6. Timing Chart at OCP Operation
External UVLO Setting
The high precision reset function is built in at the EN terminal and arbitrary low-voltage malfunction prevention is possible
by connecting EN terminal to a voltage divider from the input voltage.
If in use, please set R4 and R5 to arbitrary voltage of IC turned on (Vstart) and turned off (Vstop) through the expression
below.
LX
VOUT
VCC
BST
EN
VCC
GND
VC
R4
R5
EN
SYNC
FB
SYNC
Figure 7. External UVLO Setup
Vstart −Vstop
R4 =
ꢀꢀ ꢀ[Ω]
IEN
VEN R4
R5 =
ꢀꢀ[ꢀΩ]
Vstart −VEN
IEN: EN terminal source current 10μA (Typ) VEN: EN terminal output on threshold 1.8V (Typ)
As for the example above, when VCC voltage at which the IC turns on is 15V and turns off at 14V, R4 would be
100 kΩ and R5 would be 13.6 kΩ for the voltage divider in the diagram.
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Detailed Description - Continued
The countermeasure of voltage generation over output voltage in less than 4.9 V output voltage application
IC produces at most 100μA to the output via LX terminal from BST terminal which is drive power source terminal at the
following condition
Output of IC can generate at 4.9V max from BST voltage, so according to output voltage setting, output voltage is greater
than setting output voltage.
In order to prevent over 100μA load in output or set a resistance level that feedback resister current is more than 100μA.
[Conditions]
IC internal regulator is operating when switching is no operation.
For example, input voltage is less than internal UVLO threshold, EN terminal voltage is condition of internal REG ON.
ON/OFF
EN
VCC
10μA
UVLO
TSD
REF
CHG
REG
OCP
+
-
ENUVLO
1.8V
Current
Sense
shutdown
MAX:4.9V
BST
Current
Sense AMP
Nch FET SW
Error
AMP
FB
+
-
RꢀꢀQ
Sꢀꢀꢀ
OFF
OFF
-
0.8V
Σ
+
LX
MAX:100uA VOUT
+
Soft
Start
Maxduty
Logic
GND
Oscillator
SYNC
VC
Figure 8. Current Path at the Time of the SW off and Internal REG ON
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Detailed Description - Continued
LowDrop Out Operation
For the BST terminal charge that is the drive voltage of the High-side Nch FET, input and output voltage limit is set by
MaxDuty.
The IC has two operation modes: Steady operation mode and MaxDuty mode, to cope with wide duty output.
When the IC is in steady operation mode, FET is switching every period. When the IC is in MaxDuty mode, after ON
pulse continue 8, FET is forced off in 700ns.
Operation Duty is calculated as follows by input and output voltage to use and a load.
VOUT
Don =
100
%
VCC − RonH IOUT
MaxDuty is calculated as follows by forced-off time (Typ: 300ns) and operating frequency.
Don_max =
(
1− 300n fosc
)
100
%
In the case of 300 kHz operating frequency where the SYNC terminal is not used, MaxDuty for steady operation is 91%.
If duty requirement is beyond this level, then shift to MaxDuty mode.
During MaxDuty mode, the IC is enabled to output 100% duty for 8 periods of internal CLK and exists a forced-off
section of 700nsec.
MaxDuty in the MaxDuty mode is expressed by the following equation.
700n fosc
Don_ max 2 = 1−
100
%
8
In MaxDuty mode, switching operation does not occur every period, so the inductor ripple current and output ripple
voltage become bigger than steady operation.
Output voltage drops in the case of duty is higher than Don_max2.
MinDuty
There are output voltage restrictions by MinDuty.
The MinDuty required is as follows with worst min on time (200n).
Don_min =
(
200n fosc
)
100
%
Heat generation for the Light-Load
For the light-load, Pre-charge Nch FET of 10Ω (typ) in this IC pulls out charge into GND, and BST capacitor is charged.
When Pre-charge Nch FET pulls out charge, this IC has a loss by ON resistance 10Ω of Pre-charge Nch FET and the
flowing current.
The loss and heat generation may be increased with the condition of high input voltage, high output voltage and low
inductance value. Confirmation of efficiency and heat generation for the light-load is recommended.
When the heat generation for the light-load rises high, high inductance value is recommended.
The heat generation is decreased by dropping down the ripple current.
80
VCC
L= 15µH
L= 22µH
70
60
50
40
30
20
10
0
High-side
Nch FET
LX
VOUT
L= 33µH
L= 47µH
Pre-charge
Nch FET
0
200
400
600
800
1000
1200
1400
1600
Output Current [mA]
Figure 9. Current Passes when Light-Load
Figure 10. Junction Temperature vs Output Current
(VCC =24V, Vout= 12V)
(Rohm Board (4layers 40mm x 40mm) )
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Performance Curves (Reference Data)
(Unless Otherwise Specified, Ta= 25°C, VCC= 12V)
25°C
Temperature= 105°C
-40 °C
VCC= 12, 24, 42 V
Figure 11. Standby Current vs Temperature
Figure 12. Operating Current vs Input Voltage (VFB= 1.2V)
reset voltage
detect voltage
Figure 13. Input Circuit Current vs Temperature (VFB= 1.2V)
Figure 14. UVLO Threshold vs Temperature
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Performance Curves (Reference Data) - Continued
Figure 16. MaxDuty vs Temperature
Figure 15. Frequency vs Temperature
Figure 17. FB Threshold vs Temperature
Figure 18. FB Threshold vs Input Voltage
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Performance Curves (Reference Data) - Continued
Figure 19. Soft Start Time vs Temperature
Figure 20. High Side FET Resistance vs Temperature
Figure 21. Precharge FET Resistance vs Temperature
Figure 22. OCP Detect Current vs Temperature
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Performance Curves (Reference Data) – Continued
Figure 23. ENUVLO Threshold vs Temperature
Figure 24. EN Source Current vs Temperature
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Reference Characteristics of Typical Application Circuits
0.1µF
5V/1.5A
L1: 22µH
LX
VOUT
VCC
BST
VCC
COUT
: 47µF/16V
CVCC
: 10µF/50V
D1
GND
VC
R4
R5
EN
EN
160kΩ
0.01μF
SYNC
FB
SYNC
4.7kΩ
30kΩ
Figure 25. Typical Application Circuits
CLF12577NIT - 220M
Parts :
L1
: TDK
22μH
CVCC
COUT
D1
: murata
: murata
: Rohm
GRM32ER71H106K
GRM32EB31C476K
RB050LAM-60TFTR
10μF / 50V
47μF / 16V
100
90
80
70
60
50
40
30
20
10
0
VCC=12V
VCC=24V
VCC=36V
VCC=42V
1
10
100
1000
10000
IOUT [mA]
Figure 26. Efficiency vs IOUT
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Reference Characteristics of Typical Application Circuits - Continued
Phase
Phase
Gain
Gain
Figure 28. Frequency Characteristics
(IOUT= 1.5A)
Figure 27. Frequency Characteristics
(IOUT= 0.5A)
EN 5V/div
EN 5V/div
LX 10V/div
LX 10V/div
Input Current 200mA/div
Input Current 200mA/div
VOUT 2V/div
VOUT 2V/div
2msec/div
2msec/div
Figure 29. Startup Waveform (IOUT= 0.5A)
Figure 30. Shutdown Waveform (IOUT= 0.5A)
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Application Components Selecting Method
(1) Inductor
Shielded type that meets the current rating (current value from the
Ipeak below), with low DCR (Direct Current Resistance element) is
recommended.
The value of inductor has an effect in the inductor ripple current which
causes the output ripple.
ΔIL
In the same formula below, this ripple current can be made small with
a large value L of the inductor or as high as the switching frequency.
Peak current of internal FET is needed to be lower than OCP
threshold 2.0A (min).
Ipeak= Iout + ⊿ IL/2 [A]
(1)
Vout
VCC
Figure 31. Inductor Current
VCC-Vout
1
f
⊿ IL=
x
x
[A]
(2)
L
Where:
⊿ IL is the Inductor ripple current, f is switching frequency
For design value of inductor ripple current, please carry out design tentatively with about 20% to 50% of the maximum
output current of the IC.
The minimum value of inductance is shown in the following figure. Inductor is selected over the value of the graph.
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
Output Voltage [V]
Figure 32. Output Voltage vs inductance (min)
25
30
35
40
When current that exceeds the inductor rating flows in to the inductor, the inductor causes a magnetic saturation which
in turn causes a decline in efficiency and output oscillation. Please choose a inductor with a sufficient margin so that
peak current does not exceed rating current of the inductor.
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Application Components Selecting Method - Continued
(2) Input Capacitor
This IC needs an input decoupling capacitor. It is recommended a low ESR ceramic capacitor over 2.2μF.
The capacitance is selected considering temperature characteristics and bias voltage effect.
The input ripple voltage is determined by input capacitance (CIN). Because the IC input voltage is decreased, consider
input voltage range including ripple voltage. The input ripple voltage is estimated by the following.
IOUT(max) VOUT
Vin =
+ (IOUT(max) RESR(max) )
[Vp-p] (3)
CIN f VCC
Please notice that frequency is 1/8 times in maxduty mode when the difference between input voltage and output
voltage is small. Please refer to Detailed Description for the condition of maxduty mode.
The input capacitance has a sufficient value that keep input voltage in the recommended range.
Please confirm the characteristic of RMS ripple current – temperature.
RMS ripple current (IRMS) is following.
VOUT
VIN
VOUT
VIN
[ARMS
]
(4)
IRMS IOUT
1−
IRMS has a maximum value when VIN = 2 x VOUT
IOUT
IRMS
[ARMS
]
(5)
2
Choose an input capacitor that have enough temperature margin at the IRMS
.
(3) Output Capacitor
In order to reduce output ripple, a ceramic capacitor of low ESR is recommended.
Also, for capacitor rating, take into consideration the DC bias characteristics. Use a capacitor with maximum rating of
sufficient margin with respect to the output voltage.
Output ripple voltage is obtained through the following formula.
1
Vpp = ⊿ IL x
+ ⊿ IL x RESR
[V]
(6)
2π x f x COUT
Please set the value within allowable ripple voltage.
Confirm rush current(Irush) of the start up because the output capacitance has an effect of Irush
Irush is estimated in the following.
.
COUT VOUT fosc _ ex
Irush
+ IL + IOUTstart [A] (7)
Tsoftstart fosc
Where:
Tsoftstart is soft start time
fosc is inner frequency 300kHz
fosc_ex is SYNC frequency (If the SYNC function is not used, fosc_ex equals to fosc
IOUTstart is output current when IC is start up.
)
At least, It is required that Irush is less than 2A that is minimum value of OCP threshold.
The rush current is added the current caused by ERROR AMP delay actually.
Please confirm that start up rush current is lower than 2A.
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Application Components Selecting Method - Continued
(4) Output Voltage Setting
The ERROR AMP internal reference voltage is 0.8V. Output voltage is determined by next formula.
VOUT
ERROR AMP
R1
R2
(R1 + R2)
R2
FB
VOUT =
x 0.8 [V] (8)
VREF
0.8V
Figure 33. Voltage Feedback Resistance Setting Method
(5) Bootstrap Capacitor
Please connect a 0.1µF (Ceramic Capacitor) between BST and LX pin.
Because the absolute rating between BST-LX becomes 7V, 10V or more are recommended.
(6) About the adjustment of DC / DC Converter Frequency Characteristics
Role of phase compensation element C1, C2, R3
Vout
LX
VCC
BST
EN
VCC
GND
VC
EN
C2
C1
R3
SYNC
FB
SYNC
Figure 34. Phase Compensation Element
Stability and responsiveness of the loop are controlled through the VC terminal.
The combination of zero and pole that determines the stability and responsiveness is adjusted through the combination
of resistor and capacitor connected in series to the VC terminal.
The DC Gain of the Voltage Feedback Loop can be calculated using the following formula.
VFB
Adc = RI x GCS x AEA
x
Vout
Here, VFB is the Feedback Voltage (0.8V). AEA is the Voltage Gain of Error amplifier (Typ: 80dB),
GCS is the Trans-conductance of Current Detect (Typ: 10A / V), and RI is the Output Load Resistance value.
There are 2 poles in the control loop of this DC / DC.
The first occurs in the output resistance of phase compensation capacitor (C1) and error amplifier, the other one occurs
in the output capacitor and load resistor.
These poles appear in the frequency written below.
GEA
fp1
=
2π x C1 x AEA
1
fp2 =
2π x COUT x RI
GEA is the trans-conductance of Error amplifier (Typ: 220µA / V).
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Application Components Selecting Method - Continued
This control loop has one zero. With the zero which occurs because of phase compensation capacitor C1 and phase
compensation resistor R3, the frequency as shown below appears.
1
fz1 =
2π x C1 x R3
Also, if in this control loop the output capacitor is large, and that the ESR (RESR) is also large, has additional zero.
This ESR zero that occurs due to ESR of output capacitor and its capacitance can be calculated as follows.
1
fZESR
=
2π x COUT x RESR
(fZESR : Zero frequency of ESR)
In this case, the 3rd pole is determined with the 2nd phase compensation capacitor (C2) and phase correction resistor
(R3) is used in order to correct the ESR zero results in the loop gain.
This pole exists in the frequency shown below.
1
(fp3 : Pole frequency that corrects fZESR
)
fp 3 =
x
x
R3
π
2
C2
The target of phase compensation design is to acquire necessary band and phase margin.
It set that cross-over frequency (bandwidth):fc at which loop gain of the return loop becomes “0” .
When the cross-over frequency becomes low, power supply fluctuation response, load response, etc worsens.
when cross-over frequency becomes high, loop of phase margin becomes decrease.
In order to ensure the phase margin, cross-over frequency needs to set 1/20 or below of the switching frequency.
Selection method of Phase Compensation constant is shown below.
1. Phase compensation resistor (R3) is selected in order to set the desired cross-over frequency.
Calculation of R3 is done using the formula below.
x
π
x
2
COUT
fc
Vout
VFB
x
R3 =
x
GEA
GCS
2. Select phase compensation capacitor (C1).
By matching the zero of compensation to 1/4 and below of the cross-over frequency, sufficient phase margin can be
acquired. C1 can be calculated using the following formula.
4
C1
>
2
π x
x
fc
R3
3. Examination whether the second phase compensation capacitor C2 is necessary or not is done.
If the ESR zero of the output capacitor is smaller than half of the switching frequency, a second phase compensation
capacitor is necessary. In other words, it is the case wherein the condition below happens:
1
fs
2
<
2
x
π x
COUT RESR
In this case, add a second phase compensation capacitor C2, and match the frequency of the third pole fp3 to the
frequency of ESR zero.
C2 can be acquired using the following formula.
x
COUT
RESR
=
C2
R3
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Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous mode operations. They should
not be used if the device is working in the discontinuous conduction mode. IC internal loss is shown below.
1) Conduction loss: Pcon= IOUT2 x RonH x VOUT / VCC
2) Switching loss: Psw= 19×10-9 x VCC x IOUT x fsw
3) Gate charge loss: Pgc= 9.0×10-9 x fsw
4) Quiescent current loss: Pq= ICC x VCC
IOUT is the output current , RonH is the on-resistance of the high-side NchFET, VOUT is the output voltage.
VCC is the input voltage, fsw is the switching frequency.
Power dissipation of IC is the sum of above dissipation, and shown below.
Pd= Pcon + Psw + Pgc + Pq
Tj is shown below.
Tj= Ta + θja x Pd
The junction temperature is not more than Tjmax =150°C, so temperature design is needed sufficient margin.
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PCB Layout
Layout is a critical portion of a good power supply design. Here are several signals paths that conduct fast changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power
supply’s performance. To help eliminate these problems, the VCC terminal should be bypassed to ground with a low ESR
ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor, VCC terminal,
and anode of the catch diode.
The thermal pad should be connected to any internal PCB ground plane using multiple VIAs directly under the IC. The LX
pin should be routed to the cathode of the catch diode and to the output inductor. Since the LX connection is the switching
node, the catch diode and output inductor should be located close to the LX pin, and the area of the PCB conductor is
minimized to prevent excessive capacitive coupling.
Output
VOUT
Capacitor
Topside
Ground
Area
Output
Catch
Diode
Inductor
Input Bypass
Capacitor
LX
VCC
BST
VCC
Route BST Capacitor
Trace on another layer to
provide with wide path for
GND
CBST
topside ground
Compensation
Network
EN
VC
FB
SYNC
Signal VIA
Thermal VIA
Resistor
Divider
Figure 35. Reference Evaluation Board Pattern
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I/O Equivalent Schematic
Pin.
No
Pin.
Name
Pin.
No
Pin.
Name
Pin Equivalent Schematic
Pin Equivalent Schematic
1
2
7
8
LX
BST
VCC
SYNC
GND
GND
BST
VCC
5
SYNC
LX
GND
VCC
EN
VC
3
VC
6
EN
GND
GND
FB
4
FB
GND
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Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
In addition, including transition phenomenon, it prevents all pin except GND pin from not becoming lower than GND
pin voltage.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may
result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the
board size and copper area to prevent exceeding the maximum junction temperature rating.
6.
7.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8.
9.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
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Operational Notes – Continued
10. Inter-Pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 36. Example of Monolithic IC Structure
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
14. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and the maximum junction temperature rating are all
within the Area of Safe Operation (ASO).
15. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls
below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
16. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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Ordering Information
B
D
9
G
2
0
1
x
E
F
J
-
L
B
E
2
Production Line
None: Production line A
U:Production line B(Note11)
Package
EFJ : HTSOP-J8ES
Part
Number
Product Class
LB: for Industrial applications
Packaging Specification
E2: Embossed tape and reel
(Note11)For the purpose of improving production efficiency, this product has multi-line configuration. Electric characteristics noted in this datasheet does not
differ between the 2 lines. The additional production line B is recommended for new product.
Marking Diagram
BD9G201EFJ-LB
HTSOP-J8ES(TOP VIEW)
BD9G201UEFJ-LB
HTSOP-J8ES(TOP VIEW)
Part Number Marking
LOT Number
Part Number Marking
LOT Number
D 9 G 2 0 1
9 G 2 0 1 U
Pin 1 Mark
Pin 1 Mark
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Physical Dimension and Packing Information
Package Name
HTSOP-J8ES
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Revision History
Date
Revision
001
Changes
09.May.2018
New release
P1-28 Added a part name for production line B to the hedder
P26 Added an information for the additional production line to Ordering Information
P26 Added a marking diagram for production line B
P1 Changed the model name in the description of General Description so that it includes
BD9G201UEFJ-LB.
29.Mar.2022
30.Aug.2022
002
003
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
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BD9G201EFJ-M
本IC为可在电源电压4.5V～42V的范围内工作的内置高边FET的二极管整流型降压开关稳压器。通过电流模式控制实现了高速负载响应和简便的相位补偿设定。可用于小型二次电源，例如：可从12V、24V等电源输出3.3V/5V的降压电压。还具备与外部CLK同步的功能，可进行噪声管理。
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BD9G201UEFJ-LB
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