BD9P205MUF-C_技术文档

Nano Pulse Control^TM

Datasheet

3.5 V to 40 V Input, 2 A

Single 2.2 MHz Buck DC/DC Converter

For Automotive

BD9P2x5MUF-C Series

General Description

Key Specifications

BD9P2x5MUF-C Series are current mode synchronous

buck DC/DC converter integrating POWER MOSFETs.

◼ Input Voltage Range:

3.5 V to 40 V

(Initial startup is 4.0 V or more)

◼ Output Voltage Range

BD9P205MUF-C:

BD9P235MUF-C:

BD9P255MUF-C:

◼ Output Current:

Features

0.8 V to 8.5 V

3.3 V (Typ)

5.0 V (Typ)

◼

Nano Pulse Control^TM

AEC-Q100 Qualified^{(Note 1)}

Minimum ON Pulse 50 ns (Max)

Synchronous Buck DC/DC Converter Integrating

POWER MOSFETs

OCP_SEL = H

OCP_SEL = L

1.5 A (Max)

2.0 A (Max)

◼

Soft Start Function

Current Mode Control

Reset Function

Quiescent Current 10 μA (Typ)

with 12 V Input to 5.0 V Output

Light Load Mode (LLM)

Forced Pulse Wide Modulation (PWM) Mode

Phase Compensation Included

Selectable Spread Spectrum Switching

External Synchronization Function

Selectable Over Current Protection (OCP)

Input Under Voltage Lockout (UVLO) Protection

Thermal Shutdown (TSD) Protection

Output Over Voltage Protection (OVP)

Short Circuit Protection (SCP)

◼ Switching Frequency:

◼ Output Voltage Accuracy:

±1.75 % (-40 °C to +125 °C)

◼ Shutdown Current:

◼ Operating Temperature Range: -40 °C to +125 °C

2.2 MHz (Typ)

2.1 μA (Typ)

◼

Package

VQFN20FV4040

W (Typ) x D (Typ) x H (Max)

4.0 mm x 4.0 mm x 1.0 mm

Enlarged View

(Note 1) Grade 1

Applications

◼

Automotive Powered Supplies

Consumer Powered Supplies

VQFN20FV4040

Wettable Flank Package

Typical Application Circuit

C_BST

V_IN

VIN

BST

SW

V_OUT

L₁

PVIN

VCC_EX

C_IN

EN

VOUT_DIS

VOUT_SNS

PGND

VREG

OCP_SEL

C_OUT

R_RST

RESET

MODE

SSCG

C_REG

V_MODE

V_SSCG

GND

Figure 1. Application Circuit with Discharge Function (BD9P235MUF-C, BD9P255MUF-C)

Nano Pulse Control^TMis a trademark or a registered trademark of ROHM Co., Ltd.

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays

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Typical Application Circuit - continued

C_BST

V_IN

VIN

BST

SW

V_OUT

L₁

PVIN

VCC_EX

C_IN

EN

VOUT_DIS

VOUT_SNS

PGND

VREG

OCP_SEL

C_OUT

R_RST

RESET

MODE

SSCG

C_REG

V_MODE

V_SSCG

GND

Figure 2. Application Circuit without Discharge Function (BD9P235MUF-C, BD9P255MUF-C)

C_BST

V_IN

VIN

BST

V_OUT

L₁

SW

PVIN

VCC_EX

R_FB1

C_IN

EN

FB

PGND

VREG

OCP_SEL

VOUT_SNS

C_OUT

R_RST

RESET

MODE

SSCG

C_REG

R_FB2

V_MODE

V_SSCG

GND

Figure 3. Application Circuit (BD9P205MUF-C)

Note: The Difference between BD9P205MUF-C, BD9P235MUF-C and BD9P255MUF-C

The VOUT_DIS pin and discharge function are not available with BD9P205MUF-C. The FB pin is assigned on the

BD9P205MUF-C and the resistors dividing the output voltage are connected. The output voltage is defined by the

resistors (R_FB1, R_FB2).

The VOUT discharge function are available with BD9P235MUF-C and BD9P255MUF-C, and connect the VOUT_DIS

pin to VOUT. And connect the VOUT to the VOUT_SNS pin.

L₁

V_OUT

SW

VOUT_DIS

VOUT_SNS

C_OUT

VOUT_SNS

R_FB1

FB

R_FB2

(BD9P205MUF-C)

(BD9P235MUF-C, BD9P255MUF-C)

Figure 4. The Difference between BD9P205MUF-C, BD9P235MUF-C and BD9P255MUF-C

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Pin Configuration

PVIN

1

2

3

4

5

15 VOUT_SNS

14 VOUT_DIS

13 GND

N.C.

PGND

12 RESET

11 SSCG

(TOP VIEW)

Figure 5. Pin Configuration (BD9P235MUF-C, BD9P255MUF-C)

PVIN

1

2

3

4

5

15 FB

14 VOUT_SNS

13 GND

N.C.

PGND

12 RESET

11 SSCG

(TOP VIEW)

Figure 6. Pin Configuration (BD9P205MUF-C)

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Pin Description

Pin No.

Pin Name

Function

Power supply input pins that are used for the output stage of the switching

regulator. Connect input ceramic capacitors referring Page 33 between the

PGND pins and these pins.

1, 2

PVIN

This pin is not connected to the chip. Use this as open. If this pin is used other

than open and adjacent pins are expected to be shorted, please confirm if there

is any problem with the actual application.

3

N.C.

PGND

SW

4, 5

6, 7

Ground pins for the output stage of the switching regulator.

Switching node pins. These pins are connected to the source of the internal

High Side FET and the drain of the internal Low Side FET. Connect the power

inductor and the bootstrap capacitor.

Connect a bootstrap capacitor of 0.1 µF (Typ) between this pin and the SW

pins. The voltage of this capacitor is the gate drive of the High Side FET.

8

9

BST

This is OCP threshold selective pin. OCP threshold is set to 2.250 A (Typ) at

high, and 3.000 A (Typ) at low. These values mean the average inductor

current. Connect this pin to VREG (High) or GND (Low).

OCP_SEL

Pin to select FPWM (Forced PWM) mode, AUTO (Automatically switched

between PWM mode and LLM) mode, or SYNC (Activate synchronization)

mode. In case of using FPWM mode, set high. In case of using AUTO mode,

set low or open. In case of using SYNC mode, apply a clock to this pin.

10

11

MODE

SSCG

Pin to select Spread Spectrum function. Set high to enable Spread Spectrum

and set low to disable Spread Spectrum. Connect this pin to VREG (High) or

GND (Low).

Output reset pin with open drain. Connect a pull-up resistor to the VREG pin or

the power supply within the absolute maximum voltage ratings of the RESET

pin. Using a 5 kΩ to 100 kΩ resistance is recommended.

12

13

RESET

GND

Ground pin.

14

This pin discharges the VOUT node. Connect this pin to the VOUT when

discharge function is required. Otherwise, connect this pin to GND.

(BD9P235MUF-C,

BD9P255MUF-C)

VOUT_DIS

14

Pin to define the clamp voltage of GmAmp2 output and phase compensation.

Connect this pin to the output voltage.

(BD9P205MUF-C)

Inverting input node of the GmAmp1. This pin is used for OVP, SCP and

RESET detection. And, this pin is used for defining the clamp voltage of

GmAmp2 output and phase compensation. Connect this pin to the output

voltage.

VOUT_SNS

15

(BD9P235MUF-C,

BD9P255MUF-C)

Inverting input node of the GmAmp1. This pin is used for OVP, SCP and

RESET detection. Connect output voltage divider to this pin to set the output

voltage.

15

FB

(BD9P205MUF-C)

This pin is power supply input for internal circuit. VREG voltage is supplied from

VCC_EX when voltage between 3.2 V (V_TEXH, Max) and 5.65 V (V_EXOVPL, Min) is

connected to this pin. Connecting this pin to VOUT improves efficiency. In case

of not use this function, connect this pin to GND.

16

VCC_EX

Pin to output 3.3 V (Typ) for internal circuit. Connect a ceramic capacitor of 1.0

µF (Typ). Do not connect to any external loads except the OCP_SEL pin, the

MODE pin, the SSCG pin and a pull-up resistor to the RESET pin.

17

18

VREG

N.C.

This pin is not connected to the chip. Use this as open. If this pin is used other

than open and adjacent pins are expected to be shorted, please confirm if there

is any problem with the actual application.

Enable pin. Apply low level (0.8 V or less) to disable device and apply high level

(2.0 V or more) to enable device. This pin must not be left open.

If this pin is connected to other devices, it is recommended to insert a current

19

EN

limiting resistor to avoid damages caused by a short between pins.

Power supply input pins for the internal circuit.

Connect this pin to the PVIN pins.

20

VIN

Exposed pad. The EXP-PAD is connected to the P substrate of the IC. Connect

this pad to the internal PCB ground plane using multiple via holes to obtain

excellent heat dissipation characteristics.

-

EXP-PAD

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Block Diagram

VCC_EX

VREG

VIN

VREF

Pre Reg

VREG

tsdout

VREF

VIN

porout

uvloout

UVLO

REG

TSD

VREF

POR

GND

EN

OSC

clk

SSCG

mode

MODE

OCP_SEL

VREF

scpout

porout

VOUT_SNS

FB

SCP

uvloout

scpout

ovpout

mode

HOCP Comp

VREG

BST

VREG

GmAmp1

OCP_SEL

Clamper1

PVIN

GmAmp2

PWM Comp

VREF

Vc

Control

Logic

Driver

Soft

Start

VOUT_SNS

SW

Clamper2

EN

clk

Vr

Ramp

Sleep Comp

ZX Comp

sleep

VREF

Current

Sense

VREF

Reset

OVP

PGND

EN

porout

uvloout

tsdout

RESET

VOUT_SNS

VCC_EX

ovpout

Figure 7. Block Diagram (BD9P205MUF-C)

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Block Diagram - continued

VCC_EX

VREG

VIN

VREF

Pre Reg

VREG

tsdout

VREF

VIN

porout

uvloout

UVLO

REG

TSD

VREF

POR

GND

EN

OSC

clk

SSCG

MODE

mode

MODE

Discharge

VOUT_DIS

vout_det

OCP_SEL

vout_dis

VREG

OCP_SEL

VREF

scpout

porout

SCP

VOUT_SNS

uvloout

scpout

ovpout

mode

HOCP Comp

FB

BST

VREG

GmAmp1

OCP_SEL

Clamper1

PVIN

vout_dis

GmAmp2

PWM Comp

VREF

Vc

Control

Logic

Driver

Soft

Start

VOUT_SNS

Clamper2

SW

EN

clk

Vr

Ramp

Sleep Comp

ZX Comp

sleep

VREF

Current

Sense

VREF

Reset

OVP

PGND

VREF

EN

porout

uvloout

tsdout

RESET

VCC_EX

ovpout

Figure 8. Block Diagram (BD9P235MUF-C, BD9P255MUF-C)

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BD9P2x5MUF-C Series

Description of Blocks

-

PreReg

This block is the internal power supply for TSD and VREF circuits.

-

VREG

This block is the internal power supply circuit. It outputs 3.3 V (Typ) and is the power supply to the control circuit and

Driver.

-

TSD

This is the thermal shutdown circuit. It will shut down the device when the junction temperature (Tj) reaches to 175 °C

(Typ) or more. When the Tj falls below the TSD threshold with hysteresis of 25 °C (Typ), the circuits are automatically

restored to normal operation.

-

VREF

The VREF block generates the internal reference voltage.

POR

The POR block is power on reset for internal logic circuit. The IC releases power on reset and starts operation with soft

start when the VIN rises to 3.8 V (Typ) or more.

-

UVLO REG

The UVLO block is for under voltage lockout protection. It will shut down the device when the VREG falls to 2.85 V (Typ)

or less. This protection is released when VREG voltage increase to 2.95 V (Typ) or more.

MODE

This block detects the MODE pin signal and controls switching mode. When the MODE pin is logic high level or is

applied external clock, switching operation becomes forced PWM mode regardless load current. When the MODE pin is

open or logic low level, switching operation changes between PWM and light load operation depending on load current.

-

OSC

This block generates the clock frequency. When the clock is applied to the MODE pin, it synchronizes to external clock.

Connect the SSCG pin to GND to disable Spread Spectrum function and connect the SSCG pin to the VREG pin to

enable it.

OVP

This is the output over voltage protection (OVP) circuit. When the output voltage +7.3 % (Typ) or more of the normal

regulation voltage, VOUT is reduced by forced PWM switching. After output voltage falls +4.7 % (Typ) or less, the

operation recovers into normal condition.

SCP

This is the short circuit protection circuit. After soft start is completed, the switching is disabled if the output voltage falls

SCP Threshold voltage or less for 0.9 ms (Typ). This short circuit protection is maintained for 30 ms (Typ) and then

automatically released.

-

Soft Start

This function starts up the output voltage taking 3 ms (Typ) to prevent the overshoot.

GmAmp1

This block is an error amplifier and its inputs are the reference voltage 0.8 V (Typ) and the FB voltage.

GmAmp2

This block sends the signal Vc which is composed of the GmAmp1 output and the current sense signal to PWM Comp.

Clamper1

This block clamps GmAmp1 output voltage and inductor current. It works as the over current protection and LLM control

current.

-

Clamper2

This block clamps GmAmp2 output voltage.

Current Sense

This block detects the amount of change in inductor current through the Low Side FET and sends a current sense signal

to GmAmp2.

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Description of Blocks - continued

-

PWM Comp

This block compares the output voltage of the GmAmp2 (Vc) and the saw tooth waveform (Vr) to control the switching

duty.

-

Ramp

This block generates the saw tooth waveform (Vr) from the clock signal generated by OSC.

Control Logic

This block controls switching operation and protection functions.

-

Driver

This circuit drives the gates of the output FETs.

Sleep Comp

If output/feedback voltage becomes 101.3 % (Typ) or more, this block puts the device into SLEEP state. This state is

released when output/feedback voltage becomes 101.0 % (Typ) or less.

-

ZX Comp

This block stops the switching by detecting reverse current of the SW current at LLM control.

HOCP Comp

This block detects the current flowing through the High Side FET and limits the current of 4.0 A (Min) or more. This

function works in abnormal situation such as the SW pin shorted to GND condition in order to prevent the High Side FET

from destruction.

-

Reset

When the output voltage reaches -4.7 % (Typ) or more of the normal regulation voltage, the open drain MOSFET

connected to the RESET pin turns off in 3.6 ms (Typ) and the output of the RESET pin becomes high by its external

pull-up resistor.

When the output voltage reaches -7.2 % (Typ) or less, the RESET pin open drain MOSFET turns on and the RESET pin

is pulled down with an impedance of 190 Ω (Typ).

Discharge

This block discharges the output voltage during EN is low and before VOUT start up. The VOUT_DIS pin is pulled down

with an impedance of 75 Ω (Typ).

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Absolute Maximum Ratings

Parameter

Symbol

Rating

Unit

V_VIN, V_PVIN

V_EN

-0.3 to +42

V

Input Voltage

EN Voltage

V_BST

-0.3 to +49

BST Voltage

Voltage from SW to BST

ΔV_BST

V_SW-0.3 to V_SW+7

V_FB,V_RESET,

V_MODE,V_SSCG

V_{OCP_SEL}

FB, RESET, MODE,

SSCG, OCP_SEL Voltage

-0.3 to +7

V

VOUT_DIS Voltage

V_{VOUT_DIS}

V_{VOUT_SNS}

V_{VCC_EX}

V_REG

-0.3 to +10

-0.3 to +7

-55 to +150

150

V

VOUT_SNS Voltage

VCC_EX Voltage

V

VREG Voltage

V

Storage Temperature Range

Maximum Junction Temperature

Human Body Model (HBM)^{(Note 1)}

Tstg

˚C

kV

Tjmax

VESD_HBM

±2

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

(Note 1) These voltages are guaranteed by design. Not tested.

Thermal Resistance^{(Note 2)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 4)}

2s2p^{(Note 5)}

VQFN20FV4040

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 3)}

θ_JA

120.0

15

38.7

8

°C/W

Ψ_JT

(Note 2) Based on JESD51-2A(Still-Air).

(Note 3) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 4) Using a PCB board based on JESD51-3.

(Note 5) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

Board Size

Single

FR-4

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Layer Number of

Measurement Board

Thermal Via^{(Note 6)}

Material

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

FR-4

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Copper Pattern

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

(Note 6) This thermal via connects with the copper pattern of all layers.

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Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

V_VIN, V_PVIN

Ta

3.5

-

40

+125

8.5

-

V

˚C

V

Input Voltage

-40

-

Operating Temperature

Output Voltage for BD9P205MUF-C^{(Note 1)}

Output Voltage for BD9P235MUF-C

Output Voltage for BD9P255MUF-C

SW Minimum ON Time^{(Note 2)}

SW Minimum OFF Time (V_REG= 3.3 V)

SW Minimum OFF Time (V_REG= 5.0 V)

Output Current

V_OUT

0.8

-

V_OUT

-

3.3

V

V_OUT

5.0

-

V

t_ONMIN

t_OFFMIN

I_OUT

-

50

130

100

2

ns

A

Input Capacitor

C_IN

2.3

-

µF

(V_INContinuous Condition) ^{(Note 3)}

VREG Capacitor^{(Note 3)}

BST Capacitor^{(Note 3)}

C_REG

C_BST

0.6

1.0

0.1

2.0

0.2

µF

0.05

(Note 1) Although the output voltage is configurable at 0.8 V or more, it may be limited by the SW min ON pulse width.

For the same reason, although the output voltage is configurable at 8.5 V and more, it may be limited by the SW minimum OFF pulse width.

For the configurable range, please refer to the Output Voltage Setting in Selection of Components Externally Connected (page 30).

(Note 2) This parameter is for 1.0 A output. Not tested.

(Note 3) Ceramic capacitor is recommended. The capacitor value including temperature change, DC bias change, and aging change must be considered. If a bulk

capacitor is used with Input ceramic capacitors, please select capacitors referring page 33.

Electrical Characteristics (Unless otherwise specified Ta = -40 ˚C to +125 ˚C, V_IN= 12 V)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

General

V_EN= 0 V,

Shutdown Current

I_SDWN

I_{Q_VIN1}

-

2.1

10.0

6.0

µA

Ta = -40 ˚C to +105 ˚C

V_MODE= 0 V, V_{VCC_EX}= 5 V

V_FB= V_FB1x 1.04 (SLEEP)

V_MODE= 0 V, V_{VCC_EX}= 0 V

V_FB= V_FB1x 1.04 (SLEEP)

V_MODE= 5 V, V_{VCC_EX}= 5 V

V_FB=V_FB1x 1.04 (No SLEEP)

V_MODE= 5 V, V_{VCC_EX}= 0 V

V_FB= V_FB1x 1.04 (No SLEEP)

V_MODE= 0 V

I_{Q_VIN2}

15

30

Quiescent Current from VIN

I_{Q_VIN3}

33

66

I_{Q_VIN4}

1200

16

2400

60

I_{Q_VCC_EX1}

I_{Q_VCC_EX2}

V_{FB =}V_FB1x 1.04 (SLEEP)

V_MODE= 5 V

V_FB= V_FB1x 1.04 (No SLEEP)

Quiescent Current from VCC_EX

1500

3000

VIN Power On Reset Rising

VREG Under Voltage Lockout Falling

VREG Under Voltage Lockout Rising

EN/MODE/OCP_SEL/SSCG

EN Input Voltage High

V_{POR_R}

V_{UVLO_F}

V_{UVLO_R}

3.6

3.8

4.0

V

V_INSweep Up

2.70

2.75

2.85

2.95

3.00

3.15

V_REGSweep Down

V_REGSweep Up

V_ENH

V_ENL

2.0

-

40

0.8

0.50

1

V

EN Input Voltage Low

0

-

EN Hysteresis Voltage

V_ENHYS

I_EN

0.10

0.25

EN Input Current

-

0

-

µA V_EN= 5 V

MODE Input Voltage High

MODE Input Voltage Low

MODE Input Current

V_MODEH

V_MODEL

I_MODE

V_SELH

V_SELL

I_SEL

2.0

5.5

0.8

10

V

-

V

-

6

-

µA V_MODE= 5 V

OCP_SEL Input Voltage High

OCP_SEL Input Voltage Low

OCP_SEL Input Current

SSCG Input Voltage High

SSCG Input Voltage Low

SSCG Input Current

2.0

5.5

0.8

1

V

-

V

-

2.0

-

0

-

µA V_{OCP_SEL}= 5 V

V_SSCGH

V_SSCGL

I_SSCG

5.5

0.8

1

V

-

V

-

0

µA V_SSCG= 5 V

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Electrical Characteristics - continued (Unless otherwise specified Ta = -40 ˚C to +125 ˚C, V_IN= 12 V)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

VREG

Voltage Follower

V_{VCC_EX}= 0 V

VREG Voltage

V_REG

3.0

3.3

3.6

V

VCC_EX Switch ON Resistance

VCC_EX Threshold Voltage High

VCC_EX Threshold Voltage Low

VCC_EX OVP Threshold Voltage High

VCC_EX OVP Threshold Voltage Low

R_ONEX

V_TEXH

-

6

12

Ω

V

V_{VCC_EX}= 5 V

2.90

2.70

5.85

5.65

3.05

2.90

6.20

6.00

3.20

3.10

6.55

6.35

V_{VCC_EX}Sweep Up

V_{VCC_EX}Sweep Down

V_TEXL

V_EXOVPH

V_EXOVPL

V_EN= 0 V,

V_{OUT_DIS}= 0.3 V

VOUT_DIS Discharge ON Resistance

R_DIS

-

75

150

300

Ω

VOUT Discharge Deactivate Voltage

Oscillator

V_DISL

100

200

mV V_{OUT_DIS}Sweep Down

Switching Frequency

f_SW

2.0

1.8

2.2

2.4

MHz

Synchronization Frequency Range

f_{SW_EX}

-

MHz External Clock Input

Switching Frequency

(Spread Spectrum)

f_SWSSR

1.90

-

2.52

MHz V_SSCG= 5 V

Spread Spectrum Modulation Rate

Spread Spectrum Modulation Cycle

VREF/GmAmp

Δf_SSCG

-

4.5

-

%

V_SSCG= 5 V

t_{SSCG_CYCLE}

466

µs V_SSCG= 5 V

Feedback Reference Voltage

(BD9P205MUF-C)

Enter SLEEP State Voltage

(BD9P205MUF-C)

Exit SLEEP State Voltage

(BD9P205MUF-C)

Output Voltage

(BD9P235MUF-C)

Enter SLEEP State Voltage

(BD9P235MUF-C)

Exit SLEEP State Voltage

(BD9P235MUF-C)

Output Voltage

V_FBVoltage,

V

V_FB1

0.788

0.794

0.792

3.250

3.275

3.266

4.925

4.963

4.949

0.802

0.812

0.810

3.308

3.349

3.341

5.013

5.076

5.063

0.816

0.830

0.828

3.366

3.424

3.416

5.100

5.188

5.176

PWM Mode

V_FBRising,

Light Load Mode

V_FB2

V

V_FBFalling,

V_FB3

V

Light Load Mode

V_{OUT_SNS}Voltage,

PWM Mode

V_{OUT_SNS}Rising,

Light Load Mode

V_{OUT_SNS}Falling,

Light Load Mode

V_{OUT_SNS}Voltage,

PWM Mode

V_{OUT_SNS}Rising,

Light Load Mode

V_{OUT_SNS}Falling,

Light Load Mode

V_{OUT_SNS1}

V_{OUT_SNS2}

V_{OUT_SNS3}

V_{OUT_SNS1}

V_{OUT_SNS2}

V_{OUT_SNS3}

(BD9P255MUF-C)

Enter SLEEP State Voltage

(BD9P255MUF-C)

Exit SLEEP State Voltage

(BD9P255MUF-C)

FB Input Current for BD9P205MUF-C

VOUT_SNS Input Current

Start Delay Time

I_FB

I_{VOUT_SNS}

t_DLY

-

0

1

µA V_FB= 5 V

µA V_{OUT_SNS}= 5 V

µs

0.5

400

3.0

2.0

800

3.9

-

Soft Start Time

t_SS

2.5

ms V_FB1x 0.1 to V_FB1x 0.9

Driver

High Side FET ON Resistance

Low Side FET ON Resistance

R_ONH

R_ONL

-

140

90

310

210

mΩ V_BST-V_SW= 3.3 V

mΩ V_{VCC_EX}= 3.3 V

V_IN= 40 V, V_EN= 0 V,

Ta = 25 ˚C, V_SW= 0 V

V_IN= 40 V, V_EN= 0 V,

Ta = 25 ˚C, V_SW= 40 V

High Side FET Leakage Current

Low Side FET Leakage Current

I_LKH

-10

0

-

µA

I_LKL

I_OCP20

I_OCP15

-

10

µA

2.400

1.800

3.000

2.250

3.600

2.700

A

V_{OCP_SEL}= 0 V

V_{OCP_SEL}= 5 V

Over Current Protection Threshold

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Electrical Characteristics - continued (Unless otherwise specified Ta = -40 ˚C to +125 ˚C, V_IN= 12 V)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Reset

Reset Threshold Voltage Low

(BD9P205MUF-C)

Reset Threshold Voltage Low

(BD9P235MUF-C)

Reset Threshold Voltage Low

(BD9P255MUF-C)

Reset Threshold Voltage High

(BD9P205MUF-C)

Reset Threshold Voltage High

(BD9P235MUF-C)

Reset Threshold Voltage High

(BD9P255MUF-C)

0.718

3.000

4.550

0.738

3.08

4.66

-

0.744

3.065

4.650

0.764

3.16

4.78

0

0.770

3.130

4.750

0.790

3.24

4.90

1

V

V_FBSweep Down

V_{OUT_SNS}Sweep Down

V_FBSweep Up

V_RTL

V

V_RTH

V

V_{OUT_SNS}Sweep Up

V

V_RESET= 5.0 V,

V_FB= 0.8 V

V_IN= 2 V, V_EN= 0 V

I_RESET= 1 mA

Reset Leakage Current

Reset ON Resistance

I_RSTLK

µA

Ω

R_RST

t_RSTNACT

t_RSTNFILT

-

190

400

Reset Active Time

Reset Filtering Time

OVP/SCP

2.0

1

3.6

5

5.0

10

ms

µs

FB OVP Threshold Voltage High

(BD9P205MUF-C)

FB OVP Threshold Voltage Low

(BD9P205MUF-C)

VOUT_SNS OVP Threshold Voltage High

(BD9P205MUF-C)

VOUT_SNS OVP Threshold Voltage High

(BD9P235MUF-C)

VOUT_SNS OVP Threshold Voltage High

(BD9P255MUF-C)

VOUT_SNS OVP Threshold Voltage Low

(BD9P205MUF-C)

VOUT_SNS OVP Threshold Voltage Low

(BD9P235MUF-C)

VOUT_SNS OVP Threshold Voltage Low

(BD9P255MUF-C)

SCP Threshold Voltage High

(BD9P205MUF-C)

SCP Threshold Voltage High

(BD9P235MUF-C)

SCP Threshold Voltage High

(BD9P255MUF-C)

SCP Threshold Voltage Low

(BD9P205MUF-C)

SCP Threshold Voltage Low

(BD9P235MUF-C)

SCP Threshold Voltage Low

(BD9P255MUF-C)

V_OVPH

V_OVPL

0.825

0.805

9.0

0.860

0.840

9.5

0.895

0.875

10.0

V

V_FBSweep Up

V_FBSweep Down

V_SNSOVPH

V_SNSOVPL

V_SCPH

3.402

5.156

8.5

3.541

5.379

9.0

3.693

5.595

9.5

V_{OUT_SNS}Sweep Up

3.321

5.033

0.68

2.81

4.25

0.60

2.48

3.75

3.455

5.249

0.72

2.97

4.50

0.64

2.64

4.00

3.609

5.467

0.76

V_{OUT_SNS}Sweep Down

V_FBSweep Up

3.14

V_{OUT_SNS}Sweep Up

V_FBSweep Down

4.75

0.68

V_SCPL

2.81

V_{OUT_SNS}Sweep Down

SCP function is

4.25

SCP Deactivate Rate of VIN/VOUT_SNS

V_{SCP_DACT}

1.20

1.33

1.45

V/V deactivated this value

or less

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BD9P2x5MUF-C Series

Typical Performance Curves

0.816

0.812

0.808

0.804

0.800

0.796

0.792

0.788

0.784

10

9

8

7

Ta = +125 ˚C

6

5

Ta = +25 ˚C

4

3

2

1

0

Ta = -40 ˚C

-50 -25

0

25

50

75 100 125

0

5

10 15 20 25 30 35 40

Input Voltage : V [V]

Temperature : Ta[˚C]

IN

Figure 9. Shutdown Current vs Input Voltage

Figure 10. Feedback Reference Voltage vs Temperature

(BD9P205MUF-C)

3.360

5.100

5.075

5.050

5.025

5.000

4.975

4.950

4.925

4.900

3.345

3.330

3.315

3.300

3.285

3.270

3.255

3.240

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Temperature : Ta[˚C]

Figure 11. Output Voltage vs Temperature

Figure 12. Output Voltage vs Temperature

(BD9P235MUF-C)

(BD9P255MUF-C)

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BD9P2x5MUF-C Series

Typical Performance Curves - continued

3.15

3.10

3.05

3.00

2.95

2.90

2.85

2.80

2.75

2.70

4.0

3.9

3.8

3.7

3.6

Rising

Falling

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Temperature : Ta[˚C]

Figure 14. VREG Under Voltage Lockout vs Temperature

Figure 13. VIN Power On Reset Rising vs Temperature

2.0

1.00

0.80

0.60

1.8

High

Ta = -40 ˚C, +25 ˚C, +125 ˚C

0.40

1.6

1.4

1.2

0.20

0.00

-0.20

-0.40

-0.60

-0.80

-1.00

Low

1.0

0.8

-50 -25

0

25

50

75 100 125

0

5

10 15 20 25 30 35 40

EN Voltage : V_EN[V]

Temperature : Ta[˚C]

Figure 16. EN Input Current vs EN Voltage

Figure 15. EN Input Voltage vs Temperature

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BD9P2x5MUF-C Series

Typical Performance Curves - continued

2.0

10

9

1.8

MODE

8

High

Ta = +125 ˚C

Ta = +25 ˚C

Ta = -40 ˚C

7

1.6

1.4

6

5

4

3

Low

1.2

2

OCP_SEL, SSCG

Ta = -40 ˚C, +25 ˚C, +125 ˚C

1

1.0

0.8

0

-1

-50 -25

0

25

50 75 100 125

0

1

2

3

4

5

6

Temperature : Ta[˚C]

MODE, OCP_SEL, SSCG Voltage :

V_MODE,V_{OCP_SEL},V_SSCG[V]

Figure 17. MODE, OCP_SEL, SSCG Input Voltage vs

Temperature

Figure 18. MODE, OCP_SEL, SSCG Input Current

vs MODE, OCP_SEL, SSCG Voltage

2.40

2.35

2.30

2.25

2.20

2.15

2.10

2.05

2.00

3.6

3.4

I_OCP20(OCP_SEL = Low)

3.2

3.0

2.8

2.6

I_OCP15(OCP_SEL = High)

2.4

2.2

2.0

1.8

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Temperature : Ta[˚C]

Figure 19. Switching Frequency vs Temperature

Figure 20. Over Current Protection Threshold vs Temperature

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BD9P2x5MUF-C Series

Typical Performance Curves - continued

210

160

110

60

350

270

V_{VCC_EX}= 3.3 V

VBST-VSW = 3.3 V

190

110

V_{VCC_EX}= 5.0 V

VBST-VSW = 5.0 V

30

10

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Temperature : Ta[˚C]

Figure 21. High Side FET ON Resistance vs Temperature

Figure 22. Low Side FET ON Resistance vs Temperature

0.780

3.240

3.200

High

0.767

3.160

3.120

3.080

0.754

0.741

3.040

Low

0.728

3.000

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Temperature : Ta[˚C]

Figure 23. Reset Threshold Voltage vs Temperature

Figure 24. Reset Threshold Voltage vs Temperature

(BD9P205MUF-C)

(BD9P235MUF-C)

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BD9P2x5MUF-C Series

Typical Performance Curves - continued

0.880

0.870

0.860

0.850

0.840

0.830

0.820

4.900

4.850

High

4.800

4.750

4.700

4.650

Low

4.600

Low

4.550

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Temperature : Ta[˚C]

Figure 25. Reset Threshold Voltage vs Temperature

Figure 26. FB OVP Threshold Voltage vs Temperature

(BD9P255MUF-C)

(BD9P205MUF-C)

5.50

5.24

10.00

9.75

9.50

9.25

9.00

8.75

8.50

High

BD9P255MUF-C

High

Low

4.97

4.71

4.44

4.18

BD9P235MUF-C

High

Low

3.91

3.65

3.38

Low

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Temperature : Ta[˚C]

Figure 27. VOUT_SNS OVP Threshold Voltage vs

Temperature

Figure 28. VOUT_SNS OVP Threshold Voltage vs

Temperature

(BD9P205MUF-C)

(BD9P235MUF-C/BD9P255MUF-C)

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BD9P2x5MUF-C Series

Function Explanation

1. Nano Pulse Control^TM

Nano Pulse Control^TMis an original technology developed by ROHM Co., Ltd. It enables to control voltage stably, which

is difficult in the conventional technology, even in a narrow SW ON time such as less than 50 ns at typical condition.

Narrow SW ON Pulse enables direct convert of high input voltage to low output voltage. The output voltage V_OUT3.3 V

can be output directly from the supply voltage V_IN24 V at 2.2 MHz.

V_SW

(5 V/div)

V_IN= 24 V

V_OUT= 3.3 V

f_SW= 2.2 MHz

(5 V/div)

Time (100 ns/div)

Figure 29. Switching Waveform (V_IN= 24 V, V_OUT= 3.3 V, I_OUT= 1.0 A, f_SW= 2.2 MHz)

2. Light Load Mode Control and Forced PWM Mode Control

BD9P2x5MUF-C is a synchronous DC/DC converter with integrated POWER MOSFETs and realizes high transient

response by using current mode Pulse Width Modulation (PWM) mode control architecture. Under a heavy load, the

switching operation is performed with the PWM mode control at a fixed frequency. When the load is lighter, the operation

is changed over to the Light Load Mode (LLM) control to improve the efficiency.

Light Load Mode

PWM Mode

Output Current I_OUT[A]

Figure 30. Efficiency (Light Load Mode, PWM Mode)

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2. Light Load Mode control and Forced PWM Mode control - continued

If the output load decreases below 400 mA (Typ) (OCP_SEL = L), the output voltage rises and power state is changed to

SLEEP state when the output voltage exceeds to V_FB2(101.3 % of its setting voltage V_FB1). During SLEEP state,

switching operation is stopped and the circuit current is reduced by stopping the circuit operation except for the monitor

circuit of output voltage monitor. Then, the switching operation restarts when the output voltage decreases less than

V_FB3(101.0 % of its setting voltage V_FB1) by the load current.

If the light load mode operation is not required, the IC operates in forced PWM mode by applying high voltage or an

external clock to the MODE pin. In forced PWM mode, the IC operates with fixed frequency regardless of the output load

and the ripple voltage of output can be reduced. Also, during soft start time, the IC operates in forced PWM mode

regardless of the condition of the MODE pin. After detecting RESET high, the IC operates according to the MODE pin

condition.

If OCP_SEL set high level, then the threshold current of switched between PWM mode and LLM is changed to 300 mA

(Typ).

In addition, good EMI performance in AM band may not be provided by a load condition in LLM. To avoid this, use

Forced PWM mode.

V_EN

V_FB2= V_FB1× 101.3 % (Typ)

V_FB3= V_FB1× 101.0 % (Typ)

V_FB1

V_OUT

400 mA

I_L

400 mA

I_OUT

V_RESET

Figure 31. Timing Chart in Light Load Mode (OCP_SEL = L)

V_EN

V_FB2= V_FB1× 101.3 % (Typ)

V_FB3= V_FB1× 101.0 % (Typ)

V_FB1

V_OUT

400 mA

I_L

400 mA

I_OUT

V_RESET

Figure 32. Timing Chart in Light Load Mode after Detecting RESET High (OCP_SEL = L)

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Function Explanation - continued

3.

Enable Control

The device shutdown can be controlled by the EN pin. When V_ENreaches V_ENH(2.0 V) or more, the internal circuit is

activated. When the VOUT_DIS pin is connected to output voltage and the EN pin is low, the VOUT_DIS pin is pulled

down by the resistance of R_DIS(75 Ω, Typ) and discharges the output voltage. This discharge function is deactivated

when VOUT_DIS voltage falls below V_DISL(200 mV, Typ) at once or 30 ms (Typ) pass after the EN pin becomes high.

After being deactivated, the VOUT starts up with soft start operation. The delay time t_DLY(400 µs, Typ) is implemented

from the EN pin becoming high to VOUT starting up regardless of VOUT_DIS voltage. The soft start time (V_OUTx 0.1 to

V_OUTx 0.9) is set to t_SS(3.0 ms, Typ). When an EN voltage becomes V_ENL(0.8 V) or less, the device is shut down. When

discharge function is not required, connect the VOUT_DIS pin to GND.

The discharge function is available with only BD9P235MUF-C and BD9P255MUF-C.

V_ENH

V_ENL

2.0 V

0.8 V

V_EN

90 %

V_DISL

200 mV

(Typ)

V_DISL

200 mV

(Typ)

10 %

t_DLY

V_OUT

t_SS

400 µs 3.0 ms

(Typ)

t_SSx 1.25

ON

Discharge

OFF

t_DLY

30 ms

(Typ)

400 µs

(Typ)

Figure 33. Enable ON/OFF Timing Chart

4. Reset Function

For BD9P205MUF-C, the reset function monitors the FB pin voltage. When the output voltage reaches V_RTH(95.3 %,

Typ) or more of the normal regulation voltage, the open drain MOSFET on the RESET pin is turned off in t_RSTNACT(3.6

ms, Typ) and the output of the RESET pin becomes high by its pull-up resistor. In addition, when the FB voltage reaches

V_RTL(92.8 %, Typ) or less, the open drain MOSFET on the RESET pin is turned on and the RESET pin is pulled down

with an impedance of R_RST(190 Ω, Typ). To reject noise, the filtering time t_RSTNFILT(5 µs, Typ) is implemented after FB

voltage decreases below its threshold voltage (V_RTL).

The reset function also works when output over voltage is detected. When the output voltage reaches V_OVPH(107.3 %,

Typ) or more, the open drain MOSFET on the RESET pin is turned on. Then, when the FB voltage goes below V_OVPL

(104.7 %, Typ) or less, the open drain MOSFET on the RESET pin is turned off. The reset active time and filtering time

are activated when over voltage conditions are detected.

For BD9P235MUF-C and BD9P255MUF-C, this function monitors the VOUT_SNS pin voltage.

The RESET output voltage low level (V_{RESET_LOW(Max)}) when the open drain MOSFET is turned on is calculated by the

following equation. It is recommended to use resistance of 5 kΩ to 100 kΩ and pull it up to the VREG pin or the power

supply in the absolute maximum voltage ratings of the RESET pin.

During shutdown condition, the RESET pin is pulled down regardless the output voltage as far as V_INis 2 V or more.

V_OVPH= V_FB1× 107.3 % (Typ)

V_OVPL= V_FB1× 104.7 % (Typ)

V_FB1

V_RTH= V_FB1× 95.3 % (Typ)

V_RTL= V_FB1× 92.8 % (Typ)

V_OUT

V_RESET

t_RSTNACTUnder t_RSTNFILT

t_RSTNFILT

5 µs

(Typ)

t_RSTNACTUnder t_RSTNFILT

t_RSTNFILT

5 µs

(Typ)

t_RSTNACT

3.6 ms

(Typ)

3.6 ms

Under 5 µs

(Typ)

3.6 ms

Under 5 µs

(Typ)

Figure 34. Reset Timing Chart (BD9P205MUF-C)

푅

ꢀꢁꢂ(ꢃꢄꢅ)

푉_{푅퐸푆퐸푇_퐿푂푊(푀푎푥)}= 푉_{푃푈퐿퐿−푈푃}

×

[V]

푅

+푅

ꢆꢇꢈꢈꢉꢇꢆ

ꢀꢁꢂ(ꢃꢄꢅ)

Where:

푉_{푅퐸푆퐸푇_퐿푂푊(푀푎푥)}

푉_{푃푈퐿퐿−푈푃}

ꢊ_{푅푆푇(푀푎푥)}

is the RESET Low voltage level (Max) [V]

is the Voltage of pull-up power source [V]

is the RESET ON Resistance (Max) [Ω]

ꢊ_{푃푈퐿퐿−푈푃}

is the value of pull-up resistor to V_{PULL_UP}[Ω]

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BD9P2x5MUF-C Series

Function Explanation - continued

5. External Synchronization Function

By applying clock signal to the MODE pin, the switching frequency can be synchronized to the external clock signal.

When clock signal is applied with the synchronization frequency range between 1.8 MHz and 2.4 MHz and the duty

range between 25 % and 75 %, the Synchronous mode is started after 4 rising edges of the clock signal. In addition, this

function is enabled after V_RESETbecomes high. If the duration between each rising edge exceeds 0.9 µs (Typ) or more,

the Synchronous mode is deactivated and switching operation by internal clock is activated (the Non-Synchronous

mode). The Spread Spectrum function cannot be activated during the Synchronous mode.

V_IN

V_EN

V_RTH

V_OUT

V_SW

t_RSTNACT

3.6 ms

(Typ)

t_DLY

400 µs

(Typ)

V_RESET

V_MODE

0.9 μs (Typ)

Non-Synchronous

Synchronous

Non-Synchronous

Figure 35. External Synchronization Function

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BD9P2x5MUF-C Series

Function Explanation - continued

6. Frequency Division Function

This device drives the High Side FET with a bootstrap and requires the ON time of the Low Side FET to charge the BST

pin. Therefore, the minimum OFF time of the SW pin is specified, and the output voltage is limited by the minimum OFF

time under the condition in which the voltage between input and output are close. To prevent this situation, OFF pulses

are skipped when the voltage between input and output are small to keep the High Side FET turned on and increase the

ON duty of the SW pin. The OFF pulse skip is done for 7 consecutive switching cycles in maximum (The switching

frequency becomes a one eighth of nominal frequency). In this case, the output voltage can be calculated with the

following equation.

(

)

푉_푂푈푇= ꢋꢌꢍ퐷푢푡푦 × 푉 ꢎ ꢊ_푂푁퐻× ꢏ_푂푈푇ꢎ ꢊ_ꢐ퐶× ꢏ_푂푈푇

퐼푁

푓

ꢁꢒ

( )

ꢓ × 푉 ꢎ ꢊ_푂푁퐻× ꢏ_푂푈푇ꢎ ꢊ_ꢐ퐶× ꢏ_푂푈푇[V]

퐼푁

= ꢑ1 ꢎ 푡_{푂퐹퐹푀퐼푁}

×

8

Where:

ꢋꢌꢍ퐷푢푡푦

푉

퐼푁

is the SW pin Maximum ON Duty Cycle [%]

is the Input Voltage [V]

ꢊ_푂푁퐻

ꢏ_푂푈푇

ꢊ_ꢐ퐶

is the High Side FET ON Resistance [Ω]

is the Output Current [A]

(Refer to page 11)

is the DCR of Inductor [Ω]

푡_{푂퐹퐹푀퐼푁}

ꢔ

푆푊

is the SW pin Minimum OFF Time [s]

is the Switching Frequency [Hz]

(Refer to page 10)

(Refer to page 11)

V_IN

V_OUT

V_SW

Figure 36. Frequency Division Function

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Function Explanation - continued

7. Spread Spectrum Function

Connecting the SSCG pin with the VREG pin activates the Spread Spectrum function, reducing the EMI noise level.

When the Spread Spectrum function is activated, the switching frequency is varied with triangular wave of Δf_SSCG

(±4.5 %, Typ) amplitude centered on typical frequency f_SW(2.2 MHz, Typ). The period of the triangular wave is

t_{SSCG_CYCLE}(466 µs, Typ). However, this function is masked when the RESET output is low. Connecting the SSCG pin

with GND deactivates this function.

V_IN

V_EN

V_RTH

t_{SSCG_CYCLE}

466 µs

(Typ)

V_OUT

f_SW

2.2 MHz

(Typ)

Δf_SSCG= +4.5 % (Typ)

Δf_SSCG= -4.5 % (Typ)

f_SW

t_RSTNACT

3.6 ms

(Typ)

t_DLY

400 µs

(Typ)

V_RESET

V_SSCG

SSCG OFF

SSCG ON

Figure 37. Spread Spectrum Function

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Function Explanation - continued

8. VCC_EX Function

This IC has the function that supplies power from VOUT to internal supply VREG to improve the efficiency. When

V_{VCC_EX}goes above V_TEXH(3.05 V, Typ) or more, V_REGis supplied from the VCC_EX pin. In case of the VCC_EX pin

connected with VOUT, the output voltage is used as a power supply for the internal circuitry and driver block. To protect

the internal circuit, VOUT is reduced with PWM switching when VCC_EX voltage exceeds V_EXOVPH(6.0 V, Typ).

Therefore, the VCC_EX pin connection can be used when the output voltage is in the range of between V_TEXH(3.2 V,

Max) and V_EXOVPL(5.65 V, Min). Connect the VCC_EX pin with GND when VCC_EX function is not required.

The bias current I_BIASusing VCC_EX function can be calculated using the following formula.

ꢏ_퐵퐼퐴푆= ꢏ_{푄_ꢕ퐼푁ꢖ}ꢗ ꢏ_{푄_ꢕ퐶퐶_퐸푋ꢖ}× _휂^ꢖ× ^ꢕ

[μA]

ꢘꢙꢙ_ꢚꢛ

ꢕ

ꢜꢝ

Where:

ꢏ_퐵퐼퐴푆

is total current from VIN [µA]

ꢏ_{푄_ꢕ퐼푁ꢖ}

ꢏ_{푄_ꢕ퐶퐶_퐸푋ꢖ}

ꢞ

푉_{ꢕ퐶퐶_퐸푋}

푉

퐼푁

is quiescent current from VIN (without current from VCC_EX) [µA]

is quiescent current from VCC_EX [µA]

(Refer to page 10)

is efficiency of Buck Converter.

is the VCC_EX voltage [V]

is the input voltage [V]

VIN

VREG

VCC_EX

VREG

(LDO)

+

-

ON/OFF

V_TEXH= 3.05 V (Typ)

/ V_TEXL= 2.90 V (Typ)

Figure 38. VCC_EX Block Diagram

V_IN

V_EN

Vout Setting Level

V_TEXH

3.05 V (Typ)

V_TEXL

2.90 V (Typ)

V_OUT= V_{VCC_EX}

(Short)

V_SW

Vout Setting Level

V_REG

3.3 V (Typ)

V_REG

VCC_EX State

VCC_EX OFF

VCC_EX ON

VCC_EX OFF

Figure 39. VCC_EX Timing Chart

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Protect Function

1. Over Current Protection (OCP)

The Over Current Protection (OCP) monitors the average inductor current. The OCP detection level can be selected by

the OCP_SEL pin. When the OCP_SEL voltage is high, it is I_OCP15(2.250 A, Typ) and when the OCP_SEL voltage is low,

it is I_OCP20(3.000 A, Typ). When the average inductor current exceeds to its setting value, the duty cycle of the switching

is limited and the output voltage decreases. This protection circuit is effective in preventing damage due to sudden and

unexpected incidents. However, the IC should never be used in applications where the protection circuit operates

continuously (e.g. when a load that significantly exceeds the output current capability of the chip is connected).

I_OCP

I_L

I_OUT

V_OUT

Figure 40. Over Current Protection

2. Short Circuit Protection (SCP)

For BD9P205MUF-C, the Short Circuit Protection (SCP) block compares the FB pin voltage with the internal reference

voltage VREF. When the FB pin voltage has decreased to V_SCPL(0.64 V, Typ) or less and remained there for 0.9 ms

(Typ), SCP stops the operation for 30 ms (Typ) and subsequently initiates a restart. If the FB pin voltage decreases to

V_SCPL(0.64 V, Typ) or less and increases to V_SCPH(0.72 V, Typ) or more within 0.9 ms afterwards, SCP protection is

released and output voltage recovers to normal operation. For BD9P235MUF-C and BD9P255MUF-C, the SCP block

monitors the VOUT_SNS pin for the protection. SCP detection voltage V_SCPLis 80 % (Typ) of normal output voltage. On

the other hand, SCP release voltage V_SCPHis 90 % (Typ) of normal output voltage.

The SCP function is deactivated during 7 ms (Typ) from VOUT starting up. In addition, when VIN decreases and VOUT

also decreases, the SCP function is deactivated not to detect short circuit protection. The SCP function is likewise

deactivated when VIN voltage is lower than V_{SCP_DACT}(133 %, Typ) of the VOUT_SNS pin voltage, and then is activated

after 7 ms (Typ) from VIN voltage exceeds V_{SCP_DACT}(133 %, Typ) of the VOUT_SNS pin voltage. Therefore, in the case

of short circuit from VIN close to VOUT condition, SCP stops the switching operation after 7.9 ms (Typ) from short circuit.

However, the device should never be used in applications characterized by continuous operation of the protection circuit

(e.g. when a load that significantly exceeds the output current capability of the chip is connected).

Output

Load

Condition

Normal

Over Load

Normal

V_IN

V_OUTx 133 %

33 %

V_OUT

V_OUTx 133 %

33 %

100 %

V_FB

V_SCPH:0.72 V (Typ)

V_SCPL:0.64 V (Typ)

0.9 ms

(Typ)

0.9 ms

(Typ)

0.9 ms

(Typ)

V_SW

HiZ

OCP

Threshold

OCP

Threshold

Inductor

Current

(Internal)

SCP Mask

Delay Signal

7 ms (Typ)

7.9 ms (Typ)

(Internal)

HICCUP

Delay Signal

30 ms (Typ)

SCP Reset

Figure 41. Short Circuit Protection (SCP) Timing Chart (BD9P205MUF-C)

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Protect Function - continued

3. Power On Reset (POR)/Under Voltage Lockout Protection (UVLO)

The UVLO and POR are integrated to prevent the malfunction when the power supply voltage is decreased. The POR

monitors the VIN pin voltage. On the other hand, UVLO monitors the VREG pin voltage.

In the sequence of VIN rising, the VREG pin voltage also rises up to 3.3 V (Typ) following VIN voltage. First, UVLO is

released when VREG voltage increase above V_{UVLO_R}(2.95 V, Typ). Next, POR is released when VIN voltage increase

above V_{POR_R}(3.8 V, Typ). When both POR and UVLO are released, the IC starts up with soft start.

In the sequence of VIN falling, VREG voltage also falls. When VREG voltage decreases below V_{UVLO_F}(2.85 V, Typ),

UVLO is detected and puts the IC goes into standby state. At the same time, POR is detected. When the VCC_EX pin is

connected to VOUT, VREG voltage supplied from VCC_EX. In this case, drop voltage between VIN and VREG becomes

larger than the case of VCC_EX connected to GND because VOUT voltage is restricted by maximum duty at low VIN

condition. Therefore, UVLO is detected at higher VIN condition than the case when the VCC_EX pin is connected to

GND.

V_{POR_R}

3.8 V (Typ)

3.3 V (Typ)

V_{UVLO_R}

2.95 V (Typ)

V_{UVLO_F}

2.85 V (Typ)

V_IN

V_REG

POR

UVLO

V_OUT

Figure 42. POR/UVLO Timing Chart

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Protect Function - continued

4. Thermal Shutdown (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. If junction temperature (Tj) exceeds

TSD detection temperature (175 °C, Typ), the POWER MOSFETs are turned off. When the Tj falls below the TSD

temperature (150 °C, Typ), the IC restarts up with soft start. Where the input voltage required for the restart is the same

as that for the initial startup (Input voltage 4.0 V or more). Note that the TSD circuit operates in a situation that exceeds

the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set design or

for any purpose other than protecting the IC from heat damage.

V_IN

V_EN

TSD Detect

175 °C (Typ)

TSD Release

150 °C (Typ)

Tj

V_REG

V_{UVLO_R}

2.95 V (Typ)

V_RTH

V_OUT

t_RSTNACT

3.6 ms

(Typ)

t_DLY

400 µs

(Typ)

V_RESET

Figure 43. TSD Timing Chart

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Protect Function - continued

5. Over Voltage Protection (OVP)

This IC has Over Voltage Protection (OVP) monitoring FB to prevent the increase of output voltage in case of external

injected current to VOUT. When FB voltage exceeds V_OVPH(107.3 % of its setting voltage V_FB1), the switching regulator

sinks current from VOUT by changing state to PWM. The sink current during OVP is restricted to I_NCP(2.500 A, Typ)

(OCP_SEL = L). In addition, the RESET pin is pulled down to GND during OVP detection. To prevent the malfunction by

noise, the internal delay t_RSTNFILTof 5 µs (Typ) is implemented after OVP detection. When FB voltage falls below V_OVPL

(104.7 % of its setting voltage V_FB1), OVP function is released. The RESET pin is kept low and PWM switching is also

kept during t_RSTNACT(3.6 ms, Typ) after OVP function is released. When OCP_SEL is set high level, then I_NCPvalue is

changed to I_NCP(1.875 A, Typ).

If the FB pin is open, this IC cannot regulate VOUT correctly. In this case, if VOUT voltage exceeds V_SNSOVPHor

VCC_EX voltage exceed V_EXOVPH, the VOUT is pulled down by PWM switching to protect internal devices same as the

situation that the FB pin over voltage is detected.

V_OUT

V_OVPH

V_OVPL

V_FB

I_L

I_NCP

V_SW

t_RSTNACT

V_RESET

t_RSTNFILT

Figure 44. FB OVP Timing Chart

V_EXOVPH/V_SNSOVPH

V_EXOVPL/V_SNSOVPL

V_OUT

V_FB

I_OCP

I_L

I_NCP

V_SW

V_RESET

< t_RSTNACT

t_RSTNFILT

Figure 45. VCC_EX/VOUT_SNS OVP Timing Chart

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5. Over Voltage Protection (OVP) - continued

If VOUT is shorted to the Battery Line as following figure, the DC/DC converter (BD9P2x5MUF-C) sinks current from

VOUT to the Low Side FET. If a Reverse Polarity Protection Diode is on the Battery Line, the VIN voltage results in being

boosted up and might exceed the absolute maximum ratings.

Battery Line

Reverse Polarity

Protection Diode

D

Battery Line

VIN

L1

VOUT

SW

DC/DC Converter

Figure 46. VOUT Shorted to Battery Line

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Selection of Components Externally Connected

Contact us if not use the recommended constant in the application circuit.

Necessary parameters in designing the power supply are as follows:

Table 1. Application Sample Specification

Parameter

Input Voltage

Symbol

V_IN

Specification Case

3.5 V to 40 V

5.0 V

Output Voltage

V_OUT

ΔV_P-P

I_OUT

Output Ripple Voltage

Output Current

20 mV_p-p

Typ 1.0 A/Max 2.0 A

2.2 MHz

Switching Frequency

Operating Temperature Range

f_SW

Ta

-40 °C to +125 °C

C_BST

V_IN

VIN

BST

L₁

V_OUT

SW

PVIN

VCC_EX

R_FB1

EN

FB

C_BLKC_IN

PGND

VREG

OCP_SEL

VOUT_SNS

RESET

MODE

C_OUT

R_RST

R_FB2

V_MODE

V_SSCG

C_REG

SSCG

GND

Figure 47. Application Sample Circuit

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Selection of Components Externally Connected - continued

1. Selection of the Inductor L₁value

The inductor in the switching regulator supplies a continuous current to the load and functions as a filter to smooth the

output voltage. In current mode control, the sub-harmonic oscillation may happen. The slope compensation circuit is

integrated into the IC to prevent the sub-harmonic oscillation. The sub-harmonic oscillation depends on the rate of

increase of output switch current. If the inductor value is too small, the sub-harmonic oscillation may happen because

the inductor ripple current ΔI_Lis increased. If the inductor value is too large, the feedback loop may not achieve stability

because the inductor ripple current ΔI_Lis decreased.

The recommended inductor value for each output voltage and OCP_SEL pin setting is shown below.

Table 2. Recommended Inductor Value

Output voltage

OCP_SEL

Maximum output current

Inductor value

3.3 μH

L

H

L

2.0 A

1.5 A

2.0 A

1.5 A

1.1 V < V_OUT

4.7 μH

V_OUT≤ 1.1 V

H

6.8 μH

The peak to peak inductor current is shown by the following equation:

(

)

×ꢕ

ꢕ

−ꢕ

ꢜꢝ

ꢟꢇꢂ

∆ꢏ_퐿=

[A]

ꢕ

ꢜꢝ

×푓 ×퐿

ꢁꢒ

Where:

푉

푉_푂푈푇

is the input voltage [V]

퐼푁

is the output voltage [V]

is the switching frequency [Hz]

is the inductor value [H]

ꢔ

푆푊

ꢠ

ΔV_P-P(Output peak-to-peak ripple voltage) is shown in the following equation.

∆퐼

ꢈ

∆푉_푃−푃= ∆ꢏ_퐿× ꢡꢢꢊ ꢗ _8×퐶

[V]

(a)

×푓

ꢟꢇꢂ

ꢁꢒ

Where:

ꢡꢢꢊ

ꢣ_푂푈푇

is the equivalent series resistance of the output capacitor [Ω]

is the output capacitance [F]

ꢔ

푆푊

is the switching frequency [Hz]

The shielded type (closed magnetic circuit type) is the recommended type of inductor to be used. It is important not to

magnetic saturate the core in any situation, so please make sure that the definition of rated current is different according

to the manufactures. Please check the rated current at maximum ambient temperature of application to inductor

manufacturer.

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Selection of Components Externally Connected - continued

2. Selection of Output Capacitor C_OUT

The output capacitor is selected based on the ESR that is required from the previous page equation (a). ΔV_P-Pcan be

reduced by using a capacitor with a small ESR.

The ceramic capacitor is the best option that meets this requirement. It is because not only it has a small ESR but the

ceramic capacitor also contributes to the size reduction of the application circuit. Please confirm the frequency

characteristics of ESR from the datasheet of the capacitor manufacturer, and consider a low ESR value for the switching

frequency being used. It is necessary to consider that the capacitance of the ceramic capacitor changes obviously

according to DC biasing characteristic. For the voltage rating of the ceramic capacitor, twice or more the maximum

output voltage is usually required. By selecting a high voltage rating, it is possible to reduce the influence of DC bias

characteristics. Moreover, in order to maintain good temperature characteristics, the one with the characteristics of X7R

or better is recommended. Because the voltage rating of a large ceramic capacitor is low, the selection becomes difficult

for an application with high output voltage. In that case, please connect multiple ceramic capacitors.

These capacitors are rated in ripple current. The RMS values of the ripple current that can be obtained in the following

equation and must not exceed the ripple current rating.

∆퐼

ꢈ

ꢏ_{퐶푂푈푇(푅푀푆)}

=

[A]

ꢖ2

√

Where:

ꢏ_{퐶푂푈푇(푅푀푆)}

is the value of the ripple electric current [A]

Next, when the output setting voltage is 3.3 V or more, it is recommended that the output ceramic capacitor C_OUTis 44

μF (Typ) or more for OCP_SEL = L and 32 μF (Typ) or more for OCP_SEL = H. When the output setting voltage less

than 3.3 V, the output ceramic capacitor C_OUTis recommended to the following equation.

Table 3. Output Ceramic Capacitor Recommended Capacitance Value

OCP_SEL

V_OUT≥ 3.3 V

1.1 V < V_OUT< 3.3 V

V_OUT≤ 1.1 V

2ꢖ7.8

ꢖꢤ5.2

ꢣ_푂푈푇

≥

[μF]

L

ꢣ_푂푈푇

≥

[μF]

ꢣ_푂푈푇≥ 44 [μF]

ꢕ

ꢟꢇꢂ

ꢕ

ꢟꢇꢂ

ꢖ26.7

ꢖ05.6

[μF]

H

ꢣ_푂푈푇≥ 3ꢥ [μF]

ꢕ

ꢟꢇꢂ

ꢕ

ꢟꢇꢂ

When selecting the capacitor ensure that the capacitance C_{OUT_WORST}of the following equation is maintained at the

characteristics of DC Bias, AC Voltage, temperature, and tolerance.

Table 4. Output Ceramic Capacitor Minimum Capacitance Value

OCP_SEL

V_OUT≥ 3.3 V

1.1 V < V_OUT< 3.3 V

V_OUT≤ 1.1 V

ꢖꢤ8.5

99.0

ꢣ_푂푈푇

≥

[μF]

L

ꢣ_푂푈푇

≥

[μF]

ꢣ_푂푈푇≥ 3ꢦ [μF]

ꢕ

ꢟꢇꢂ

ꢕ

ꢟꢇꢂ

ꢖ00.0

66.0

[μF]

H

ꢣ_푂푈푇≥ ꢥꢦ [μF]

ꢕ

ꢟꢇꢂ

ꢕ

ꢟꢇꢂ

If the capacitance falls below this value, the oscillation may happen. When using the electrolytic capacitor and the

conductive polymer hybrid aluminum electrolytic capacitor, please place it in addition to the ceramic capacitors with the

capacity described above. Actually, the changes in the frequency characteristic are greatly affected by the type and the

condition (temperature, etc.) of parts that are used, the wire routing and layout of the PCB. Please confirm stability and

responsiveness in actual application. And please place PCB patterns that allows C_OUTadjustment from the initial design

in case of insufficient stability and responsiveness.

In addition, for the total value of capacitance in the output line C_OUT(Max), please choose a capacitance value less than

the value obtained by the following equation:

ꢧ

×ꢖ.25×ꢨ퐼

−퐼

ꢪ

ꢁꢁ(ꢃ푖푛)

ꢟꢙꢆ(ꢃ푖푛) ꢟꢇꢂ_ꢁꢂꢩꢀꢂ(ꢃꢄꢅ)

ꢣ_{푂푈푇(푀푎푥)}

<

[F]

ꢕ

ꢟꢇꢂ

Where:

ꢏ_{푂퐶푃(푀ꢫꢬ)}

푡_{푆푆(푀ꢫꢬ)}

is the OCP operation current (Min) [A]

is the Soft Start Time (Min) [s]

ꢏ_{푂푈푇_푆푇퐴푅푇(푀푎푥)}is the maximum load current during startup [A]

is the output voltage [V]

푉_푂푈푇

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Selection of Components Externally Connected - continued

3. Selection of Input Capacitor C_IN, C_BLK

For input capacitors, there are two types of capacitor: decoupling capacitors C_INand bulk capacitors C_BLK

.

Ceramic capacitors with total values 2.3 µF or more are necessary for the decoupling capacitors C_INfor ripple noise

reduction. If a low ESR electrolytic capacitor with large capacitance is connected parallel to the decoupling capacitors as

a bulk capacitor, ceramic capacitors with 0.5 µF or more are necessary for the decoupling capacitors. (However, to

reduce EMI noise level, 2.3 µF or more are recommended for ceramic capacitors.) These capacitor values including

device variation, temperature characteristics, DC bias characteristics, and aging change must be larger than minimum

value. It is effective for switching noise reduction to place one of ceramic capacitor close to the PVIN and the VIN pins.

The voltage rating of the capacitors is recommended to be 1.2 times or more the maximum input voltage, or twice the

normal input voltage. Also, the IC might not operate properly when the PCB layout or the position of the capacitor is not

good. Please check “PCB Layout Design” on page 48.

The bulk capacitor is optional. The bulk capacitor prevents the decrease in the line voltage and serves as a backup

power supply to keep the input voltage constant. A low ESR electrolytic capacitor with large capacitance is suitable for

the bulk capacitor. It is necessary to select the best capacitance value for each of application. In that case, please take

note not to exceed the rated ripple current of the capacitor.

The RMS value of the input ripple current I_CIN(RMS)is obtained in the following equation:

ꢕ

ꢖ

ꢟꢇꢂ

2

ꢏ_{퐶퐼푁 푅푀푆}

=

)

× {ꢏ_{푂푈푇(푀푎푥)}²× ꢑ1 ꢎ ^ꢟꢇꢂꢓ ꢗ _ꢖ2× 훥ꢏ_퐿} [A]

ꢕ

ꢜꢝ ꢜꢝ

ꢭ

(

ꢕ

Where:

ꢏ_{푂푈푇(푀푎푥)}

is the output current (Max) [A]

In addition, in automotive and other applications requiring high reliability, it is recommended to connect the capacitors in

parallel to accommodate multiple electrolytic capacitors and minimize the chances of drying up. For ceramic capacitors,

it is recommended to make two series + two parallel structures to decrease the risk of capacitor destruction due to short

circuit conditions.

When the impedance on the input side is high for some reason (because the wiring from the power supply to the VIN pin

is long, etc.), then high capacitance is required. In actual conditions, it is necessary to verify that there are no problems

like IC is turned off, or the output overshoots due to the change in V_INat transient response.

4. Selection of the Bootstrap Capacitor

For Bootstrap capacitor C_BST, please connect a 0.1 μF (Typ) ceramic capacitor as close as possible between the BST

pin and the SW pin.

5. Selection of the VREG Capacitor.

For VREG capacitor C_REG, please connect a 1.0 μF (Typ) ceramic capacitor between the VREG pin and GND.

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BD9P2x5MUF-C Series

Selection of Components Externally Connected - continued

6. Selection of Output Voltage Setting Resistor R_FB1, R_FB2(BD9P205MUF-C)

For the BD9P205MUF-C, the output voltage is set with output voltage setting resistors R_FB1and R_FB2.The reference

voltage of GmAmp1 is set to 0.8 V and the IC operates to regulate the FB pin voltage to 0.8 V. The output voltage is

defined by the formula (1). R_FB1and R_FB2should be adjusted to set the required output voltage. If R_FB1and R_FB2are large,

the current flowing through on these resistors is small and the circuit current at no load can be reduced. However, the

phase shift is likely to happen because of the parasitic capacitance of IC and PCB on the FB pin. Therefore, the

combined resistance R_FB1//R_FB2should be set to 100 kΩ or less. If the combined resistance R_FB1//R_FB2is 100 kΩ or more,

C_FB1and C_FB2should be chosen to satisfy the formula (2). In this case, the value of C_FB1and C_FB2should be chose the

capacitor of 47 pF or more that is much larger than C_P.

푅

+푅

ꢮꢯꢰ

푉_푂푈푇

=

^ꢮꢯꢱ× ꢦ.ꢲ [V]

(1)

푅

ꢮꢯꢱ

푅

×퐶

ꢮꢯꢰ

ꢮꢯꢱ

ꢮꢯꢰ

≈ 1

(2)

ꢮꢯꢱ

VOUT

C_FB1

R_FB1

FB

Gm Amp1

comp

0.80 V

R_FB2

C_FB2

C_P

Figure 48. Setting for Output Setting Resistor

The changes in the frequency characteristic are greatly affected by the type and the condition (temperature, etc.) of

parts that are used. Please ensure a phase margin of 45° or more and a gain margin of 5 dB or more in actual

application. If it cannot ensure, C_FB1and C_FB2should be chosen to satisfy the following equation as a guide. Please place

PCB patterns that allows C_FB1and C_FB2adjustment from the initial design in case of insufficient stability and

responsiveness.

8000

ꢣ_퐹퐵ꢖ

≤

[pF]

푅

ꢮꢯꢰ

ꢣ_퐹퐵ꢖ× ꢑ_푅^푅^ꢮꢯꢰꢓ ≤ ꢣ_퐹퐵2≤ ꢣ_퐹퐵ꢖ× ꢑ^5×푅^ꢮꢯꢰꢗ 4ꢓ [pF]

푅

ꢮꢯꢱ

Where:

ꢊ_퐹퐵ꢖ

ꢊ_퐹퐵2

is the output voltage setting resistors [kΩ]

If the voltage between input and output increases and the ON time of the SW decreases to under t_ONMIN, the switching

frequency is decreased. To ensure stable switching frequency, the output voltage must satisfy the following equation. If

this equation is not satisfied, the SW pulse is skipped. In this case, the switching frequency decreases and the output

voltage ripple increases.

푉_푂푈푇≥ 푉

× ꢔ

× 푡_{푂푁푀퐼푁(푀푎푥)}[V]

퐼푁(푀푎푥)

푆푊(푀푎푥)

Where:

푉

is the Input Voltage (Max) [V]

퐼푁(푀푎푥)

ꢔ

is the Switching Frequency (Max) [Hz]

(Refer to page 11)

(Refer to page 10)

푆푊(푀푎푥)

푡_{푂푁푀퐼푁(푀푎푥)}is the SW Minimum ON time (Max) [s]

If the voltage between input and output decreases, the ON time of the SW increases by skipping the off time and the

switching frequency is decreased. To keep switching frequency stably, the following equation must be satisfied.

푉_푂푈푇≤ 푉

× (1 ꢎ ꢔ

× 푡

₎) [V]

(

)

(

)

(

퐼푁 푀ꢫꢬ

푆푊 푀푎푥

푂퐹퐹푀퐼푁 푀푎푥

Where:

푡_{푂퐹퐹푀퐼푁(푀푎푥)}is the SW Minimum OFF Time (Max) [s] (Refer to page 10)

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BD9P2x5MUF-C Series

Application Examples 1

Table 5. Specification Example 1

Parameter

Product Name

Symbol

IC

Specification Case

BD9P205MUF-C

8 V to 18 V

Input Voltage

V_IN

Output Voltage

V_OUT

I_OUT

Ta

6.0 V

Output Current

Typ 1.0 A / Max 2.0 A

-40 °C to +125 °C

Operating Temperature Range

C_BST

L_F1

V_IN

V_BAT

VIN

PVIN

EN

BST

L₁

V_OUT

SW

VCC_EX

R_FB1

FB

C_IN2C_IN1

C_F1

C_F2C_BLK

PGND

VOUT_SNS

C_OUT1C_OUT2

R_RST

RESET

MODE

SSCG

VREG

R_FB2

V_MODE

V_SSCG

OCP_SEL

C_REG

GND

Π-type filter

Figure 49. Reference Circuit 1

Table 6. Application Example 1 Parts List with π-type Filter

No.

Package

Parameters

1 µF, X7R, 50 V

2.2 µH

Part Name (Series)

Type

Manufacturer

(Note 1)

C_F1

3216

GCJ31MR71H105K

CLF6045NIT-2R2N-D

GCM155R71H104K

Ceramic

Inductor

Ceramic

MURATA

TDK

L_F1

W6.0 x H4.5 x L6.3 mm³

1005

C_F2

0.1 µF, X7R, 50 V

MURATA

Electrolytic

capacitor

C_BLK

φ10 mm x L10 mm

220 µF, 35 V

UWD1V221MCL1GS

NICHICON

(Note 1)

C_IN2

3216

1 µF, X7R, 50 V

0.1 µF, X7R, 50 V

1 µF, X7R, 16 V

0.1 µF, X7R, 50 V

10 kΩ, 1 %, 1/16 W

3.3 µH

GCJ31MR71H105K

GCM155R71H104K

GCM21BR71C105K

GCM155R71H104K

MCR01MZPF1002

CLF6045NIT-3R3N-D

GCM32ER71A226K

MCR01MZPF1303

MCR01MZPF2002

Ceramic

MURATA

ROHM

C_IN1

C_REG

C_BST

R_RST

L₁

1005

2012

Ceramic

1005

Ceramic

1005

Chip resistor

Inductor

W6.0 x H4.5 x L6.3 mm³

TDK

C_OUT1

C_OUT2

R_FB1

R_FB2

3225

1005

22 µF, X7R, 10 V

130 kΩ, 1 %, 1/16 W

20 kΩ, 1 %, 1/16 W

Ceramic

MURATA

ROHM

Ceramic

Chip resistor

ROHM

(Note 1) To reduce EMI noise level, 4.7 µF, (3225, X7R, 50 V, GCM32ER71H475K) is recommended for C_F1and C_IN2

.

Table 7. Application Example 1 Parts List without π-type Filter

No.

C_F1

Package

Parameters

Open

Part Name (Series)

Type

Manufacturer

-

L_F1

-

Open

-

C_F2

-

Open

-

C_BLK

C_IN2

C_IN1

-

Open

-

3225

1005

4.7 µF, X7R, 50 V

0.1 µF, X7R, 50 V

GCM32ER71H475K

GCM155R71H104K

Ceramic

MURATA

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BD9P2x5MUF-C Series

Application Examples 1 - continued

(Ta = 25 °C)

100

90

10000

1000

100

10

MODE = High

80

70

MODE = Low

60

50

40

1

30

MODE = High

20

10

0

0.1

MODE = Low

0.01

0.1

1

10

100

1000 10000

0.01

0.1

1

10

100 1000 10000

Output Current [mA]

Figure 50. Efficiency vs Output Current

(V_IN= 12 V)

Figure 51. Input Current vs Output Current

(V_IN= 12 V)

80

180

135

90

60

40

Phase

V_MODE(5 V/div)

V_SW(5 V/div)

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

Gain

V_OUT(100 mV/div) offset 6 V

Time (200 µs/div)

100

1k

10k

100k

1M

Frequency [Hz]

Figure 52. Frequency Characteristic

(V_IN= 12 V, I_OUT= 1.0 A)

Figure 53. MODE ON/OFF Response

(V_IN= 12 V, I_OUT= 50 mA)

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BD9P2x5MUF-C Series

Application Examples 1 - continued

(Ta = 25 °C)

I_OUT(1.0 A/div)

offset 6 V

V_OUT(100 mV/div)

V_OUT(100 mV/div) offset 6 V

Time (1 ms/div)

Figure 54. Load Response 1

(V_IN= 12 V, V_MODE= 5 V, I_OUT= 0 A to 2 A)

Figure 55. Load Response 2

(V_IN= 12 V, V_MODE= 0 V, I_OUT= 0 A to 2 A)

V_IN(5 V/div)

V_IN(2 V/div)

V_OUT(2 V/div)

offset 6 V

V_OUT(100 mV/div)

Time (200 µs/div)

Figure 56. Line Response 1

(V_IN= 16 V to 8 V, I_OUT= 2 A)

Figure 57. Line Response 2

(V_IN= 16 V to 5 V, I_OUT= 2 A)

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BD9P2x5MUF-C Series

Application Examples 1 - continued

(Ta = 25 °C)

8

7

6

5

4

3

2

1

0

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

Input Voltage [V]

Figure 58. Output Voltage vs Input Voltage 1

(R_LOAD= 300 Ω)

Figure 59. Output Voltage vs Input Voltage 2

(R_LOAD= 3 Ω)

6.100

6.050

6.000

5.950

5.900

6.100

6.050

6.000

5.950

5.900

0

500

1000

1500

2000

8

10

12

14

16

18

Output Current [mA]

Input Voltage [V]

Figure 60. Line Regulation

(I_OUT= 2 A)

Figure 61. Load Regulation

(V_IN= 12 V)

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BD9P2x5MUF-C Series

Application Examples 2

Table 8. Specification Example 2

Parameter

Product Name

Symbol

IC

Specification Case

BD9P235MUF-C

8 V to 18 V

Input Voltage

V_IN

Output Voltage

V_OUT

I_OUT

Ta

3.3 V

Output Current

Typ 1.0 A / Max 2.0 A

-40 °C to +125 °C

Operating Temperature Range

C_BST

L_F1

V_IN

V_BAT

VIN

PVIN

EN

BST

SW

L₁

V_OUT

VCC_EX

VOUT_DIS

C_IN2C_IN1

C_F1

C_F2C_BLK

PGND

VOUT_SNS

RESET

MODE

C_OUT1C_OUT2

R_RST

VREG

V_MODE

V_SSCG

OCP_SEL

C_REG

SSCG

GND

Π-type filter

Figure 62. Reference Circuit 2

Table 9. Application Example 2 Parts List with π-type Filter

No.

Package

Parameters

1 µF, X7R, 50 V

2.2 µH

Part Name (Series)

Type

Manufacturer

(Note 1)

C_F1

3216

GCJ31MR71H105K

CLF6045NIT-2R2N-D

GCM155R71H104K

Ceramic

Inductor

Ceramic

MURATA

TDK

L_F1

W6.0 x H4.5 x L6.3 mm³

1005

C_F2

0.1 µF, X7R, 50 V

MURATA

Electrolytic

capacitor

C_BLK

φ10 mm x L10 mm

220 µF, 35 V

UWD1V221MCL1GS

NICHICON

(Note 1)

C_IN2

3216

1 µF, X7R, 50 V

0.1 µF, X7R, 50 V

1 µF, X7R, 16 V

0.1 µF, X7R, 50 V

10 kΩ, 1 %, 1/16 W

3.3 µH

GCJ31MR71H105K

GCM155R71H104K

GCM21BR71C105K

GCM155R71H104K

MCR01MZPF1002

CLF6045NIT-3R3N-D

GCM32ER71A226K

Ceramic

Chip resistor

Inductor

MURATA

ROHM

C_IN1

C_REG

C_BST

R_RST

L₁

1005

2012

1005

W6.0 x H4.5 x L6.3 mm³

TDK

C_OUT1

3225

22 µF, X7R, 10 V

Ceramic

MURATA

C_OUT2

3225

22 µF, X7R, 10 V

Ceramic

(Note 1) To reduce EMI noise level, 4.7 µF, (3225, X7R, 50 V, GCM32ER71H475K) is recommended for C_F1and C_IN2

.

Table 10. Application Example 2 Parts List without π-type Filter

No.

C_F1

Package

Parameters

Open

Part Name (Series)

Type

Manufacturer

-

L_F1

-

Open

-

C_F2

-

Open

-

C_BLK

C_IN2

C_IN1

-

Open

-

3225

1005

4.7 µF, X7R, 50 V

0.1 µF, X7R, 50 V

GCM32ER71H475K

GCM155R71H104K

Ceramic

MURATA

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BD9P2x5MUF-C Series

Application Examples 2 - continued

(Ta = 25 °C)

100

90

1000

100

10

80

MODE = High

70

MODE = Low

60

50

40

1

30

20

10

0

MODE = High

0.1

0.01

MODE = Low

0.01

0.1

1

10

100

1000 10000

0.01

0.1

1

10

100 1000 10000

Output Current [mA]

Figure 63. Efficiency vs Output Current

(V_IN= 12 V)

Figure 64. Input Current vs Output Current

(V_IN= 12 V)

80

60

180

135

90

Phase

V_MODE(5 V/div)

V_SW(5 V/div)

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

Gain

V_OUT(100 mV/div) offset 3.3 V

Time (200 µs/div)

100

1k

10k

100k

1M

Frequency [Hz]

Figure 65. Frequency Characteristic

(V_IN= 12 V, I_OUT= 1.0 A)

Figure 66. MODE ON/OFF Response

(V_IN= 12 V, I_OUT= 50 mA)

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BD9P2x5MUF-C Series

Application Examples 2 - continued

(Ta = 25 °C)

I_OUT(1.0 A/div)

offset 3.3 V

V_OUT(100 mV/div)

V_OUT(100 mV/div) offset 3.3 V

Time (1 ms/div)

Figure 67. Load Response 1

(V_IN= 12 V, V_MODE= 5 V, I_OUT= 0 A to 2 A)

Figure 68. Load Response 2

(V_IN= 12 V, V_MODE= 0 V, I_OUT= 0 A to 2 A)

V_IN(5 V/div)

V_IN(2 V/div)

offset 3.3 V

V_OUT(100 mV/div)

V_OUT(2 V/div)

Time (200 µs/div)

Figure 69. Line Response 1

(V_IN= 16 V to 8 V, I_OUT= 2 A)

Figure 70. Line Response 2

(V_IN= 16 V to 3.5 V, I_OUT= 2 A)

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BD9P2x5MUF-C Series

Application Examples 2 - continued

(Ta = 25 °C)

8

7

6

5

4

3

2

1

0

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

Input Voltage [V]

Figure 71. Output Voltage vs Input Voltage 1

(R_LOAD= 165 Ω)

Figure 72. Output Voltage vs Input Voltage 2

(R_LOAD= 1.65 Ω)

3.366

3.337

3.308

3.279

3.250

3.366

3.337

3.308

3.279

3.250

8

10

12

14

16

18

0

500

1000

1500

2000

Input Voltage [V]

Output Current [mA]

Figure 73. Line Regulation

(I_OUT= 2 A)

Figure 74. Load Regulation

(V_IN= 12 V)

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BD9P2x5MUF-C Series

Application Examples 3

Table 11. Specification Example 3

Parameter

Product Name

Symbol

IC

Specification Case

BD9P255MUF-C

8 V to 18 V

Input Voltage

V_IN

Output Voltage

V_OUT

I_OUT

Ta

5.0 V

Output Current

Typ 1.0 A / Max 2.0 A

-40 °C to +125 °C

Operating Temperature Range

C_BST

L_F1

V_IN

V_BAT

VIN

PVIN

EN

BST

SW

L₁

V_OUT

VCC_EX

VOUT_DIS

C_IN2C_IN1

C_F1

C_F2C_BLK

PGND

VOUT_SNS

RESET

MODE

C_OUT1C_OUT2

R_RST

VREG

V_MODE

V_SSCG

OCP_SEL

C_REG

SSCG

GND

Π-type filter

Figure 75. Reference Circuit 3

Table 12. Application Example 3 Parts List with π-type Filter

No.

Package

Parameters

1 µF, X7R, 50 V

2.2 µH

Part Name (Series)

Type

Manufacturer

(Note 1)

C_F1

3216

GCJ31MR71H105K

CLF6045NIT-2R2N-D

GCM155R71H104K

Ceramic

Inductor

Ceramic

MURATA

TDK

L_F1

W6.0 x H4.5 x L6.3 mm³

1005

C_F2

0.1 µF, X7R, 50 V

MURATA

Electrolytic

capacitor

C_BLK

φ10 mm x L10 mm

220 µF, 35 V

UWD1V221MCL1GS

NICHICON

(Note 1)

C_IN2

3216

1 µF, X7R, 50 V

0.1 µF, X7R, 50 V

1 µF, X7R, 16 V

0.1 µF, X7R, 50 V

10 kΩ, 1 %, 1/16 W

3.3 µH

GCJ31MR71H105K

GCM155R71H104K

GCM21BR71C105K

GCM155R71H104K

MCR01MZPF1002

CLF6045NIT-3R3N-D

GCM32ER71A226K

Ceramic

Chip resistor

Inductor

MURATA

ROHM

C_IN1

C_REG

C_BST

R_RST

L₁

1005

2012

1005

W6.0 x H4.5 x L6.3 mm³

TDK

C_OUT1

3225

22 µF, X7R, 10 V

Ceramic

MURATA

C_OUT2

3225

22 µF, X7R, 10 V

Ceramic

(Note 1) To reduce EMI noise level, 4.7 µF, (3225, X7R, 50 V, GCM32ER71H475K) is recommended for C_F1and C_IN2

.

Table 13. Application Example 3 Parts List without π-type Filter

No.

C_F1

Package

Parameters

Open

Part Name (Series)

Type

Manufacturer

-

L_F1

-

Open

-

C_F2

-

Open

-

C_BLK

C_IN2

C_IN1

-

Open

-

3225

1005

4.7 µF, X7R, 50 V

0.1 µF, X7R, 50 V

GCM32ER71H475K

GCM155R71H104K

Ceramic

MURATA

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BD9P2x5MUF-C Series

Application Examples 3 - continued

(Ta = 25 °C)

100

90

10000

1000

100

10

80

MODE = High

70

MODE = Low

60

50

40

1

30

20

10

0

MODE = High

0.1

MODE = Low

0.01

0.1

1

10

100

1000 10000

0.01

0.1

1

10

100 1000 10000

Output Current [mA]

Figure 76. Efficiency vs Output Current

(V_IN= 12 V)

Figure 77. Input Current vs Output Current

(V_IN= 12 V)

80

60

180

135

90

Phase

V_MODE(5 V/div)

V_SW(5 V/div)

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

V_OUT(100 mV/div) offset 5 V

Gain

Time (200 µs/div)

100

1k

10k

100k

1M

Frequency [Hz]

Figure 78. Frequency Characteristic

(V_IN= 12 V, I_OUT= 1.0 A)

Figure 79. MODE ON/OFF Response

(V_IN= 12 V, I_OUT= 50 mA)

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BD9P2x5MUF-C Series

Application Examples 3 - continued

(Ta = 25 °C)

I_OUT(1.0 A/div)

V_OUT(100 mV/div) offset 5 V

offset 5 V

V_OUT(100 mV/div)

Time (1 ms/div)

Figure 80. Load Response 1

(V_IN= 12 V, V_MODE= 5 V, I_OUT= 0 A to 2 A)

Figure 81. Load Response 2

(V_IN= 12 V, V_MODE= 0 V, I_OUT= 0 A to 2 A)

V_IN(5 V/div)

V_IN(2 V/div)

V_OUT(2 V/div)

offset 5 V

V_OUT(100 mV/div)

Time (200 µs/div)

Figure 82. Line Response 1

(V_IN= 16 V to 8 V, I_OUT= 2 A)

Figure 83. Line Response 2

(V_IN= 16 V to 4 V, I_OUT= 2 A)

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BD9P2x5MUF-C Series

Application Examples 3 - continued

(Ta = 25 °C)

8

7

6

5

4

3

2

1

0

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

Input Voltage [V]

Figure 84. Output Voltage vs Input Voltage 1

(R_LOAD= 250 Ω)

Figure 85. Output Voltage vs Input Voltage 2

(R_LOAD= 2.5 Ω)

5.100

5.065

5.030

4.995

4.960

4.925

5.100

5.065

5.030

4.995

4.960

4.925

8

10

12

14

16

18

0

500

1000

1500

2000

Input Voltage [V]

Output Current [mA]

Figure 86. Line Regulation

(I_OUT= 2 A)

Figure 87. Load Regulation

(V_IN= 12 V)

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Automotive Power Supply Line Circuit

Reverse Polarity

Protection Diode

D

Battery Line

VIN

DC/DC Converter

L

C

TVS

π-type filter

Figure 88. Automotive Power Supply Line Circuit

As a reference, the automotive power supply line circuit example is given in figure above.

The π-type filter is a third-order LC filter. In general, it is used in combination with decoupling capacitors for high frequency.

Since large attenuation characteristics can be obtained, excellent characteristic is also obtained as an EMI filter. Devices

used for π-type filters should be placed close to each other.

TVS (Transient Voltage Suppressors) is used for primary protection of the automotive power supply line. Since it is

necessary to withstand high energy of load dump surge, a general zener diode is insufficient. Recommended device is

shown in the following table.

In addition, a reverse polarity protection diode is needed considering if a power supply such as Battery is accidentally

connected in the opposite direction.

Table 14. Reference Parts of Automotive Power Supply Line Circuit

Device

Part name (series)

CLF series

Manufacturer

TDK

Device

TVS

D

Part name (series)

SMB series

Manufacturer

Vishay

L

XAL series

Coilcraft

S3A to S3M series

Vishay

C

CJ series / CZ series

NICHICON

Recommended Parts Manufacturer List

Shown below is the list of the recommended parts manufacturers for reference.

Type

Electrolytic Capacitor

Ceramic Capacitor

Hybrid Capacitor

Inductor

Manufacturer

NICHICON

Murata

URL

www.nichicon.co.jp

www.murata.com

www.sunelec.co.jp

product.tdk.com

www.coilcraft.com

www.sumida.com

www.vishay.com

www.rohm.com

Suncon

TDK

Inductor

Coilcraft

SUMIDA

Vishay

Inductor

Diode

Diode/Resistor

ROHM

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PCB Layout Design

PCB layout design for DC/DC converter power supply IC is as important as the circuit design. Appropriate layout can avoid

various problems caused by power supply circuit. Figure 89 (a) to Figure 89 (c) figure the current path in a buck converter

circuit. The Loop1 in Figure 89 (a) is a current path when High Side Switch is ON and Low Side Switch is OFF, the Loop2 in

Figure 89 (b) is when High Side Switch is OFF and Low Side Switch is ON. The thick line in Figure 89 (c) shows the

difference between Loop1 and Loop2. The current in thick line changes sharply each time the switching element High Side

Switch and Low Side Switch change from OFF to ON, and vice versa. These sharp changes induce several harmonics in the

waveform. Therefore, the loop area of thick line that is consisted by input capacitor and IC should be as small as possible to

minimize noise. For more detail, refer to application note of switching regulator series “PCB Layout Techniques of Buck

Converter”.

Loop1

V_IN

V_OUT

L

High Side Switch

C_IN

C_OUT

Low Side Switch

GND

Figure 89 (a). Current Path when High Side Switch = ON, Low Side Switch = OFF

V_IN

V_OUT

L

High Side Switch

C_IN

C_OUT

Loop2

Low Side Switch

GND

V_IN

GND

Figure 89 (b). Current Path when High Side Switch = OFF, Low Side Switch = ON

V_OUT

L

High Side FET

C_IN

C_OUT

Low Side FET

GND

Figure 89 (c). Difference of Current and Critical Area in Layout

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PCB Layout Design – continued

When designing the PCB layout, please pay extra attention to the following points.

1. The decoupling capacitors (C_IN1) for the VIN pin (pin 20) and the PVIN pins (pin 1, 2) should be placed closest to the

PVIN pins and the PGND pins (pin 4, 5). In addition, placing a capacitor 0.1 μF close to the PVIN pin results in

minimizing the high-frequency noise.

2. The device, the input capacitor, the output inductor and the output capacitor should be placed on the same side of the

board and the connection of each part should be made on the same layer.

3. Place the ground plane in a layer closest to the surface layer where the device is mounted.

4. The GND pin (pin 13) is the reference ground and the PGND pins are the power ground. These pins should be

connected through the back side of the device. The power systems ground should be connected to the ground plane

using as many vias as possible.

5. The capacitor for VREG should be placed closest to the VREG pin (pin 17), the GND pin and the PGND pin. As

shown in the Recommended Board Layout Example, it can be realized that connecting with the shortest distance for

the GND pin and the PGND pins by placing the capacitor for VREG on the closest to the VREG pin and wiring at the

back side of the IC.

6. Place Bootstrap capacitor C_BSTclose to the device with short traces to the SW pins (pin 6, 7) and the BST pin (pin 8).

7. To minimize the emission noise from switching node, the distance between the SW pins to inductor should be as

short as possible and not to expand the copper area more than necessary.

8. Place the output capacitor close to the inductor and power ground area.

9. Make the feedback line from the output away from the inductor and the switching node. If this line is affected by

external noise, an error may be occurred in the output voltage or the control may become unstable. Therefore, move

the feedback line to back side layer of the board through via and connect it to the VOUT_SNS pin (pin 14

[BD9P205MUF-C], pin 15 [BD9P235MUF-C, BD9P255MUF-C]). When the VCC_EX function and the output

discharge function are used, connect it to the VCC_EX (pin 16) and the VOUT_DIS pin (pin 14 [BD9P235MUF-C,

BD9P255MUF-C]) as well, respectively.

10. R_FB1and R_FB2Feedback resistors are needed for BD9P205MUF-C. Place R_FB1, R_FB2close to the FB pin (pin 15).

11. R_FB0is for measuring the frequency characteristic of the feedback. By inserting a resistor in R_FB0, the frequency

characteristics (phase margin) of the feedback can be measured. R_FB0should be short-circuited for the normal use.

Reference Ground Area

Power Ground Area

Figure 90. Recommended Board Layout Example (for BD9P2x5MUF-C)

L₁

V_OUT

SW

VCC_EX

C_OUT

( R_FB0

)

VOUT_SNS

FB

R_FB1

R_FB2

Figure 91. The Resistor for Measuring the Frequency Characteristic of the Feedback

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Power Dissipation

For thermal design, be sure to operate the IC within the following conditions.

(Since the temperatures described hereunder are all guaranteed temperatures, take margin into account.)

1. The ambient temperature Ta is to be 125 °C or less.

2. The chip junction temperature Tj is to be 150 °C or less.

The chip junction temperature Tj can be considered in the following two patterns:

1. To obtain Tj from the package surface center temperature Tt in actual use

ꢳ푗 = ꢳ푡 ꢗ 휓_퐽푇× ꢴ [°C]

2. To obtain Tj from the ambient temperature Ta

ꢳ푗 = ꢳꢌ ꢗ 휃_퐽퐴× ꢴ [°C]

Where:

휓_퐽푇

휃_퐽퐴

is junction to top characterization parameter.

is junction to ambient.

(Refer to page 9)

The heat loss W of the IC can be obtained by the formula shown below.

This formula is approximation, please confirm this on the actual application circuit.

푉_푂푈푇

2

ꢴ = ꢊ_푂푁퐻× ꢏ_푂푈푇

×

ꢗ ꢊ_푂푁퐿× ꢏ_푂푈푇²ꢵ1 ꢎ

ꢶ

푉

퐼푁

ꢖ

(

)

ꢗ푉 × ꢏ_{푄_ꢕ퐼푁ꢤ}ꢗ 푉_푂푈푇× ꢏ_{푄_ꢕ퐶퐶_퐸푋2}ꢗ × 푡푟 ꢗ 푡ꢔ × 푉 × ꢏ_푂푈푇× ꢔ

[W]

퐼푁

푆푊

2

Where:

ꢊ_푂푁퐻

ꢊ_푂푁퐿

ꢏ_푂푈푇

is the High Side FET ON Resistance [Ω]

is the Low Side FET ON Resistance [Ω]

is the Load Current [A]

(Refer to page 11)

푉_푂푈푇

is the Output Voltage [V]

푉

퐼푁

is the Input Voltage [V]

ꢏ_{푄_ꢕ퐼푁ꢤ}

ꢏ_{푄_ꢕ퐶퐶_퐸푋2}

푡푟

푡ꢔ

is the Quiescent Current from VIN [A]

is the Quiescent Current from VCC_EX [A]

is the Switching Rise Time [s] (5 ns, Typ)

is the Switching Fall Time [s] (5 ns, Typ)

is the Switching Frequency [Hz]

(Refer to page 10)

ꢔ

푆푊

(Refer to page 11)

tr

tf

2

1. ꢊ_푂푁퐻× ꢏ_푂푈푇

2

2. ꢊ_푂푁퐿× ꢏ_푂푈푇

3. ^ꢖ× (푡푟 ꢗ 푡ꢔ) × 푉 × ꢏ_푂푈푇× ꢔ

퐼푁

푆푊

2

Figure 92. SW Waveform

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I/O Equivalence Circuits

19. EN

10. MODE

VREG

10 kΩ

EN

50 kΩ

MODE

850 kΩ

GND

GND GND

12. RESET

GND

6,7. SW, 8.BST

BST

SW

VREG

PVIN

RESET

100 Ω

VREG

GND

PGND

GND

9. OCP_SEL, 11. SSCG

14. VOUT_DIS

(BD9P235MUF-C, BD9P255MUF-C)

VREG

VOUT_DIS

56 Ω

50 kΩ

OCP_SEL/

SSCG

GND

*Resistance value is Typ.

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I/O Equivalence Circuits - continued

14. VOUT_SNS, 15. FB (BD9P205MUF-C)

15. VOUT_SNS (BD9P255MUF-C)

VOUT_SNS

21 MΩ

4 MΩ

VREG

GND

GND GND

10 kΩ

FB

10 kΩ

GND

15. VOUT_SNS (BD9P235MUF-C)

16. VCC_EX, 17. VREG

VIN

VOUT_SNS

12.5 MΩ

4 MΩ

VREG

GND GND

10 kΩ

GND

VCC_EX

15 MΩ

GND

*Resistance value is Typ.

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,

pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground

due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below

ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions

such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

6. Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

8. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

9. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge

acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause

unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power

supply or ground line.

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Operational Notes - continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 93. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

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BD9P2x5MUF-C Series

Ordering Information

B D 9 P 2

x

5 M U F -

C E 2

Part

Output Voltage

Package

Product Rank

Number

0: Adjustable

3: 3.3 V

5: 5.0 V

MUF: VQFN20FV4040

C: for Automotive

Packaging Specification

E2: Embossed tape and reel

Marking Diagram

VQFN20FV4040 (TOP VIEW)

Part Number Marking

LOT Number

Pin 1 Mark

Orderable Part Number

Output Voltage

Part Number Making

BD9P205MUF-CE2

BD9P235MUF-CE2

BD9P255MUF-CE2

Adjustable

3.3 V

9P205

9P235

9P255

5.0 V

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Physical Dimension and Packing Information

Package Name

VQFN20FV4040

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Revision History

Date

Revision

001

Changes

28.Apr.2020

New Release

Selection of Components Externally Connected

Change description of selection of the inductor L₁value

Change description of selection of Output Capacitor C_OUT

Change description of selection of Output Voltage Setting Resistor R_FB1, R_FB2

04.Oct.2022

002

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BD9P205MUF-C
厂家：	ROHM
描述：	BD9P系列是兼顾高速响应和高效率的42V耐压车载一次DC/DC转换器IC。其特点是通过Nano Pulse Control™实现的稳定且较大的降压比、通过扩频功能实现的低EMI（低噪声）、在电池刚启动时也能稳定供电的高速响应性能，有助于降低系统功耗和降低BOM成本。包括ADAS的传感器、摄像头、雷达，以及车载信息娱乐、仪表盘、 BCM（车身控制模块）在内，适用于汽车中要求小型化、高效率化、高可靠性的应用。a.productlink{color: #dc2039; text-decoration: underline !important;}a.productlink:hover {opacity: 0.6;} 电池仪表雷达传感器转换器
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BD9P205MUF-C [ROHM]

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