BM81810MUF-M [ROHM]
BM81810MUF-M is a power management IC for TFT-LCD panels which are used in car navigation, in-vehicle center panel, and instrument cluster. This IC incorporates VCOM amplifier, Gate Pulse Modulation (GPM) in addition to the power supply for panel driver (SOURCE, GATE, and LOGIC power supplies). Moreover, this IC has a built-in EEPROM for sequence and output voltage setting retention.;
| 型号： | BM81810MUF-M |
| 厂家： | 
ROHM |
| 描述： | BM81810MUF-M is a power management IC for TFT-LCD panels which are used in car navigation, in-vehicle center panel, and instrument cluster. This IC incorporates VCOM amplifier, Gate Pulse Modulation (GPM) in addition to the power supply for panel driver (SOURCE, GATE, and LOGIC power supplies). Moreover, this IC has a built-in EEPROM for sequence and output voltage setting retention. 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 栅 CD |
| 文件： | 总78页 (文件大小：3637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Power Supply IC Series for TFT-LCD Panels
Automotive Panel Power Management IC
BM81810MUF-M
General Description
Features
AEC-Q100 Qualified(Note 1)
BM81810MUF-M is
a power management IC for
TFT-LCD panels which are used in car navigation,
in-vehicle center panel, and instrument cluster.
Alternative Synchronous Buck DC/DC converter or LDO
for VDD output
This IC incorporates VCOM amplifier, Gate Pulse
Modulation (GPM) in addition to the power supply for
panel driver (SOURCE, GATE, and LOGIC power
supplies). Moreover, this IC has a built-in EEPROM for
sequence and output voltage setting retention.
Synchronous Boost DC/DC converter for AVDD output
with integrated load switch.
VCOM amplifier with 7bit calibrator
Positive charge pump (Integrated diode, x2/x3) for VGH
output
Negative charge pump for VGL output
VGH and VCOM temperature compensation
Gate Pulse Modulation(GPM)
Key Specifications
Input voltage range:
2.6V to 5.5V
5.0V to 17.0V
8.0V to 35.0V
-4.0V to -14.0V
0.9V to 3.4V
I2C Interface Output Voltage Setting Control Function
(Integrated EEPROM)
AVDD Output voltage range:
VGH Output voltage range:
VGL Output voltage range:
VDD Output voltage range:
VCOM Output current:
Switching Frequency:
Operating temperature range:
Standby current:
Switching frequency switching function
(525kHz, 1.05MHz, 2.1MHz)
Protection circuits
200 mA (Typ)
525KHz, 1.05MHz, 2.1MHz
Under-Voltage Lockout
Thermal Shut Down
Over-Current Protection
Over-Voltage Protection
-40°C to +105°C
2.0 μA (Typ)
Under Voltage Protection (Timer Latch type)
Special Characteristics
AVDD output voltage accuracy:
Oscillator Frequency:
Input tolerant (SCL, SDA, EN, GSIN)
(Note1: Grade 2)
±2%
±10%
Package
W(Typ) x D(Typ) x H(Max)
5.0mm x 5.0mm x 1.0mm
Applications
VQFN32FBV050
TFT-LCD Panels which are used in car navigation,
in-vehicle center panel, and instrument cluster.
Typical Application Circuit (TOP VIEW)
R_NTC2
R_NTC1
R_NTC3
WPN
R_FLT
VIN
R_RE
GSOUT
VIN
R_PG
Θ
VGH
FAULT
C_DRP2
CPP2
PG / LDSW
C_VGH
D_VGL
4 2 3 2 2 2 1 2 0 2 9 1 8 1 7 1
C_VCP
VCP
VIN
GSIN
SDA
C_DRP1
CPP1
R_RST
SCL
RST
DRP
DRN
C_DRN
VGL
VDD
SWB
EN
VCOM
L_SWB
C_VDD
C_VCOM
C_VGL
1
2
3
4
5
6
7
8
AVDD
AVDD
C_VINB
C_VIN
C_REG
(D_SW)
VIN
C_AVD
C_LSO
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 14 • 001
1/75
BM81810MUF-M
Contents
General Description........................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Special Characteristics ...................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Package……………….. ..................................................................................................................................................................1
Typical Application Circuit...............................................................................................................................................................1
Pin Configuration ............................................................................................................................................................................3
Pin Descriptions..............................................................................................................................................................................3
Absolute Maximum Ratings ............................................................................................................................................................4
Thermal Resistance........................................................................................................................................................................5
Recommended Operating Ratings ................................................................................................................................................5
Electrical Characteristics ...............................................................................................................................................................6
Typical Performance Curves.........................................................................................................................................................10
Application Example 1 ................................................................................................................................................................25
Timing Chart1 ...............................................................................................................................................................................27
Application Example 2 ................................................................................................................................................................29
Timing Chart2 ...............................................................................................................................................................................29
Application Example 3 ................................................................................................................................................................31
Timing Chart3 ...............................................................................................................................................................................33
Serial communication ...................................................................................................................................................................35
WPN Timing..................................................................................................................................................................................36
I2C Timing Diagram......................................................................................................................................................................37
Automatic EEPROM Read Function at Start-up ...........................................................................................................................38
EEPROM Parameter Setting ........................................................................................................................................................39
Register Map ................................................................................................................................................................................40
Command Table............................................................................................................................................................................41
Check Sum ...................................................................................................................................................................................45
Soft Start Time..............................................................................................................................................................................46
Block Diagram ..............................................................................................................................................................................47
AVDD Block Function....................................................................................................................................................................48
VGH Block Function .....................................................................................................................................................................51
VGL Block Function ......................................................................................................................................................................54
VCOM Block Function ..................................................................................................................................................................55
VDD Block Function......................................................................................................................................................................56
GPM Block Function.....................................................................................................................................................................58
RESET Block Function .................................................................................................................................................................59
PG/LDSW Block Function.............................................................................................................................................................60
NTC Block Function......................................................................................................................................................................61
EN Block Function ........................................................................................................................................................................61
VGH and VCOM temperature compensation................................................................................................................................62
FAULT Block Function ..................................................................................................................................................................63
Fail Register Function...................................................................................................................................................................63
Protection function explanation of POWER MANAGEMENT block ..............................................................................................64
Double Register............................................................................................................................................................................65
Data Refresh.................................................................................................................................................................................65
PCB Layout Guide........................................................................................................................................................................66
EMC Layout Guide .......................................................................................................................................................................67
I/O Equivalence Circuit .................................................................................................................................................................68
Operational Notes.........................................................................................................................................................................71
Ordering Information.....................................................................................................................................................................73
Marking Diagram ..........................................................................................................................................................................73
Physical Dimension, Tape and Reel Information...........................................................................................................................74
Revision History............................................................................................................................................................................75
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
2/75
BM81810MUF-M
Pin Configuration
(TOP VIEW)
EXP-PAD
EXP-PAD
4 2 3 2 2 2 1 2 0 2 9 1 8 1 7 1
VCP
GSIN
SDA
SCL
CPP1
DRP
DRN
RST
VGL
VDD
SWB
PGNDB
EN
CGND
VCOM
NEG
EXP-PAD
1
2
3
4
5
6
7
8
EXP-PAD
EXP-PAD
Pin Descriptions
Pin
No.
Pin
Name
Pin
No
Pin
Name
Function
Function
Built-in Positive charge pump switching Di
output 3
1
2
VINB
Buck DC/DC power supply input
Inner power supply output
17
18
CPP2
Positive charge pump feedback & Power Input
of Gate Pulse Modulation
VREG
VGH
3
4
VIN
Boost DC/DC load switch input
Boost DC/DC load switch output
19 GSOUT Output of Gate Pulse Modulation
VLSO
20
21
RE
Slope Setting Pin for Gate Pulse Modulation
Active Low of EEPROM Writing protection.
5
6
PGND
SW
Boost DC/DC ground
WPN
Slope setting pin for temperature compensation
of the VON and VCOM
Boost DC/DC switching pin
22
23
NTC
Boost DC/DC output & output feedback
Power Input of DRN
7
8
PAVDD
AVDD
FAULT FAULT signal output
PG/
Power Good signal output or
Power Input of VCOM , DRP
24
LDSW Load SW of PAVDD.
9
NEG
VCOM
CGND
VGL
Negative Input of VCOM Amplifier
VCOM amplifier output
25
26
27
28
29
30
GSIN
SDA
SCL
Input of Gate Pulse Modulation
10
11
12
13
14
Serial clock data input (I2C)
Serial clock input (I2C)
Charge pump ground
Negative charge pump feedback
Negative charge pump driver pin
Positive charge pump driver pin
RST
VDD
SWB
Reset output
DRN
Buck DC/DC or LDO output feedback input
Buck DC/DC switching pin or LDO output pin
DRP
Built-in Positive charge pump switching Di
output 1
15
16
CPP1
VCP
31 PGNDB Buck DC/DC ground
Built-in Positive charge pump switching Di
output 2
32
-
EN
Enable input
EXP
-PAD
Connect to Ground.
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
3/75
BM81810MUF-M
Absolute Maximum Ratings
Limits
Parameter
Symbol
Unit
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-15
Typ
Max
+6.5
Power Supply Voltage
VIN, VINB
SWB
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
VINB+0.3
+6.5
VDD
AVDD, PAVDD, SW
VLSO
+19
+6.5
VCOM
AVDD+0.3
AVDD+0.3
PAVDD+0.3
+36
DRP
DRN
Output Pin
CPP1,CPP2,VCP
VGH,GSOUT,RE
VGL
+36
+0.3
VREG
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
VIN+0.3
+6.5
FAULT
PG/LDSW
RST, NTC
NEG
+19
-
-
-
-
-
-
VIN+0.3
AVDD+0.3
+6.5
Input Pin
SCL, SDA, EN, GSIN
Functional Pin Voltage
WPN
VIN+0.3
+150
Maximum Junction temperature
Storage Temperature Range
Tjmax (Note 1)
Tstg
-55
+150
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
(Note 1) Junction temperature at storage time.
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
4/75
BM81810MUF-M
Thermal Resistance (Note 1)
Thermal Resistance (Typ)
Symbol
Unit
Parameter
1s(Note 3)
2s2p(Note 4)
VQFN32FBV050
Junction to Ambient
θJA
138.9
11
39.1
5
°C/W
°C/W
Junction to Top Characterization Parameter(Note 2)
ΨJT
(Note 1)Based on JESD51-2A(Still-Air).
(Note 2)The thermal characterization parameter to report the difference between junction temperature and the temperature
at the top center of the outside surface of the component package.
(Note 3)Using a PCB board based on JESD51-3.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3mm x 76.2mm x 1.57mm
Top
Copper Pattern
Thickness
70µm
Footprints and Traces
(Note 4)Using a PCB board based on JESD51-5, 7.
Thermal Via(Note 5)
Layer Number of
Measurement Board
Material
FR-4
Board Size
Pitch
1.20mm
Diameter
4 Layers
114.3mm x 76.2mm x 1.6mmt
2 Internal Layers
Φ0.30mm
Top
Bottom
Copper Pattern
Thickness
70µm
Copper Pattern
Thickness
35µm
Copper Pattern
Thickness
70µm
Footprints and Traces
74.2mm x 74.2mm
74.2mm x 74.2mm
(Note 5) This thermal via connects with the copper pattern of all layers.
Recommended Operating Ratings (Ta=-40 °C to +105 °C)
Parameter
Symbol
Unit
V
Min
2.6
Typ
-
Max
5.5
Power Supply Voltage
VIN,VINB
SWB Current
ISWB
ISW
-
-
-
-
1.0
2.0
A
A
SW Current
Functional Pin Voltage
2 Line Serial Pin Voltage
2 Line Serial Frequency
Operating Ambient Temperature
Operating Junction Temperature
EN,GSIN,WPN
SDA, SCL
FCLK
-0.1
-0.1
-
-
-
-
-
-
+5.5
+5.5
400
V
V
kHz
°C
°C
TA
-40
-40
+105
+125
TJ
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
5/75
BM81810MUF-M
Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V)
1. VDD regulator block (Alternative Buck converter or LDO)
Limits
Symbol
Parameter
Unit
Condition
50 mV step
Min
Typ
Max
3.4
Output Voltage Range
VDD
0.9
-
V
V
Output Voltage Accuracy 1
VDD_R1
2.462
-2.0
2.5
-
2.538
+2.0
VDD=2.5 V setting
VDD=2.5 V to 3.4 V setting
(Ta=-40 to +105 °C)
Output Voltage Accuracy 2
Output Voltage Accuracy 3
VDD_R2
VDD_R3
%
%
VDD=0.9
setting
V to 2.45 V
-3.0
-
+3.0
1.15
(Ta=-40 to +105 °C)
Soft Start time
VDD_SS
VDD_UVP
RONH_SWB
RONL_SWB
RON_SWB
IL_ SWBH
0.85
1
ms
V
VDD=1.2 V setting
Under-Voltage Protection voltage
SWB H Side ON Resistance
SWB L Side ON Resistance
SWB H Side ON Resistance
SWB H Side Leak Current
SWB L Side Leak Current
Current Limit
VDD×0.7 VDD×0.8 VDD×0.9
-
300
300
1.0
0
480
480
2.0
20
mΩ
mΩ
Ω
DCDC mode
-
-
DCDC mode
LDO mode
-
µA
µA
A
(Ta=-40 to +105 °C)
(Ta=-40 to +105 °C)
Buck DCDC mode
IL_ SWBL
-
0
20
ILMT_SWB1
ILMT_SWB2
1.0
0.3
1.7
0.5
2.7
0.7
Current Limit
A
LDO mode
Freq=1.05 MHz
Maximum Duty
DMAX_SWB
DISR_VDD
87
-
95
25
-
%
(Freq=0.525 MHz:98%typ)
(Freq=2.10 MHz:87%typ)
Discharge Resistance
50
Ω
2. Boost DC/DC converter block (AVDD)
Parameter
Limits
Typ
-
Symbol
Unit
Condition
Min
5.0
Max
17.0
Output Voltage Range
AVDD
V
V
0.1 V step
Output Voltage Accuracy1
AVDD_R1
10.342
10.5
10.66
AVDD=10.5 V setting
AVDD=10.5 V setting
(Ta=-40 to +105 °C)
Output Voltage Accuracy2
Load Switch Soft Start time
Soft Start Time
AVDD_R2
LS_SS
10.29
1.7
10.5
2
10.71
2.3
V
ms
ms
AVDD=10.5 V setting
5 ms setting
AVDD_SS
4.25
5
5.75
AVDD×0.7 AVDD×0.8 AVDD×0.9
AVDD×1.03 AVDDx1.1 AVDD×1.2
Under-Voltage Protection voltage
Over-Voltage Protection voltage
SW H Side On Resistance
SW L Side On Resistance
SW H Side Leak Current
SW L Side Leak Current
Current Limit
AVDD_UVP
AVDD_OVP
RON_SW
RON_SW
IL_SWH
V
V
-
250
200
0
480
350
20
mΩ
mΩ
µA
µA
A
-
-
(Ta=-40 to +105 °C)
(Ta=-40 to +105 °C)
AVDD OCP=2 A setting
AVDD OCP=1 A setting
IL_SWL
-
0
20
ILMT_SW
ILMT_SW
RON_LS
2.0
1.0
-
4.0
2.0
200
6.0
2.5
350
Current Limit
A
Load Switch ON Resistance
mΩ
Freq=1.05 MHz
Maximum Duty
DMAX_SW
83
-
90
25
-
%
(Freq=0.525 MHz:95%typ)
(Freq=2.10 MHz:80%typ)
Discharge Resistance
DISR_AVDD
50
Ω
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
6/75
BM81810MUF-M
Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) – continued
3. VCOM amplifier block (VCOM)
Limits
Unit
V
Condition
Symbol
Parameter
Output Voltage Range1
Output Voltage Range2
Output Voltage Range3
Min
Typ
Max
0.5x
AVDD
- 4.0
VCOM
HOT
0.5x
AVDD
+ 4.0
0.5x
AVDD
VCOM_HOT
VCOM_COLD
VCOM_CAL
40 mV step
VCOM
HOT
-
V
10 mV step
10 mV step
- 0.63
VCOM
HOT
VCOM
HOT
+0.63V
VCOM
HOT
V
- 0.63
Output Voltage Range4
Calibration Resolution
Integral Non-Linearity Error
(INL)
VCOM_RNG 0.2xAVDD
-
7
-
0.7x AVDD
V
RES_CAL
INL_CAL
-
-
Bit
-1
+1
LSB
Differential Non-Linearity Error
(DNL)
Output Current Ability
(Source)
DNLCAL
-1
-
-
+1
-
LSB
mA
ISOURCE
200
Output Current Ability (Sink)
Load Stability
ISINK
VLOAD
SR
-
-
200
10
-
mA
mV
Io=-15 mA to +15 mA
70
Slew Rate
30
60
V/µs
80
4. Positive charge pump block (VGH)
Parameter
Limits
Typ
-
Unit
V
Condition
0.2 V step
Symbol
Min
8.0
Max
35
VGH
HOT
+15V
Output Voltage Range 1
Output Voltage Range 2
VGH_HOT
VGH_COLD
VGH
HOT
0.2 V step
*Max = 35 V
-
V
Output Voltage Accuracy 1
Output Voltage Accuracy 2
VGH_R1
VGH_R2
17.46
17.1
4.25
18
18
5
18.54
18.9
5.75
V
V
VGH=18 V setting
VGH=18 V setting
(Ta=-40 to +105 °C)
Soft Start time
VGH_SS
VGH_UVP
ms
V
VGH=18 V setting
VGH×0.7 VGH×0.8 VGH×0.9
Under-Voltage Protection voltage
DRP H Side On Resistance
DRP L Side On Resistance
AVDD-CPP1 On Resistance
CPP1-VCP On Resistance
VCP-CPP2 On Resistance
CPP2-VGH On Resistance
Discharge Resistance
RON_DRPH
RON_DRPL
RON_CPP1
RON_CPP2
RON_CPP3
RON_CPP4
DISR_VGH
-
-
-
-
-
-
-
10
10
20
20
Ω
Ω
Ω
Ω
Ω
Ω
Ω
10
20
10
20
10
20
10
20
150
300
5. Negative charge pump block (VGL)
Parameter
Limits
Typ
-
Unit
Condition
Symbol
Min
Max
-4.0
Output Voltage Range
VGL
-14.0
-6.18
V
V
0.1 V step
Output Voltage Accuracy 1
VGL_R1
-6
-5.82
VGL=-6.0 V setting
VGL=-6.0 V setting
(Ta=-40 to +105 °C)
Output Voltage Accuracy 2
VGL_R2
-6.3
-6
5
-5.7
V
Soft Start time
VGL_SS
VGL_UVP
4.25
5.75
ms
V
VGL×0.7 VGL×0.8 VGL×0.9
Under-Voltage Protection voltage
DRN H Side On Resistance
DRN L Side On Resistance
Discharge Resistance
RON_DRNH
RON_DRNN
DISR_VGL
-
-
-
10
10
20
20
Ω
Ω
250
500
Ω
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
7/75
BM81810MUF-M
Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) – continued
6. Temperature compensation block (NTC)
Limits
Unit
Condition
Symbol
Parameter
Min
0.475
1.1875
36
Typ
0.5
1.25
40
Max
0.525
1.3125
44
NTC HOT Voltage
NTC COLD Voltage
NTC Current
VNTC_H
VNTC_H
INTC
V
V
µA
Bit
NTC Resolution
RES_NTC
-
4
-
7. Gate Pulse Modulation block (GPM)
Limits
Typ
Unit
Condition
Symbol
Parameter
Min
-
Max
30
GPM High Switch On
Resistance
GPM Low Switch On
Resistance
RON_GPMH
RON_GPML
15
Ω
Ω
-
-
30
-
No Capacitive Load
0.1 µs setting
GPM Propagation Delay1
GPM Propagation Delay2
GPM Propagation Delay3
GPM Propagation Delay4
T_GPM1
T_GPM2
T_GPM3
T_GPM4
0.1
0.3
µs
µs
µs
µs
No Capacitive Load
0.5 µs setting
-
-
-
0.5
1.0
1.5
1.0
1.75
2.5
No Capacitive Load
1.0 µs setting
No Capacitive Load
1.5 µs setting
GSIN Pull Down Resistance
GSIN Input High Voltage
GSIN Input Low Voltage
RGSIN
VGSINH
VGSINL
70
1.5
-
100
130
-
kΩ
V
-
-
V
0.6
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
8/75
BM81810MUF-M
Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) – continued
8. Overall (Entire device)
Limits
Symbol
Parameter
Unit
Condition
Min
Typ
Max
Inside Regulator Voltage
VREG Output Voltage
Load Stability
VREG
2.15
-
2.3
20
2.45
100
V
ΔV
mV
IVREG=5 mA
Oscillator Block
Oscillating Frequency 1
Oscillating Frequency 2
Oscillating Frequency 3
Under Voltage Lock Out (UVLO) Circuit
UVLO release voltage
UVLO detection voltage
FOSC1
FOSC2
FOSC3
475
950
525
1050
2100
575
1150
2300
KHz
KHz
KHz
1900
VUVLO1
VUVLO2
2.5
2.0
-
2.55
2.1
2.6
2.2
-
V
V
V
Hysteresis
VHYS_UVL
0.45
Reset Circuit Block
Reset Voltage Range
Reset Voltage Accuracy
Hysteresis
*
VRST
0.6
1.9
-
3.3
2.1
-
V
V
0.1 V step
VRST_R1
VHYS_RST
T_Delay2
2.0
0.1
-
VRST=2.0 V setting
V
Reset Delay time Range
0
40
ms
FAULT/ PG / RST Signal Output Block
Output Off Leak Current
IL
-
-
0
1
10
2
µA
Output On Resistance
RON_O
kΩ
Control Signal Block1 SDA, SCL, WPN
Minimum Output Voltage
H Level Input Voltage
VSDA
VIH
-
1.5
-
-
0.4
-
V
V
ISDA=3 mA
-
-
L Level Input Voltage
VIL
0.6
130
V
WPN Pull Down Resistance
Control Signal Block2 EN
RWPN
70
100
kΩ
REN_L
REN_H
280
420
400
600
520
780
kΩ
kΩ
EN=Low
EN=High
Pull-Down Resistance Value
H Level Input Voltage
VENH
VENL
1.5
-
-
-
-
V
V
L Level Input Voltage
Overall
0.6
Standby Current1
ISTB1
ISTB2
ICC1
-
-
-
2.0
-
5.0
20
µA
µA
EN=GND
EN=GND
(Ta=-40 to +105 °C)
Standby Current2
Consumption Current
EN=VIN, No switching
2.0
5.0
mA
9. EEPROM
Parameter
Limits
Symbol
Unit
Condition
Min
100
-
Typ
Max
Rewritable cycle
Programmable time
Data hold years
Cyc
Twr
-
-
-
-
50
-
Times
ms
TJ<125 °C
DHY
20
Years
TJ<125 °C
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
9/75
BM81810MUF-M
Typical Performance Curves
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
5
4
3
2
1
0
20
18
16
14
12
10
8
Ta=25℃
Ta=105℃
Ta=-40℃
Ta=105℃
6
Ta=-40℃
Ta=25℃
4
2
0
2.6
3.1
3.6
4.1
4.6
5.1
2.6
3.1
3.6
4.1
VIN [V]
4.6
5.1
VIN [V]
Figure 3. Standby Current(EN=L)
Figure 4. Circuit Current(EN=H, no switching)
1.15
1.10
1.05
1.00
0.95
1.15
1.10
1.05
1.00
0.95
Ta=25℃
Ta=-40℃
VIN=3.3V
VIN=2.6V
VIN=5.5V
Ta=105℃
2.6
3.1
3.6
4.1
4.6
5.1
-40 -20
0
20
40
60
80 100
Ta [℃]
VIN [V]
Figure 5. Switching Frequency
( Dependent on input voltage)
Figure 6. Switching Frequency
( Dependent on temperature)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
10/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
3.0
EN(4V/div.)
2.5
2.0
1.5
1.0
0.5
0.0
VGH(4V/div.)
PAVDD(4V/div.)
AVDD(4V/div.)
Ta=105℃
Ta=25℃
VCOM(4V/div.)
VDD(4V/div.)
GSOUT(4V/div.)
Ta=-40℃
VGL(4V/div.)
0
0.5
1
1.5
2
2.5
3
3.5 4 4.5 5 5.5
10msec/div.
EN [V]
Figure 7. H/L threshold voltage
(control signals)
Figure 8. Power on waveform
(when operated by EN control, Function select = PG)
VIN, EN
(4V/div.)
EN(4V/div.)
VGH(4V/div.)
VGH(4V/div.)
PAVDD(4V/div.)
AVDD(4V/div.)
PAVDD(4V/div.)
AVDD(4V/div.)
VCOM(4V/div.)
VDD(4V/div.)
VCOM(4V/div.)
GSOUT(4V/div.)
VDD(4V/div.)
GSOUT(4V/div.)
VGL(4V/div.)
VGL(4V/div.)
10msec/div.
10msec/div.
Figure 9. Power off waveform
(when operated by EN control, Function select = PG)
Figure 10. Power on waveform
(when operated with EN=VCC, Function select = PG)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
11/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
VIN, EN
(4V/div.)
VIN(4V/div.)
VGH(4V/div.)
VGH(4V/div.)
PAVDD(4V/div.)
AVDD(4V/div.)
AVDD(4V/div.)
PAVDD(4V/div.)
VCOM(4V/div.)
VDD(4V/div.)
VCOM(4V/div.)
VDD(4V/div.)
GSOUT(4V/div.)
GSOUT(4V/div.)
VGL(4V/div.)
VGL(4V/div.)
10msec/div.
10msec/div.
Figure 11. Power off waveform
Figure 12. Power on waveform
(when operated with EN=VCC, Function select = PG)
(when operated by EN control, Function select = LDSW)
VIN, EN
(4V/div.)
VIN(4V/div.)
VGH(4V/div.)
VGH(4V/div.)
AVDD(4V/div.)
PAVDD(4V/div.)
VCOM(4V/div.)
AVDD(4V/div.)
VCOM(4V/div.)
VDD(4V/div.)
VDD(4V/div.)
GSOUT(4V/div.) PAVDD(4V/div.)
GSOUT(4V/div.)
VGL(4V/div.)
VGL(4V/div.)
10msec/div.
10msec/div.
Figure 13. Power off waveform
Figure 14. Power on waveform
(when operated by EN control, Function select = LDSW)
(when operated with EN=VCC, Function select = LDSW)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
12/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
100
VIN, EN
(4V/div.)
90
80
VGH(4V/div.)
70
GSOUT(4V/div.)
60
VIN=5.5V
PAVDD(4V/div.)
50
VIN=3.3V
VCOM(4V/div.)
VDD(4V/div.)
40
30
20
10
0
AVDD(4V/div.)
VIN=2.6V
VDD=2.5V
1.05MHz
Ta=25℃
VGL(4V/div.)
1
10
100
Load [mA]
1000
100msec/div.
Figure 15. Power off waveform
(when operated with EN=VCC, Function select = LDSW)
Figure 16. Efficiency
(VDD DC/DC mode)
1.5
1.0
2.0
1.5
1.0
0.5
VIN=5.5V
VIN=5.5V
0.5
VIN=2.7V
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-0.5
VIN=3.3V
VIN=2.6V
VIN=3.3V
-1.0
-1.5
0.9
1.4
1.9
2.4
2.9
3.4
-40 -20
0
20
40
60
80 100
setting voltage [V]
Ta [℃]
Figure 17. Output voltage accuracy
(VDD DC/DC mode, dependent on input voltage)
Figure 18. Output voltage accuracy
(VDD DC/DC mode, dependent on temperature)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
13/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
2.0
1.5
1.0
0.5
0.0
Ta=105℃
Ta=25℃
Ta=-40℃
-0.5
-1.0
-1.5
-2.0
VIN=3.3V
VDD=1.8V
2.1MHz
Ta=25℃
Load=200mA
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load [A]
1
Figure 19. Phase margin
(VDD DC/DC mode)
Figure 20. Load Regulation
(VDD DC/DC mode)
VDD
(100mV/div.)
VDD(AC, 5mV/div.)
SWB(3V/div.)
Load
0mA⇔200mA
IL(0.2A/div.)
Iout
(0.1A/div.)
Iout(0.2A/div.)
100usec/div.
2usec/div.
Figure 21. Load Transient
(VDD DC/DC mode)
Figure 22. Switching waveform
(VDD DC/DC mode)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
14/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
100
90
80
70
60
50
40
30
20
10
0
1.5
1.0
VIN=2.6V
VIN=5.5V
0.5
VIN=3.3V
0.0
VIN=3.3V
VIN=2.6V
-0.5
-1.0
-1.5
VIN=5.5V
0.9
1.4
1.9
2.4
2.9
3.4
1
10
100
setting voltage [V]
Load [mA]
Figure 23. Efficiency
(VDD LDO mode)
Figure 24. Output voltage accuracy
(VDD LDO mode, dependent on input voltage)
2.0
1.5
1.0
0.5
VIN=3.3V
VIN=5.5V
0.0
-0.5
-1.0
-1.5
-2.0
VIN=2.6V
VIN=3.3V
VDD=2.5V
Ta=25℃
Load=250mA
-40 -20
0
20
40
60
80 100
Ta [℃]
Figure 25. Output voltage accuracy
(VDD LDO mode, dependent on temperature)
Figure 26. Phase margin
(VDD LDO mode)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
15/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
2.0
VDD
(100mV/div.)
1.5
1.0
0.5
Ta=-40℃
0.0
-0.5
-1.0
-1.5
-2.0
Load
10mA⇔200mA
Ta=105℃
Ta=25℃
Iout
(0.1A/div.)
0
100
200
300
400
500
600
100usec/div.
Load [mA]
Figure 27. Load Regulation
(VDD LDO mode)
Figure 28. Load Transient
(VDD LDO mode)
100
90
80
70
60
50
40
30
20
10
0
1.5
1.0
VIN=5.5V
VIN=5.5V
VIN=3.3V
VIN=2.6V
VIN=3.3V
0.5
VIN=2.6V
0.0
-0.5
-1.0
-1.5
5
1
10
100
7
9
11
13
15
17
Load [mA]
setting voltage [V]
Figure 29. Efficiency
(AVDD)
Figure 30. Output voltage accuracy
(AVDD, dependent on input voltage)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
16/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
2.0
1.5
1.0
VIN=5.5V
VIN=3.3V
0.5
0.0
VIN=2.6V
-0.5
-1.0
-1.5
-2.0
2.1MHz
Ta=25℃
Load=200mA
-40 -20
0
20
40
60
80 100
Ta [℃]
Figure 31. Output voltage accuracy
(AVDD, dependent on temperature)
Figure 32. Phase margin
(AVDD)
2.0
1.5
AVDD
(100mV/div.)
1.0
0.5
Ta=105℃
Ta=25℃
Ta=-40℃
0.0
Load
0mA⇔100mA
-0.5
-1.0
-1.5
-2.0
Iout
(0.1A/div.)
0
50
100
150
200
100usec/div.
Load [mA]
Figure 33. Load Regulation
(AVDD)
Figure 34. Load Transient
(AVDD)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
17/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
12
AVDD(AC, 20mV/div.)
Ta=105℃
10
SW(10V/div.)
IL(0.2A/div.)
8
6
4
2
0
Ta=-40℃
Ta=25℃
AVDD=13V
VCOM=6.5V setting
Iout(0.2A/div.)
-400 -300 -200 -100
0
100 200 300 400
2usec/div.
Load [mA]
Figure 35. Switching waveform
(AVDD)
Figure 36. Output Current
(VCOM)
1.0
0.8
1.0
0.8
Ta=105℃
0.6
0.6
0.4
0.4
Ta=25℃
Ta=-40℃
0.2
0.2
Ta=-40℃
0.0
0.0
Ta=25℃
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
Ta=105℃
AVDD=15V
VCOM=3.5V ~ 11.5V
AVDD=15V
VCOM=3.5V ~ 11.5V
E4 D0 BC A8 94 80 14 28 3C 50 64
Data [HEX]
E4 D0 BC A8 94 80 14 28 3C 50 64
Data [HEX]
Figure 37. DAC INL
(VCOM)
Figure 38. DAC DNL
(VCOM)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
18/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
AVDD=13V
VCOM
2[V/div.]
VCOM
2[V/div.]
AVDD=13V
Figure 39. Slew Rate
(VCOM, rise)
Figure 40. Slew Rate
(VCOM, fall)
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-15
6.5
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
Ta=25℃
Ta=105℃
Ta=-40℃
VCOM HOT=5.93V
VCOM COLD=4.97V
-10
-5
0
5
10
15
0.3
0.5
0.7
0.9
1.1
1.3
1.5
Load [mA]
NTC [V]
Figure 41. Load Regulation
(VCOM)
Figure 42. NTC Function
(VCOM)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
19/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
100
90
80
70
60
50
40
30
20
10
0
3.0
2.0
VGH=18V
3 stage
AVDD=17V
1.0
AVDD=8V
0.0
AVDD=10.5V
AVDD=8V
-1.0
-2.0
-3.0
AVDD=10.5V
AVDD=17V
1
5
25
8
11 14 17 20 23 26 29 32 35
setting voltage [V]
Load [mA]
Figure 43. Efficiency
(VGH)
Figure 44. Output voltage accuracy
(VGH, dependent on input voltage)
5
4
3
2
AVDD=8V
1
AVDD=10.5V
0
-1
-2
-3
-4
-5
AVDD=17V
3 stage
1.05MHz
Load=10mA
-40 -20
0
20
40
60
80 100
Ta [℃]
Figure 45. Output voltage accuracy
(VGH, dependent on temperature)
Figure 46. Phase margin
(VGH)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
20/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
2.0
VGH
(700mV/div.)
1.5
1.0
0.5
Ta=25℃
Ta=-40℃
Load
0mA⇔10mA
0.0
-0.5
-1.0
-1.5
-2.0
Ta=105℃
Iout
(10mA/div.)
0
2
4
6
8
10
100usec/div.
Load [mA]
Figure 47. Load Regulation
(VGH)
Figure 48. Load Transient
(VGH)
22
21
20
19
18
17
16
15
14
VGH(AC, 100mV/div.)
DRP(10V/div.)
CPP1(10V/div.)
CPP2(10V/div.)
Iout(20mA/div.)
VGH HOT=15V
VGH COLD=20V
13
0.3
0.5
0.7
0.9
NTC [V]
1.1
1.3
1.5
2usec/div.
Figure 49. Switching waveform
(VGH)
Figure 50. NTC Function
(VGH)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
21/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
100
90
80
70
60
50
40
30
20
10
0
3
2
AVDD=8V
1
AVDD=17V
0
AVDD=10.5V
AVDD=17V
AVDD=8V
-1
-2
-3
AVDD=10.5V
-14
-12
-10
-8
-6
-4
1
5
25
setting voltage [V]
Load [mA]
Figure 51. Efficiency
(VGL)
Figure 52. Output voltage accuracy
(VGL, dependent on input voltage)
5
4
3
2
AVDD=17V
1
AVDD=8V
0
-1
-2
-3
-4
-5
AVDD=10.5V
1.05MHz
Load=10mA
-40 -20
0
20
40
60
80 100
Ta [℃]
Figure 53. Output voltage accuracy
(VGL, dependent on temperature)
Figure 54. Phase margin
(VGL)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
22/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
2.0
VGL
(100mV/div.)
1.5
1.0
0.5
0.0
Ta=25℃
Ta=-40℃
Load
1mA⇔10mA
Ta=105℃
-0.5
-1.0
-1.5
-2.0
Iout
(10mA/div.)
0
2
4
6
8
10
100usec/div.
Load [mA]
Figure 55. Load Regulation
(VGL)
Figure 56. Load Transient
(VGL)
44
42
40
38
36
VGL(AC, 20mV/div.)
DRN(5V/div.)
VIN=5.5V
VIN=2.6V
VIN=3.3V
Iout(10mA/div.)
-40 -20
0
20
Ta [℃]
40
60
80 100
2usec/div.
Figure 57. Switching waveform
(VGL)
Figure 58. NTC current
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
23/75
BM81810MUF-M
Typical Performance Curves - continued
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
GSIN
(2V/div.)
GSIN
(2V/div.)
0.1usec setting
0.5usec setting
1.0usec setting
1.5usec setting
GSOUT
(4V/div.)
GSOUT
(4V/div.)
250nsec/div.
25nsec/div.
Figure 59. Propagation Delay
(GPM, rise)
Figure 60. Propagation Delay
(GPM, fall)
GSIN
(2V/div.)
GSOUT
(4V/div.)
10usec/div.
Figure 61. Waveform
(GPM)
.
www.rohm.com
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
24/75
BM81810MUF-M
Application Example 1 (when operated by EN control)
R_NTC2
R_NTC1
R_NTC3
WPN
R_FLT
VIN
VIN
R_RE
GSOUT
VGH
R_PG
FAULT
PG / LDSW
Θ
C_DRP2
CPP2
C_VGH
D_VGL
4 2 3 2 2 2 1 2 0 2 9 1 8 1 7 1
C_VCP
VIN
VCP
GSIN
SDA
C_DRP1
CPP1
DRP
DRN
R_RST
SCL
RST
C_DRN
VGL
VDD
SWB
EN
VCOM
L_SWB
C_VDD
C_VCOM
C_VGL
1
2
3
4
5
6
7
8
AVDD
AVDD
C_VINB
C_VIN
C_REG
(D_SW)
VIN
C_AVD
C_LSO
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
25/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Application Example 1 (when operated by EN control) – continued
Application circuit components list
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V)
Value
Parts
Unit Company
Parts Number
Comment
name
Min
Typ
Max
(Note 1)
C_VIN
10
10 x 2
10
-
-
μF
μF
MURATA
MURATA
GRT21BC81A106KE01
GRT21BC81A106KE01
No need @ VDD LDO
mode
C_VINB
4.7
C_REG
C_LSO
C_AVD
L_SW
0.047
10
0.1
10 x 2
10 x 3
4.7
0.47
μF
μF
μF
μH
MURATA
MURATA
MURATA
TDK
GRT188R71H104KE13
GRT21BC81A106KE01
GRT31CC81E106KE01
LTF5022T-4R7N2R0-H
-
10 x 6
-
5.0
-
See p.49 in detail.
See p.49 in detail.
Please insert D_SW when
improving the efficiency is
necessary.
D_SW
-
-
-
-
ROHM
(RB060M-30DD)
C_VDD
L_SWB
C_VCOM
C_VGL
C_DRN
D_VGL
C_VGH
C_CPP1
C_VCP
C_CPP2
R_RE
10
10 x 2
4.7
-
47
μF
μH
μF
μF
μF
-
MURATA
TDK
GRT21BC81A106KE01
LTF5022T-4R7N2R0-H
-
-
-
-
-
0.47
-
MURATA
MURATA
MURATA
ROHM
1.0
0.1
-
4.7
-
GRT21BC81E105KE13
GRT188R71H104KE13
RB558WFH
0.47
2.2
0.1
1.0
0.1
2.0
4.7
33
4.7
μF
μF
μF
μF
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
MURATA
MURATA
MURATA
MURATA
ROHM
GRT21BC8YA225KE13
GRT188R71H104KE13
GRT188C81E105KE13
GRT188R71H104KE13
MCR03
-
-
-
-
-
-
0.2
-
-
-
R_NTC1
R_NTC2
R_NTC3
R_FLT
ROHM
MCR03
-
-
ROHM
MCR03
-
10
-
MURATA
ROHM
NCU18XH103F6SRB
MCR03
47
47
47
100
100
100
200
200
200
R_PG
ROHM
MCR03
R_RST
ROHM
MCR03
(Note 1)Please set in consideration of temperature properties and DC bias properties not to become less than the minimum.
Please consider it based on enough evaluations with the actual model.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
26/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Application Example 1 (when operated by EN control) – continued
Timing Chart1
Start-up Sequence (when operated by EN control)
Vcc UVLO release
Vcc=2.55V
(Inner logic, reset EEPROM)
VIN
Enable=L⇒H
EN
VREG
EEPROM
Discharge
0～5ms
Auto Read
EEROM
Discharge
1ms
(when VDD=1.2V)
VDD
VDD
AVDD
VGL
90%
Soft Start time
5ms (when 10.5V is set)
AVDD
delay1
(0～300ms)
VIN
level
load
SW ON
VGL
delay3
(0～40ms)
Soft Start time
5ms (when -6V is set)
VCOM ⇒
Start up by following to
AVDD voltage
VCOM
VGH
Soft Start time
5ms (when 18V is set)
AVDD
level
EEPROM Register
Data write-able zone
GSOUT
delay4
(0～40ms)
delay2
(0～40ms)
RST
PG
Reset monitor is setting VDD.
FAULT
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
27/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Application Example 1 (when operated by EN control) – continued
OFF Sequence (when operated by EN control)
Vcc UVLO detectꢀVcc=2.1V
(Inner logic, reset EEPROM)
VIN
VREG
EEROM
Discharge
Enable=H⇒L
delay5
EN
(0～10ms)
VDD
Discharge
VDD
AVDD
Discharge
AVDD
VGL
VGL
VGL Hi-Z
Discharge
VCOM
Discharge
VCOM
VGH
VGH
Discharge
VGH Hi-Z
EEPROM Register
Data write-able zone
GSOUT
RST
PG
FAULT
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
28/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Application Example 2 (when operated with EN= VCC condition)
Timing Chart2
Start-up Sequence (when operated with EN= VCC condition)
Vcc UVLO release
Vcc=2.55V
(Inner logic, reset EEPROM)
VIN,
VINB,
EN
VREG
EEPROM
Discharge
0～5ms
Auto Read
EEROM
Discharge
1ms
(when VDD=1.2V)
VDD
The order of starting VDD
can be changed by the
VDD
90%
register setting.
Soft Start time
5ms (when 10.5V is set)
AVDD
delay1
(0～300ms)
AVDD
VIN
level
load
SW ON
VGL
VGL
delay3
(0～40ms)
Soft Start time
5ms (when -6V is set)
VCOM
VGH
Soft Start time
5ms (when 18V is set)
AVDD
level
EEPROM Register
Data write-able zone
GSOUT
delay4
(0～40ms)
delay2
(0～40ms)
RST
Reset monitor is setting VDD.
PG
FAULT
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
29/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Timing Chart2 - continued
OFF Sequence (when operated with EN= VCC condition)
Vcc UVLO detectꢀVcc=2.1V
(Inner logic, reset EEPROM)
VIN,
VINB,
EN
VREG
EEROM
Discharge
discharge after Vcc UVLO detect
VDD
Discharge
VDD
AVDD
Discharge
AVDD
VGL
Discharge
VGL
VCOM
VGH
VGH
Discharge
*Discharge enable
EEPROM Register
Data write-able zone
GSOUT
RST
PG
FAULT
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
30/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Application Example 3 (using LDSW mode)
In case of activating in order of VGL => AVDD => VGH, changing the application contracture to following make is possible. In this
case please set Register08h (Function Select) of the EEPROM to "1".
R_NTC2
R_NTC3
WPN
R_NTC1
VIN
R_RE
GSOUT
VGH
R_FLT
Θ
FAULT
PG / LDSW
C_DRP2
CPP2
C_VGH
D_VGL
4 2 3 2 2 2 1 2 0 2 9 1 8 1 7 1
C_VCP
VIN
VCP
GSIN
SDA
C_DRP1
CPP1
DRP
DRN
R_RST
SCL
RST
C_DRN
VGL
VDD
SWB
EN
VCOM
L_SWB
C_VDD
C_VGL
C_VCOM
1
2
3
4
5
6
7
8
AVDD
PAVDD
AVDD
M_LDSW
C_VINB
C_VIN
C_REG
C_AVD
VIN
C_GD
C_PAV
LDSW
R_LSGATE
R_LDSW
C_LDSW
(D_SW)
C_LSO
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
31/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Application Example 3 (using LDSW mode) - continued
Application circuit components list
(Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C)
Value
Parts name
Unit Company
Parts Number
Comment
Min
(Note 1)
Typ
Max
C_VIN
10
10 x 2
10
-
-
μF
μF
MURATA
MURATA
GRT21BC81A106KE01
GRT21BC81A106KE01
No need @ VDD LDO
mode
C_VINB
4.7
C_REG
C_LSO
C_PAVD
C_AVD
L_SW
0.047
10
0.1
10 x 2
10 x 2
4.7
0.47
μF
μF
μF
μF
μH
MURATA
MURATA
MURATA
MURATA
TDK
GRT188R71H104KE13
GRT21BC81A106KE01
GRT31CC81E106KE01
GRT31CC81E475KE01
LTF5022T-4R7N2R0-H
-
10 x 5
10
5.0
2.2
-
See p.49 in detail.
See p.49 in detail.
See p.49 in detail.
4.7
-
Please insert D_SW when
improving the efficiency is
necessary.
D_SW
-
-
-
-
ROHM
(RB060M-30DD)
M_LDSW
R_LDSW
C_LDSW
C_GD
-
-
100
0.47
33
-
-
ROHM
ROHM
RTR030P02FHA
MCR03
-
-
kΩ
μF
nF
kΩ
μF
μH
μF
μF
μF
-
-
-
-
MURATA
MURATA
ROHM
GRT21BR71H474KE01
GRT155R71H333KE01
MCR03
-
R_LSGATE
C_VDD
L_SWB
C_VCOM
C_VGL
-
100
10 x 2
4.7
-
-
10
47
-
MURATA
TDK
GRT21BC81A106KE01
LTF5022T-4R7N2R0-H
-
-
-
0.47
-
-
MURATA
MURATA
MURATA
ROHM
1.0
0.1
-
4.7
-
GRT21BC81E105KE13
GRT188R71H104KE13
RB558WFH
C_DRN
D_VGL
C_VGH
C_CPP1
C_VCP
0.47
2.2
0.1
1.0
0.1
2.0
4.7
33
4.7
μF
μF
μF
μF
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
MURATA
MURATA
MURATA
MURATA
ROHM
GRT21BC8YA225KE13
GRT188R71H104KE13
GRT188C81E105KE13
GRT188R71H104KE13
MCR03
-
-
-
-
C_CPP2
R_RE
-
-
0.2
-
-
R_NTC1
R_NTC2
R_NTC3
R_FLT
-
-
ROHM
MCR03
-
ROHM
MCR03
-
10
-
MURATA
ROHM
NCU18XH103F6SRB
MCR03
47
47
100
100
200
200
R_RST
ROHM
MCR03
(Note 1)Please set in consideration of temperature properties and DC bias properties not to become less than the minimum.
Please consider it based on enough evaluations with the actual model.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
32/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Timing Chart3
Start-up Sequence (when operated with LDSW function)
Vcc UVLO release
Vcc=2.55V
(Inner logic, reset EEPROM)
VIN,
VINB
Enable=L⇒H
EN
VREG
EEPROM
Auto Read
Discharge
0～5ms
EEROM
Discharge
1ms
(when VDD=1.2V)
VDD
VDD
AVDD
VGL
90%
Soft Start time
5ms (when 10.5V is set)
delay1
(0～300ms)
PAVDD
AVDD
VIN
level
load
SW ON
VGL
Soft Start time
5ms (when -6V is set)
VCOM ⇒
Start up by following to
AVDD voltage
VCOM
VGH
Soft Start time
5ms (when 18V is set)
AVDD
level
delay3
(0～40ms)
EEPROM Register
Data write-able zone
GSOUT
delay4
(0～40ms)
delay2
(0～40ms)
RST
Reset monitor is setting VDD.
LDSW
FAULT
Figure 68. Start-Up Sequence Diagram (when operated with LDSW Function)
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
33/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Timing Chart3 - continued
OFF Sequence (when operated with LDSW function)
Vcc UVLO detectꢀVcc=2.1V
(Inner logic, reset EEPROM)
VIN,
VINB
VREG
EEROM
Discharge
Enable=H⇒L
delay5
EN
(0～10ms)
VDD
Discharge
VDD
AVDD
Discharge
AVDD
VGL
VGL
VGL Hi-Z
Discharge
VCOM
Discharge
VCOM
VGH
VGH
Discharge
VGH Hi-Z
EEPROM Register
Data write-able zone
GSOUT
RST
LDSW
FAULT
Figure 69. OFF Sequence Diagram (when operated with LDSW Function)
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
34/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Serial communication
This IC has two device-address-differential EEPROM installed and data is send or received to/from EEPROM using 2-line serial
interface (SCL, SDA). Communication format for data sending or receiving to/from each EEPROM is shown below.
EEPROM I2C Format for DVR (VCOM calibrator)
Device address
R/W ACK
DATA
D3 D2
DATA
D3 D2
ACK
0
Write
operation
Start
Start
STOP
STOP
1
1
0
0
0
1
1
1
1
1
1
0
0
D6
D6
D5
D5
D4
D4
D1
D1
D0
D0
P
X
Device address
R/W ACK
ACK
1
Read
operation
0
1
1
1
0
When Device Address = 1001111(R/W) is selected, Data is Read or Write EEPROM for DVR(VCOM calibrator).
During Write mode
•When P=1, the sending data is written only to Register.
•When WPN=Low and P=0, the sending data is written only to Register.
•When WPN=High and P=0, the sending data is written both to Register and EEPROM.
During Read mode
The last bit of received data is “Don’t care”.
“D6” is ± select bit: 0 = “+”, 1=”-” from VCOM(HOT) value.
[D5:D0] are voltage band from VCOM(HOT).
The voltage band is calculated; 10mV x [D5:D0],
For example,
[D6:D0,P] = 82h(D6=1, [D5:D0]=1’d, P=0) ••• VCOM = VCOM(HOT) – 1 x 10mV;
[D6:D0,P] = 7Eh(D6=0, [D5:D0]=63’d, P=0) ••• VCOM = VCOM(HOT) + 63 x 10mV;
Sequence of DVR side EEPROM during Read/Write mode is shown in below chart.
Figure 70
Figure 71
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
35/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Serial communication - continued
EEPROM I2C Format for Power Management IC (PMIC)
R/W ACK
ACK
ACK
Device address
Register Address
00h ～ 0Dh, 10h, 11h
Register Address
Write
operation
Read
Start
N-bytes Data
Device Address
Stop
Stop
1
0
0
Device address
0
0
0
0
0
R/W ACK
0
0
ACK
0
ACK
ACK
0
Repeated
Start
Start
N-bytes Data
00h ～ 0Dh, 10h, 11h
operation
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
Device Address of BM81810MUF-M is 1000 000x.
Multi write is possible until Register 00h to 0Dh.
EN
Low
High
WPN Start-up( 0Ch[7] ) PMIC ( 00h to 0Dh)
Output Function
Shutdown
Active
1
2
Low
Low
-
-
-
Register
0*
Register &
EEPROM
3
4
High
High
High
High
Shutdown
Active
1
Register &
EEPROM
* In the mass production shipment process, please write Start-up ( 0Ch[7] ) to "1" in EEPROM.
The following are the settings if you want to send the Data by I2C.
Device Address?
1000_0000
Receive register address
Yes
Read
Write
No
Restart?
Device Address
1000_0001
Input data to register
Output register data
Low
WPN
High
Write data to EEPROM
End process
Figure 72
WPN Timing
WPN is normally fixed as Low.
In case of writing to EEPROM, WPN is set to High, and the timing will be as below.
Because the maximum of the auto-read time from EEPROM is 5ms, please between EN signal and I2C input than 5ms.
Also, because the maximum of writing time to EEPROM is 50ms, please between I2C STOP signal and EN falling signal
than 50ms.
VIN
EEPROM Data
Auto Read
> 5msec
EEPROMꢀWrite Time
> 50msec
EN
WPN
tSU;WPN
> 0usec
tHD;WPN
> 10usec
S
T
A
R
T
S
T
O
P
SCL
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Device
Address
Register
Address
・・・・・
DATA
DATA
DATA
Figure 73
36/75
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
I2C Timing Diagram
tR
tHIGH
tF
70%
30%
SCL
tLOW
tPD
tHD:STA
tSU;DAT
tHD;DAT
70%
30%
SDA
(IN)
tBUF
tDH
70%
30%
SDA
(OUT)
70%
SCL
SDA
tHD;STA
tSU;STA
tSU;STO
70%
30%
tl
S： START Bit
P： STOP Bit
S
P
Figure 74. I2C Timing Diagram
Timing standard values
Parameter
NORMAL MODE
FAST MODE
Typ
Symbol
Unit
Min
Typ
Max
Min
Max
SCL frequency
SCL high time
fSCL
tHIGH
tLOW
tR
-
4.0
4.7
-
-
-
100
-
-
0.6
1.2
-
-
-
400
-
kHz
μs
μs
SCL low time
-
-
-
-
μs
μs
μs
μs
Rise Time
-
1.0
-
0.3
Fall Time
tF
-
-
0.3
-
-
0.3
Start condition hold time
Start condition setup time
SDA hold time
tHD;STA
tSU;STA
tHD;DAT
tSU;DAT
tPD
4.0
4.7
0
-
-
0.6
0.6
0
-
-
-
-
-
-
-
-
-
-
ns
SDA setup time
200
-
-
-
-
100
-
-
-
-
ns
μs
Acknowledge delay time
Acknowledge hold time
Stop condition setup time
Bus release time
Noise spike width
0.9
0.9
μs
μs
μs
μs
tDH
-
0.1
-
-
-
-
-
-
0.1
-
-
-
-
-
tSU;STO
tBUF
4.0
4.7
-
0.6
1.2
-
-
-
Tl
0.1
0.1
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
37/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Automatic EEPROM Read Function at Start-up
Upon BM81810MUF-M start-up, a reset signal is generated and each register is initialized.
After VREG activation is finished, data which is stored in the EEPROM is copied to the registers.
The automatic EEPROM read function at start-up is further explained by the flow chart below.
VREG ACTIVE
EEPROM READ
TRANSFER DATA
REGISTER
NO
CHECK
SUM
3times
NG?
NG
OK
YES
START OPERATION
SHUT DOWN
Figure 75. Automatic EEPROM Read Function at Start-up
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
38/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
EEPROM Parameter Setting
■EEPROM / Main Register Map ( device address : 1000000x )
Device Address: 1000000x (PMIC)
Register
Address
Bits
Function
Resolution
Comments
AVDD Output voltage setting
VGH(HOT) Output voltage setting
00h
8
AVDD Output voltage
VGH(HOT) Output voltage
0.1V[5.0Vto 17.0V]
0.2V[8.0Vto 35.0V]
01h
02h
03h
04h
05h
8
Δ VGH(COLD) Voltage [6:0]
0.2V [VGH(HOT) + 15V]
0:Disable, 1:Enable
8
VGH NTC Enalbe [7]
8
VGL Output voltage
0.1V[-14.0Vto -4.0V]
VGL Output voltage setting
8
VCOM(HOT) Output voltage
40mV [0.5xAVDD ±4.0V]
VCOM(HOT) Output voltage setting
Δ VCOM(COLD) Voltage [6:0]
VCOM NTC Enalbe [7]
VDD Output voltage [5:0]
VDD mode select [6]
VDD Phase [7]
10mV[VCOM(HOT) - 0.63V]
0:Disable, 1:Enable
0.05V[0.9Vto 3.4V]
0 : DC/DC, 1 : LDO
See P.56 page.
8
VDD Output voltage setting
Select VDD operation mode DC/DC or LDO
select VDD Phase
06h
07h
08h
8
8
8
Reset Voltage [4:0]
Reset monitor select [5]
GPM input delay [7:6]
Discharge time [2:0]
Delay1 time [6:3]
0.1V[0.6Vto 3.3V]
0:VDD, 1:VIN
00: 0.1usec, 01: 0.5usec, 10: 1.0usec, 11: 1.5usec
Reset voltage setting
Select monitor pin of reset function
GPM input propagation delay time setting
Pre-discharge time setting
Load sw itch of AVDD start-up delay time setting
24pin function select
1msec [0 to 5msec]
[0 to 300msec]
Function Select [7]
Delay2 time [2:0]
0: PG, 1: LDSW
5msec [0 to 30msec, 40msec]
0: Disable, 1: Enable
5msec [0 to 30msec, 40msec]
0: Disable, 1: Enable
5msec [0 to 30msec, 40msec]
0: 0.5sec, 1: 1.0sec
Reset start delay time setting
Double Register Function
DoubleReg [3]
09h
0Ah
8
8
Delay3 time [6:4]
VGL or VGH start-up delay time setting
Data Refresh Function
DataRef [7]
Delay4 time [2:0]
GPM start delay time setting
Data Refresh Time
AR_Time [3]
Delay5 time [6:4]
2msec [0 to 10msec]
0: Enable, 1: Disable
See p.49 page.
VDD stop delay time setting
VGH Discharge function enable
VGH Discharge enable [7]
AVDD Coil[1:0]
select AVDD Coil indactance
4step slew rate setting
(11:fast → 00:slow)
AVDD SW Slew Rate [3:2]
See p.48 page.
0Bh
0Ch
8
8
AVDD SS time [5:4]
AVDD OCP Select [6]
AVDD COMP [7]
5msec [5msec to 20msec]
0: 2A, 1: 1A
AVDD softstart time setting
AVDD OCP min value select
AVDD phase compensation setting
See p.49 page.
00:2.1MHz, 01:1.05MHz, 10:525KHz, 11:525KHz
AVDD Frequecy [1:0]
VDD Frequecy [3:2]
Seletc AVDD switching frequency
Select VDD switching frequency
Select VGH and VGL switching
frequency. Choose only "00".
Select VGH charge pump mode
00:2.1MHz, 01:1.05MHz, 10:525KHz, 11:525KHz
AVDD Freqency
( 00: x1, 01: --, 10: --, 11: -- )
0: x3 mode, 1: x2 or x4 mode
0:Disable, 1:Enable
VGH / VGL Frequecy [5:4]
VGH mode select [6]
start-up bit [7]
Device Address: 1001111x (VCOM)
Register
Address
Bits
Function
Resolution
Comments
-
7
VCOMCalibrator
+/- 0.01V [ VCOM+/- 0.63V]
VCOMCalibrator
When Start-up bit(REG0Ch[7]) is ”1”, below Register cannot be modified.
VGH NTC Enable REG02h[7]
VCOM NTC Enable REG05h[7]
VDD mode select
Function select
VGH mode select
REG06h[6]
REG08h[7]
REG0Ch[6]
To change those Register setting, start-up bit(REG0Ch[7]) should be in ”0”.
After changing the register value, set the Start-up bit(REG0Ch[7]) to “1” again to start up with the changed setting.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
39/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Register Map
Device Address : 1000000x (PMIC)
Register
Address
D7
D6
D5
D4
D3
D2
D1
D0
Default
AVDD Output Voltage
VGH HOT Output Voltage
⊿VGH COLD Voltage
VGL Output Voltage
00h
68h
59h
83h
3Bh
80h
99h
20h
04h
09h
13h
87h
3Ch
05h
60h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
10h
VGH
NTC Enable
VCOMHOT Output Voltage
⊿VCOMCOLD Votlage
VCOM
NTC Enable
VDD
VDD
VDD Output Voltage
Phase Select
MODE
GPM
Input Delay
Function
Reset
Reset Voltage
Monitor Select
Delay1 time
Discharge time
Delay2 time
Delay4 time
Select
Data Refresh
Delay3 time
Delayt5 time
DoubleReg
AR_Time
VGH
Discharge Enable
AVDD
COMP
Start-up
Bit
AVDD
OCP Select
VGH
AVDD
AVDD
SW Slew Rate
VDD
AVDD
SS Time
VGH/VGL
Frequency
Coil Select
AVDD
mode select
Frequency
Frequency
Check Sum
Double
Register Error
Check sum
Error
AVDD UVP
VDD UVP
VGH UVP
VGL UVP
AVDD OCP
TSD
Device Address : 1001111x (VCOM)
Register
Address
D6
D5
D4
D3
D2
D1
D0
P
P
Default
80h
VCOMCalibration Voltage
-
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
40/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Register Map - continued
Command Table
Regitser Address
02h
⊿VGH COLD
Voltage
[6:0]
05h
06h
07h
08h
00h
01h
03h
04h
AVDD
Output
Voltage
[7:0]
VGH HOT
Output
Voltage
[7:0]
VGL
Output
Voltage
[7:0]
VCOM HOT
Output
Voltage
[7:0]
⊿VCOM
VDD
Output
Voltage
[5:0]
GPM
Input
Delay
[7:6]
Reset
Monitor
Selecet
[5]
VGH
NTC Enable
[7]
VCOM
NTC Enable
[7]
VDD
Phase
[7]
VDD
MODE
[6]
Reset
Voltage
[4:0]
Function
Select
[7]
Delay1
time
[6:3]
Discharge
time
[2:0]
DATA
(HEX)
COLD
Voltage
[6:0]
+0.0V
+0.2V
+0.4V
+0.6V
+0.8V
+1.0V
+1.2V
+1.4V
+1.6V
+1.8V
+2.0V
+2.2V
+2.4V
+2.6V
+2.8V
+3.0V
+3.2V
+3.4V
+3.6V
+3.8V
+4.0V
+4.2V
+4.4V
+4.6V
+4.8V
+5.0V
+5.2V
+5.4V
+5.6V
+5.8V
+6.0V
+6.2V
+6.4V
+6.6V
+6.8V
+7.0V
+7.2V
+7.4V
+7.6V
+7.8V
+8.0V
+8.2V
+8.4V
+8.6V
+8.8V
+9.0V
+9.2V
+9.4V
+9.6V
+9.8V
+10.0V
+10.2V
+10.4V
+10.6V
+10.8V
+11.0V
+11.2V
+11.4V
+11.6V
+11.8V
+12.0V
+12.2V
+12.4V
+12.6V
+12.8V
+13.0V
+13.2V
+13.4V
+13.6V
+13.8V
+14.0V
+14.2V
+14.4V
+14.6V
+14.8V
AVDD/2
-0.00V
-0.01V
-0.02V
-0.03V
-0.04V
-0.05V
-0.06V
-0.07V
-0.08V
-0.09V
-0.10V
-0.11V
-0.12V
-0.13V
-0.14V
-0.15V
-0.16V
-0.17V
-0.18V
-0.19V
-0.20V
-0.21V
-0.22V
-0.23V
-0.24V
-0.25V
-0.26V
-0.27V
-0.28V
-0.29V
-0.30V
-0.31V
-0.32V
-0.33V
-0.34V
-0.35V
-0.36V
-0.37V
-0.38V
-0.39V
-0.40V
-0.41V
-0.42V
-0.43V
-0.44V
-0.45V
-0.46V
-0.47V
-0.48V
-0.49V
-0.50V
-0.51V
-0.52V
-0.53V
-0.54V
-0.55V
-0.56V
-0.57V
-0.58V
-0.59V
-0.60V
-0.61V
-0.62V
-0.63V
-0.64V
-0.65V
-0.66V
-0.67V
-0.68V
-0.69V
-0.70V
-0.71V
-0.72V
-0.73V
-0.74V
-0.75V
-0.76V
-0.77V
-0.78V
-0.79V
-0.80V
-0.81V
-0.82V
-0.83V
-0.84V
-0.85V
-0.86V
-0.87V
-0.88V
-0.89V
-0.90V
-0.91V
-0.92V
-0.93V
-0.94V
-0.95V
-0.96V
-0.97V
-0.98V
-0.99V
-1.00V
-1.01V
-1.02V
-1.03V
-1.04V
-1.05V
-1.06V
-1.07V
-1.08V
-1.09V
-1.10V
-1.11V
-1.12V
-1.13V
-1.14V
-1.15V
-1.16V
-1.17V
-1.18V
-1.19V
-1.20V
-1.21V
-1.22V
-1.23V
-1.24V
-1.25V
-1.26V
-1.27V
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
AVDD/2 +0.04V
AVDD/2 +0.08V
AVDD/2 +0.12V
AVDD/2 +0.16V
AVDD/2 +0.20V
AVDD/2 +0.24V
AVDD/2 +0.28V
AVDD/2 +0.32V
AVDD/2 +0.36V
AVDD/2 +0.40V
AVDD/2 +0.44V
AVDD/2 +0.48V
AVDD/2 +0.52V
AVDD/2 +0.56V
AVDD/2 +0.60V
AVDD/2 +0.64V
AVDD/2 +0.68V
AVDD/2 +0.72V
AVDD/2 +0.76V
AVDD/2 +0.80V
AVDD/2 +0.84V
AVDD/2 +0.88V
AVDD/2 +0.92V
AVDD/2 +0.96V
AVDD/2 +1.00V
AVDD/2 +1.04V
AVDD/2 +1.08V
AVDD/2 +1.12V
AVDD/2 +1.16V
AVDD/2 +1.20V
AVDD/2 +1.24V
AVDD/2 +1.28V
AVDD/2 +1.32V
AVDD/2 +1.36V
AVDD/2 +1.40V
AVDD/2 +1.44V
AVDD/2 +1.48V
AVDD/2 +1.52V
AVDD/2 +1.56V
AVDD/2 +1.60V
AVDD/2 +1.64V
AVDD/2 +1.68V
AVDD/2 +1.72V
AVDD/2 +1.76V
AVDD/2 +1.80V
AVDD/2 +1.84V
AVDD/2 +1.88V
AVDD/2 +1.92V
AVDD/2 +1.96V
AVDD/2 +2.00V
AVDD/2 +2.04V
AVDD/2 +2.08V
AVDD/2 +2.12V
AVDD/2 +2.16V
AVDD/2 +2.20V
AVDD/2 +2.24V
AVDD/2 +2.28V
AVDD/2 +2.32V
AVDD/2 +2.36V
AVDD/2 +2.40V
AVDD/2 +2.44V
AVDD/2 +2.48V
AVDD/2 +2.52V
AVDD/2 +2.56V
AVDD/2 +2.60V
AVDD/2 +2.64V
AVDD/2 +2.68V
AVDD/2 +2.72V
AVDD/2 +2.76V
AVDD/2 +2.80V
AVDD/2 +2.84V
AVDD/2 +2.88V
AVDD/2 +2.92V
AVDD/2 +2.96V
AVDD/2 +3.00V
AVDD/2 +3.04V
AVDD/2 +3.08V
AVDD/2 +3.12V
AVDD/2 +3.16V
AVDD/2 +3.20V
AVDD/2 +3.24V
AVDD/2 +3.28V
AVDD/2 +3.32V
AVDD/2 +3.36V
AVDD/2 +3.40V
AVDD/2 +3.44V
AVDD/2 +3.48V
AVDD/2 +3.52V
AVDD/2 +3.56V
AVDD/2 +3.60V
AVDD/2 +3.64V
AVDD/2 +3.68V
AVDD/2 +3.72V
AVDD/2 +3.76V
AVDD/2 +3.80V
AVDD/2 +3.84V
AVDD/2 +3.88V
AVDD/2 +3.92V
AVDD/2 +3.96V
AVDD/2 +4.00V
AVDD/2 +4.04V
AVDD/2 +4.08V
AVDD/2 +4.12V
AVDD/2 +4.16V
AVDD/2 +4.20V
AVDD/2 +4.24V
AVDD/2 +4.28V
AVDD/2 +4.32V
AVDD/2 +4.36V
AVDD/2 +4.40V
AVDD/2 +4.44V
AVDD/2 +4.48V
AVDD/2 +4.52V
AVDD/2 +4.56V
AVDD/2 +4.60V
AVDD/2 +4.64V
AVDD/2 +4.68V
AVDD/2 +4.72V
AVDD/2 +4.76V
AVDD/2 +4.80V
AVDD/2 +4.84V
AVDD/2 +4.88V
AVDD/2 +4.92V
AVDD/2 +4.96V
AVDD/2 +5.00V
AVDD/2 +5.04V
AVDD/2 +5.08V
0 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
5 msec
VDD
0 msec
1 msec
2 msec
3 msec
4 msec
8.0
V
-4.0
V
10 msec
15 msec
20 msec
25 msec
30 msec
35 msec
40 msec
60 msec
80 msec
100 msec
150 msec
200 msec
250 msec
300 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5.0
V
3.3
V
5 msec
DC/DC
0.1 usec
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
V
V
V
V
V
V
V
V
V
-4.1
-4.2
-4.3
-4.4
-4.5
-4.6
-4.7
-4.8
-4.9
-5.0
-5.1
-5.2
-5.3
-5.4
-5.5
-5.6
-5.7
-5.8
-5.9
-6.0
-6.1
-6.2
-6.3
-6.4
-6.5
-6.6
-6.7
-6.8
-6.9
-7.0
-7.1
-7.2
-7.3
-7.4
-7.5
-7.6
-7.7
-7.8
-7.9
-8.0
-8.1
-8.2
-8.3
-8.4
-8.5
-8.6
-8.7
-8.8
-8.9
-9.0
-9.1
-9.2
-9.3
-9.4
-9.5
-9.6
-9.7
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
VIN
9.8
0 msec
1 msec
2 msec
3 msec
4 msec
10.0
10.2
10.4
10.6
10.8
11.0
11.2
11.4
11.6
11.8
12.0
12.2
12.4
12.6
12.8
13.0
13.2
13.4
13.6
13.8
14.0
14.2
14.4
14.6
14.8
15.0
15.2
15.4
15.6
15.8
16.0
16.2
16.4
16.6
16.8
17.0
17.2
17.4
17.6
17.8
18.0
18.2
18.4
18.6
18.8
19.0
19.2
19.4
19.6
19.8
20.0
20.2
20.4
20.6
20.8
21.0
21.2
21.4
21.6
21.8
22.0
22.2
22.4
22.6
22.8
23.0
23.2
23.4
23.6
23.8
24.0
24.2
24.4
24.6
24.8
25.0
25.2
25.4
25.6
V
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.0
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8.0
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9.0
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.0
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12.0
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
3.40
V
3.3
V
5 msec
VD_Phase_
Set 1
Disable
Disable
Disable
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
VDD
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
3.3
V
5 msec
LDO
0.5 usec
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
-9.8
-9.9
V
-10.0
-10.1
-10.2
-10.3
-10.4
-10.5
-10.6
-10.7
-10.8
-10.9
-11.0
-11.1
-11.2
-11.3
-11.4
-11.5
-11.6
-11.7
-11.8
-11.9
-12.0
-12.1
-12.2
-12.3
-12.4
-12.5
-12.6
-12.7
-12.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
+15.0V
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
VIN
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
3.40
V
3.3
V
5 msec
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
41/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Command Table - continued
Regitser Address
02h
⊿VGH COLD
Voltage
[6:0]
05h
06h
07h
08h
00h
01h
03h
04h
AVDD
Output
Voltage
[7:0]
VGH HOT
Output
Voltage
[7:0]
VGL
Output
Voltage
[7:0]
VCOM HOT
Output
Voltage
[7:0]
⊿VCOM
VDD
Output
Voltage
[5:0]
GPM
Input
Delay
[7:6]
Reset
Monitor
Selecet
[5]
VGH
NTC Enable
[7]
VCOM
NTC Enable
[7]
VDD
Phase
[7]
VDD
MODE
[6]
Reset
Voltage
[4:0]
Function
Select
[7]
Delay1
time
[6:3]
Discharge
time
[2:0]
DATA
(HEX)
COLD
Voltage
[6:0]
+0.0V
+0.2V
+0.4V
+0.6V
+0.8V
+1.0V
+1.2V
+1.4V
+1.6V
+1.8V
+2.0V
+2.2V
+2.4V
+2.6V
+2.8V
+3.0V
+3.2V
+3.4V
+3.6V
+3.8V
+4.0V
+4.2V
+4.4V
+4.6V
+4.8V
+5.0V
+5.2V
+5.4V
+5.6V
+5.8V
+6.0V
+6.2V
+6.4V
+6.6V
+6.8V
+7.0V
+7.2V
+7.4V
+7.6V
+7.8V
+8.0V
+8.2V
+8.4V
+8.6V
+8.8V
+9.0V
+9.2V
+9.4V
+9.6V
+9.8V
+10.0V
+10.2V
+10.4V
+10.6V
+10.8V
+11.0V
+11.2V
+11.4V
+11.6V
+11.8V
+12.0V
+12.2V
+12.4V
+12.6V
+12.8V
+13.0V
+13.2V
+13.4V
+13.6V
+13.8V
+14.0V
+14.2V
+14.4V
+14.6V
+14.8V
AVDD/2
-0.00V
-0.01V
-0.02V
-0.03V
-0.04V
-0.05V
-0.06V
-0.07V
-0.08V
-0.09V
-0.10V
-0.11V
-0.12V
-0.13V
-0.14V
-0.15V
-0.16V
-0.17V
-0.18V
-0.19V
-0.20V
-0.21V
-0.22V
-0.23V
-0.24V
-0.25V
-0.26V
-0.27V
-0.28V
-0.29V
-0.30V
-0.31V
-0.32V
-0.33V
-0.34V
-0.35V
-0.36V
-0.37V
-0.38V
-0.39V
-0.40V
-0.41V
-0.42V
-0.43V
-0.44V
-0.45V
-0.46V
-0.47V
-0.48V
-0.49V
-0.50V
-0.51V
-0.52V
-0.53V
-0.54V
-0.55V
-0.56V
-0.57V
-0.58V
-0.59V
-0.60V
-0.61V
-0.62V
-0.63V
-0.64V
-0.65V
-0.66V
-0.67V
-0.68V
-0.69V
-0.70V
-0.71V
-0.72V
-0.73V
-0.74V
-0.75V
-0.76V
-0.77V
-0.78V
-0.79V
-0.80V
-0.81V
-0.82V
-0.83V
-0.84V
-0.85V
-0.86V
-0.87V
-0.88V
-0.89V
-0.90V
-0.91V
-0.92V
-0.93V
-0.94V
-0.95V
-0.96V
-0.97V
-0.98V
-0.99V
-1.00V
-1.01V
-1.02V
-1.03V
-1.04V
-1.05V
-1.06V
-1.07V
-1.08V
-1.09V
-1.10V
-1.11V
-1.12V
-1.13V
-1.14V
-1.15V
-1.16V
-1.17V
-1.18V
-1.19V
-1.20V
-1.21V
-1.22V
-1.23V
-1.24V
-1.25V
-1.26V
-1.27V
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
12.9
13.0
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
15.0
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
16.0
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
25.8
26.0
26.2
26.4
26.6
26.8
27.0
27.2
27.4
27.6
27.8
28.0
28.2
28.4
28.6
28.8
29.0
29.2
29.4
29.6
29.8
30.0
30.2
30.4
30.6
30.8
31.0
31.2
31.4
31.6
31.8
32.0
32.2
32.4
32.6
32.8
33.0
33.2
33.4
33.6
33.8
34.0
34.2
34.4
34.6
34.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-12.9
-13.0
-13.1
-13.2
-13.3
-13.4
-13.5
-13.6
-13.7
-13.8
-13.9
V
V
V
V
V
V
V
V
V
V
V
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
AVDD/2 -0.04V
AVDD/2 -0.08V
AVDD/2 -0.12V
AVDD/2 -0.16V
AVDD/2 -0.20V
AVDD/2 -0.24V
AVDD/2 -0.28V
AVDD/2 -0.32V
AVDD/2 -0.36V
AVDD/2 -0.40V
AVDD/2 -0.44V
AVDD/2 -0.48V
AVDD/2 -0.52V
AVDD/2 -0.56V
AVDD/2 -0.60V
AVDD/2 -0.64V
AVDD/2 -0.68V
AVDD/2 -0.72V
AVDD/2 -0.76V
AVDD/2 -0.80V
AVDD/2 -0.84V
AVDD/2 -0.88V
AVDD/2 -0.92V
AVDD/2 -0.96V
AVDD/2 -1.00V
AVDD/2 -1.04V
AVDD/2 -1.08V
AVDD/2 -1.12V
AVDD/2 -1.16V
AVDD/2 -1.20V
AVDD/2 -1.24V
AVDD/2 -1.28V
AVDD/2 -1.32V
AVDD/2 -1.36V
AVDD/2 -1.40V
AVDD/2 -1.44V
AVDD/2 -1.48V
AVDD/2 -1.52V
AVDD/2 -1.56V
AVDD/2 -1.60V
AVDD/2 -1.64V
AVDD/2 -1.68V
AVDD/2 -1.72V
AVDD/2 -1.76V
AVDD/2 -1.80V
AVDD/2 -1.84V
AVDD/2 -1.88V
AVDD/2 -1.92V
AVDD/2 -1.96V
AVDD/2 -2.00V
AVDD/2 -2.04V
AVDD/2 -2.08V
AVDD/2 -2.12V
AVDD/2 -2.16V
AVDD/2 -2.20V
AVDD/2 -2.24V
AVDD/2 -2.28V
AVDD/2 -2.32V
AVDD/2 -2.36V
AVDD/2 -2.40V
AVDD/2 -2.44V
AVDD/2 -2.48V
AVDD/2 -2.52V
AVDD/2 -2.56V
AVDD/2 -2.60V
AVDD/2 -2.64V
AVDD/2 -2.68V
AVDD/2 -2.72V
AVDD/2 -2.76V
AVDD/2 -2.80V
AVDD/2 -2.84V
AVDD/2 -2.88V
AVDD/2 -2.92V
AVDD/2 -2.96V
AVDD/2 -3.00V
AVDD/2 -3.04V
AVDD/2 -3.08V
AVDD/2 -3.12V
AVDD/2 -3.16V
AVDD/2 -3.20V
AVDD/2 -3.24V
AVDD/2 -3.28V
AVDD/2 -3.32V
AVDD/2 -3.36V
AVDD/2 -3.40V
AVDD/2 -3.44V
AVDD/2 -3.48V
AVDD/2 -3.52V
AVDD/2 -3.56V
AVDD/2 -3.60V
AVDD/2 -3.64V
AVDD/2 -3.68V
AVDD/2 -3.72V
AVDD/2 -3.76V
AVDD/2 -3.80V
AVDD/2 -3.84V
AVDD/2 -3.88V
AVDD/2 -3.92V
AVDD/2 -3.96V
AVDD/2 -4.00V
AVDD/2 -4.04V
AVDD/2 -4.08V
AVDD/2 -4.12V
AVDD/2 -4.16V
AVDD/2 -4.20V
AVDD/2 -4.24V
AVDD/2 -4.28V
AVDD/2 -4.32V
AVDD/2 -4.36V
AVDD/2 -4.40V
AVDD/2 -4.44V
AVDD/2 -4.48V
AVDD/2 -4.52V
AVDD/2 -4.56V
AVDD/2 -4.60V
AVDD/2 -4.64V
AVDD/2 -4.68V
AVDD/2 -4.72V
AVDD/2 -4.76V
AVDD/2 -4.80V
AVDD/2 -4.84V
AVDD/2 -4.88V
AVDD/2 -4.92V
AVDD/2 -4.96V
AVDD/2 -5.00V
AVDD/2 -5.04V
AVDD/2 -5.08V
0 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
5 msec
VDD
0 msec
1 msec
2 msec
3 msec
4 msec
10 msec
15 msec
20 msec
25 msec
30 msec
35 msec
40 msec
60 msec
80 msec
100 msec
150 msec
200 msec
250 msec
300 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
3.3
V
5 msec
DC/DC
1.0 usec
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
VIN
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
3.40
V
3.3
V
5 msec
VD_Phase_
Set 2
Enable
Enable
Enable
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
-14.0
V
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
VDD
0 msec
1 msec
2 msec
3 msec
4 msec
17.0
V
5 msec
35.0
V
0 msec
1 msec
2 msec
3 msec
4 msec
3.3
V
5 msec
LDO
1.5 usec
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0 msec
1 msec
2 msec
3 msec
4 msec
+15.0V
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
VIN
0 msec
1 msec
2 msec
3 msec
4 msec
5 msec
0 msec
1 msec
2 msec
3 msec
4 msec
3.40
V
3.3
V
5 msec
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
42/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Command Table - continued
Regitser Address
09h
0Ah
0Bh
0Ch
0Dh
VGH
Discharge
Enable
[7]
AVDD
AVDD
SS
time
[5:4]
AVDD
SW
Slew Rate
[3:2]
VGH
VGH/VGL
VDD
AVDD
Delay3
time
[6:4]
Delay2
time
[2:0]
Delay5
time
[6:4]
Delay4
time
[2:0]
AVDD
OCP
COMP
Select
[7]
AVDD
COIL
[1:0]
Start-up
Bit
[7]
Check
Sum
[7:0]
DATA
(HEX)
DataRef
[7]
DoubleReg
[3]
AR_Time
[3]
mode Frequenc Frequenc Frequenc
select
[6]
y
[5:4]
y
[3:2]
y
[1:0]
[6]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
0 msec
5 msec
0 msec
5 msec
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
2.1MHz
1.05MHz
2.1MHz
1.05MHz
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
0.5 sec
2.1MHz
1.05MHz
2.1MHz
1.05MHz
1.05MHz
525KHz
525KHz
0 msec
0 msec
2 msec
4 msec
6 msec
8 msec
5 msec
10 msec
15 msec
20 msec
5 msec
2.1MHz
1.05MHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
525KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
1.05MHz
256KHz
525KHz
5 msec
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
256KHz
525KHz
2.0 A
x3 mode
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
1.05MHz
128KHz
525KHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
AV_COM
P_Set 1
Disable
Enable
Disable
2.1MHz
1.05MHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
1.05MHz
525KHz
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
525KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
525KHz
1.05MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
256KHz
525KHz
10 msec
15 msec
20 msec
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
2.1MHz
1.05MHz
525KHz
2.1MHz
1.05MHz
256KHz
525KHz
1.0 A
x2 mode
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
525KHz
1.05MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
10 msec
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
2.1MHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
525KHz
1.05MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
128KHz
525KHz
2.1MHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
43/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Command Table – continued
Regitser Address
09h
0Ah
0Bh
0Ch
0Dh
VGH
Discharge
Enable
[7]
AVDD
AVDD
SS
time
[5:4]
AVDD
SW
Slew Rate
[3:2]
VGH
VGH/VGL
VDD
AVDD
Delay3
time
[6:4]
Delay2
time
[2:0]
Delay5
time
[6:4]
Delay4
time
[2:0]
AVDD
OCP
COMP
Select
[7]
AVDD
COIL
[1:0]
Start-up
Bit
[7]
Check
Sum
[7:0]
DATA
(HEX)
DataRef
[7]
DoubleReg
[3]
AR_Time
[3]
mode Frequenc Frequenc Frequenc
select
[6]
y
[5:4]
y
[3:2]
y
[1:0]
[6]
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
0 msec
5 msec
0 msec
5 msec
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
AVC_Set1
AVC_Set2
AVC_Set3
AVC_Set4
2.1MHz
1.05MHz
2.1MHz
1.05MHz
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
Slow2
Slow1
Fast1
Fast2
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
0.5 sec
2.1MHz
1.05MHz
2.1MHz
1.05MHz
1.05MHz
525KHz
525KHz
0 msec
0 msec
2 msec
4 msec
6 msec
8 msec
5 msec
10 msec
15 msec
20 msec
5 msec
2.1MHz
1.05MHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
0.5 sec
1.0 sec
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
525KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
1.05MHz
256KHz
525KHz
5 msec
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
256KHz
525KHz
2.0 A
x3 mode
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
1.05MHz
128KHz
525KHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
AV_COM
P_Set 2
Enable
Disable
Enable
2.1MHz
1.05MHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
1.05MHz
525KHz
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
525KHz
525KHz
525KHz
2.1MHz
1.05MHz
2.1MHz
1.05MHz
525KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
1.05MHz
256KHz
525KHz
10 msec
15 msec
20 msec
1.05MHz
525KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
256KHz
525KHz
525KHz
1.05MHz
525KHz
2.1MHz
1.05MHz
256KHz
525KHz
1.0 A
x2 mode
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
1.05MHz
128KHz
525KHz
10 msec
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
2.1MHz
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
0 msec
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
1.05MHz
128KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
5 msec
5 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
10 msec
15 msec
20 msec
25 msec
30 msec
40 msec
128KHz
525KHz
525KHz
525KHz
256KHz
2.1MHz
1.05MHz
128KHz
525KHz
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
44/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Check Sum
Check Sum which has been adopted in BM81810MUF-M is shown below.
You will calculate the Check Sum that the sum of the data, including the Check Sum(CHK7 to CHK0) is 00h.
Register
00h
[7]
A7
B7
C7
D7
E7
[6]
A6
B6
C6
D6
E6
[5]
A5
B5
C5
D5
E5
[4]
A4
B4
C4
D4
E4
[3]
A3
B3
C3
D3
E3
[2]
A2
B2
C2
D2
E2
[1]
A1
B1
C1
D1
E1
[0]
A0
B0
C0
D0
E0
01h
02h
03h
04h
05h
06h
07h
08h
F7
F6
F5
F4
F3
F2
F1
F0
G7
H7
I7
G6
H6
I6
G5
H5
I5
G4
H4
I4
G3
H3
I3
G2
H2
I2
G1
H1
I1
G0
H0
I0
09h
J7
K7
L7
M7
CHK7
J6
K6
L6
M6
CHK6
J5
K5
L5
M5
CHK5
J4
K4
L4
M4
CHK4
J3
K3
L3
M3
CHK3
J2
K2
L2
M2
CHK2
J1
K1
L1
M1
CHK1
J0
K0
L0
M0
CHK0
0Ah
0Bh
0Ch
0Dh
[A7:A0] + [B7:B0] + [C7:C0] + [D7:D0] + [E7:E0] + [F7:F0] + [G7:G0] + [H7:H0] + [I7:I0] + [J7:J0]
+ [K7:K0] + [L7:L0] + [M7:M0] + [CHK7:CHK0] = 00h
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
45/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Soft Start Time
BM81810MUF-M has soft start function on AVDD, VGH, VGL and VDD.
Time of the soft start is up to the output voltage reaches the typ Value.
The output voltage typ Value of each block is shown in the following table.
Soft Start
Output Voltage Typ Value
BLOCK
Soft Start Time
AVDD
VGH
VGL
10.5 V
18.0 V
-6.0 V
1.2 V
Set Register
5 ms
5 ms
VDD
1 ms
The time setting Soft Start of AVDD is shown in the table below.
Bit
AVDD Soft Start Time
0
0
1
1
0
1
0
1
5 ms
10 ms
15 ms
20 ms
The soft-start time of VGH and VGL are 5ms.
The soft-start time of VDD is 1ms.
The soft-start setting an example of AVDD and VGH are shown in the figure below.
ex： Case of AVDD
ex： Case of VGH
Error of Soft-Start Time
Error of Soft-Start Time
Set Voltage＞ Typ.
Set Voltage＞ Typ.
Soft-Start
Time
Soft-Start
Time
VGH(Typ.)
AVDD(Typ.)
AVDD(Typ.)
AVDD
Error of Soft-Start Time
Time
Time
Figure 76. Soft-Start Time
If you change the setting voltage from typ values, occurs error in the soft-start time.
•The setting voltage > Typ Value ••• Soft-start will be more slow.
•The setting voltage < Typ Value ••• Soft-start will be more faster.
No error of soft-start is occurred for change of frequency.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
46/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Block Diagram
VDD
erramp
REGISTER
DAC
pwmcomp
VDD
SWB
30
driver
PGNDB
31
29
VREF
VDD
VINB
1
LDO
RST
28
VREG
2
VREG
RESET
VIN
3
4
AVDD
load SW
VLSO
NTC
22
ADC
SW
6
7
AVDD
PAVDD
erramp
REGISTER
DAC
pwmcomp
Θ
driver
EEPROM
PGND
5
SCL 27
SDA 26
VGL
erramp
REGISTER
DAC
DRN
LOGIC
13
driver
CP_CLK
WPN
21
VGL
12
8
VGL
EN 32
I/F
AVDD
VCOM
logic
OSC
OSCGND
REGISTER
REGISTER
DAC
DAC
VCOM
10
9
NEG
DRP
VGH
erramp
14
driver
24
PG/LDSW
VGH
VGH
Power Good
18
level shift
level shift
CPP2
17
23
FAULT
VCP
16
FAULT
level shift
level shift
CPP1
15
CGND
11
CP_CLK
GPM
level shift
level shift
GSOUT
19
GSIN 25
control
RE
20
Figure 77. Block Diagram
47/75
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
AVDD Block Function
VIN
LOAD SWITCH
VLSO
SW
PAVDD
ERRAMP
REGISTER
DAC
PWM
DRIVER
PGND
DISCHARGE
Figure 78. AVDD Block Diagram
AVDD Block (Boost DC / DC) can set the following functions by EEPROM.
1. AVDD Voltage (Register Address 00h [7:0])
AVDD voltage can be set in 0.1V step from 5.0V to 17.0V.
2. SW Switching Frequency (Register Address 0Ch [1:0])
The switching frequency can be set at 525KHz, 1.05MHz or 2.1MHz.
3. Soft Start Time (Register Address 0Bh [5:4])
Soft Start Time of AVDD can be set in 5ms step from 5ms to 20ms.
4. SW Switching Slew Rate (Register Address 0Bh [3:2])
SW pin switching Slew Rate can be controlled by the register setting.
11’b is the fastest slew rate setting, 00’b is the slowest slew rate setting.
The slew rate by each setting is as follows.
Slew Rate changes by the external part and load electric current conditions such as a coil or the diode, but adjustment
is possible on a true set condition because Slew Rate changes by Slew Rate setting change like Figure.79.
The EMI properties are improved by slowing a slew rate, but please do enough evaluations after a slew rate change
because efficiency becomes the tendency to decrease.
<xx>:AVDD Slew Rate setting
<11>
<11>
<10>
<01>
<01>
<00>
<10>
<00>
Figure 79. AVDD Switching Slew Rate
(VIN=3.3V, AVDD=10.5V, Freq=2.1MHz, L=4.7μH, IAVDD=100mA)
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
48/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
AVDD Block Function - continued
AVDD Efficiency
90
85
80
75
70
65
60
55
50
45
<00>
<01>
<10>
<11>
<xx>:AVDD Slew Rate setting
40
0
50
100
150
200
250
Load [mA]
Figure 80. AVDD Efficiency
(dependent on Slew Rate)
(VIN=3.3V, AVDD=10.5V, Freq=2.1MHz, L=4.7μH, IAVDD=100mA)
5. OCP Detect Level (Register Address 0Bh [6])
SW pin Over Current Protection detection level can be set at 1.0A(Min) or 2.0A(Min).
6. COMP Adjust (Register Address 0B [7])
Phase Margin can be adjusted.
0’b: AV_COMP_SET1
1’b: AV_COMP_SET2
7. COIL Adjust (Register Address 0Bh [1:0])
You can adjust the settings to match the coil constant to be used.
00’b:AV_COIL_SET1
01’b:AV_COIL_SET2
10’b:AV_COIL_SET3
11’b:AV_COIL_SET4
Please set the setting of COIL Adjust by frequency setting (fs) and a coil to use.
Coil Adjust
0Bh[1:0]
00'b
Comp Adjust
fOSC[kHz] Coil[μH]
0Bh[7]
0'b
0'b
525
525
4.7
10
11'b
1050
1050
2100
2100
4.7
10
4.7
10
00'b
11'b
00'b
11'b
0'b
0'b
0'b
0'b
*Please become more than 10μF/25V product (GRT31CC81E106KE01) x3 with AVDD output capacitor at the time of the use
with a coil of 10μH.
In addition, COMP Adjust coordinates phase constant of the ERRAMP output and is effective to shift to the zero point 25% low
frequency side to produce by the ERRAMP output by making Comp Adjust 1'b and is effective in reducing ringing at the time of
the load response by the responsiveness adjustment with the actual machine.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
49/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
AVDD Block Function – continued
About the phase characteristic, please consider it based on enough evaluations with the actual model.
(1) Setting the Output L Constant (Boost Converter)
The coil to use for output is decided by the rating current ILR and input current maximum value IINMAX of the coil.
VIN
IINMAX + 1/2 x ΔIL should not reach
IL
the rating value level
IL
L
ILR
AVDD
IINMAX
average current
Co
Figure 81. Coil Current Waveform
Adjust so that IINMAX +∆IL does not reach the rating current value ILR. ∆IL can be obtained by the following equation.
Figure 82. Output Application Circuit Diagram
1
AVDD - VIN
1
[A]
Here, f is the switching frequency.
∆IL =
VIN
L
AVDD
f
Set with sufficient margin because the coil value may have the dispersion of 30%. If the coil current exceeds the
rating current ILR of the coil, it may damage the IC internal element.
BM81810MUF-M uses the current mode DC/DC converter control and has the optimized design at the coil value. A coil
inductance (L) of 4.7 μH to 10 μH is recommended from viewpoints of electric power efficiency, response, and stability.
(2) Output Capacity Settings
For the capacitor to use for the output, select the capacitor which has the larger value in the ripple voltage VPP
allowance value and the drop voltage allowance value at the time of sudden load change. Output ripple voltage is
decided by the following equation.
Here, f is the switching frequency
and RESR is ESR of output capacitor.
[V]
1
VIN
∆IL
∆VPP
=
ILMAX RESR +
(ILMAX -
)
fCo
AVDD
2
Perform setting so that the voltage is within the allowable ripple voltage range.
For the drop voltage during sudden load change; VDR, please perform the rough calculation by the following equation.
∆I
VDR =
10 μs
[V]
Co
However, 10 μs is the rough calculation value of the DC/DC response speed. Please set the capacitance considering
the sufficient margin so that these two values are within the standard value range.
(3) Selecting the Input Capacitor
Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at
the input side. For the reason, the low ESR capacitor is recommended as an input capacitor which has the value more
than 10 μF and less than 100 mΩ. If a capacitor out of this range is selected, the excessive ripple voltage is
superposed on the input voltage, accordingly it may cause the malfunction of IC.
However these conditions may vary according to the load current, input voltage, output voltage, inductance and
switching frequency. Be sure to perform the margin check using the actual product.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
50/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VGH Block Function
AVDD
DRP
ERRAMP
REGISTER
DAC
DRIVER
VGH
VGH
level shift
level shift
CPP2
DISCHARGE
VCP
level shift
level shift
CPP1
CP_CLK
Figure 83. VGH Block Diagram
VGH Block (Positive Charge Pump) can set below functions by EEPROM.
1. VGH (HOT) Voltage (Register Address 01h [7:0])
VGH (HOT) voltage can be set in 0.2V step from 8.0V to 35.0V.
2. DRP Switching Frequency (Register Address 0Ch [5:4])
Switching frequency can be set at AVDD frequency x1, x1/2, or x1/4.
3. VGH (COLD) Voltage (Register Address 02h [6:0])
To set VGH (COLD) voltage can have the VGH voltage relates to NTC Pin voltage, when NTC Function is used.
VGH (COLD) voltage range can be set in 0.2V step from VGH (HOT) + 0V to VGH (HOT) + 15.0V.
Refer “NTC Block Function” for the detail description of NTC Function.
4. VGH Mode Select (Register Address 0Ch [6])
Boost Stage of Positive Charge Pump can be set by x2, x3, or x4.
x2, x3 can be formed with internal element by EEPROM setting.
x4 can be formed by connecting with external Diode.
Since this function switch needs to change the application construction,
input writing signal by I2C cannot perform Register writing.
To write this Register setting, start-up bit(REG0Ch[7]) should be ”0”.
The VGH voltage output range with the AVDD voltage is related, and may take UVP without being able to output the
VGH voltage of the setting when do not choose appropriate constitution.
Please choose appropriate constitution referring after the following pages.
5. VGH Discharge enable (Register Address 0Ah [7])
When OFF sequence, VGH pin Discharge function can be Enable/Disable.
This function is to confirm when IC starts to operate. If read-and-write is performed after IC starts, the first time
OFF sequence will not be reflected.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
51/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VGH Block Function - continued
Application Example for VGH (3rd Stage Positive Charge Pump)
Depending on the circuit construction, output voltage range of Charge Pump can be limited.
Besides, increasing VGH negative current can lower the possible output voltage.
Please consider the actual application need to select appropriate circuit construction.
Below Figure shows the circuit construction of 3rd Stage Positive Charge Pump.
Under this circuit, the possible setting range of VGH output voltage is (AVDD + 2) V to ( AVDD x 3 - 2 ) V.
(When VGH negative current is 0mA)
AVDD
ERRAMP
REGISTER
DAC
C_AVD
DRP
DRIVER
VGH
VGH
C_VGH
level shift
level shift
C_DRP2
C_VCP
CPP2
DISCHARGE
VCP
level shift
level shift
C_DRP1
CPP1
CP_CLK
Figure 84. 3rd Stage Positive Charge Pump
Application Example for VGH (2nd Stage Positive Charge Pump)
Below Figure shows the circuit construction of 2nd Stage Positive Charge Pump.
Under this circuit, the possible setting range of VGH output voltage is (AVDD + 1) V to (AVDD x 2-1) V
(When VGH negative current is 0mA)
AVDD
ERRAMP
REGISTER
DAC
C_AVD
DRP
DRIVER
VGH
VGH
C_VGH
level shift
level shift
CPP2
DISCHARGE
VCP
level shift
level shift
C_DRP1
CPP1
CP_CLK
Figure 85. 2nd Stage Positive Charge Pump
52/75
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VGH Block Function - continued
Application Example for VGH (4th Stage Positive Charge Pump)
Below Figure shows the circuit construction of 4th Stage Positive Charge Pump.
Under this circuit, the possible setting range of VGH output voltage is (AVDD + 3) V to (AVDD x 4 - 3) V
(When VGH negative current is 0mA)
AVDD
ERRAMP
REGISTER
DAC
C_AVD
DRP
DRIVER
VGH
VGH
D_VGH2
C_VGH
C_DRP3
C_DRP2
level shift
level shift
CPP2
C_VCP2
D_VGH1
C_VCP1
DISCHARGE
VCP
level shift
level shift
C_DRP1
CPP1
CP_CLK
Figure 86. 4th Stage Positive Charge Pump
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
53/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VGL Block Function
PAVDD
DRN
ERRAMP
REGISTER
DAC
DRIVER
CP_CLK
DISCHARGE
VGL
VGL
Figure 87. VGL Block Diagram
VGL Block (Negative Charge Pump) can set below functions by EEPROM.
1. VGL Voltage (Register Address 03h [7:0])
VGL voltage can be set by 0.1V step from -4.0V to -14.0V.
2. DRN Switching Frequency (Register Address 0Ch [5:4])
Switching frequency can set AVDD frequency x1, x1/2, or x1/4.
Application Example for VGL (1st Stage Negative Charge Pump)
Below Figure shows the circuit construction of 1st Stage Negative Charge Pump.
Under this circuit, the possible setting range of VGL output voltage is -4 V to -(AVDD – 2Vf) V
(When VGL positive current is 0mA)
PAVDD
ERRAMP
REGISTER
DAC
C_DRN
DRN
DRIVER
D_VGL
CP_CLK
DISCHARGE
VGL
VGL
C_VGL
Figure 88. 1st Stage Negative Charge Pump
Application Example for VGL (2nd Stage Negative Charge Pump)
Below Figure shows the circuit construction of 2nd Stage Negative Charge Pump.
Under this circuit, the possible setting range of VGL output voltage is -4 V to -(AVDDx2 – 4Vf) V
(When VGL positive current is 0mA)
PAVDD
ERRAMP
REGISTER
DAC
DRN
DRIVER
CP_CLK
C_DRN2
D_VGL2
C_DRN1
D_VGL1
DISCHARGE
VGL
VGL
C_VGL
C_VCN
Figure 89. 2nd Stage Negative Charge Pump
54/75
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VCOM Block Function
AVDD
VCOM
NEG
REGISTER
DAC
Figure 90. VCOM Block Diagram
VCOM Block (VCOM Calibrator) can set below functions by EEPROM.
1. VCOM (HOT) Voltage (Register Address 04h [7:0])
VCOM (HOT) voltage can be set by 40mV step from AVDD/2 +/- 0.0V to 4.0V.
2. VCOM (CAL) Voltage (Device Address 1001111x)
VCOM (CAL) voltage is the function to make minor adjustment of VCOM (HOT) voltage value.
VCOM (HOT) can be set by 10mV step from +/- 0.0V to 0.63V.
Refer Page 19, “EEPROM I2C Format for DVR (VCOM calibrator)” for VCOM (CAL) voltage setting.
3. VCOM (COLD) Voltage (Register Address 05h [6:0])
To set VCOM (COLD) voltage can have the VCOM voltage relates to NTC Pin voltage, when NTC Function is used.
VCOM (COLD) voltage range can be set by 10mV step from VCOM (CAL)–0V to VCOM (CAL)+0.63V.
Refer “NTC Block Function” for the detail description of NTC Function.
However, VCOM output voltage setting range is AVDD x0.7 to AVDD x0.2 or AVDD/2+4.8V to AVDD/2-4.8V.
For Example AVDD = 13.0V
11.13V
+0.63V
VCOM Max Voltage
10.5V
AVDD x 0.7 = 13 x 0.7 = 9.1V
AVDD/2 = 6.5V
VCOM Min Voltage
2.5V
AVDD x 0.2 = 13 x 0.2 = 2.6V
-0.63V
1.87V
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
55/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VDD Block Function
VINB
ERRAMP
REGISTER
DAC
PWM
VDD
SWB
DRIVER
PGNDB
VDD
LDO
DISCHARGE
Figure 91. VDD Block Diagram
VDD Block (Buck DC/DC) can set below functions by EEPROM.
1. VDD Voltage (Register Address 06h [5:0])
VDD voltage can be set by 0.05V step from 0.9V to 3.4V.
2. SWB Switching Frequency (Register Address 0Ch [3:2])
Switching frequency can be set at 525KHz, 1.05MHz, or 2.1MHz.
3. VDD Phase Adjust (Register Address 06h [7])
Phase Margin can be adjusted.
0’b : VD_Phase_Set1
1’b : VD_Phase_Set2
VIN[V]
5
VDD[V]
0.9 to 1.25
1.3 to
VDD Phase Adjust
1'b
0'b
0'b
3.3
0.9 to
Set VDD Phase Adjust 1’b when On-duty < 25%.
4. VDD Mode Select (Register Address 06h [6])
VDD Block can be switched to DC/DC or LDO Mode.
Since this function switch needs to change the application construction,
input writing signal by I2C cannot perform Register writing.
To write this Register setting, start-up bit(REG0Ch[7]) should be ”0”.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
56/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VDD Block Function – continued
Application Example for VDD (Buck DC/DC)
VDD application can select Buck DC/DC or LDO by “VDD Mode Select” of EEPROM setting.
When VDD Mode is selected at ”0”, Buck DC/DC operates.
Below figure shows example of Buck DC/DC application circuit.
VINB
C_VINB
ERRAMP
REGISTER
DAC
PWM
L_SWB
SWB
VDD
DRIVER
C_VDD
PGNDB
VDD
LDO
DISCHARGE
Figure 92. VDD Block Diagram(Buck DC/DC)
Application Example for VDD (LDO)
When VDD Mode is selected at ”1”, LDO operates.
Below figure shows example of LDO application circuit.
VINB
SWB
C_VINB
ERRAMP
REGISTER
DAC
PWM
VDD
DRIVER
C_VDD
PGNDB
VDD
LDO
DISCHARGE
Figure 93. VDD Block Diagram(LDO)
C_VDD in LDO mode, please use 1.0μF to 10μF.
In addition, when VDD function is not used, please set in VDD LDO mode, and, please connect capacitor more than 1.0μF.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
57/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
GPM Block Function
VGH
level shift
level shift
GSOUT
RE
GSIN
control
Figure 94. GPM Block Diagram
GPM Block (Gate Pulse Modulation) can set below functions by EEPROM.
1. Input Delay Time (Register Address 07h [7:6])
Falling timing of input signal can be set at 0.1μs, 0.5μs, 1.0μs, or 1.5μs.
GSIN
Input Delay Time
GSOUT
Figure 95. GPM Input Delay Time
Pin connection when GPM is not used
When GPM function is not used, connect GSIN pin to VIN.
Connect RE pin to resistance (2.0kΩ).
GSOUT pin should be OPEN.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
58/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
RESET Block Function
VIN
VDD
RST
RESET
DELAY
REGISTER
DAC
Figure 96. RESET Block Diagram
RESET Block can set below functions by EEPROM.
1. RESET Detect Voltage (Register Address 07h [4:0])
RESET detection voltage can be set by 0.1V step from 0.6V to 3.3V.
2. RESET Monitor Select (Register Address 07h [5])
RESET detection pin can select from VDD and VIN.
3. Delay2 Time (Register Address 09h [2:0])
RESET detection time can be set from 0ms to 40ms.
Detect Voltage
RESET
Monitor pin
(VIN or VDD)
Detect Voltage -0.1V
Delay2 Time
RST
Figure 97. RESET Function
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
59/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
PG/LDSW Block Function
PG/LDSW Block can switch PG (Power Good) and LDSW (Load Switch) function by EEPROM.
Case of PG Function,
When GPM Block becomes workable, PG pin will change from High to Low to recognize as all boost sequence is completed.
PG/LDSW
SEQUENCE
LOGIC
VGL
Figure 98. PG/LDSW Block Diagram
PG/LDSW
Case of LDSW Function,
This function is used when VGL voltage output is prior to AVDD voltage output.
With below application construction, ”Timing Chart 3” sequence can be realized.
PAVDD
M_LDSW
Gate
Voltage
AVDD
LSW ON Delay
C_LDSW
C_GD
M_LDSW
PAVDD
AVDD
EN
PG/LDSW
R_LDSW
R_LSGATE
M_LDSW
Gate
Voltage
PG/LDSW
SEQUENCE
LOGIC
AVDD
LDSW OFF
Delay
Figure 99. LDSW Function
Figure 100. LDSW Delay Time
LDSW on delay can be set by the formula below.
ꢓꢍꢏꢔꢕꢖꢗ ꢑ ꢓꢍꢎꢏꢐ
ꢓꢍꢏꢔꢕꢖꢗ ꢘ ꢓꢍꢎꢏꢐ
ꢓꢍꢏꢔꢕꢖꢗ ꢘ ꢓꢍꢎꢏꢐ
ꢝꢞꢟ
ꢀꢁꢂꢃꢄꢅꢃꢀꢆꢇꢈꢉ ꢊ ꢋꢌꢍꢎꢏꢐ ꢑ ꢒ
ꢙ ꢚꢛ ꢒꢜ ꢋ
ꢑ
ꢙꢃꢡꢢꢆꢣꢤ
ꢓꢍꢎꢏꢐ
ꢠꢝꢀꢀ
LDSW off delay can be set by the formula below.
ꢓꢍꢏꢔꢕꢖꢗ ꢘ ꢓꢍꢎꢏꢐ
ꢝꢞꢟ
ꢀꢁꢂꢃꢄꢥꢥꢃꢀꢆꢇꢈꢉ ꢊ ꢋꢌꢦ ꢀꢁꢂ ꢑ ꢓꢦ ꢀꢁꢂ ꢑ ꢚꢛ ꢒ
ꢑ
ꢙ ꢡꢢꢆꢣꢤ
ꢓꢍꢎꢏꢐ
ꢠꢝꢀꢀ
where:
AVDD is AVDD setting voltage.
Vth is M_LDSW gate threshold voltage
When using the LDSW function, set the delay3 time to be longer than or equal to the sum of the maximum value including the
variation of the load switch ON delay time and VGL soft start time. If the delay3 time setting is short, UVP is applied at startup.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
60/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
NTC Block Function
VGH
REGISTER
REGISTER
DAC
NTC
ADC
4bit
LOGIC
VCOM
DAC
Θ
Figure 101. NTC Block Diagram
NTC Block is the function to adjust VGH, VCOM voltage depending on NTC pin voltage.
NTC pin will output 40μA (Typ) current.
Connecting thermistor element can perform temperature adjustment function.
Below functions can be set by EEPROM.
1. VGH NTC Enable (Register Address 02h [7])
VGH Block NTC Function can be changed to Enable or Disable.
2. VCOM NTC Enable (Register Address 05h [7])
VCOM Block NTC Function can be changed to Enable or Disable.
Pin connection when NTC is not used.
When NTC function is not used, connect NTC pin to OPEN.
EN Block Function
VEN
Rup
EN
100KΩ
-
+
VREF
(0.9V)
300KΩ
200KΩ
Figure 102. EN Block Diagram
When inserting resistor to EN terminal, EN threshold voltage is decided by resistance division with internal resistor.
Threshold Voltage calculation;
EN threshold voltage high typical ( VENH ) = 0.9/300x (400+Rup) [V]
EN threshold voltage low typical ( VENL ) = 0.9/500x (600+Rup) [V]
The EN threshold voltage including unevenness is as follows;
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
61/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
VGH and VCOM temperature compensation
NTC[V]
1.25V
0.5V
Ta[℃]
VGH[V]
VGH + VGH
Fh
Eh
Dh
Ch
Bh
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
(HOT) (COLD)
VGH
(HOT)
Ta[℃]
VCOM[V]
VCOM
(CAL)
Fh
Eh
Dh
Ch
Bh
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
VCOM + VCOM
(CAL) (COLD)
Ta[℃]
Figure 103. NTC Function
NTC Function can adjust VGH, VCOM voltage depending on NTC voltage (VNTC).
4 bit ADC is used to detect NTC voltage.
When NTC pin voltage VNTC ≤ 0.5V, NTC function will judge as HOT setting.
In this case, VGH and VCOM output voltage can be calculated by below formula.
VGH = VGH (HOT)
VCOM = VCOM (CAL)
When NTC pin voltage VNTC ≥ 1.25V, NTC function will judge as COLD setting.
VGH = VGH (HOT) + ΔVGH (COLD)
VCOM = VCOM (CAL) – ΔVCOM (COLD)
When NTC pin voltage is 0.5V < VNTC < 1.25V, VGH and VCOM can be estimated by below formula.
ꢩꢝꢧꢨꢪꢌꢄ ꢀꢫ
ꢬꢭ
ꢝꢅꢱꢌ ꢋ ꢲꢳꢴꢝ
ꢲꢳꢲꢵꢶꢝ
ꢪ
ꢫ
ꢝꢧꢨ ꢊ
ꢮ ꢒꢓꢄꢯꢅꢀꢯꢰ ꢒ
ꢙ ꢋ ꢬꢙ ꢘ ꢝꢧꢨ ꢨꢄꢱ ꢃꢡꢷꢤ
ꢪ
ꢫ
ꢩꢷꢹꢺꢻ ꢹꢄ ꢀ
ꢝꢅꢱꢌ ꢋ ꢲꢳꢴꢝ
ꢪ
ꢫ
ꢝꢌꢄꢸ ꢊ ꢝꢌꢄꢸ ꢌꢠ ꢋ
ꢮ ꢒꢓꢄꢯꢅꢀꢯꢰ ꢒ
ꢙ ꢋ ꢬꢙꢃꢡꢝꢤ
ꢬꢭ
ꢲꢳꢲꢵꢶꢝ
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
62/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
FAULT Block Function
FAULT
UVLO
TSD
Shut Down
by UVP and OCP
LOGIC
Check Sum
I2C
Fail Register
Figure 104. FAULT Block Diagram
FAULT Function is to inform IC situation to outside.
When the operation is normal, FAULT pin will be High.
When the operation is abnormal, FAULT pin will be Low.
Below are the conditions to have FAULT pin to Low.
I. Detect UVLO
II. Start TSD
III. Shutdown by UVP or OCP
IV. Check Sum NG
Fail Register Function
When FAULT PIN is Low, it is possible to confirm which protection circuit is activating by reading Data from Fail Register.
Fail Register will reflect the protection detected circuit at the moment of FAULT=Low
Register Address of Fail Register is 10h.
Register
Address
D7
D6
D5
D4
D3
D2
D1
D0
Double
Register AVDD OCP
Error
Check sum
Error
AVDD UVP VDD UVP
VGH UVP
VGL UVP
TSD
10h
Fail Register does not have EEPROM writing function.
When VIN UVLO is detected, the data will be deleted.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
63/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Protection function explanation of POWER MANAGEMENT block
I. UNDER VOLTAGE LOCK OUT (UVLO)
The BM81810MUF-M has UVLO function for VIN and a circuit miss-operation during in under UVLO voltage operation is
prevented. If VIN below UVLO voltage, it shuts down VDD, AVDD, VGH, VGL, GPM, VCOM and RESET.
II. THERMAL SHUTDOWN (TSD)
The BM81810MUF-M incorporates a Thermal Shut Down (TSD) function. If IC temperature exceeds 175°C (TYP), it shuts
down VDD, AVDD, VGH, VGL, GPM, VCOM and RESET.
III. UNDER VOLTAGE PROTECTION (UVP)
This block has Under Voltage Protection (UVP) function for VDD, AVDD, VGH and VGL output.
When detecting UVP, inner Counter will be activated, and after 5ms passed, it shuts down VDD, AVDD, VGH, VGL, GPM,
and VCOM. (It also shuts down RESET when RESET monitors VDD voltage.)
IV. OVER VOLTAGE PROTECTION (OVP)
This block has Over Voltage Protection (OVP) function for AVDD output.
When detecting OVP, output voltage rising is limited by forcing Switching turn off. If output voltage falls, Switching is
restarted.
V. OVER CURRENT PROTECTION (OCP)
This block has Over Current Protection (OCP) function for VDD and AVDD.
When detecting OCP, it controls Switching and limits generating over current in FET.
BLOCK
VDD
Protective Function
Working Condition
ISWB > 1.0 A (Min)
Action
Protective removal
ISWB < 1.0 A (Min)
Over current Protection
( Buck DCDC mode )
Control switching pulse duty to not over
current limit
Over current Protection
( LDO mode )
ISWB > 0.3 A (Min)
Control LDO to not over current limit.
ISWB < 0.3 A (Min)
IC restart
Detect : VDD<Target value x 0.8
Release : VDD>Target value x 0.9
IC shutdown
if UVP status maintains during 5ms
Under Voltage Protection
Over Voltage Protection
AVDD > (Target value x 1.1)
Switching STOP
AVDD < ( Target Value x 1.05 )
Control switching pulse duty to not
over current limit
IC shutdown
if OCP status maintains during 5ms
ISW < 1.0 A (Min) or 2.0 A (Min)
IC restart
Over current Protection
Under Voltage Protection
ISW > 1.0 A (Min) or 2.0 A (Min)
AVDD
Detect : AVDD<Target value x 0.8
Release : AVDD>Target value x 0.9
IC shutdown
if UVP status maintains during 5ms
IC restart
Detect : VGH<Target value x 0.8
Release : VGH>Target value x 0.9
IC shutdown
if UVP status maintains during 5ms
VGH
VGL
Under Voltage Protection
Under Voltage Protection
Under Voltage Lockout
Thermal shutdown
IC restart
IC restart
Detect : VGL>Target value x 0.8
Release : VGL<Target value x 0.85
IC shutdown
if UVP status maintains during 5ms
VIN < 2.0V (Min)
Tj > 175°C (Typ)
IC shutdown
IC shutdown
VIN > 2.55V (Typ)
Tj < 150°C (Typ)
General
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
64/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Double Register
BM81810MUF-M can perform various setting by Register.
If these settings are changed without intension, to avoid application abnormal operation, certain specific Register has error
detection function.
Below shows the Register with anomaly detection function.
Register
Address
D7
D6
D5
D4
D3
D2
D1
D0
AVDD Output Voltage
VGH HOT Output Voltage
⊿VGH COLD Voltage
VGL Output Voltage
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
10h
VGH
NTC Enable
VCOMHOT Output Voltage
VCOMCOLD Votlage
VCOM
NTC Enable
VDD
VDD
VDD Output Voltage
Phase
MODE
GPM
Input Delay
Function
Reset
Reset Voltage
Monitor Select
Delay1 time
Discharge time
Delay2 time
Delay4 time
Select
Data Refresh
Delay3 time
Delayt5 time
DoubleReg
AR_Time
VGH
Discharge Enable
AVDD
COMP
Start-up
Bit
AVDD
OCP Select
VGH
AVDD
AVDD
SW Slew Rate
VDD
AVDD
SS Time
VGH/VGL
Frequency
COIL
AVDD
mode select
Frequency
Frequency
Check Sum
Double Register
Error
Check sum
Error
AVDD UVP
VDD UVP
VGH UVP
VGL UVP
AVDD OCP
TSD
Double Register correspond BIT
Data Refresh
Data Refresh is the Function to read Data from EEPROM periodically.
If Register setting is suddenly changed without intension, Data Refresh function can read Data from EEPROM to recover to the
normal Data.
Data Refresh performs at certain cycle period.
The time of period can be set by Register at 0.5s or 1.0s.
In the case of WPN=Low, Double Register Function and Data Refresh Function can be set by Register as Enable or Disable.
Below table shows the function by each combination.
In the case of WPN=High, Double Register Function and Data Refresh Function are Disable.
Data
Refresh
Double
Register
WPN
Data Refresh Operation
Double Register Check
Disable
Low
0 : Disable
0 : Disable
0 : Disable
1 : Enable
Disable
（Keep working even logic abnormality happens）
Enable
Low
Disable
（First shutdown once logic abnormality detects.
After Fault to be low for 1msec, then re-start）
Enable
Disable
Low
Low
High
1 : Enable
1 : Enable
-
0 : Disable
1 : Enable
-
（Data Refresh at set period）
（Keep working even logic abnormality happens）
Enable
Enable
（Data Refresh at set period）
(Perform Data Refresh once logic abnormality detects)
Disable
Disable
（Keep working even logic abnormality happens）
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
65/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
PCB Layout Guide
GND Wiring Pattern
The high current GND (PGND) should be wired thick. To reduce line impedance, the GND lines must be as short and
thick as possible and uses few via. Therefore design at PCB board four layers or above is recommended. (Please use
the middle layer as GND shielding and directly connect each GND.) In the case of two layers or less at PCB board
designs, please enough confirm with the actual model about the heat and the noise with care to a GND wiring.
Switching-Line Wiring Pattern
The wiring from switching line (SW pin) of DC/DC converter to inductor and diode must be as short and thick as
possible. If a wiring is long, ringing by switching increases, and the voltage over the resistance of this IC might be
generated. Please note that switching line does not vary PCB layer.
Switching line and wiring easily affected by noise such as feedback line must be placed separately.
Switching noise spread may cause the lack of operation stability. In case the multi-layer PCB board, please note that a
switching line and a line easily affected by noise or the external components are not adjacent between layers.
Drawing GND shield line between switching line and these lines easily affected by noise is recommended if these lines
are placed close.
Power Supply Voltage Line Wiring Pattern
For power supply voltage (VIN, VINB, VLSO, PAVDD, AVDD, VGH), place smooth capacitor nearby IC pin.
Please note that smooth capacitor does not vary PCB layer.
The figure 105 shows an application circuit on the basis of the basic PCB layout pattern guideline mentioned above.
Bold line: High current line
Blue line(two dots and dashed line): Wiring easily affected by noise
Red line (dashed line): Noise source line such as switching line.
Place smooth capacitor nearby IC pin
D_SW locates it near SW terminal / PAVDD terminal of BM81810MUF-M, and a current loop of SW terminal ••• SBD
••• PAVDD, please become as short as possible.
R_NTC2
R_NTC3
WPN
R_NTC1
R_FLT
VIN
R_RE
GSOUT
VGH
VIN
R_PG
Θ
FAULT
PG / LDSW
C_DRP2
CPP2
C_VGH
D_VGL
4 2 3 2 2 2 1 2 0 2 9 1 8 1 7 1
C_VCP
VIN
VCP
GSIN
SDA
C_DRP1
CPP1
R_RST
SCL
RST
DRP
DRN
C_DRN
VGL
VDD
SWB
EN
VCOM
L_SWB
C_VDD
C_VCOM
C_VGL
1
2
3
4
5
6
7
8
AVDD
AVDD
C_VINB
C_VIN
C_REG
(D_SW)
VIN
C_AVD
C_LSO
Figure 105. PCB Layout Indications
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
66/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
EMC Layout Guide
Introduce the plan that can design on the PCB as EMC measures.
Measures by the board pattern
•Wire AVDD line briefly thickly. (1)
•Wire the current loop of Boost DC/DC briefly thickly. (2)
Measures by the external component
•Insert a common mode filter or a beads coil in the AVDD line and form the EMC filter. (3)
•Place output capacitor and small capacitor (10pF - 1,000pF) in parallel. (4)
•Insert the snubber circuit in SW pin. (Assumed the efficiency becomes worse) (5)
Figure 106. EMI Circuit 1
(2)
Figure 107. EMI Circuit 2
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
67/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
I/O Equivalence Circuit
1. VINB
2. VREG
3. VIN
VIN
VINB
VIN
VREG
4. VLSO
6. SW
7. PAVDD
VIN
PAVDD
PAVDD
VLSO
SW
8. AVDD
9. NEG
10. VCOM
AVDD
AVDD
AVDD
AVDD
VCOM
NEG
12. VGL
13. DRN
14. DRP
PAVDD
PAVDD
AVDD
AVDD
Internal reg.
DRN
DRP
VGL
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
68/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
I/O Equivalence Circuit - continued
15. CPP1
16. VCP
17. CPP2
VGH
VGH
VGH
CPP2
CPP2
CPP2
VCP
VCP
VCP
CPP1
CPP1
CPP1
AVDD
VGH
AVDD
VGH
AVDD
18. VGH
19. GSOUT
20. RE
VGH
GSOUT
GSOUT
RE
RE
21. WPN
22. NTC
23. FAULT
VREG
VREG
FAULT
WPN
NTC
24. PG/LDSW
25. GSIN
26. SDA
VREG
VREG
PG/LDSW
SDA
GSIN
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
69/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
I/O Equivalence Circuit - continued
27. SCL
28. RST
29. VDD
VREG
VDD
RST
SCL
30. SWB
32. EN
VREG
VINB
EN
SWB
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
70/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
6.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
71/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Operational Notes – continued
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
10.
Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 108. Example of Monolithic IC Structure
11.
12.
Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13.
Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
72/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Ordering Information
B M 8 1 8 1 0 M U F
-
ME2
Part Number
Package
Product Rank
MUF: VQFN32FBV050
M: for Automotive
Packaging specification
E2: Embossed tape and reel
Marking Diagram
VQFN32FBV050(TOP VIEW)
Part Number Marking
B M
LOT Number
8 1 8 1 0 F
Pin 1 Mark
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
73/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Physical Dimension, Tape and Reel Information
Package Name
VQFN32FBV050
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
74/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
BM81810MUF-M
Revision History
Date
15.May.2020
Revision
001
Changes
New Release
.
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
75/75
TSZ02201-0A3A0AS00510-1-2
15.May.2020 Rev.001
Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明