BR24A16F-WLB(H2)_技术文档

Datasheet

Serial EEPROM Series Industrial EEPROM

105℃ Operation I²C BUS EEPROM (2-Wire)

BR24AxxF-WLB

(1K 2K 4K 8K 16K 32K 64K)

General Description

This is the product guarantees long time support in Industrial market.

BR24AxxF-WLB is a serial EEPROM of I²C BUS interface method.

Features

Package W(Typ.) x D(Typ.) x H(Max.)

 Long Time Support Product for Industrial Applications.

 Completely conforming to the world standard I²C BUS.

All controls available by 2 ports of serial clock

(SCL) and serial data (SDA)

 Wide temperature range -40℃ to +105℃

 Other devices than EEPROM can be connected to

the same port, saving microcontroller port

 2.5V to 5.5V single power source operation most

suitable for battery use

SOP8

5.00mm x 6.20mm x 1.71mm

 Page write mode useful for initial value write at

factory shipment

Application

Industrial Equipment

 Auto erase and auto end function at data rewrite

 Low current consumption



At write operation (5V)

At read operation (5V)

At standby condition (5V) : 0.1μA (Typ.)

: 1.2mA (Typ.) ^*1

: 0.2mA (Typ.)

 Write mistake prevention function



Write (write protect) function added

Write mistake prevention function at low voltage

 Data rewrite up to 1,000,000 times(Ta≦25℃）

 Data kept for 40 years(Ta≦25℃）

 Noise filter built in SCL / SDA terminal

 Shipment data all address FFh

*1 BR24A32F-WLB, BR24A64F-WLB : 1.5mA

Page write

Number of Pages

8Byte

16Byte

32Byte

BR24A04F-WLB

BR24A08F-WLB

BR24A16F-WLB

Product

number

BR24A01AF-WLB

BR24A02F-WLB

BR24A32F-WLB

BR24A64F-WLB

BR24AxxF-WLB

Capacity

Bit format

128×8

256×8

512×8

1K×8

Type

Power source voltage

Package

SOP8

1Kbit

BR24A01AF-WLB

BR24A02F-WLB

BR24A04F-WLB

BR24A08F-WLB

BR24A16F-WLB

BR24A32F-WLB

BR24A64F-WLB

2.5V to 5.5V

2Kbit

4Kbit

8Kbit

16Kbit

32Kbit

64Kbit

2K×8

4K×8

8K×8

○Product structure: Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays

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Absolute Maximum Ratings (Ta=25℃)

Parameter

Symbol

Ratings

-0.3 to +6.5

0.45

Unit

V

Remarks

Supply Voltage

V_CC

Power Dissipation

Storage Temperature

Operating Temperature

Terminal Voltage

Pd

W

℃

V

When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.

Tstg

Topr

‐

-65 to +125

-40 to +105

-0.3 to V_CC+1.0

Memory cell characteristics (V_CC=2.5V to 5.5V)

Limits

Typ.

-

Parameter

Min.

1,000,000

Number of data rewrite times ^*1

100,000

Unit

Times

Years

Conditions

Max

-

Ta≦25℃

Ta≦105℃

Ta≦25℃

Ta≦105℃

40

10

Data hold years ^*1

○Shipment data all address FFh

*1Not 100% TESTED

Recommended Operating Ratings

Parameter

Power source voltage

Input voltage

Symbol

V_CC

V_IN

Ratings

2.5 to 5.5

0 to V_CC

Unit

V

Electrical characteristics (Unless otherwise specified, Ta=-40℃ to +105℃, V_CC=2.5V to 5.5V)

Limits

Typ.

Parameter

Symbol

Unit

Conditions

Min.

0.7 V_CC

Max.

-

0.3 V_CC

0.4

“HIGH” input voltage

“LOW” input voltage

“LOW” output voltage 1

Input leak current

VIH

VIL

VOL

ILI

-

V

μA

-

-1

IOL=3.0mA (SDA)

VIN=0V to V_CC

VOUT=0V to V_CC, (SDA)

V_CC=5.5V,fSCL=400kHz, tWR=5ms,

Byte write, Page write

V_CC=5.5V,fSCL=400kHz

Random read, current read, sequential read

V_CC=5.5V, SDA・SCL= V_CC

A0, A1, A2=GND, WP=GND

1

Output leak current

ILO

2.0 ^*1

3.0 ^*2

ICC1

ICC2

ISB

-

mA

μA

Current consumption

0.5

2.0

Standby current

*1 BR24A01AF/02F/04F/08F/16F-WLB, *2 BR24A32F/64F-WLB

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Operating timing characteristics (Unless otherwise specified, Ta=-40℃ to +105℃, V_CC=2.5V to 5.5V)

FAST-MODE

STANDARD-MODE

2.5V≦V_CC≦5.5V

Parameter

Symbol

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

SCL frequency

fSCL

tHIGH

tLOW

tR

tF

tHD:STA

tSU:STA

tHD:DAT

tSU:DAT

tPD

tDH

tSU:STO

tBUF

-

0.6

1.2

-

400

-

0.3

-

4.0

4.7

-

100

-

1.0

0.3

-

kHz

μs

ns

μs

ms

μs

ns

μs

Data clock “HIGH“ time

Data clock “LOW“ time

SDA, SCL rise time ^*1

SDA, SCL fall time ^*1

-

Start condition hold time

Start condition setup time

Input data hold time

Input data setup time

Output data delay time

Output data hold time

Stop condition setup time

Bus release time before transfer start

Internal write cycle time

Noise removal valid period (SDA, SCL terminal)

WP hold time

0.6

0

100

0.1

0.6

1.2

-

0

0.1

1.0

4.0

4.7

0

250

0.2

4.7

-

0

0.1

1.0

-

0.9

-

3.5

-

tWR

tI

tHD:WP

tSU:WP

tHIGH:WP

5

0.1

-

5

0.1

-

WP setup time

WP valid time

*1 Not 100% tested

FAST-MODE and STANDARD-MODE

FAST-MODE and STANDARD-MODE are of same operations, and mode is changed. They are distinguished by operating

speeds. 100kHz operation is called STANDARD-MODE, and 400kHz operation is called FAST-MODE. This operating

frequency is the maximum operating frequency, so 100kHz clock may be used in FAST-MODE. At V_CC=2.5V to 5.5V,

400kHz, namely, operation is made in FASTMODE. (Operation is made also in STANDARD-MODE.)

Sync Data Input / Output Timing

tR

tF

tSU:DAT tLOW

tPD

tHIGH

SCL

SDA

tHD:STA

tBUF

tHD:DAT

tSU:STA

tHD:STA

tSU:STO

SDA

(入力)

(input)

tDH

SDA

(output)

(出力)

START BIT

STOP BIT

○Input read at the rise edge of SCL

○Data output in sync with the fall of SCL

Figure 1-(a) Sync data input / output timing

Figure 1-(b) Start-stop bit timing

SCL

DATA(1)

D1 D0 ACK

DATA(n)

SCL

ACK

SDA

WP

ｔWR

SDA

D0

ACK

Stop condition

ストップコンディション

Write data

ｔWR

Stop condition

(n-th address)

Start condition

tSU：WP

ｔHD：WP

Figure 1-(c) Write cycle timing

Figure 1-(d) WP timing at write execution

SCL

DATA(n)

DATA(1)

D1 D0 ACK

ACK

SDA

WP

tHIGH:WP

tWR

○At write execution, in the area from the D0 taken clock rise of the first

DATA(1), to tWR, set WP=“LOW”.

○By setting WP “HIGH” in the area, write can be cancelled.

When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of

address under access is not guaranteed, therefore write it once again.

Figure 1-(e) WP timing at write cancel

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Block Diagram

*2

1Kbit to 64Kbit EEPROM array

A0

A1

VCC

WP

1

8

*1

7bit

8bit

11bit

12bit

8bit

9bit 13bit

10bit

*2

Data

register

Address

decoder

Slave - word

address register

7bit 11bit

8bit 12bit

9bit 13bit

10bit

2

3

4

7

6

5

*1

START

STOP

*2

A2

SCL

SDA

Control circuit

ACK

High voltage

generating circuit

Power source

voltage detection

GND

*1

^*2 A0=N.C.

A0, A1=N.C.

A0, A1= N.C. A2=Don’t Use

: BR24A04F-WLB

: BR24A08F-WLB

: BR24A16F-WLB

7bit : BR24A01AF-WLB

8bit : BR24A02F-WLB

9bit : BR24A04F-WLB

10bit : BR24A08F-WLB

11bit : BR24A16F-WLB

12bit : BR24A32F-WLB

13bit : BR24A64F-WLB

Pin Configuration

(TOP VIEW)

A0

A1

VCC

WP

1

2

8

BR24A01AF-WLB

BR24A02F-WLB

BR24A04F-WLB

BR24A08F-WLB

BR24A16F-WLB

BR24A32F-WLB

BR24A64F-WLB

7

6

A2

SCL

SDA

3

4

GND

5

Pin Descriptions

Function

Terminal Input /

name

output

BR24A01AF-WLB BR24A02F-WLB

BR24A04F-WLB

BR24A08F-WLB

BR24A16F-WLB

BR24A32F-WLB BR24A64F-WLB

Slave address setting

A0

A1

Input

-

Slave address setting

Not connected

Slave address setting

Reference voltage of all input / output, 0V

Not connected

A2

Not used

GND

SDA

SCL

WP

VCC

Input /

output

Slave and word address, Serial data input serial data output

Serial clock input

Input

-

Write protect terminal

Connect the power source.

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BR24AxxF-WLB (1K 2K 4K 8K 16K 32K 64K)

Typical Performance Curves

(The following values are Typ. ones.)

6

5

4

6

5

4

3

2

1

0

Ta=105℃

Ta=-40℃

Ta=25℃

3

2

1

0

SPEC

Ta=105℃

Ta=-40℃

Ta=25℃

SPEC

5

0

1

2

3

Vcc[V]

4

5

6

0

1

2

3

4

6

Vcc[V]

Figure 3. L input voltageVIL1,2

(SCL,SDA,WP)

Figure 2. H input voltage VIH1,2

(SCL,SDA,WP)

1

0.8

0.6

0.4

0.2

0

1.2

1.0

0.8

0.6

0.4

0.2

0

SPEC

Ta=105℃

Ta=25℃

Ta=105℃

Ta=25℃

Ta=-40℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

IOL1[mA]

Figure 4. L output voltage VOL1-IOL1

(V_CC=2.5V)

Figure 5. Input leak current ILI (SCL,WP)

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Typical Performance Curves‐Continued

1.2

2.5

2.0

1.5

1.0

0.5

[BR24A01AF/02F/04F/08F/16F-WLB]

SPEC

1

fSCL=400kHz SPEC

DATA=AAh

0.8

0.6

0.4

Ta=105℃

Ta=25℃

Ta=-40℃

Ta=25℃

Ta=105℃

Ta=-40℃

0.2

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 7. Current consumption at WRITE operation

ICC1 (fSCL=400kHz)

Figure 6. Output leak current ILO(SDA)

3.5

0.6

0.5

0.4

0.3

0.2

0.1

0

[BR24A32F/64F-WLB]

SPEC

3.0

2.5

2.0

1.5

1.0

0.5

0

fSCL=400kHz

SPEC

fSCL=400kHz

DATA=AAh

Ta=105℃

Ta=25℃

Ta=105℃

Ta=-40℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 8. Current consumption at WRITE operation

ICC1 (fSCL=400kHz)

Figure 9. Current consumption at READ operation

ICC2 (fSCL=400kHz)

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Typical Performance Curves‐Continued

3.5

2.5

[BR24A01AF/02F/04F/08F/16F-WLB]

[BR24A32F/64F-WLB]

SPEC

3.0

2.5

2.0

fSCL=100kHz

DATA=AAh

fSCL=100kHz

DATA=AAh

SPEC

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

Ta=25℃

Ta=105℃

Ta=-40℃

Ta=25℃

Ta=105℃

Ta=-40℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 11. Current consumption at WRITE operation

ICC1 (fSCL=100kHz)

Figure 10. Current consumption at WRITE operation

ICC1 (fSCL=100kHz)

0.6

2.5

SPEC

0.5

2.0

1.5

1.0

0.5

0

fSCL=100kHz

DATA=AAh

0.4

0.3

Ta=105℃

0.2

Ta=25℃

Ta=105℃

0.1

Ta=-40℃ Ta=25℃

Ta=-40℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 12. Current consumption at READ operation

ICC2 (fSCL=100kHz)

Figure 13. Standby current ISB

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Typical Performance Curves‐Continued

10000

5

4

3

2

1

0

SPEC2

1000

Ta=105℃

Ta=25℃

Ta=-40℃

SPEC1

100

SPEC2

Ta=-40℃

Ta=25℃

Ta=105℃

10

1

SPEC1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 14. SCL frequency fSCL

Figure 15. Data clock "H" time tHIGH

5

4

3

2

1

0

5

SPEC2

4

3

2

1

0

SPEC1

Ta=105℃

Ta=25℃

Ta=-40℃

SPEC1

Ta=-40℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 16. Data clock "L" time tLOW

Figure 17. Start condition hold time tHD:STA

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Typical Performance Curves‐Continued

50

0

6

SPEC1, 2

SPEC2

5

Ta=-40℃

Ta=25℃

Ta=105℃

4

3

-50

-100

-150

-200

2

Ta=-40℃

Ta=25℃

Ta=105℃

1

SPEC1

3

0

1

2

3

4

5

6

0

1

2

4

5

6

Vcc[V]

Figure 18. Start condition setup time tSU:STA

Figure 19. Input data hold time tHD:DAT(HIGH)

50

300

200

100

0

SPEC1, 2

SPEC2

SPEC1

0

-50

Ta=105℃

Ta=25℃

-100

-150

-200

Ta=105℃

Ta=25℃

Ta=-40℃

-100

-200

Ta=-40℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 20. Input data hold time tHD:DAT(LOW)

Figure 21. Input data setup time tSU:DAT(HIGH)

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BR24AxxF-WLB (1K 2K 4K 8K 16K 32K 64K)

Typical Performance Curves‐Continued

300

4

3

2

1

0

SPEC2

200

SPEC2

SPEC1

100

Ta=105℃

0

Ta=25℃

Ta=-40℃

SPEC1

Ta=-40℃

-100

-200

Ta=25℃

SPEC2

SPEC1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 22. Input data setup time tSU:DAT(LOW)

Figure 23. Output data delay time tPD0

4

3

2

1

0

5

SPEC2

4

3

2

1

0

SPEC2

Ta=-40℃

Ta=25℃

Ta=105℃

Ta=-40℃

SPEC1

Ta=25℃

Ta=105℃

SPEC2

SPEC1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 25. Bus release time before transfer start tBUF

Figure 24. Output data delay time tPD1

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BR24AxxF-WLB (1K 2K 4K 8K 16K 32K 64K)

Typical Performance Curves‐Continued

0.6

0.5

0.4

0.3

0.2

0.1

0

6

SPEC1, 2

5

Ta=25℃

4

Ta=-40℃

Ta=25℃

3

Ta=105℃

SPEC1, 2

2

1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 26. Internal write cycle time tWR

Figure 27. Noise removal valid time tI(SCL H)

0.6

0.5

0.4

0.3

0.2

0.1

0

0.6

0.5

0.4

0.3

0.2

0.1

0

Ta=-40℃

Ta=25℃

Ta=-40℃

Ta=105℃

Ta=25℃

Ta=105℃

SPEC1, 2

SPEC1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 29. Noise removal valid time tI(SDA H)

Figure 28. Noise removal valid time tI(SCL L)

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BR24AxxF-WLB (1K 2K 4K 8K 16K 32K 64K)

Typical Performance Curves‐Continued

0.6

0.5

0.4

0.2

0

SPEC1, 2

Ta=-40℃

0.3

-0.2

-0.4

-0.6

Ta=25℃

Ta=105℃

0.2

Ta=25℃

SPEC1

0.1

Ta=-40℃

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Vcc[V]

Figure 31. WP setup time tSU:WP

Figure 30. Noise removal valid time tI(SDA L)

1.2

1

SPEC1, 2

0.8

0.6

0.4

0.2

0

Ta=-40℃

Ta=25℃

Ta=105℃

0

1

2

3

4

5

6

Vcc[V]

Figure 32. WP valid time tHIGH:WP

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BR24AxxF-WLB (1K 2K 4K 8K 16K 32K 64K)

I²C BUS Communication

○I²C BUS data communication

I²C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and

acknowledge is always required after each byte. I²C BUS carries out data transmission with plural devices connected by

2 communication lines of serial data (SDA) and serial clock (SCL).

Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is

controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during

data communication is called “transmitter”, and the device that receives data is called “receiver”.

SDA

1-7

8

9

8

9

8

9

SCL

S

P

START ADDRESS R/W

condition

ACK

DATA

ACK

DATA

ACK

STOP

condition

Figure 33. Data transfer timing

○Start condition (Start bit recognition)

・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL

is 'HIGH' is necessary.

・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition

is satisfied, any command is executed.

○Stop condition (stop bit recongnition)

・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'

○Acknowledge (ACK) signal

・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In

master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data

output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data.

・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read

command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK

signal) showing that it has received the 8bit data.

・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.

・Each write operation outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write

data).

・Each read operation outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.

・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this

IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and

recognizes stop condition (stop bit), and ends read operation. And this IC gets in status.

○Device addressing

・Output slave address after start condition from master.

・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.

・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same

bus according to the number of device addresses.

・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read operation, and is

as shown below.

Setting R / W to 0 ------- write (setting 0 to word address setting of random read)

Setting R / W to 1 ------- read

Maximum number of

A0

A1

1

8

Type

Slave address

Vcc

WP

SCL

SDA

1

connected buses

BR24A01AF-WLB

BR24A02F-WLB

―

R/W

―

BR24A01AF-WLB

BR24A02F-WLB

BR24A04F-WLB

BR24A08F-WLB

BR24A16F-WLB

BR24A32F-WLB

BR24A64F-WLB

1

0

1

0

A2

P2

A2

A1

P1

A1

A0

PS

P0

A0

8

4

2

1

8

2

7

1

_BR24A04F-WLB

R/W

―

1

BR24A08F-WLB

R/W

―

A2

3

6

BR24A16F-WLB

BR24A32F-WLB

BR24A64F-WLB

1

R/W

―

R/W

―

GND

4

5

1

R/W

―

R/W

PS, P0 to P2 are page select bits.

Note) Up to 4 units BR24A04F-WLB, up to 2 units of BR24A08F-WLB, and one unit of BR24A16F-WLB can be connected.

Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.

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Write Command

○Write cycle

・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous

data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is

specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24A32F / A64F-WLB)

S

T

A

R

T

W

R

I

T

E

S

T

O

SLAVE

ADDRESS

WORD

ADDRESS

DATA

P

SDA

LINE

WA

7

WA

0

1

0

1

0 A2A1A0

Note)

D7

D0

*1 As for WA7, BR24A01AF-WLB becomes Don’t care.

A

C

K

A

C

K

R

/

W

A

C

K

*1

Figure 34. Byte write cycle (BR24A01AF/02F/04F/08F/16F-WLB)

S

T

A

R

T

W

R

I

T

E

S

T

O

P

SLAVE

ADDRESS

1st WORD

ADDRESS

2nd WORD

ADDRESS

DATA

SDA

LINE

WAWA

WA

0

1

0

1

0 A2A1A0

Note)

D7

D0

*

12 11

*1 As for WA12, BR24A32F-WLB becomes Don’t care.

A

C

K

A

C

K

A

C

K

R

/

W

A

C

K

*1

Figure 35. Byte write cycle (BR24A32F/64F-WLB)

S

T

A

R

T

W

R

I

T

E

S

T

O

P

SLAVE

ADDRESS

WORD

ADDRESS(n)

*2

DATA(n)

DATA(n+15)

SDA

LINE

WA

7

WA

0

1 0 1 0 A2A1A0

D7

D0

*1 As for WA7, BR24A01AF-WLB becomes Don’t care.

*2 As for BR24A01AF/02F-WLB become (n+7).

A

C

K

R A

/ C *1

W K

A

C

K

A

C

K

Note)

Figure 36. Page write cycle (BR24A01AF/02F/04F/08F/16F-WLB)

S

T

A

R

T

W

R

I

T

E

S

T

O

P

SLAVE

ADDRESS

1st WORD

ADDRESS(n)

2nd WORD

ADDRESS(n)

DATA(n)

DATA(n+31)

SDA

LINE

WAWA

WA

0

1

0 1 0 A2A1A0

D7

D0

*

12 11

*1 As for WA12, BR24A32F-WLB becomes Don’t care.

A

C

K

R A

/ C

W K

A

C

K

A

C

K

A

C

K

*1

Note)

Figure 37. Page write cycle (BR24A32F/64F-WLB)

・Data is written to the address designated by word address (n-th address)

・By issuing stop bit after 8bit data input, write to memory cell inside starts.

・When internal write is started, command is not accepted for tWR (5ms at maximum).

・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01AF-WLB, BR24A02F-WLB）

: Up to 16bytes (BR24A04F-WLB,

BR24A08F-WLB,BR24A16F-WLB）

: Up to 32bytes (BR24A32F-WLB, BR24A64F-WLB

And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.

(Refer to "Internal address increment" in Page 15.)

・As for page write cycle of BR24A01AF-WLB and BR24A02F-WLB, after the significant 5 bits (4 significant bits in

BR24A01AF-WLB) of word address are designated arbitrarily, and as for page write command of BR24A04F-WLB,

BR24A08F-WLB, and BR24A16F-WLB, after page select bit (PS) of slave address is designated arbitrarily, by continuing

data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24A01AF-WLB, and

BR24A02F-WLB) is incremented internally, and data up to 16 bytes (up to 8 bytes in BR24A01AF-WLB and

BR24A02F-WLB) can be written.

・As for page write cycle of BR24A32F-WLB and BR24A64F-WLB, after the significant 7 bits (in the case of

BR24A32F-WLB) of word address, or the significant 8 bits (in the case of BR24A64F-WLB) of word address are designated

arbitrarily, by continuing data input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes

can be written.

*1 In BR24A16F-WLB, A2 becomes P2.

Note)

*1*2 *3

A1

1 0 1 0 A2 A0

*2 In BR24A08F-WLB, BR24A16F-WLB, A1 become P1.

*3 In BR24A04F-WLB, A0 becomes PS, and in BR24A08F-WLB and

BR24A16F-WLB, A0 becomes P0.

Figure 38. Difference of slave address of each

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○Notes on write cycle continuous input

At STOP (stop bit),

write starts.

S

T

A

R

T

W

R

I

T

E

S

T

A

R

T

S

T

O

P

SLAVE

ADDRESS

WORD

ADDRESS（ｎ）

*2

DATA(n+7)

*3

DATA(n)

SDA

LINE

*1

WA

0

WA

7

1

0

1

0 A2A1A0

D7

D0

1 0 1 0

R A

/ C

W K

A

C

K

A

C

K

A

C

K

Next command

Note)

tWR(maximum : 5ms)

Command is not accepted for this period.

Figure 39. Page write cycle

*1 BR24A01AF-WLB becomes Don’t care.

*2 BR24A04F-WLB, BR24A08F-WLB, and BR24A16F-WLB become (n+15).

*3 BR24A32F-WLB and BR24A64F-WLB become (n+31).

Note)

*1*2 *3

A1

1 0 1 0 A2 A0

*1 In BR24A16F-WLB, A2 becomes P2.

*2 In BR24A08F-WLB, BR24A16F-WLB, A1 become P1.

*3 In BR24A04F-WLB, A0 becomes PS, and in BR24A08F-WLB

and in BR24A16F-WLB, A0 becomes P0.

Figure 40. Difference of each type of slave address

○Notes on page write cycle

List of numbers of page write

Number of Pages

8Byte

16Byte

32Byte

BR24A04F-WLB

BR24A08F-WLB

BR24A16F-WLB

Product

number

BR24A01AF-WLB

BR24A02F-WLB

BR24A32F-WLB

BR24A64F-WLB

The above numbers are maximum bytes for respective types.

Any bytes below these can be written.

In the case BR24A02F-WLB, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write.

It does not stand 5ms at maximum × 8byte=40ms(Max.).

○Internal address increment

Page write mode (in the case of BR24A02F-WLB)

WA7 ----- WA4 WA3 WA2 WA1 WA0

0

-----

0

1

0

1

0

Increment

0

-----

0

1

0

1

0

1

0

06h

Significant bit is fixed.

No digit up

For example, when it is started from address 06h, therefore, increment is made as below,

06h → 07h → 00h → 01h ---, which please note.

*06h･･･06 in hexadecimal, therefore, 00000110 becomes a binary number.

○Write protect (WP) terminal

・Write protect (WP) function

When WP terminal is set V_CC(H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of

all address is enabled. Be sure to connect this terminal to V_CCor GND, or control it to H level or L level. Do not use it open.

At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.

During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.

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Read Command

○Read cycle

Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.

Random read cycle is a command to read data by designating address, and is used generally.

Current read cycle is a command to read data of internal address register without designating address, and is used when

to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be

read in succession.

W

R

I

T

E

It is necessary to input 'H' to

the last ACK.

S

T

A

R

T

S

T

A

R

T

R

E

A

D

S

T

O

SLAVE

ADDRESS

SLAVE

ADDRESS

WORD

ADDRESS(n)

DATA(n)

P

SDA

LINE

WA

7

WA

0

1

0

1

0 A2A1A0

1

0 1 0 A2A1A0

D7

D0

A

C

K

*1

R A

/ C

W K

A

C

K

R A

/ C

W K

Note)

*1 As for WA7, BR24A01AF-WLB become Don’t care.

Figure 41. Random read cycle (BR24A01AF/02F/04F/08F/16F-WLB)

S

T

A

R

T

W

R

I

T

E

S

T

A

R

T

R

E

A

D

S

T

O

P

SLAVE

ADDRESS

1st WORD

ADDRESS（ｎ）

2nd WORD

ADDRESS（ｎ）

SLAVE

ADDRESS

DATA(n)

SDA

LINE

WA

0

* * ^WAWA

12 11

A2

A1A0

1

0

1

0

1 0 1 0

A1A0

D7

D0

A2

*

R

/ C

W K

A

C

K

A

C

K

R

/

W

A

C

K

A

C

K

*1

Note)

*1 As for WA12, BR24A32F-WLB become Don’t care.

Figure 42. Random read cycle (BR24A32F/64F-WLB)

S

R

E

A

D

S

T

O

T

A

R

T

It is necessary to input 'H' to

the last ACK.

SLAVE

ADDRESS

DATA(n)

P

SDA

LINE

1 0 1 0 A2A1A0

D7

D0

A

C

K

R A

/ C

W K

Note)

Figure 43. Current read cycle

S

T

A

R

E

A

D

S

T

O

P

SLAVE

ADDRESS

DATA(n)

DATA(n+x)

T

SDA

LINE

A2 A0

A1

1

0

1

0

D7

D0

D7

D0

R

/

W

A

C

K

A

C

K

A

C

K

A

C

K

Note）

Figure 44. Sequential read cycle (in the case of current read cycle)

・In random read cycle, data of designated word address can be read.

・When the command just before current read cycle is random read cycle, current read cycle (each including sequential

read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.

・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address

data can be read in succession.

・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .

・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.

Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to

input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.

・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL

signal 'H'.

Note)

*1*2 *3

A1

*1 In BR24A16F-WLB, A2 becomes P2.

1 0 1 0 A2 A0

*2 In BR24A08F-WLB, BR24A16F-WLB, A1 become P1.

*3 In BR24A04F-WLB, A0 becomes PS, and in BR24A08F-WLB

and BR24A16F-WLB, A0 becomes P0.

Figure 45. Difference of slave address of each type

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Software reset

Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset

has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 46(a), Figure 46(b), and Figure 46(c).)

In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'

level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading

to instantaneous power failure of system power source or influence upon devices.

Dummy clock×14

Start×2

SCL

SDA

Normal command

13

2

14

1

Figure 46-(a) The case of dummy clock +START+START+ command input

Start

Dummy clock×9

Start

SCL

SDA

Normal command

1

2

8

9

Figure 46-(b) The case of START +9 dummy clocks +START+ command input

Start×9

SCL

SDA

Normal command

7

2

3

8

9

1

Figure 46-(c) START×9+ command input

※

Start command from START input.

Acknowledge polling

During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic

write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then

it means end of write operation, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next

command can be executed without waiting for tWR = 5ms.

When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if

ACK signal sends back 'L', then execute word address input and data output and so forth.

During internal write,

ACK = HIGH is sent back.

First write command

S

T

A

R

T

S

T

A

R

T

S

T

A

R

T

A

C

K

H

S

T

O

P

A

C

K

H

Slave

Write command

address

t_WR

Second write command

S

T

A

R

T

S

T

A

R

T

A

C

K

L

A

C

K

L

A

C

K

L

S

T

O

P

Slave

C

address

Word

Slave

…

Data

K

H

address

t_WR

After completion of internal write,

ACK=LOW is sent back, so input next

word address and data in succession.

Figure 47. Case to continuously write by acknowledge polling

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WP valid timing (write cancel)

WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP

valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte

write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of

data(in page write cycle, the first byte data) is cancel invalid area.

WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise

of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,

write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Figure 48.)

After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).

・Rise of D0 taken clock

SCL

・Rise of SDA

SCL

SDA

D1

D0

SDA

ACK

D0

ACK

Enlarged view

S

A

C

K

L

S

T

O

P

A

C

K

L

tWR

A

C

K

L

T

A

R

T

Slave

address

Word

address

SDA

WP

C

K

L

Data

D6

D7

D5

D2 D1 D0

D4 D3

Write forced end

WP cancels invalid area

WP cancels valid area

Data is not written.

Data not guaranteed

Figure 48. WP valid timing

Command cancel by start condition and stop condition

During command input, by continuously inputting start condition and stop condition, command can be cancelled.

(Refer to Figure 49.)

However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop

condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by

start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not

determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in

succession, carry out random read cycle.

SCL

SDA

1

0

Start condition

Stop condition

Figure 49. Case of cancel by start, stop condition during slave address input

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I/O peripheral circuit

○Pull up resistance of SDA terminal

SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R_PU), select an appropriate value to

this resistance value from microcontroller V_IL, I_L, and V_OL-I_OLcharacteristics of this IC. If R_PUis large, operating frequency is

limited. The smaller the R_PU, the larger the consumption current at operation.

○Maximum value of R_PU

The maximum value of R_PUis determined by the following factors.

(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of R_PUand SDA should be tR or below.

And AC timing should be satisfied even when SDA rise time is late.

(2)The bus electric potential A to be determined by input leak total (I_L) of device connected to bus at output of 'H' to SDA

○

bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended

noise margin 0.2 V_CC

.

Vcc - I_LR_PU-0.2Vcc ≧ V_IH

BR24AXXF

Microcontroller

0.8Vcc - V_IH

I_L

∴

R_PU=

R_PU

SDA terminal

Ex. ) When V_CC=3V, I_L=10μA, V_IH=0.7 V_CC

,

A

from (2)

0.8×3- 0.7×3

IL

R_PU

≦

10×10^-6

Bus line

バスライン容量

capacity

≦ 300 [kΩ]

CBUS

○Minimum value of R_PU

The minimum value of R_PUis determined by the following factors.

(1)When IC outputs LOW, it should be satisfied that V_OLMAX=0.4V and I_OLMAX=3mA.

Figure 50. I/O circuit diagram

V_C-V_OL

I_OL

V_CC-V_OL

R_PU

≦ I_OL

∴

R_PU≦

(2)V_OLMAX=0.4V should secure the input 'L' level (V_IL) of microcontroller and EEPROM including recommended noise

margin 0.1 V_CC

.

VOLMAX ≦ VIL-0.1 V_CC

Ex. ) When V_CC=3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3 V_CC

from (1)

3－0.4

3×10 ^-3

R_PU

≧

867 [Ω]

And

V_OL= 0.4 [V]

V_IL= 0.3×3

= 0.9 [V]

Therefore, the condition (2) is satisfied.

○Pull up resistance of SCL terminal

When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes

'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ to several ten kΩ is recommended in

consideration of drive performance of output port of microcontroller.

A0, A1, A2, WP process

○Process of device address terminals (A0,A1,A2)

Check whether the set device address coincides with device address input sent from the master side or not, and select

one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or V_CCor GND. And,

pins (N, C, PIN) not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.

Types with N.C.PIN

BR24A16F-WLB

BR24A08F-WLB

BR24A04F-WLB

A0, A1, A2

A0, A1

A0

○Process of WP terminal

WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and

WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is

recommended to connect it to pull up or V_CC. In the case to use both READ and WRITE, control WP terminal or connect it

to pull down or GND.

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Cautions on microcontroller connection

○Rs

In I²C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of

tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.

This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON

simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open

drain input/output, Rs can be used.

ACK

RPU

SCL

RS

SDA

'H' output of microcontroller

'L' output of EEPROM

Microcontroller

EEPROM

Over current flows to SDA line by 'H'

output of microcontroller and 'L'

output of EEPROM.

Figure 51. I/O circuit diagram

Figure 52. Input / output collision timing

○Maximum value of Rs

The maximum value of Rs is determined by the following relations.

(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.

And AC timing should be satisfied even when SDA rise time is late.

(2)The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus

○

should sufficiently secure the input 'L' level (V_IL) of microcontroller including recommended noise margin 0.1 V_CC

.

VCC

(VCC－VOL)×RS

+

VOL+0.1VCC≦VIL

A

RPU

RPU+RS

R^S

VOL

VIL－VOL－0.1VCC

1.1VCC－VIL

∴

RS

≦

×

RPU

I^OL

Bus line

capacity CBUS

Example）When VCC=3V,ꢀVIL=0.3VCC,ꢀVOL=0.4V,ꢀRPU=20kΩ ,

0.3×3－0.4－0.1×3

20×10³

VIL

from(2), RS

≦

×

EEPROM

Microcontroller

1.1×3－0.3×3

Figure 53. I/O circuit diagram

1.67［kΩ ］

≦

○Minimum value of Rs

The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source

line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following

relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so

forth. Set the over current to EEPROM 10mA or below.

VCC

RS

≦

≧

I

R_PU

R_S

'L' output

VCC

I

∴

RS

Over currentⅠ

Example）When VCC=3V, I=10mA

'H' output

3

RS

≧

10×10^-3

EEPROM

Microcontroller

300［Ω ］

Figure 54. I/O circuit diagram

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I²C BUS input / output circuit

○Input (A0,A2,SCL)

Figure 55. Input pin circuit diagram

○Input / output (SDA)

Figure 56. Input / output pin circuit diagram

○Input (A1, WP)

Figure 57. Input pin circuit diagram

Notes on power ON

At power on, in IC internal circuit and set, V_CCrises through unstable low voltage area, and IC inside is not completely reset,

and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the operation,

observe the following conditions at power on.

1. Set SDA = 'H' and SCL ='L' or 'H'

2. Start power source so as to satisfy the recommended conditions of t_R, t_OFF, and Vbot for operating POR circuit.

t_R

VCC

Recommended conditions of t_R, t_OFF,Vbot

t_R

t_OFF

Vbot

10ms or below

100ms or below

10ms or longer

0.3V or below

0.2V or below

t_OFF

Vbot

0

Figure 58. Rise waveform diagram

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3. Set SDA and SCL so as not to become 'Hi-Z'.

When the above conditions 1 and 2 cannot be observed, take the following countermeasures.

a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on.

→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.

V_CC

t_LOW

SCL

SDA

After Vcc becomes stable

t_DH

t_SU:DAT

Figure 59. When SCL= 'H' and SDA= 'L'

Figure 60. When SCL='L' and SDA='L'

b) In the case when the above condition 2 cannot be observed.

→After power source becomes stable, execute software reset(Page 17).

c) In the case when the above conditions 1 and 2 cannot be observed.

→Carry out a), and then carry out b).

Low voltage malfunction prevention function

LVCC circuit prevents data rewrite operation at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below,

it prevent data rewrite.

V_CCnoise countermeasures

○Bypass capacitor

When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is

recommended to attach a by pass capacitor (0.1μF) between IC V_CCand GND. At that moment, attach it as closeto IC as possible.

And, it is also recommended to attach a bypass capacitor between board V_CCand GND.

Note of use

(1) Described numeric values and data are design representative values, and the values are not guaranteed.

(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further

sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin

in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.

(3) Absolute maximum ratings

If the absolute maximum ratings such as impressed voltage and operation temperature range and so forth are exceeded,

LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of

fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that

conditions exceeding the absolute maximum ratings should not be impressed to LSI.

(4)GND electric potential

Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is lower than

that of GND terminal.

(5)Terminal design

In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.

(6)Terminal to terminal shortcircuit and wrong packaging

When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may

destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND

owing to foreign matter, LSI may be destructed.

(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.

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Ordering Information

Product Code Description

B

R

2 4

A

x x

F - W L B H 2

BUS type

24: I²C

Operating temperature

- 40℃ to +105℃

Capacity

01A=1K

08=8K

64=64K

02=2K

04=4K

16=16K

32=32K

Package

F

: SOP8

W

: Double Cell

Product class

LB for Industrial applications

Packaging and forming specification

H2 : Embossed tape and reel

(SOP8)

Lineup

Package

Orderable Part Number

Capacity

Type

SOP8

Quantity

Reel of 250

BR24A01AF-WLBH2

BR24A02F-WLBH2

BR24A04F-WLBH2

BR24A08F-WLBH2

BR24A16F-WLBH2

BR24A32F-WLBH2

BR24A64F-WLBH2

1K

2K

4K

8K

16K

32K

64K

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Physical Dimension Tape and Reel Information

Package Name

SOP8

Max 5.35 (include. BURR)

Drawing: EX112-5001-1

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Marking Diagram

SOP8(TOP VIEW)

Part Number Marking

LOT Number

1PIN MARK

Marking Information

Capacity

1K

Product Name Marking

A01A

A02

A04

A08

A16

A32

A64

2K

4K

8K

16K

32K

64K

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Revision History

Date

Revision

001

Changes

15.Nov.2013

27.Feb.2014

New Release

002

Delete sentence “and log life cycle” in General Description and Futures.

P.10 Modify Figure23 to be able to read comment

P.12 Modify Figure31 to add value in Y-axis

29.Jan.2018

003

P.14 Replace Figure 36 with Figure 37 to correct mistake

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.003

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.003


型号：	BR24A16F-WLB(H2)
厂家：	ROHM
描述：	本产品是面向工业设备市场的产品，保证可长期稳定供货。是适合这些用途的产品。串行EEPROM(Electrically Erasable Programmable Read Only Memory)为非易失性存储器，可在基板上进行电气改写。可以字节(byte)为单位进行改写，适用于保存数据。罗姆的串行EEPROM是实现了高可靠性的高级系列。罗姆的串行EEPROM备有各种容量、接口和封装类型，在全球市场上拥有较高的占有率。罗姆的串行EEPROM采用世界标准的总线形式(Micro wire、²、SPI)，且工作电源电压范围广(1.8V～5.5V、2.5V～5.5V)，适合电池用途。所有产品均为无铅产品，符合RoHS指令。可编程只读存储器电动程控只读存储器电可擦编程只读存储器电池
文件：	总29页 (文件大小：2646K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BR24A16F-WLB(H2) [ROHM]

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