BR25H040F-WC [ROHM]
EEPROM, 512X8, Serial, CMOS, PDSO8, ROHS COMPLIANT, SOP-8;
| 型号： | BR25H040F-WC |
| 厂家： | 
ROHM |
| 描述： | EEPROM, 512X8, Serial, CMOS, PDSO8, ROHS COMPLIANT, SOP-8 存储 内存集成电路 光电二极管 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 |
| 文件： | 总17页 (文件大小：1148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
HIGH GRADE Specification HIGH RELIABILITY series
SPI BUS Serial EEPROMs
Supply voltage 2.5V~5.5V
Operating temperature -40°C ~ +125°C type
☆
☆
BR25H010-W, BR25H020-W, BR25H040-W, BR25H080-W, BR25H160-W, BR25H320-W
☆ : Under development
●Description
BR25H□□□-W series is a serial EEPROM of SPI BUS interface method.
●Features
● High speed clock action up to 5MHz (Max.)
● Wait function by HOLDB terminal.
● Part or whole of memory arrays settable as read only memory area by program.
● 2.5～5.5V single power source action most suitable for battery use.
● Page write mode useful for initial value write at factory shipment.
● Highly reliable connection by Au pad and Au wire.
● For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
● Auto erase and auto end function at data rewrite.
● Low current consumption
●Page write
Number of
pages
16 Byte
32 Byte
At write action (5V)
At read action (5V)
: 1.5mA (Typ.)
: 1.0mA (Typ.)
BR25H010-W
BR25H020-W
BR25H040-W
BR25H080-W
BR25H160-W
BR25H320-W
Product
number
At standby action (5V) : 0.1μA (Typ.)
● Address auto increment function at read action
● Write mistake prevention function
Write prohibition at power on.
Write prohibition by command code (WRDI).
Write prohibition by WPB pin.
Write prohibition block setting by status registers (BP1, BP0)
Write mistake prevention function at low voltage.
● SOP8, SOP-J8 Package
● Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0
● Data kept for 40 years.
● Data rewrite up to 1,000,000times.
●BR25H series
Power source
Capacity Bit format
Type
SOP8 SOP-J8
voltage
2.5~5.5V
2.5~5.5V
2.5~5.5V
2.5~5.5V
2.5~5.5V
2.5~5.5V
1Kbit
2Kbit
128×8
256×8
512×8
1K×8
2K×8
4Kx8
BR25H010-W
BR25H020-W
BR25H040-W
BR25H080-W
BR25H160-W
BR25H320-W
●
●
●
●
●
●
●
●
●
●
●
●
4Kbit
8Kbit
16Kbit
32Kbit
Ver A. Aug. 2007
●Absolute maximum ratings (Ta=25°C)
●Recommended action conditions
Parameter
Impressed voltage
Permissible
Symbol
Vcc
Limits
-0.3~+6.5
450(SOP8)
450(SOP-J8)
Unit
V
Parameter
Power source voltage
Input voltage
Symbol
Vcc
Vin
Limits
2.5~5.5
0~Vcc
Unit
V
*1
*2
Pd
mW
°C
dissipation
Storage
temperature range
Operating
Tstg
-65~150
●Input / output capacity (Ta=25°C, frequency=5MHz)
Topr
–
-40~125
°C
V
temperature range
Parameter
Symbol
CIN
Conditions
VIN=GND
Min.
–
Max.
8
Unit
-0.3~Vcc+0.3
Terminal voltage
ж1
ж1
Input capacity
・When using at Ta=25℃ or higher, 3.6mW (*1,*2) to be reduced per 1℃
pF
Output capacity
COUT
–
8
VOUT=GND
●Memory cell characteristics (Vcc=2.5V～5.5V)
*1: Not 100% TESTED
Limits
Parameter
Unit
Condition
Min
1,000,000
500,000
300,000
40
Typ.
Max
Ta≤85℃
Ta≤105℃
Ta≤125℃
Ta≤25°C
Ta≤85°C
-
-
-
-
-
-
-
-
-
-
Times
Times
Times
Years
Years
Number of data
rewrite times
ж1
Data hold years
ж1
20
ж1:Not 100% TESTED
●Electrical characteristics (Unless otherwise specified, Ta=-40~+125°C, Vcc=2.5~5.5V)
Limits
Parameter
Conditions
Symbol
VIH
Unit
V
Min. Typ. Max.
0.7x
Vcc
Vcc
+0.3
0.3x
Vcc
0.4
“H” input voltage
–
2.5≤Vcc≤5.5V
“L” output voltage
“L” output voltage
“H” output voltage
VIL
VOL
VOH
-0.3
–
–
–
V
V
V
2.5≤Vcc≤5.5V
IOL=2.1mA
0
Vcc
-0.5
-10
Vcc
IOH=-0.4mA
Input leak current
ILI
–
–
10
10
μA
μA
VIN=0~Vcc
Output lead current
ILO
-10
VOUT=0~Vcc, CSB=Vcc
Vcc=2.5V,fSCK=5MHz, tE/W=5ms
VIH/VIL=0.9Vcc/0.1Vcc,
Byte write, Page write
ICC
1
2
–
–
2.0
mA
mA
Current consumption at write
action
Write status regisuter
Vcc=5.5V,fSCK=5MHz, tE/W=5ms
VIH/VIL=0.9Vcc/0.1Vcc
Byte write, Page write
ICC
–
–
–
–
3.0
1.5
Write status register
Vcc=2.5V,fSCK=5MHz
ICC
3
4
mA VIH/VIL=0.9Vcc/0.1Vcc,
Read, Read status register
Vcc=5.5V,fSCK=5MHz
Current consumption at read
action
ICC
–
–
–
–
2.0
10
mA VIH/VIL=0.9Vcc/0.1Vcc
Read, Read status register
Vcc=5.5V
Standby current
ISB
μA
CSB=HOLDB=WPB=Vcc, SCK=SI=Vcc or =GND, SO=OPEN
・Radiation resistance design is not made
●Block diagram
VOLTAGE
CSB
INSTRUCTION DECODE
CONTROL CLOCK
GENERATION
DETECTION
SCK
HIGH VOLTAGE
WRITE
*1 7bit: BR25H010-W
GENERATOR
INHIBITION
8bit: BR25H020-W
9bit: BR25H040-W
SI
INSTRUCTION
REGISTER
STATUS REGISTER
10bit: BR25H080-W
11bit: BR25H160-W
12bit: BR25H320-W
ADDRESS
HOLDB
ADDRESS
7～12bit *1
7～12bit *1
REGISTER
DECODER
1～32K
EEPROM
DATA
READ/WRITE
AMP
WPB
SO
8bit
8bit
REGISTER
Fig.1 Block diagram
2/16
●Pin assignment and description
Terminal name Input/Output
Function
Power source to be connected
All input / output reference voltage, 0V
Chip select input
Serial clock input
Start bit, ope code, address, and serial data input
Serial data output
Vcc
HOLDB SCK
SI
Vcc
GND
CSB
SCK
SI
–
–
Input
Input
Input
Output
BR25H010-W
BR25H020-W
BR25H040-W
BR25H080-W
BR25H160-W
BR25H320-W
SO
Hold input
HOLDB
WPB
Input
Input
Command communications may be suspended temporarily
(HOLD status)
Write protect input
CSB
SO
WPB
GND
Write command is prohibited *1
Write status register command is prohibited.
*1:BR25H010/020/040-W
Fig.2 Pin assignment diagram
●Operating timing characteristics
●
Sync data input
timing
/
output
(Ta=-40~+125°C, unless otherwise specified, load capacity CL1=100pF)
2.5≤Vcc≤5.5V
Min. Typ. Max
Parameter
Symbol
Unit
tCSS
tCS
CSB
SCK
tSCKS
SCK frequency
SCK high time
SCK low time
CSB high time
CSB setup time
CSB hold time
SCK setup time
SCK hold time
SI setup time
fSCK
tSCKWH
tSCKWL
tCS
–
–
–
–
–
–
–
–
–
–
–
–
5
–
–
–
–
–
–
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tFC
tSCKWH
tSCKWL
tDIS
85
85
85
90
85
90
90
20
30
–
tDIH
SI
High-Z
SO
tCSS
tCSH
tSCKS
tSCKH
tDIS
Fig.3 Input timing
SI is taken into IC inside in sync with data rise edge of SCK.
Input address and data from the most significant bit MSB.
tCS
SI hold time
tDIH
–
70
Data output delay time1
Data output delay time1
(CL2=30pF)
tPD1
tSCKH
CSB
tCSH
SCK
SI
tPD2
–
–
55
ns
tPD
tRO,tFO
tOZ
tOH
High-Z
Output hold time
Output disable time
HOLDB setting
setup time
HOLDB setting
hold time
HOLDB release
setup time
HOLDB release
hold time
Time from HOLDB
to output High-Z
Time from HOLDB
To output change
SCK rise time
SCK fall time
tOH
tOZ
0
–
–
–
–
100
ns
ns
SO
Fig.4 Input / Output timing
tHFS
tHFH
tHRS
tHRH
tHOZ
tHPD
0
40
0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
SO is output in sync with data fall edge of SCK. Data is output
from the most significant bit MSB.
"H"
CSB
"L"
–
tHFS tHFH
tHRS tHRH
SCK
SI
70
–
–
tDIS
n
n+1
n-1
tHOZ
Dn
tHPD
High-Z
100
70
SO
Dn+1
Dn
Dn-1
HOLDB
–
Ж1
tRC
tFC
–
–
–
–
1
1
μs
μs
Ж1
Fig.5 HOLD timing
Ж1
OUTPUT
rise time
OUTPUT
fall time
tRO
–
–
50
ns
Ж1
tFO
–
–
–
–
50
5
ns
Write time
tE/W
ms
Ж1 NOT 100% TESTED
●AC measurement conditions
Limits
Min. Typ. Max
Parameter
Symbol
Unit
Load capacity 1
Load capacity 2
Input rise time
Input fall time
Input voltage
CL1
CL2
–
–
–
–
–
–
–
–
–
–
–
100
30
50
pF
pF
ns
ns
V
50
0.2Vcc/0.8Vcc
0.3Vcc/0.7Vcc
Input / Output judgment voltage
–
V
3/16
●Characteristic data (The following characteristic data are Typ. Values.)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
1
0.8
0.6
0.4
0.2
0
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
SPEC
SPEC
4
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
5
6
0
1
2
3
4
5
6
IOL[mA]
Vcc[V]
Fig.7 ꢀ"L" input voltageꢀVIL(CSB,SCK,SI,HOLDB,WPB)
Fig.8ꢀ"L" output voltageꢀVOL-IOL(Vcc=2.5V)
Fig.6 ꢀ"H" input voltageꢀVIH(CSB,SCK,SI,HOLDB,WPB)
12
10
8
12
2.6
2.5
2.4
2.3
2.2
2.1
SPEC
SPEC
10
8
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
6
6
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
4
4
2
1.9
1.8
2
2
0
0
0
0.4
0.8
1.2
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
VOUT[V]
IOH[mA]
Fig.11ꢀOutput leak current ILO(SO)(Vcc=5.5V)
Fig.10ꢀInput leak current ILI(CSB,SCK,SI,HOLDB,WPB)
Fig.9ꢀ"H" output voltage VOH-IOH(Vcc=2.5V)
12
10
8
4
3
2
1
0
2.5
2
fSCK=5MHz
DATA=AAh
fSCK=5MHz
SPEC
SPEC
SPEC
DATA=00h
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
1.5
1
SPEC
6
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
4
0.5
0
2
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.12ꢀCurrent consumption at WRITE operation
Fig.14ꢀConsumption current at standby operation ISB
Fig.13ꢀConsumption Current at READ operation
ICC1,2
ICC3,4
100
100
80
60
40
20
0
100
80
60
40
20
0
SPEC
SPEC
10
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
1
0.1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.15ꢀSCK frequency fSCK
Fig.16 SCK high timeꢀtSCKWH
Fig.17 SCK low timeꢀtSCKWL
100
80
60
40
20
0
100
80
60
40
20
0
100
80
60
40
20
0
SPEC
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.19ꢀCSB setup timeꢀtCSS
Fig.20ꢀCSB hold timeꢀtCSH
Fig.18 CSB high timeꢀtCS
4/16
50
40
30
20
10
0
100
80
60
40
20
0
30
20
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
SPEC
SPEC
10
0
Ta=-40℃
Ta=25℃
Ta=125℃
-10
-20
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Fig.21ꢀSI setup timeꢀtDIS
Vcc[V]
Fig.22ꢀSI hold timeꢀtDIH
Fig.23ꢀData output delay timeꢀtPD1(CL=100pF)
120
100
80
60
40
20
0
100
80
60
40
20
0
80
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
60
40
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
20
0
-20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.25ꢀOutput disable time tOZ
Fig.26ꢀHOLDB setting hold time tHFH
Fig.24ꢀData output delay time tPD2(CL-30pF)
120
100
80
60
40
20
0
80
60
40
20
0
80
60
40
20
0
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
-20
-20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.27ꢀHOLDB release hold time tHRH
Fig.28ꢀTime from HOLDB to output High-Z tHOZ
Fig.29ꢀTime from HOLDB to output change tHPD
100
80
60
40
20
0
100
80
60
40
20
0
8
6
4
2
0
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
Ta=-40℃
Ta=25℃
Ta=125℃
SPEC
Ta=125℃
SPEC
Ta=-40℃
Ta=25℃
SPEC
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Vcc[V]
Fig.32 Write cycle time tE/W
Fig.31 Output fall time tFO
Fig.30 Output rise time tRO
5/16
●Features
○Status registers
This IC has status registers. The status registers are of 8 bits and express the following parameters.
BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are
valid even when power source is turned off.
Rewrite characteristics and data hold time are same as characteristics of the EEPROM.
WEN can be set by write enable command and write disable command. WEN becomes write disable status when power
source is turned off. R/B is for write confirmation, therefore cannot be set externally.
The value of status register can be read by read status command.
●Status registers
Product number
BR25H010-W
BR25H020-W
BR25H040-W
BR25H080-W
BR25H160-W
BR25H320-W
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
BP1
bit 2
BP0
bit 1
bit 0
R/B
WEN
R/B
WPEN
0
0
0
BP1
BP0
WEN
Memory
bit
Function
Contents
location
WPB pin enable / disable designation bit
WPEN=0=invalid
This enables / disables the functions
of WPB pin.
WPEN EEPROM
WPEN=1=valid
This designates the write disable area
of EEPROM. Write designation areas
of product numbers are shown below.
BP1
EEPROM
BP0
EEPROM write disable block designation bit
Write and write status register write enable / disable status confirmation bit
WEN Register
WEN=0=prohibited
WEN=1=permitted
Write cycle status (READY / BUSY) status confirmation bit
R/B=0=READY
Register
R/B
R/B=1=BUSY
●Write disable block setting
Write disable block
BP1 BP0
BR25H010-W
None
BR25H020-W
None
BR25H040-W
BR25H080-W
None
BR25H160-W BR25H320-W
0
0
1
1
0
1
0
1
None
None
None
60h-7Fh
40h-7Fh
00h-7Fh
C0h-FFh
80h-FFh
00h-FFh
180h-1FFh
100h-1FFh
000h-1FFh
300h-3FFh
200h-3FFh
000h-3FFh
600h-7FFh
400h-7FFh
000h-7FFh
C00h-FFFh
800h-FFFh
000h-FFFh
○
WPB pin
By setting WPB=LOW, write command is prohibited. As for BR25H080, 160, 320-W, only when WPEN bit is set “1”, the WPB
pin functions become valid. And the write command to be disabled at this moment is WRSR. As for BR25H010, 020,040-W,
both WRITE and WRSR commands are prohibited.
However, when write cycle is in execution, no interruption can be made.
Product number
WRSR
WRITE
BR25H010-W
BR25H020-W
BR25H040-W
BR25H080-W
BR25H160-W
BR25H320-W
Prohibition
possible
Prohibition
possible
Prohibition possible
but WPEN bit “1”
Prohibition
impossible
○HOLDB pin
By HOLDB pin, data transfer can be interrupted. When SCK=”1”, by making HOLDB from “1” into”0”, data transfer to
EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted.
6/16
●Command mode
Ope code
BR25H080-W
BR25H040-W BR25H160-W
BR25H320-W
Command
Contents
BR25H010-W
BR25H020-W
WREN Write enable
WRDI Write disable
READ Read
Write enable command
Write disable command 0000
0000
ж110 0000
ж100 0000
ж110
ж100
0000
0000 0100
0011
ж010 0000 A8010 0000 0010
0110
Read command
Write command
Status register read
command
Status register write
command
0000
0000
ж011 0000 A8011 0000
WRITE Write
RDSR Read status register
WRSR Write status register
0000
0000
ж101 0000
ж101
0000 0101
0000 0001
ж001 0000
ж001
●Timing chart
1. Write enable (WREN) / disable (WRDI) cycle
1. WREN (WRITE ENABLE): Write enable
CSB
SCK
SI
0
1
2
3
4
5
6
7
0
0
0
0
*1
1
1
0
High-Z
SO
ж1 BR25H010/020/040-W= Don’t care
BR25H080/160/320-W= “0” input
Fig.33 Write enable command
1. WRDI (WRITE DISABLE): Write disable
CSB
SCK
SI
0
1
2
3
4
5
6
7
0
0
0
0
*1
1
0
0
High-Z
SO
ж1 BR25H010/020/040-W= Don’t care
BR25H080/160/320-W= “0” input
Fig.34 Write disable
○This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is set
to write disable status by write disable command. As for these commands, set CSB LOW, and then input the respective ope
codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks, command becomes
valid.
When to carry out write and write status register command, it is necessary to set write enable status by the write enable
command. If write or write status register command is input in the write disable status, commands are cancelled. And even in
the write enable status, once write and write status register command is executed, it gets in the write disable status. After
power on, this IC is in write disable status.
7/16
2. Read command (READ)
CSB
～～
～～
～～
～～
Product
Address
length
A6-A0
A7-A0
A8-A0
0
1
2
3
4
5
6
7
8
9
10
11
15
16
22
SCK
SI
number
～～
BR25H010-W
BR25H020-W
BR25H040-W
0
0
0
0
*1
0
1
1
A7 A6 A5
A4
A1 A0
～～
～～
～～
～～
High-Z
D7 D6
D2 D1 D0
SO
ж1 BR25H010/020-W=Don’t care
BR25H040-W=A8
Fig.35 Read command (BR25H010/020/040-W)
CSB
SCK
～
～
～～
～～
～～
Product
Address
length
～～
number
0
1
2
3
4
5
6
7
8
12
23
24
30
～～
BR25H080-W
BR25H160-W
BR25H320-W
A9-A0
～～
～～
A10-A0
A11-A0
～～ ж
～～
～～
ж
ж
0
0
0
0
0
0
1
1
A11
A1 A0
～～
SI
～～
～～
High-Z
D7 D6
D2 D1 D0
SO
ж=Don’t Care
Fig.36 Read command (BR25H080/160/320-W)
By read command, data of EEPROM can be read. As for this command, set CSB LOW, then input address after read ope code.
EEPROM starts data output of the designated address. Data output is started from SCK fall of 15/23ж1 clock, and from D7 to D0
sequentially. This IC has increment read function. After output of data for 1 byte (8bits), by continuing input of SCK, data of the
next address can be read. Increment read can read all the addresses of EEPROM. After reading data of the most significant
address, by continuing increment read, data of the most insignificant address is read.
ж1 BR25H010/020/040-W=15 clocks
BR25H080/160/320-W=23 clocks
3. Write command (WRITE)
CSB
～～
～～
～～
～～
Product
Address
length
A6-A0
A7-A0
A8-A0
0
1
2
3
4
5
6
7
8
15
16
22
23
SCK
number
～～
～～
～～
BR25H010-W
BR25H020-W
BR25H040-W
0
0
0
0
ж1
0
1
0
A7
A6
A5
A4
A1
A0
D7 D6
D2
～～
D1
D0
SI
～～
～～
High-Z
SO
ж1 BR25H010/020-W=Don’t care
BR25H040-W=A8
Fig.37 Write command (BR25H010/020/040-W)
CSB
～～
～～
Product
Address
length
～～
number
0
1
2
3
4
5
6
7
8
23
24
30
31
SCK
～～
～～
BR25H080-W
BR25H160-W
BR25H320-W
A9-A0
～～
ж
ж
ж
～～
A10-A0
A11-A0
0
0
0
0
0
0
1
0
A11
A1
A0
D7 D6
D2
～～
D1
D0
SI
High-Z
～～
～～
SO
ж=Don't care
Fig.38 Write command (BR25H080/160/320-W)
By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data after
write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time of tE/W
(Max 5ms). During tE/W, other than status read command is not accepted. Start CSB after taking the last data (D0), and
before the next SCK clock starts. At other timing, write command is not executed, and this write command is cancelled. This
IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without starting CSB, data up to
16/32*1bytes can be written for one tE/W. In page write, the insignificant 4/5ж2 bit of the designated address is incremented
internally at every time when data of 1 byte is input and data is written to respective addresses. When data of the maximum
bytes or higher is input, address rolls over, and previously input data is overwritten.
ж1 BR25H010/020/040-W=16 bytes at maximum
BR25H080/160/320-W=32 bytes at maximum
ж2 BR25H010/020/040-W=Insignificant 4 bits
BR25H080/160/320-W=Insignificant 5 bits
8/16
4. Status register write / read command
CSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ж
ж
ж
ж
ж
ж
ж
0
0
0
0
0
0
1
BP1 BP0
SI
High-Z
SO
ж=Don't care
Fig.39 Status register write command (BR25H010/020/040-W)
CSB
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
bit7
WPEN
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
0
0
1
BP1 BP0
SI
*
*
*
*
*
High-Z
SO
ж=Don't care
Fig.40 Status register write command (BR25H080/160/320-W)
Write status register command can write status register data. The data can be written by this command are 2 bitsж1, that is,
BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As for
this command, set CSB LOW, and input ope code of write status register, and input data. Then, by making CSB HIGH,
EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise, start CSB after taking the last
data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is determined
by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array. (Refer to the write
disable block setting table.) To the write disabled block, write cannot be made, and only read can be made.
*1 3bits including BR25H080/160/320-W WPEN (bit7)
CSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
0
0
0
0
ж
1
0
1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/B
ж=Don’t care
High-Z
WEN
1
1
1
BP1 BP0
SO
1
Fig.41 Status register read command (BR25H010/020/040-W)
CSB
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
1
SI
0
bit7
WPEN
bit6
bit5
bit4
bit3
bit2
bit1
WEN
bit0
R/B
High-Z
0
0
0
BP1 BP0
SO
Fig.42 Status register read command (BR25H080/160/320-W)
9/16
●At standby
○Current at standby
Set CSB “H”, and be sure to set SCK, SI, WPB, HOLDB input “L” or “H”. Do not input intermediate electric potantial.
○Timing
As shown in Fig.43, at standby, when SCK is “H”, even if CSB is fallen, SI status is not read at fall edge. SI status is read at
SCK rise edge after fall of CSB. At standby and at power ON/OFF, set CSB “H” status.
Even if CSB is fallen at SCK=SI=”H”,
SI status is not read at that edge.
CSB
Command start here. SI is read.
SCK
SI
0
1
2
Fig.43 Operating timing
●WPB cancel valid area
WPB is normally fixed to “H” or “L” for use, but when WPB is controlled so as to cancel write status register command and write
command, pay attention to the following WPB valid timing.
While write or write status register command is executed, by setting WPB = “L” in cancel valid area, command can be
cancelled. The area from command ope code before CSB rise at internal automatic write start becomes the cancel valid area.
However, once write is started, any input cannot be cancelled. WPB input becomes Don’t Care, and cancellation becomes
invalid.
SCK
15
16
CSB
tE/W
Ope code
Data
data write time
WPB cancel invalid area
WPB cancel invalid area WPB cancel invalid area
invalid
Fig.44 WPB valid timing (WRSR)
tE/W
Ope code
Address
Data
data write time
WPB cancel invalid area
WPB cancel invalid area
valid
WPB cancel invalid area
invalid
Fig.45 WPB valid timing (WRITE)
●HOLDB pin
By HOLDB pin, command communication can be stopped temporarily. (HOLD status) The HOLDB pin carries out command
communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK=LOW, set the
HOLDB pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To release the
HOLD status, set the HOLDB pin HIGH when SCK=LOW. After that, communication can be restarted from the point before the
HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD status, by starting
A4 address input, read can be restarted. When in HOLD status, leave CSB LOW. When it is set CSB=HIGH in HOLD status,
the IC is reset, therefore communication after that cannot be restarted.
10/16
●Method to cancel each command
○READ
・Method to cancel : cancel by CSB = “H”
Ope code
8 bit
Address
Data
8 bit
8 bit/16bit
Cancel available in all areas of read mode
Fig.46 READ cancel valid timing
○RDSR
・Method to cancel : cancel by CSB = “H”
Data
8 bit
Ope code
8 bit
Cancel available in all
areas of read mode
Fig.47 RDSR cancel valid timing
○WRITE、PAGE WRITE
a：Ope code, address input area.
Address
Data
tE/W
d
Ope code
8bit
Cancellation is available by CSB=”H”
8bit/16bit
8bit
b
b：Data input area (D7~D1 input area)
Cancellation is available by CSB=”H”
a
c
c：Data input area (D0 area)
Fig.48 WRITE cancel valid timing
When CSB is started, write starts.
After CSB rise, cancellation cannot be made by any means.
d：tE/W area.
SCK
SI
Cancellation is available by CSB = “H”. However, when
write starts (CSB is started) in the area c, cancellation
cannot be made by any means. And by inputting on
SCK clock, cancellation cannot be made. In page write
mode, there is write enable area at every 8 clocks.
D7 D6 D5 D4 D3 D2 D1 D0
c
b
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore
write it once again.
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○WRSR
a：From ope code to 15 rise.
14 15
16
17
Cancel by CSB =”H”.
D1
D0
b：From 15 clock rise to 16 clock rise (write enable area).
When CSB is started, write starts.
a
b
c
After CSB rise, cancellation cannot be made by any means.
c：After 16 clock rise.
tE/W
c
Ope code
8 bit
Data
8 bit
Cancel by CSB=”H”. However, when write starts (CSB is started)
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
a
b
Fig.49 WRSR cancel valid timing
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
7
8
9
SCK
○WREN/WRDI
a
b
a：From ope code to 7-th clock rise, cancel by CSB = “H”.
b：Cancellation is not available when CSB is started after 7-th clock.
Ope code
8 bit
a
b
Fig.50 WREN/WRDI cancel valid timing
11/16
●High speed operation
In order to realize stable high speed operations, pay attention to the following input / output pin conditions.
○Input pin pull up, pull down resistance
When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller VOL,
IOL from VIL characteristics of this IC.
○Pull up resistance
VCC-VOLM
･･･①
･･･②
RPU≥
IOLM
VOLM
≤
VILE
Microcontroller
VOLM
“L” output
IOLM
EEPROM
VILE
Example) When Vcc=5V, VILE=1.5V, VOLM=0.4V, IOLM=2mA,
from the equation ①,
“L” input
5-0.4
2×10-3
RPU≥
Fig.51 Pull up resistance
∴RPU
≥
2.3[kΩ]
With the value of Rpu to satisfy the above equation, VOLM
becomes 0.4V or higher, and with VILE (=1.5V), the equation ② is
also satisfied.
・VILE :EEPROM VIL specifications
・VOLM :Microcontroller VOL specifications
・IOLM :Microcontroller IOL specifications
And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CSB pull up.
○Pull down resistance
VOHM
Microcontroller
VOHM
EEPROM
VIHE
･･･③
･･･④
RPD
≥
IOHM
VOHM
≥
VIHE
“H” output
“H” input
IOHM
Example) When VCC=5V, VOHM=VCC-0.5V, IOHM＝0.4mA,
VIHE=VCC×0.7V, from the equation③,
Fig.52 Pull down resistance
5-0.5
0.4×10-3
RPD≥
∴RPU
≥
11.3[kΩ]
Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude of
VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC /
0.2Vcc is input, operation speed becomes slow.
12/16
In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as possible,
and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level.
(ж1 At this moment, operating timing guaranteed value is guaranteed.)
tPD-VIL characteristics
80
70
60
50
40
30
20
10
0
Vcc=2.5V
Ta=25
℃
VIH=Vcc
CL=100pF
0
0.2
0.4
0.6
0.8
1
VIL[V]
Fig.53 VIL dependency of
data output delay time
○SO load capacity condition
Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLDB to
High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, “Do not
connect many devices to SO bus”, “Make the wire between the controller and EEPROM short”, and so forth.
tPD-CL characteristics
80
ꢀ
℃
Vcc=2.5V Ta=25
70
60
50
40
30
20
VIH/VIL=0.8Vcc/0.2Vcc
EEPROM
SO
CL
0
20
40
60
80
100
120
CL[V]
Fig.54 SO load dependency of data output delay time
○Other cautions
Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold violation
to EEPROM, owing to difference of wire length of each input.
13/16
●Equivalent circuit
○Output circuit
SO
OEint.
Fig.55 SO output equivalent circuit
○Input circuit
RESETint.
CSB
Fig.56 CSB input equivalent circuit
SCK
SI
Fig.57 SCK input equivalent circuit
Fig.58 SI input equivalent circuit
HOLDB
WPB
Fig.59 HOLDB input equivalent circuit
Fig.60 WPB input equivalent circuit
14/16
●Notes on power ON/OFF
○At power ON/OFF, set CSB “H” (=Vcc).
When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction,
mistake write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all inputs are canceled.)
Vcc
Vcc
GND
Vcc
CSB
GND
Good Example
Bad example
Fig.61 CSB timing at power ON/OFF
(Good example) CSB terminal is pulled up to Vcc.
At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition, the IC internal
circuit may not be reset, which please note.
(Bad example)
CSB terminal is “L” at power ON/OFF.
In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction, mistake write owing to
noises and the likes.
Even when CSB input is High-Z, the status becomes like this case, which please note.
○LVCC circuit
LVCC (Vcc-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.9V) or below, it prevent data rewrite.
○P.O.R. circuit
This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR
circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the
following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes.
Recommended conditions of tR, tOFF, Vbot
tR
Vcc
tR
tOFF
Vbot
10ms or below
100ms or below
10ms or higher
10ms or higher
0.3V or below
0.2V or below
tOFF
Vbot
0
Fig.62 Rise waveform
●Noise countermeasures
○Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a
bypass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
○SCK noise
When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement.
To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about 0.2V, if noises exist at SCK input,
set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise
time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible.
○WPB noise
During execution of write status register command, if there exist noises on WPB pin, mistake in recognition may occur and forcible
cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WPB input. In the same manner, a Schmitt trigger
circuit is built in SI input and HOLDB input too.
●Cautions on use
(1)Described numeric values and data are design representative values, and the values are not guaranteed.
(2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by
changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and
fluctuations of external parts and our LSI.
(3)Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed. Do not impress
voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety
countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4)GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.
(5)Heat design
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
(6)Terminal to terminal short circuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit
between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed.
(7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
15/16
●Selection of order type
2 5
H
0 1 0
W
E 2
F
B R
Capacity
010= 1K
020= 2K
040= 4K
080= 8K
160=16K
320=32K
Package type
F: SOP8
FJ: SOP-J8
Package specifications
E2：reel shape emboss taping
Rohm type
name
Operating temperature
H :-40℃～+125℃
BUS type
25: SPI
Double cell
●Package specifications
SOP8/SOP-J8
<External appearance>
<Package specifications> SOP8/SOP-J8
Package type
Emboss taping
・SOP8
・SOP-J8
Package quantity
Package direction
2500pcs
E2
4.9 0.2
5.0 0.2
8
7
6
5
8
5
4
(When the reel gripped by the left hand, and the tape is
pulled out by the right hand, No.1 pin of product is at the
left top.)
1
2
3
4
0.2 0.1
0.1
1
0.15 0.1
0.1
1.27
0.42 0.1
1.27
Pulling side
Pin No.1
Reel
*For ordering, specify a number of multiples of the package quantity.
0.4 0.1
(Unit:mm)
16/16
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
THE AMERICAS / EUPOPE / ASIA / JAPAN
ROHM Customer Support System
Contact us : webmaster@ rohm.co.jp
www.rohm.com
TEL : +81-75-311-2121
FAX : +81-75-315-0172
Copyright © 2007 ROHM CO.,LTD.
21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
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SI9137DB
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