BR25H040FVT-WE2 [ROHM]

EEPROM, 512X8, Serial, CMOS, PDSO8, LEAD FREE, TSSOP-8;


型号：	BR25H040FVT-WE2
厂家：	ROHM
描述：	EEPROM, 512X8, Serial, CMOS, PDSO8, LEAD FREE, TSSOP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总17页 (文件大小：1138K)
中文：	中文翻译
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TECHNICAL NOTE

HIGH GRADE Specification HIGH RELIABILITY series

SPI BUS Serial EEPROMs

Supply voltage 1.8V~5.5V

Operating temperature –40°C~+85°C type

BR25L010-W, BR25L020-W, BR25L040-W, BR25L080-W, BR25L160-W, BR25L320-W, BR25L640-W

Description

●

BR25L-W series is a serial EEPROM of SPI BUS interface method.

Features

y High speed clock action up to 5MHz (Max.)

y Wait function by HOLD terminal

y Part or whole of memory arrays settable as read only memory area by program

y 1.8 ~ 5.5V single power source action most suitable for battery use

y Page write mode useful for initial value write at factory shipment

y Highly reliable connection by Au pad and Au wire

y For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1)

y Auto erase and auto end function at data rewrite

y Low current consumption

At write action (5V)

At read action (5V)

At standby action (5V) : 0.1µA (Typ.)

: 1.5mA (Typ.)

: 1.0mA (Typ.)

Page write

Number of

pages

y Address auto increment function at read action

y Write mistake prevention function

16 Byte

32 Byte

BR25L080-W

BR25L160-W

BR25L320-W

BR25L640-W

Write prohibition at power on

Write prohibition by command code (WRDI)

Write prohibition by WP pin

BR25L010-W

BR25L020-W

BR25L040-W

Product

number

Write prohibition block setting by status registers (BP1, BP0)

Write mistake prevention function at low voltage

y SOP8, SOP-J8, SSOP-B8, TSSOP-B8, MSOP8 TSSOP-B8J package *1 *2

y DataꢀatꢀshipmentꢀꢀMemoryꢀarrayꢀ:ꢀFFh,ꢀstatusꢀregisterꢀWPEN,ꢀBP1,ꢀBP0ꢀ:ꢀ0

y Data kept for 40 years

y Data rewrite up to 1,000,000 times

*1 BR25L080/160-W : SOP8, SOP-J8, SSOP-B8, TSSOP-B8

*2 BR25L320/640-W : SOP8, SOP-J8

BR25L series

Power source

Capacity

1Kbit

Bit format

128 × 8

256 × 8

512 × 8

1K × 8

Type

SOP8

SOP-J8

SSOP-B8

TSSOP-B8

MSOP8

TSSOP-B8J

voltage

BR25L010-W

BR25L020-W

BR25L040-W

BR25L080-W

1.8 ~ 5.5V

2Kbit

1.8 ~ 5.5V

4Kbit

8Kbit

16Kbit

32Kbit

64Kbit

2K × 8

4K × 8

8K × 8

BR25L160-W

BR25L320-W

BR25L640-W

1.8 ~ 5.5V

Ver.B Oct.2005

Recommended action conditions

Absolute maximum ratings (Ta = 25˚C)

Parameter

Power source voltage

Input voltage

Symbol

VCC

Limits

1.8 ~ 5.5

0 ~ VCC

Unit

Parameter

Symbol

VCC

Unit

Limits

Impressed voltage

0.3 ~ +6.5

Vin

450(SOP8)

450(SOP-J8)

300(SSOP-B8)

Memory cell characteristics (Ta=25˚C, VCC=1.8 ~ 5.5V)

Permissible

dissipation

Limits

Parameter

Unit

Min.

1,000,000

Typ.

–

Max.

330(TSSOP-B8

)

Number of data rewrite times

–

Times

Years

310(MSOP8)

Data hold years

310(TSSOP-B8J) ^*6

*1:Not 100% TESTED

Storage

temperature range

Operating

temperature range

˚C

Tstg

Topr

–

65 ~ +125

Input / output capacity (Ta=25˚C, frequency=5MHz)

40 ~ +85

Terminal voltage

0.3 ~ VCC+0.3

Parameter

Input capacity

Output capacity

Symbol Conditions

Min.

–

Max.

Unit

CIN

VIN=GND

yWhen using at Ta = 25˚C or higher, 4.5mW (*1, *2), 3.0mW (*3),

3.3mW(*4), 3.1mW (*5, *6) to be reduced per 1˚C

COUT

VOUT=GND

*1:Not 100% TESTED

Electrical characteristics (Unless otherwise specified, Ta = –40 ~ +85˚C, VCC = 1.8 ~ 5.5V)

Limits

Typ.

Parameter

"H" input voltage 1

"L" input voltage 1

Symbol

VIH1

Unit

Conditions

Min.

Max.

0.7x

VCC

+0.3

–

1.8≤VCC≤5.5V

0.3x

VCC

VIL1

-0.3

–

IOL 2.1mA(VCC 2.5V ~ 5.5V)

"L" output voltage 1

"L" output voltage 2

VOL1

VOL2

–

0.4

0.2

IOL 150µA(VCC 1.8V ~ 2.5V)

VCC

"H" output voltage 1

"H" output voltage 2

VOH1

VOH2

IOH

0.4mA(VCC 2.5V ~ 5.5V)

–

-0.5

VCC

100µA(VCC 1.8V ~ 2.5V)

-0.2

ILI

µA

Input leak current

–

VIN 0 ~ VCC

Output leak current

ILO

-1

VOUT 0 ~ VCC,CS VCC

VCC 1.8V,fSCK 2MHz,tE/W 5ms

Byte write

Page write

Write status register

1.0

2.0

ICC1

ICC2

–

VCC 2.5V,fSCK 5MHz,tE/W 5ms

Byte write

Page write

Current consumption at write

action

–

Write status register

VCC 5.5V,fSCK 5MHz,tE/W 5ms

Byte write

Page write

Write status register

–

3.0

1.5

ICC3

ICC4

–

VCC 2.5V,fSCK 5MHz

Read

Read status register

Current consumption at read

action

VCC 5.5V,fSCK 5MHz

Read

Read status register

–

2.0

–

ICC5

ISB

CC 5.5V

µA

Standby current

CS HOLD WP VCC,SCK SI VCC or GND,SO=OPEN

• Radiation resistance design is not made.

Block diagram

VOLTAGE

DETECTION

INSTRUCTION DECODE

CONTROL CLOCK

GENERATION

WRITE

HIGH VOLTAGE

GENERATOR

SCK

INHIBITION

INSTRUCTION

STATUS REGISTER

ADDRESS

DECODER

*1 7bit : BR25L010-W

8bit : BR25L020-W

9bit : BR25L040-W

10bit : BR25L080-W

11bit : BR25L160-W

12bit : BR25L320-W

13bit : BR25L640-W

7~13bit *1

8bit

HOLD

7~13bit *1

8bit

1K~64K

EEPROM

READ/WRITE

AMP

DATA

Fig.1 Block diagram

2/16

Pin assignment and description

Terminal name Input/output

Function

Power source to be connected

VCC

–

VCC

HOLD SCK

GND

SCK

–

Input

All input / output reference voltage, 0V

Chip select input

BR25L010-W

BR25L020-W

BR25L040-W

BR25L080-W

BR25L160-W

BR25L320-W

BR25L640-W

Input

Serial clock input

Start bit, ope code, address, and serial data input

Output Serial data output

Hold input

Input

HOLD

Command communications may be suspended temporarily (HOLD status).

Write protect input

Write command is prohibited.^*1

Write status register command is prohibited.

Input

GND

Fig. 2 Pin assignment diagram

*1:BR25L010/020/040-W

Sync data input / output timing

Operating timing characteristics

(Ta = -40 ~ +85˚C, unless otherwise specified, load capacity CL1 100pF)

tCS

tCSS

1.8≤VCC<2.5V

2.5≤VCC<5.5V

Parameter

Symbol

Unit

tSCKS

Min. Typ. Max. Min. Typ. Max.

tRC

tFC

tSCKWL

tSCKWH

SCK frequency

SCK high time

SCK low time

CS high time

fSCK

–

MHz

SCK

tDIS tDIH

tSCKWH 200

tSCKWL 200

–

tCS

tCSS

tCSH

tSCKS

tSCKH

tDIS

200

High-Z

CS setup time

CS hold time

Fig. 3 Input timing

SI is taken into IC inside in sync with data rise edge of SCK. Input

address and data from the most significant bit MSB.

SCK setup time

SCK hold time

SI setup time

SI hold time

tCS

tDIH

–

150

–

tSCKH

tCSH

Data output delay time 1

tPD1

–

Data output delay time 2

(CL2=30pF)

SCK

tPD2

–

145

–

Output hold time

tOH

tOZ

–

250

–

100

tPD

tOZ

tRO,tFO

tOH

High-Z

Output disable time

HOLD setting

setup time

tHFS

tHFH

tHRS

tHRH

tHOZ

tHPD

tRC

120

140

–

µs

Fig. 4 Input / output timing

HOLD setting

hold time

SO is output in sync with data fall edge of SCK. Data is output

from the most significant bit MSB.

HOLD release

setup time

"H"

–

"L"

tHFS tHFH

tHRS tHRH

HOLD release

hold time

–

SCK

tDIS

Time from HOLD

to output High-Z

n+1

n-1

250

150

100

tHOZ

tHPD

High-Z

Dn+1

Dn-1

Time from HOLD

to output change

–

HOLD

SCK

rise time

–

Fig. 5 HOLD timing

SCK

fall time

tFC

–

OUTPUT

rise time

tRO

–

100

–

OUTPUT

fall time

tFO

–

100

–

Write time

tE/W

*1NOT 100% TESTED

AC measurement conditions

Parameter

Limits

Symbol

Unit

Min. Typ. Max.

Load capacity 1

Load capacity 2

Input rise time

C^L1

CL2

–

100

Input fall time

Input voltage

0.2VCC/0.8VCC

0.3VCC/0.7VCC

Input / output judgment voltage

–

3/16

Characteristic data (The following characteristic data are Typ. values.)

0.8

0.6

0.4

0.2

Ta=85˚C

Ta=25˚C

Ta=85˚C

Ta=25˚C

SPEC

Ta=-40˚C

SPEC

Ta=85˚C

Ta=25˚C

Ta=

40˚C

SPEC

Ta=-40˚C

VCC[V]

IOL[mA]

VCC[V]

Fig.6 "H" input voltage VIH(CS,SCK,SI,HOLD,WP)

Fig.7 "L" input voltage VIL(CS,SCK,SI,HOLD,WP)

Fig.8 "L" output voltage VOL-IOL(VCC=1.8V)

2.6

2.4

2.2

Ta=-40˚C

0.8

1.8

1.6

1.4

1.2

0.6

0.4

0.2

Ta=25˚C

Ta=85˚C

Ta=25˚C

Ta=85˚C

SPEC

Ta=85˚C

Ta=25˚C

SPEC

Ta=

-40˚C

1.8

0.4

IOH[mA]

0.8

0.4

IOH[mA]

0.8

IOL[mA]

Fig.9 "H" output voltage VOH-IOH(VCC=1.8V)

Fig.10 "L" output voltage VOL-IOL(VCC=2.5V)

Fig.11 "H" output voltage VOH-IOH(VCC=2.5V)

CC=2.5V 2mA

CC=5.5V 3mA

1.2

SPEC

fSCK=5MHz

DATA=55h

SPEC

0.8

0.4

0.2

0.8

0.6

0.4

0.2

SPEC

Ta=25˚C

Ta=-40˚C

Ta=85˚C

Ta=25˚C

Ta=85˚C

Ta=25˚C

Ta=

40˚C

Ta=

40˚C

Ta=85˚C

VCC[V]

Fig.12 Input leak current ILI(CS,SCK,SI,WP,HOLD)

Fig.13 Output leak current ILO(SO)

Fig.14 Current consumption at WRITE operation

ICC1,2,3(WRITE,PAGE WRITE,WRSR,fSCK=5MHz)

BR25L010-W,BR25L020-W,BR25L040-W

Vcc=2.5V 1.5mA

Vcc=5.5V 2.0mA

2.5

100

Ta=25˚C

fSCK=5MHz

Ta=-

40˚C

SPEC

DATA=55h

SPEC

Ta=85˚C

Ta=

-40˚C

1.5

Ta=25˚C

SPEC

Ta=85˚C

Ta=25˚C

Ta= 40˚C

Ta=85˚C

0.5

0.1

VCC[V]

Fig.15 Consumption current at READ operation

ICC4,5(READ,WRSR,fSK=5MHz)

Fig.16 Consumption current at standby operation ISB

Fig.17 SCK frequency fSCK

250

200

150

100

SPEC

200

150

100

200

150

SPEC

100

SPEC

Ta=-40˚C

Ta=25˚C

Ta=85˚C

Ta=-40˚C

Ta=85˚C

Ta=25˚C

Ta=

40˚C

Ta=25˚C

Ta=85˚C

VCC[V]

Fig.18 tSCK high time tSCKWH

Fig.19 SCK low time tSCKWL

Fig.20 CS high time tCS

4/16

250

200

150

100

250

200

150

100

SPEC

Ta=25˚C

Ta=85˚C

Ta=25˚C

Ta=-40˚C

-20

-40

Ta=

40˚C

Ta=-40˚C Ta=25˚C

[ ]

VCC V

[ ]

CC V

[ ]

CC V

CS setup time

Fig.22 CS hold time tCSH

SI setup time

Fig.23 tDIS

Fig.21

tCSS

200

150

100

200

150

100

SPEC

Ta=85˚C

SPEC

Ta=85˚C

Ta=-40˚C

SPEC

Ta=

40˚C

Ta=25˚C

Ta=

40˚C

[

[ ]

CC V

[

]

Fig.24 SI hold time tDIH

Fig.25 Data output delay time tPD1(CL 100pF)

Fig.26 Data output delay time tPD2(CL 30pF)

150

120

300

250

200

150

100

140

120

100

SPEC

Ta=85˚C

Ta=25˚C

Ta=

-40˚C

Ta=25˚C

Ta=

40˚C

Ta=-40˚C

-20

-30

[

CC V

]

[ ]

VCC[V]

Fig.27 Output disable time tOZ

Fig.28 HOLD setting hold time tHFH

Fig.29 HOLD release hold time tHRH

160

120

300

250

200

SPEC

150

100

SPEC

Ta=85˚C

Ta=25˚C

Ta=85˚C

Ta=25˚C

Ta=85˚C

Ta=25˚C

Ta=-40˚C

Ta=

-40˚C

Ta=-40˚C

-40

[

]

[ ]

VCC V

[ ]

CC V

Fig.30 Time from HOLD to output High-Z tHOZ

Fig.31 Time from HOLD to output change tHPD

Fig.32 Output rise time tRO

120

SPEC

Ta=-40˚C

Ta=85˚C

Ta=25˚C

Ta=85˚C

Ta=

-40˚C

[ ]

VCC V

Fig.33 Output fall time

Fig.34 Write cycle time tE/W

5/16

Features

Status registers

This IC has status registers. The status registers are of 8 bits and express the following parameters.

BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are

valid even when power source is turned off.

Rewrite characteristics and data hold time are same as characteristics of the EEPROM.

WEN can be set by write enable command and write disable command. WEN becomes write disable status when power

source is turned off. R/B is for write confirmation, therefore cannot be set externally.

The value of status register can be read by read status command.

Status registers

Product number

BR25L010-W

BR25L020-W

BR25L040-W

BR25L080-W

BR25L160-W

BR25L320-W

BR25L640-W

bit 7

bit 6

bit 5

bit 4

bit 3

BP1

bit 2

BP0

bit 1

bit 0

WEN

R/B

WPEN

BP1

BP0

WEN

R/B

Memory

location

bit

Function

Contents

WP pin enable / disable designation bit

This enables / disables the functions

of WP pin.

WPEN EEPROM

WPEN = 0 = invalid

WPEN = 1 = valid

This designates the write disable area

of EEPROM. Write designation areas

of product numbers are shown below.

BP1

EEPROM

BP0

EEPROM write disable block designation bit

Write and write status register write enable / disable status confirmation bit

WEN

WEN = 0 = prohibited

WEN = 1 = permitted

Write cycle status (READY / BUSY) status confirmation bit

R/B

= =

R/B 0 READY

R/B 1 BUSY

Write disable block setting

Write disable block

BR25L010-W BR25L020-W BR25L040-W BR25L080-W BR25L160-W BR25L320-W BR25L640-W

BP1

BP0

None

60h-7Fh

40h-7Fh

00h-7Fh

C0h-FFh

80h-FFh

00h-FFh

180h-1FFh

100h-1FFh

000h-1FFh

300h-3FFh

200h-3FFh

000h-3FFh

600h-7FFh

400h-7FFh

000h-7FFh

C00h-FFFh

800h-FFFh

000h-FFFh

1800h-1FFFh

1000h-1FFFh

0000h-1FFFh

WP pin

By setting WP = LOW, write command is prohibited. As for BR25L080, 160, 320, 640-W, only when WPEN bit is set "1",

the WP pin functions become valid. And the write command to be disabled at this moment is WRSR. As for BR25L010,

020, 040-W, both WRITE and WRSR commands are prohibited.

However, when write cycle is in execution, no interruption can be made.

Product number

BR25L010-W

BR25L020-W

BR25L040-W

BR25L080-W

BR25L160-W

BR25L320-W

BR25L640-W

WRSR

WRITE

Prohibition

possible

Prohibition

possible

Prohibition

possible but

WPEN bit "1"

Prohibition

impossible

HOLD pin

By HOLD pin, data transfer can be interrupted. When SCK = "1", by making HOLD from "1" into "0", data transfer to

EEPROM is interrupted. When SCK = "0", by making HOLD from "0" into "1", data transfer is restarted.

6/16

Command mode

Ope code

BR25L080-W

BR25L160-W

BR25L320-W

BR25L640-W

Command

Contents

BR25L010-W

BR25L020-W

BR25L040-W

WREN Write enable

WRDI Write disable

READ Read

Write enable command 0000 * 110

0000

* 110 0000 0110

Write disable command 0000 * 100 0000 * 100 0000 0100

Read command

Write command

0000 * 011 0000 A8011 0000 0011

0000 * 010 0000 A8010 0000 0010

WRITE Write

Status register read

command

RDSR

Read status register

0000 * 101 0000 * 101 0000 0101

0000 * 001 0000 * 001 0000 0001

Status register write

command

WRSR Write status register

Timing chart

1. Write enable (WREN) / disable (WRDI) cycle

1.WREN (WRITE ENABLE) : Write enable

SCK

* 1

High-Z

Don't care

*1 BR25L010/020/040-W=

BR25L080/160/320/640-W=

Fig. 35 Write enable command

“0” input

1.WRDI (WRITE DISABLE) : Write disable

SCK

* 1

High-Z

Don't care

-W=

*1 BR25L010/020/040

BR25L080/160/320/640

Fig. 36 Write disable

“0” input

-W=

This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is

set to write disable status by write disable command. As for these commands, set CS LOW, and then input the respective

ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks, command

becomes valid.

When to carry out write and write status register command, it is necessary to set write enable status by the write enable

command. If write or write status register command is input in the write disable status, commands are cancelled. And even

in the write enable status, once write and write status register command is executed once, it gets in the write disable

status. After power on, this IC is in write disable status.

7/16

2. Read command (READ)

Product

number

Address

length

SCK

A6-A0

A7-A0

A8-A0

BR25L010-W

BR25L020-W

BR25L040-W

* 1

High-Z

D7 D6

* 1 BR25L010/020-W Don't care

Fig. 37 Read command (BR25L010/020/040-W)

BR25L040-W A8

Product

number

Address

length

SCK

A9-A0

A10-A0

A11-A0

A12-A0

BR25L080-W

BR25L160-W

BR25L320-W

BR25L640-W

A12

High-Z

* =

Don't care

Fig. 38 Read command (BR25L080/160/320/640-W)

By read command, data of EEPROM can be read. As for this command, set CS LOW, then input address after read ope

code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 15/23^*1clock, and

from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8 bits), by continuing input

of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data

of the most significant address, by continuing increment read, data of the most insignificant address is read.

* 1 BR25L010/020/040-W 15 clocks

* =

Don't care

BR25L080/160/320/640-W 23 clocks

3. Write command (WRITE)

Product

number

Address

length

22 23

SCK

A6-A0

A7-A0

A8-A0

BR25L010-W

BR25L020-W

BR25L040-W

A7 A6 A5 A4

A0 D7 D6

D2 D1 D0

* 1

High-Z

* 1 BR25L010/020-W Don't care

Fig.39 Write command (BR25L010/020/040-W)

BR25L040-W A8

Product

number

Address

length

SCK

A9-A0

A10-A0

A11-A0

A12-A0

BR25L080-W

BR25L160-W

BR25L320-W

BR25L640-W

A12

A0 D7 D6

D2 D1 D0

High-Z

* =

Don't care

Fig.40 Write command (BR25L080/160/320/640-W)

By write command, data of EEPROM can be written. As for this command, set CS LOW, then input address and data

after write ope code. Then, by making CS HIGH, the EEPROM starts writing. The write time of EEPROM requires time of

tE/W (Max 5ms). During tE/W, other than status read command is not accepted. Start CS after taking the last data (D0),

and before the next SCL clock starts. At other timing, write command is not executed, and this write command is

cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without

starting CS, data up to 16/32^*1bytes can be written for one tE/W. In page write, the insignificant 4/5^*2bit of the

designated address is incremented internally at every time when data of 1 byte is input, and data is written to respective

addresses. When data of the maximum bytes or higher is input, address rolls over, and previously input data is

overwritten.

* 1 BR25L010/020/040-W 16 bytes at maximum

BR25L080/160/320/640-W 32 bytes at maximum

* 2 BR25L010/020/040-W Insignificant 4 bits

BR25L080/160/320/640-W Insignificant 5 bits

8/16

4. Status register write / read command

12 13

SCK

bit7

bit6

bit5

bit4

bit3 bit2

bit1

bit0

BP1 BP0

High Z

* =

Don't care

Fig.41 Status register write command (BR25L010/020/040-W)

SCK

bit7

bit6 bit5

bit4

bit3

bit2

bit1

bit0

WPEN

BP1 BP0

High Z

* =

Don't care

Fig.42 Status register write command (BR25L080/160/320/640-W)

Write status register command can write status register data. The data the can be written by this command are 2 bits *1,

that is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be

set. As for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS

HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking the

last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is

determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array.

(Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be

made.

* 3 bits including BR25L080, 160, 320, 640-W WPEN (bit7)

SCK

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

High Z

BP1 BP0 WEN R/B

* =

Don't care

Fig.43 Status register read command (BR25L010/020/040-W)

SCK

bit7

WPEN

bit6

bit5

bit4

bit3

bit2

bit1

bit0

High Z

BP1 BP0 WEN R/B

Fig.44 Status register read command (BR25L080/160/320/640-W)

9/16

At standby

Current at standby

Set CS "H", and be sure to set SCK, SI, WP, HOLD input "L" or "H". Do not input intermediate electric potential.

Timing

As shown in Fig. 45, at standby, when SCK is "H", even if CS is fallen, SI status is not read at fall edge. SI status is read

at SCK rise edge after fall of CS. At standby and at power ON/OFF, set CS "H" status.

Even if CS is fallen at SCL = SI = "H",

SI status is not read at that edge.

Command start here. SI is read.

SCK

Fig.45 Operating timing

WP cancel valid area

WP is normally fixed to "H" or "L" for use, but when WP is controlled so as to cancel write status register command and write

command, pay attention to the following WP valid timing.

While write or write status register command is executed, by setting WP = "L" in cancel valid area, command can be

cancelled. The area from command ope code before CS rise at internal automatic write start becomes the cancel valid area.

However, once write is started, any input cannot be cancelled. WP input becomes Don't Care, and cancellation becomes

invalid.

SCK

tE/W

data write time

Ope code

Data

WP cancel invalid area WP cancel invalid area

invalid

WP cancel invalid area

Fig.46 WP valid timing (WRSR)

tE/W

data write time

Ope code

Address

Data

WP cancel invalid area

invalid

WP cancel invalid area

valid

WP cancel invalid area

Fig.47 WP valid timing (WRITE)

HOLD pin

By HOLD pin, command communication can be stopped temporarily. (HOLD status) The HOLD pin carries out command

communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK = LOW, set

the HOLD pin LOW. At HOLD status, SCK and SI become Don't Care, and SO becomes high impedance (High-Z). To

release the HOLD status, set the HOLD pin HIGH when SCK = LOW. After that, communication can be restarted from the

point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of

HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CS LOW. When it is set

CS = HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted.

10/16

Method to cancel each command

READ

Ope code

8 bits

Address

Data

y Method to cancel : cancel by CS = "H"

8 bits /16bits

8 bits

Cancel available in all areas of read mode

Fig.48 READ cancel valid timing

RDSR

Ope code

8 bits

Data

y Method to cancel : cancel by CS = "H"

8 bits

Cancel available in all

areas of read mode

Fig.49 RDSR cancel valid timing

WRITE, PAGE WRITE

a : Ope code, address input area.

Cancellation is available by CS = "H".

b : Data input area (D7 ~ D1 input area)

Cancellation is available by CS = "H".

c : Data input area (D0 area)

Ope code

8 bits

Address

Data (n)

tE/W

8 bits

Fig.50 WRITE cancel valid timing

When CS is started, write starts.

After CS rise, cancellation cannot be made by any

means.

d : tE/W area

SCK

Cancellation is available by CS = "H". However, when

write starts (CS is started) in the area c, cancellation

cannot be made by any means. And, by inputting on

SCK clock, cancellation cannot be made. In page write

mode, there is write enable area at every 8 clocks.

SI D7

Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once

again.

Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,

therefore, it is recommended to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS / tCSH or higher.

SCK

WRSR

a : From ope code to 15 clock rise

Cancel by CS = "H".

SI D1

b : From 15 clock rise to 16 clock rise (write enable area)

When CS is started, write starts.

After CS rise, cancellation cannot be made by any

means.

Ope code

8 bit

Address

8 bit

tE/W

c : After 16 clock rise

Cancel by CS = "H". However, when write starts (CS is

started) in the area b, cancellation cannot be made by

any means. And, by inputting on SCK clock, cancellation

cannot be made.

Fig.51 WRSR cancel valid timing

Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once

again.

Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,

therefore, it is recommended to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS/tCSH or higher.

WREN/WRDI

SCK

a : From ope code to clock rise, cancel by CS = "H".

b : Cancellation is not available when CS is started after 7 clock.

Ope code

8 bit

Fig.52 WREN / WRDI cancel valid timing

11/16

High speed operation

In order to realize stable high speed operations, pay attention to the following input / output pin conditions.

Input pin pull up, pull down resistance

When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller

VOL, IOL from VIL characteristics of this IC.

Pull up resistance

VCC

-VOLM

RPU ≥

IOLM

VOLM ≤

VILE

Microcontroller

I^OHM

EEPROM

VOLM

VILE

Example) When Vcc = 5V, VILM = 1.5V, VOLM = 0.4V, IOLM = 2mA,

from the equation

"L" output

"L" input

-0.4

RPU≥

2 × 10^-3

Fig.53 Pull up resistance

2.3[k

]

With the value of Rpu to satisfy the above equation, VOLM

becomes 0.4V or higher, and with VILE (= 1.5V), the equation

is also satisfied.

y V^ILM: EEPROM VIH specifications

y V^OLM: Microcontroller VOL specifications

y I^OLM: Microcontroller IOL specifications

And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CS pull up.

Pull down resistance

VOHM

IOHM

EEPROM

RPD ≥

VOHM

VIHE

VOHM ≥

VIHE

IOHM

Example) When Vcc = 5V, VOHM = Vcc - 0.5V, IOHM = 0.4mA,

VIHM = Vcc × 0.7V, from the equation

Fig.54 Pull down resistance

0.5

RPD≥

0.4 × 10^-3

11.3[k

]

Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude of

VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC /

0.2VCC is input, operation speed becomes slow.

12/16

In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as

possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level.

(*1 At this moment, operating timing guaranteed value is guaranteed.)

tPD-VIL characteristics

VCC 1.8V

Ta 25°C

VIH VCC

CL 100pF

0.2

0.4

0.6

VIL[V]

0.8

Fig.55 VIL dependency of

data output delay time

SO load capacity condition

Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLD

to High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, "Do

not connect many devices to SO bus", "Make the wire between the controller and EEPROM short", and so forth.

tPD-CL characteristics

V^CC1.8V Ta 25°C

VIH/VIL 0.8V^CC/0.2VCC

EEPROM

100

120

CL [V]

Fig.56 SO load dependency of data output delay time

Other cautions

Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold violation

to EEPROM, owing to difference of wire length of each input.

13/16

Equivalent circuit

Output circuit

OEint.

Fig.57 SO output equivalent circuit

Input circuit

RESETint.

Fig.58 CS input equivalent circuit

SCK

Fig.59 SCK input equivalent circuit

Fig.60 SI input equivalent circuit

HOLD

Fig.61 HOLD input equivalent circuit

Fig.62 WP input equivalent circuit

14/16

Notes on power ON/OFF

At power ON/OFF, set CS "H" (= VCC).

When CS is "L", this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause

malfunction, mistake write or so. To prevent these, at power ON, set CS "H". (When CS is in "H" status, all inputs are canceled.)

Vcc

GND

Vcc

GND

Bad example

Good example

Fig.63 CS timing at power ON/OFF

(Good example) CS terminal is pulled up to VCC.

At power OFF, take 10ms or higher before re supply. If power is turned on without observing this condition, the IC internal

circuit may not be reset, which please note.

(Bad example)

PORcircuit

CS terminal is "L" at power ON/OFF.

In this case, CS always becomes "L" (active status), and EEPROM may have malfunction, mistake write owing to noises

and the likes.

Even when CS input is High-Z, the status becomes like this case, which please note.

This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR

circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the

following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes.

V^CC

Recommended conditions of tR, tOFF, Vbot

tOFF

Vbot

10ms or below 10ms or higher 0.3V or below

100ms or below 10ms or higher 0.2V or below

tOFF

Vbot

Fig.64ꢀꢀRiseꢀwaveform

Noise countermeasures

Vcc noise (bypass capacitor)

When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a

by pass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.

And, it is also recommended to attach a bypass capacitor between board Vcc and GND.

SCK noise

When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement.

To avoid this, a Schmitt trigger circuit is built in SCK input. The hysteresis width of this circuit is set about 0.2V, if noises exist at SCK input,

set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise

time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible.

WP noise

During execution of write status register command, if there exist noises on WP pin, mistake in recognition may occur and forcible cancellation

may result, which please note. To avoid this, a Schmitt trigger circuit is built in WP input. In the same manner, a Schmitt trigger circuit is

built in SI input and HOLD input too.

Cautions on use

(1) Described numeric values and data are design representative values, and the values are not guaranteed.

(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case

of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics

and transition characteristics and fluctuations of external parts and our LSI.

(3) Absolute maximum ratings

If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed.

Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum

ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should

not be impressed to LSI.

(4) GND electric potential

Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.

(5) Heat design

In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.

(6) Terminal to terminal short circuit and wrong packaging

When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in

the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be

destructed.

(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.

15/16

Selection of order type

B R

2 5

0 1 0

F - W E 2

Double cell

Rohm type BUS type Operating temperature Capacity Package type

Package specifications

name

25:SPI

1 K

2 K

4 K

010=

020=

040=

080=

160=

320=

640=

L −40℃〜＋85℃

F SOP8

E2 : reel shape emboss taping

TR : reel shape emboss taping

(MSOP8 package only)

FJ SOP-J8

ꢀ

Hꢀ −40℃〜＋125℃

FV SSOP-B8

8 K

FVT :TSSOP-B8

16K

32K

64K

FVM MSOP8

FVJ : TSSOP-B8J

Package specifications

SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J

<Package specifications>SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J

Package type

Emboss taping

• SOP8

• SOP-J8

• SSOP-B8

• TSSOP-B8 • TSSOP-B8J

Package quantity

Package direction

2500pcs

3.0±0.2

3.0±0.1

4.9±0.2

5.0±0.2

(When the reel is gripped by the left hand, and the tape is pulled

out by the right hand, No.1 pin of the product is at the left top.)

+0.05

0.145 0.03

0.15±0.1

+0.05

0.03

0.145

0.2±0.1

0.1

+0.1

0.05

0.17

0.1

0.08 S

+0.05

0.08

+0.05

1.27

0.42±0.1

1.27

0.42±0.1

0.245 0.04

0.65

0.22±0.1

(0.52) 0.65

0.32 0.04

0.65

Pulling side

Pin No.1

Reel

* For ordering, specify a number of multiples of the package quantity.

(Unitꢀ:ꢀmm)

MSOP8

<Package specifications> MSOP8

Package type

Emboss taping

2.9 ± 0.1

3000pcs

Package quantity

Package direction

(When the reel is gripped by the left hand, and the tape is pulled

out by the right hand, No.1 pin of the product is at the right top.)

+0.05

0.03

0.145

0.475

+0.05

0.22 0.04

0.08

0.65

0.08 S

Ｘ

Pin No.1

Pulling side

Reel

(Unitꢀ:ꢀmm)

* For ordering, specify a number of multiples of the package quantity.

The contents described herein are correct as of October, 2005

The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.

Any part of this application note must not be duplicated or copied without our permission.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding

upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any

warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such

infringement, or arising from or connected with or related to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other

proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.

The products described herein utilize silicon as the main material.

The products described herein are not designed to be X ray proof.

Published by

Application Engineering Group

Appendix

Notes

No technical content pages of this document may be reproduced in any form or transmitted by any

means without prior permission of ROHM CO.,LTD.

The contents described herein are subject to change without notice. The specifications for the

product described in this document are for reference only. Upon actual use, therefore, please request

that specifications to be separately delivered.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard

use and operation. Please pay careful attention to the peripheral conditions when designing circuits

and deciding upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams information, described herein

are intended only as illustrations of such devices and not as the specifications for such devices. ROHM

CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any

third party's intellectual property rights or other proprietary rights, and further, assumes no liability of

whatsoever nature in the event of any such infringement, or arising from or connected with or related

to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or

otherwise dispose of the same, no express or implied right or license to practice or commercially

exploit any intellectual property rights or other proprietary rights owned or controlled by

ROHM CO., LTD. is granted to any such buyer.

Products listed in this document are no antiradiation design.

The products listed in this document are designed to be used with ordinary electronic equipment or devices

(such as audio visual equipment, office-automation equipment, communications devices, electrical

appliances and electronic toys).

Should you intend to use these products with equipment or devices which require an extremely high level

of reliability and the malfunction of which would directly endanger human life (such as medical

instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers

and other safety devices), please be sure to consult with our sales representative in advance.

It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance

of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow

for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in

order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM

cannot be held responsible for any damages arising from the use of the products under conditions out of the

range of the specifications or due to non-compliance with the NOTES specified in this catalog.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact your nearest sales office.

THE AMERICAS / EUPOPE / ASIA / JAPAN

ROHM Customer Support System

www.rohm.com

TEL : +81-75-311-2121

FAX : +81-75-315-0172

21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan

Appendix1-Rev2.0

BR25H040FVT-WE2 [ROHM]

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