BR93H66FJ-W [ROHM]
EEPROM, 256X16, Serial, CMOS, PDSO8, LEAD FREE, SOP-8;
| 型号： | BR93H66FJ-W |
| 厂家： | 
ROHM |
| 描述： | EEPROM, 256X16, Serial, CMOS, PDSO8, LEAD FREE, SOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总17页 (文件大小：1045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
HIGH GRADE Specification HIGH RELIABILITY series
Microwire BUS Serial EEPROMs
Supply voltage 2.5V~5.5V
Operating temperature –40°C~+105°C type
BR93A46-W, BR93A56-W, BR93A66-W, BR93A76-W, BR93A86-W
Description
BR93A□□-W series is a serial EEPROM of serial 3-line interface method.
Features
•
•
•
•
•
•
•
•
3-line communications of chip select, serial clock, serial data input / output (the case where input and output are shared)
Actions available at high speed 2MHz clock (2.5V ~ 5.5V)
Speed write available (write time 5 ms max.)
Same package and pin layout from 1Kbit to 16Kbit
2.5 ~ 5.5V single power source action
Highly reliable connection by Au pad and Au wire
Address auto increment function at read action
Write mistake prevention function
Write prohibition at power on
Write prohibition by command code
Write mistake prevention function at low voltage
Program cycle auto delete and auto end function
Program condition display by READY / BUSY
Low current consumption
•
•
•
At write action (at 5V)
At read action (at 5V)
: 1.2mA (Typ.)
: 0.3mA (Typ.)
At standby action (at 5V) : 0.1µA (Typ.) (CMOS input)
TTL compatible input / output
•
•
•
•
•
Compact package SOP8, SOP-J8,
Data retention for 40 years
Data rewrite up to 1,000,000 times
Data at shipment all addresses FFFFh
BR93A Series
Capacity Bit format
Type
Power source voltage
SOP8
SOP-J8
FJ RFJ
SSOP-B8
TSSOP-B8
MSOP8 TSSOP-B8J
RFVJ
F
RF
FV RFV FVT RFVT RFVM
Package type
BR93A46-W
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
64 × 16
128 × 16
256 × 16
512 × 16
1K × 16
2.5 ~ 5.5V
2.5 ~ 5.5V
2.5 ~ 5.5V
2.5 ~ 5.5V
2.5 ~ 5.5V
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
BR93A56-W
BR93A66-W
BR93A76-W
BR93A86-W
●
●
●
●
Ver.A Oct.2005
Absolute Maximum Ratings (Ta=25˚C)
Parameter
Symbol
VCC
Unit
V
Limits
Impressed voltage
-0.3ꢀ~ꢀ+6.5
SOP8ꢀ(F,ꢀRF)
450ꢀ(*1)
450ꢀ(*2)
Permissible dissipation
Pd
mW
SOP-J8ꢀ(FJ,ꢀRFJ)
-65ꢀ~ꢀ+125
-40ꢀ~ꢀ+105
-0.3ꢀ~ꢀVCC+0.3
°C
°C
V
Storage temperature range
Action temperature range
Terminal voltage
Tstg
Topr
-
* When using at Ta = 25˚C or higher, 4.5mW (*1, *2) to be reduced per 1˚C.
Recommended action conditions
Parameter
Power source voltage
Input voltage
Symbol
VCC
Limits
2.5 ~ 5.5
0 ~ VCC
Unit
V
VIN
V
Electrical characteristics (Unless otherwise specified, Ta=-40 ~ +105˚C, Vcc=2.5 ~ 5.5V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
4.0V VCC 5.5V
VIL1
VIL2
VIH1
VIH2
VOL1
VOL2
VOH1
VOH2
ILI
-0.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+0.8
0.2xVCC
VCC+0.3
VCC+0.3
0.4
V
V
"L" input voltage 1
"L" input voltage 2
"H" input voltage 1
"H" input voltage 2
"L" output voltage 1
"L" output voltage 2
"H" output voltage 1
"H" output voltage 2
Input leak current
-0.3
VCC 4.0V
2.0
V
4.0V VCC 5.5V
0.7xVCC
V
VCC 4.0V
0
V
IOL=2.1mA, 4.0V VCC 5.5V
IOL=100µA
0
0.2
V
2.4
VCC
V
IOH=-0.4mA, 4.0V VCC 5.5V
IOH=-100µA
VCC-0.2
VCC
V
-1
-1
-
+1
µA
µA
mA
mA
mA
µA
VIN=0~VCC
Output leak current
ILO
+1
VOUT=0~VCC, CS=0V
fSK=2MHz, tE/W=5ms (WRITE)
fSK=2MHz (READ)
fSK=2MHz, tE/W=5ms (WRAL,ERAL)
CS=0V, DO=OPEN
ICC1
ICC2
ICC3
ISB
3.0
Current consumption at
action
-
1.5
-
4.5
Standby current
-
2
Radiation resistance design is not made.
Memory cell characteristics (Vcc=2.5 ~ 5.5V)
Parameter
Min.
Typ.
Max.
Unit
Conditions
-
-
-
-
-
-
-
-
1,000,000
1,00,000
40
Times
Times
Years
Years
Ta≦25°C
Ta≦105°C
Ta≦25°C
Ta≦50°C
Number of data rewrite times*1
Data hold years
*1
10
*1 Not 100% TESTED
2/16
Action timing characteristics (Ta=-40 ~ +105˚C, Vcc=2.5 ~ 5.5V)
Parameter
Symbol Min.
Typ.
Max.
Unit
MHz
ns
SK frequency
SK "H" time
SK "L" time
CS "L" time
CS setup time
fSK
tSKH
tSKL
tCS
-
230
230
200
50
100
0
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
ns
-
-
ns
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
ns
DI setup time
CS hold time
-
ns
-
ns
DI hold time
100
-
-
ns
Data "1" output delay time
Data "0" output delay time
Time from CS to output establishment
Time from CS to High-Z
Write cycle time
200
200
150
150
5
ns
-
ns
-
ns
tDF
-
ns
tE/W
-
ms
Sync data input / output timing
CS
tCSS
tSKH
tSKL
tCSH
SK
DI
tDIS
tDIH
tPD0
tPD1
DO (READ)
DO (WRITE)
tDF
STATUS VALID
Fig.1 Sync data input / output timing
Data is taken by DI in sync with the rise of SK.
At read action, data is output from DO in sync with the rise of SK.
The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area
DO where CS is "H", and valid until the next command start bit is input. And, while CS is "L", DO becomes High-Z.
After completion of each mode execution, set CS "L" once for internal circuit reset, and execute the following action
mode.
3/16
Characteristic data
6
5
4
3
2
1
0
6
5
4
3
2
1
0
1
0.8
0.6
0.4
0.2
0
Ta=105°C
Ta=25°C
Ta=-40°C
SPEC
Ta=25°C
SPEC
Ta=105°C
Ta=-40°C
Ta=25°C
Ta=105°C
SPEC
4
Ta=-40°C
0
1
2
3
4
5
6
0
1
2
3
5
6
0
1
2
3
4
5
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
LꢀꢀOUTPUTꢀꢀCURRENTꢀ:ꢀIOLꢀ(mA)
Fig.4ꢁL output voltage VOL-IOL(VCC=2.5V)
Fig. 2 H input voltage VIH (CS,SK,DI)
Fig. 3 H input voltage VIL(CS,SK,DI)
1
5
4
3
5
Ta=-40°C
0.8
4
Ta=25°C
Ta=105°C
SPEC
0.6
0.4
0.2
0
3
2
1
0
Ta=-40°C
SPEC
SPEC
Ta=25°C
Ta=105°C
2
1
0
Ta=25°C
Ta=105°C
Ta=-40°C
0
1
2
3
4
5
0
0.4
0.8
1.2
1.6
0
0.4
0.8
1.2
1.6
LꢀꢀOUTPUTꢀꢀCURRENTꢀ:ꢀIOLꢀ(mA)
HꢀꢀOUTPUTꢀꢀCURRENTꢀ:ꢀIOHꢀ(mA)
HꢀꢀOUTPUTꢀꢀCURRENTꢀ:ꢀIOHꢀ(mA)
Fig.ꢀ6ꢁH output voltage VOH-IOH(VCC=2.5V)
Fig.ꢀ7ꢁH output voltage VOH-IOH(VCC=4.0V)
Fig.ꢀ5ꢁL output voltage VOL-IOL(VCC=4.0V)
1.2
1.2
5
SPEC
SPEC
fSK=2MHz
1
0.8
0.6
1
0.8
0.6
DATA=0000h
4
SPEC
3
2
Ta=105°C
0.4
0.4
Ta=25°C
Ta=105°C
Ta=25°C
Ta=-40°C
Ta=105°C
Ta=25°C
Ta=-40°C
Ta=-40°C
1
0.2
0.2
0
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
Fig.ꢀ9ꢁOutput leak current ILO (DO)
Fig.ꢀ8ꢁInput leak current ILI (CS,SK,DI)
Fig.ꢀ10ꢁCurrent consumption at WRITE action
ICC1(WRITE,fSK=2MHz)
2.5
5
2.5
fSK=2MHz
DATA=0000h
2
fSK=2MHz
DATA=0000h
SPEC
SPEC
4
3
2
SPEC
1.5
1
1.5
2
1
Ta=105°C
Ta=105°C
Ta=25°C
Ta=-40°C
Ta=25°C
Ta=-40°C
1
0.5
0.5
Ta=25°C
Ta=-40°C
Ta=105°C
0
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
Fig.ꢀ12ꢁConsumption current at WRAL action
Fig.ꢀ11ꢁConsumption current at READ action
Fig.ꢀ13ꢁConsumption current at standby action ISB
ICC3(WRAL,fSK=2MHz)
ICC2(READ,fSK=2MHz)
4/16
100
10
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
Ta=-40°C
Ta=25°C
Ta=105°C
SPEC
1
SPEC
SPEC
0.1
0.01
Ta=-40°C
Ta=25°C
Ta=105°C
Ta=-40°C
Ta=25°C
Ta=105°C
0
1
2
3
4
5
6
0
1
2
3
4
5
6ꢀ
0
1
2
3
4
5
6
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
Fig. 15 SK high time tSKH
Fig. 16 SK low time tSKL
Fig. 14 SK frequency fSK
1.2
1
50
0
300
200
100
0
SPEC
0.8
0.6
0.4
0.2
0
-50
SPEC
-100
-150
-200
Ta=-40°C
SPEC
Ta=-40°C
Ta=25°C
Ta=105°C
Ta=105°C
-100
-200
Ta=25°C
Ta=105°C
Ta=25°C
Ta=-40°C
0
1
2
3
4
5
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
Fig.17ꢁCSロウ時間ꢀtCS
Fig.ꢀ18ꢁCS hold time tCSH
Fig.ꢀ19ꢁCS setup time tCSS
150
150
100
50
1
0.8
0.6
0.4
0.2
0
SPEC
SPEC
100
50
Ta=-40°C
Ta=25°C
Ta=-40°C
Ta=25°C
Ta=105°C
0
0
SPEC
Ta=105°C
Ta=25°C
Ta=105°C
Ta=-40°C
-50
-50
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
Fig.20ꢀꢁDI hold time tDIH
Fig.ꢀ21ꢁDI setup time tDIS
Fig.ꢀ22ꢁData "0" output delay time tPD0
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
250
200
SPEC
150
Ta=105°C
100
Ta=105°C
Ta=25°C
Ta=25°C
SPEC
Ta=105°C SPEC
Ta=25°C
50
Ta=-40°C
Ta=-40°C
Ta=-40°C
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
Fig.ꢀ23ꢁOutput data "1" delay time tPD1
Fig.ꢀ24ꢁTime from CS to output establishment tSV
Fig.ꢀ25ꢁTime from CS to High-Z tDF
6
SPEC
5
Ta=105°C
4
Ta=-40°C
3
Ta=25°C
2
1
0
0
1
2
3
4
5
6
SUPPLYꢀꢀVOLTAGEꢀ:ꢀVCCꢀ(V)
Fig.ꢀ26ꢁWrite cycle time tE/W
5/16
Block diagram
Command decode
Control
CS
Power source voltage detection
Clock generation
Write
prohibition
SK
DI
High voltage occurrence
6bit
7bit
6bit
7bit
Address
buffer
Address
decoder
1,024 bit
2,048 bit
4,096 bit
8,192 bit
16,384 bit
EEPROM
8bit
8bit
9bit
Command
register
9bit
10bit
10bit
Data
register
R/W
16bit
16bit
amplifier
DO
Dummy bit
Fig. 27 Block diagram
Pin assignment and function
NC
GND
DO
DI
VCC
NC
NC
GND
BR93AXXF-W:SOP8
BR93AXXFJ-W:SOP-J8
BR93AXXRF-W:SOP8
BR93AXXRFJ-W:SOP-J8
NC
VCC
CS
SK
CS
SK
DI
DO
Fig. 28 Pin assignment diagram
Pin name
VCC
I / O
-
Function
Power source
GND
CS
-
All input / output reference voltage, 0V
Chip select input
Input
Input
Input
SK
Serial clock input
DI
Start bit, ope code, address, and serial data input
DO
NC
Output
-
Serial data output, READY / BUSY internal condition display output
Non connected terminal, Vcc, GND or OPEN
6/16
Description of operations
Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input), DO (serial data output), and CS
(chip select) for device selection.
When to connect one EEPROM to a microcontroller, connect it as shown in Fig. 34 (a) or Fig. 34 (b). When to use the input and
output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig. 34 (b) (Refer to pages 13/16.),
and connection by 3 lines is available.
In the case of plural connections, refer to Fig. 34 (c).
Micro-
controller
CS3
CS1
CS0
SK
DO
DI
Micro-
controller
Micro-
controller
BR93AXX
CS
BR93AXX
CS
CS
SK
DO
DI
CS
SK
DI
SK
SK
DI
DIO
DO
DO
Device 1
Device 2
Device 3
Fig. 29-(a) Connection by 4 lines Fig. 29-(b) Connection by 3 lines
Fig. 29-(c) Connection example of plural devices
Fig. 29 Connection method with microcontroller
Communications of the Microwire Bus are started by the first "1" input after the rise of CS. This input is called a start bit. After
input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners.
"0" input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the
microcontroller, input "0" before the start bit input, to control the bit width.
Command mode
Address
Data
Command
Read (READ)
Start bit Ope code
BR93A46-W
BR93A56/66-W
BR93A76/86-W
D15 ~ D0
(READ DATA)
*1
1
1
10
00
A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
Write enable (WEN)
Write (WRITE)
D15 ~ D0
(WRITE DATA)
A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
*2
*2
01
A5,A4,A3,A2,A1,A0
A5,A4,A3,A2,A1,A0
1
1
D15 ~ D0
(WRITE DATA)
Write all (WRAL)
Write disable (WDS)
Erase (ERASE)
00
00
11
1
1
A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
Chip erase (ERAL)
00
1
• Input the address and the data in MSB first manners.
• As for , input either VIH or VIL.
A7 of BR93A56-W becomes Don't Care.
A9 of BR93A76-W becomes Don't Care.
*
Start bit
Acceptance of all the commands of this IC starts at recognition of the start bit.
The start bit means the first "1" input after the rise of CS.
*1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and address data in significant order are
sequentially output continuously. (Auto increment function)
*2 When the read, and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written.
7/16
Timing chart
1) Read cycle (READ)
CS
1
*
BR93A46-W : n=25, m=5
BR93A56/66-W : n=27, m=7
BR93A76/86-W : n=29, m=9
1
4
n
n+1
2
1
SK
DI
Am
A1
A0
1
0
2
*
D15
D14
D1 D0 D15
D14
DO
0
High-Z
*1 Start bit
When data "1" is input for the first time after the rise of CS, this is recognized as a start bit. And when "1" is input after plural "0" are input, it is recognized as a start
bit, and the following operation is started. This is common to all the commands to described hereafter.
Fig. 30 Read cycle
When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0,
in sync with the rise of SK, "0" (dummy bit) is output. And, the following data is output in sync with the rise of SK.
This IC has address auto increment function valid only at read command. This is the function where after the above
read execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto
increment, keep CS at "H".
2) Write cycle (WRITE)
CS
tCS
n
STATUS
1
2
4
BR93A46-W : n=25, m=5
BR93A56/66-W : n=27, m=7
BR93A76/86-W : n=29, m=9
SK
DI
Am
A1 A0 D15 D14
D1
D0
1
0
1
tSV
BUSY READY
DO
High-Z
tE/W
Fig. 31 Write cycle
In this command, input 16bit data (D15 ~ D0) are written to designated addresses (Am ~ A0). The actual write starts by
the fall of CS of D0 taken SK clock.
When STATUS is not detected, (CS = "L" fixed) Max. 5ms in conformity with tE/W, and when STATUS is detected (CS
= "H"), all commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any
command.
3) Write all cycle (WRAL)
CS
STATUS
tCS
n
1
2
5
BR93A46-W : n=25
SK
DI
BR93A56/66-W : n=27
BR93A76/86-W : n=29
D15 D14
D1
D0
1
0
0
0
1
tSV
BUSY READY
DO
High-Z
tE/W
Fig. 32 Write all cycle
In this command, input 16bit data is written simultaneously to all addresses. Data is not written continuously per one
word but is written in bulk, the write time is only Max. 5ms in conformity with tE/W.
8/16
4) Write enable (WEN) / disable (WDS) cycle
CS
SK
1
2
3
4
5
6
7
8
n
BR93A46-W : n=9
ENABLE = 1
DISABLE= 0
1
0
BR93A56/66-W : n=11
BR93A76/86-W : n=13
DI
1
0
0
DO
High-Z
Fig. 33 Write enable (WEN) / disable (WDS) cycle
At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid until the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
disable command. Input to SK after 6 clocks of this command is available by either "H" or "L", but be sure to input it.
When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
canceled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
5) Erase cycle timing (ERASE)
CS
SK
tCS
STATUS
1
2
4
n
BR93A46-W : n=9, m=5
BR93A56/66-W : n=11, m=7
BR93A76/86-W : n=13, m=9
DI
Am
A3
A2 A1
A0
1
1
1
tSV
BUSY READY
DO
High-Z
tE/W
Fig. 34 Erase cycle timing
In this command, data of the designated address is made into "1". The data of the designated address becomes
"FFFFh". Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock.
In ERASE, status can be detected in the same manner as in WRITE command.
6) Chip erase cycle timing (ERAL)
CS
SK
tCS
n
STATUS
1
2
4
BR93A46-W : n=9
BR93A56/66-W : n=11
BR93A76/86-W : n=13
DI
1
0
0
1
0
tSV
BUSY READY
DO
High-Z
tE/W
Fig. 35 Chip erase cycle timing
In this command, data of all addresses is erased. Data of all addresses becomes "FFFFh". Actual ERASE starts at the
fall of CS after the fall of the n-th clock from the start bit input.
In ERAL, status can be detected in the same manner as in WRITE command.
9/16
Application
1) Method to cancel each command
READ
1
*
Start bit
1 bit
Ope code
Address
6 bits
Data
(In the case of BR93A46-W)
2 bits
16 bits
Cancel is available in all areas in read mode.
• Method to cancel : cancel by CS = "L"
*1 Address is 8 bits in BR93A56-W, and BR93A66-W.
Address is 10 bits in BR93A76-W, and BR93A86-W.
Fig. 36 READ cancel available timing
2
*
• 25 Rise of clock
SK
DI D1
24
25
D0
Enlarged figure
WRITE, WRAL
1
*
tE/W
b
Start bit
1 bit
Ope code
2 bits
Address
Data
16 bits
(In the case of BR93A46-W)
6 bits
a
2
*
*1 Address is 8 bits in BR93A56-W, and BR93A66-W.
Address is 10 bits in BR93A76-W, and BR93A86-W.
*2 27 clocks in BR93A56-W, and BR93A66-W
29 clocks in BR93A76-W, and BR93A86-W
a : From start bit to 25 clock rise
Cancel by CS = "L"
2
*
b : 25 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
Fig. 37 WRITE, WRAL cancel available timing
ERASE, ERAL
3
*
• 9 Rise of clock
SK
8
9
DI A1
A0
Enlarged figure
1
*
1/2
Start bit
1 bit
Ope code
2 bits
Address
(In the case of BR93A46-W)
tE/W
6 bits
a
b
3
*
*1 Address is 8 bits in BR93A56-W, and BR93A66-W.
Address is 10 bits in BR93A76-W, and BR93A86-W.
*2 11 clocks in BR93A56-W, and BR93A66-W
13 clocks in BR93A76-W, and BR93A86-W
a : From start bit to 9 clock rise
Cancel by CS = "L"
3
*
b : 9 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
Fig. 38 ERASE, ERAL cancel available timing
2) At standby
Standby current
When CS is "L", SK input is "L", DI input is "H", and even with middle electric potential, current does not increase.
Timing
As shown in Fig. 40, when SK at standby is "H", if CS is started, DI status may be read at the rise edge.
At standby and at power ON/OFF, when to start CS, set SK input or DI input to "L" status. (Refer to Fig. 39.)
CS = SK = DI = "H"
Wrong recognition as a start but
If CS is started when SK = "L" or DI = "L", a start
bit is recognized correctly.
CS
SK
DI
CS
SK
DI
Start bit input
Start bit input
Fig. 40 Normal action timing
Fig. 39 Wrong action timing
10/16
3) Equivalent circuit
Output circuit
Input circuit
RESETint.
CSint.
DO
CS
OEint.
Fig. 41 Output circuit (DO)
Fig. 42 Input circuit (CS)
CSint.
Input circuit
Input circuit
CSint.
SK
DI
Fig. 43 Input circuit (DI)
Fig. 44 Input circuit (SK)
4) I/O peripheral circuit
4-1) Pull down CS.
By making CS = "L" at power ON/OFF, mistake in operation and mistake write are prevented.
Pull down resistance Rpd of CS pin
To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary. Select an
appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC.
VOHM
.
.
.
Rpd
≥
≥
IOHM
.
.
.
VOHM
VIHE
Microcontroller
VOHM
EEPROM
Example) When Vcc = 5V, VIHE = 2V, VOHM = 2.4V, IOHM = 2mA,
from the equation
,
VIHE
2.4
2×10-3
Rpd
Rpd
≥
≥
IOHM
Rpd
"H" output
"L" input
1.2 (K
)
With the value of Rpd to satisfy the above equation, VOHM becomes
Fig. 45 CS pull down resistance
2.4V or higher, and with VIHE (= 2.0V), the equation
is also satisfied.
y VIHE : EEPROM VIH specifications
y VOHM : Microcontroller VOH specifications
y IOHM : Microcontroller IOH specifications
4-2) DO is available in both pull up and pull down.
DO output become "High-Z" in other READY / BUSY output timing than after data output at read command and write
command.
When malfunction occurs at "High-Z" input of the microcontroller port connected to DO, it is necessary to pull down and
pull up DO.
When there is no influence upon the microcontroller actions, DO may be OPEN.
If DO is OPEN, and at timing to output status READY, at timing of CS = "H", SK = "H", DI = "H", EEPROM recognizes this
as a start bit, resets READY output, and DO = "High-Z", therefore, READY signal cannot be detected. To avoid such
output, pull up DO pin for improvement.
"H"
CS
CS
SK
DI
SK
DI
Enlarged
D0
CS = SK = DI = "H"
When DO = OPEN
High-Z
High-Z
READY
DO
DO
BUSY
BUSY
BUSY
Improvement by DO pull up
READY
CS = SK = DI = "H"
When DO = pull up
DO
Fig. 46 READY output timing at DO = OPEN
11/16
Pull up resistance Rpu and pull down resistance Rpd of DO pin
As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller
VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC.
VCC-VOLE
.
.
.
.
.
.
Rpu
≥
≤
IOLE
VILM
Microcontroller
EEPROM
VOLE
Rpu
Example) When Vcc = 5V, VOLE = 0.4V, IOLE = 2.1mA, VILM = 0.8V,
from the equation
VILM
IOLE
,
VOLE
5-0.4
2.1×10-3
Rpu
Rpu
≥
≥
"L" input
2.2 (K
)
"L" output
With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V
or below, and with VILM (= 0.8V), the equation
is also satisfied.
y VOLE : EEPROM VOL specifications
y IOLE : EEPROM IOL specifications
y VILM : Microcontroller VIL specifications
Fig. 47 DO pull up resistance
VOHE
.
.
.
.
.
.
Rpd ≥
IOHE
VIHM
EEPROM
VOHE ≥
Microcontroller
Example) When Vcc = 5V, VOHE = Vcc - 0.2V, IOHE = 0.1mA, VIHM =
VIHM
Vcc × 0.7V from the equation
,
VOHE
5-0.2
Rpd ≥
0.1×10-3
IOHE
"H" output
"H" input
Rpd
Rpd ≥
48 (K )
With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V
or below, and with VIHM (= 3.5V), the equation
is also satisfied.
Fig. 48 DO pull down resistance
y VOHE : EEPROM VOH specifications
y IOHE : EEPROM IOH specifications
y VIHM : Microcontroller VIH specifications
5) READY / BUSY status display (DO terminal) (common to BR93A46-W, BR93A56-W, BR93A66-W, BR93A76-W, BR93A86-W)
This display outputs the internal status signal. When CS is started after tCS (Min. 200ns)
from CS fall after write command input, "H" or "L" is output.
R/B display = "L" (BUSY) = write under execution
(D0 status)
After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically.
And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted.
R/B display = "H" (READY) = command wait status
(D0 status)
Even after tE/W (Max. 5ms) from write of the memory cell, the following command is accepted.
Therefore, CS = "H" in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI = "L" in
the area CS = "H". (Especially, in the case of shared input port, attention is required.)
* Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted. Therefore,
status READY output is cancelled, and malfunction and mistake write may be made.
CS
SK
DI
STATUS
CLOCK
WRITE
INSTRUCTION
tSV
High-Z
READY
DO
BUSY
Fig. 49 R/B status output timing chart
12/16
6) When to directly connect DI and DO
This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart,
meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1
control line.
EEPROM
Microcontroller
DI / O PORT
DI
R
DO
Fig. 50 DI, DO control line common connection
Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input
Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the
same time in the following points.
(1) 1 clock cycle to take in A0 address data at read command
Dummy bit "0" is output to DO terminal.
→When address data A0 = "1" input, through current route occurs.
EEPROM CS input
EEPROM SK input
EEPROM DI input
"H"
A1
A1
A0
A0
Collision of DI input and DO output
D15
0
EEPROM DO output
Microcontroller DI/O port
D14 D13
High-Z
High-Z
Microcontroller input
Microcontroller output
Fig. 51 Collision timing at read data output at DI, DO direct connection
(1) Timing of CS = "H" after write command. DO terminal in READY / BUSY function output.
When the next start bit input is recognized, "HIGH-Z" gets in.
→Especially, at command input after write, when CS input is started with microcontroller DI/O output "L",
READY output "H" is output from DO terminal, and through current route occurs.
Feedback input at timing of these (1) and (2) does not cause disorder in basic operations, if resistance R is inserted.
EEPROM CS input
EEPROM SK input
EEPROM DI input
Write command
Write command
Write command
READY
READY
READY
High-Z
EEPROM DO output
Microcontroller DI/O port
Write command
BUSY
BUSY
Collision of DI input and DO output
Write command
Microcontroller output
Microcontroller output
Microcontroller input
Fig. 52 Collision timing at DI, DO direct connection
Note) As for the case (2), attention must be paid to the following.
When status READY is output, DO and DO are shared, DI = "H" and the microcontroller DI/O = "High-Z" or the microcontroller
DI/O = "H", if SK clock is input, DO output is input to DI and is recognized as a start bit, and malfunction may occur. As a
method to avoid malfunction, at status READY output, set SK = "L", or start CS within 4 clocks after "H" of READY signal is
output.
Start bit
CS
SK
DI
Because DI = "H", set
SK = "L" at CS rise.
READY
DO
High-Z
Fig. 53 Start bit input timing at DI, DO direct connection
13/16
Selection of resistance value R
The resistance R becomes through current limit resistance at data collision. When through current flows, noises of
power source line and instantaneous stop of power source may occur. When allowable through current is defined as I,
the following relation should be satisfied. Determine allowable current amount in consideration of impedance and so
forth of power source line in set. And insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL
even under influence of voltage decline owing to leak current and so forth. Insertion of R will not cause any influence
upon basic operations.
(1) Address data A0 = "1" input, dummy bit "0" output timing
(When microcontroller DI/O output is "H", EEPROM DO outputs "L", and "H" is input to DI)
Make the through current to EEPROM 10mA or below.
• See to it that the input level VIH of EEPROM should satisfy the following.
Conditions
Microcontroller
EEPROM
VOHM
VOHM
VIHE
IOHM × R + VOLE
DI/O PORT
VOHM
DI
At this moment, if VOLE = 0V,
"H" output
VOHM
R
IOHM × R
IOHM
R
VOHM
IOHM
.
. .
DO
ꢀVIHE : EEPROM VIH specifications
ꢀVOLE : EEPROM VOL specifications
ꢀVOHM : Microcontroller VOH specifications
ꢀIOHM : Microcontroller IOH specifications
VOLE
"L" output
Fig. 54 Circuit at DI, DO direct connection (Microcontroller DI/O "H" output, EEPROM "L" output)
(2) DO status READY output timing
(When the microcontroller DI/O is "L", EEPROM DO outputs "H", and "L" is input to DI)
• Set the EEPROM input level VIL so as to satisfy the following.
Conditions
Microcontroller
"L" output
EEPROM
VOLM
VOLM
VILE
VOHE - IOLM × R
DI/O PORT
VOLM
DI
At this moment, VOHE=VCC,
VOLM
R
VCC - IOLM × R
IOHM
R
VCC - VOLM
IOLM
DO
.
. .
VOHE
"H" output
ꢀVILE : EEPROM VIL specifications
ꢀVOHE : EEPROM VOH specifications
ꢀVOLM : Microcontroller VOL specifications
ꢀIOLM : Microcontroller IOL specifications
Fig. 55 Circuit at DI, DO direct connection (Microcontroller DI/O "L" output, EEPROM "H" output)
Example) When Vcc = 5V, VOHM = 5V, IOHM = 0.4mA, VOLM = 5V, IOLM = 0.4mA,
From the equation
,
From the equation
R
,
VCC - VOLM
IOLM
VOHM
IOHM
R
5 - 0.4
5
R
R
R
2.1×10-3
0.4×10-3
.
. .
.
. .
2.2 [k
]
R
12.5 [k
]
Therefore, from the equations
12.5 [k
and
,
R
]
14/16
7) Notes on power ON/OFF
• At power ON/OFF, set CS "L".
When CS is "H", this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause
malfunction, mistake write or so. To prevent these, at power ON, set CS "L". (When CS is in "L" status, all inputs are cancelled.) And at
power decline, owing to power line capacity and so forth, low power status may continue long. At this case too, owing to the same
reason, malfunction, mistake write may occur, therefore, at power OFF too, set CS "L".
VCC
VCC
GND
VCC
CS
GND
Good example
Bad example
Fig. 56 Timing at power ON/OFF
(Good example) It is "L" at power ON/OFF.
(Bad example) CS pin is pulled up to Vcc.
In this case, CS becomes "H" (active status), and EEPROM may have malfunction,
Set 10ms or higher to recharge at power OFF.
mistake write owing to noises and the likes.
Even when CS input is High-Z, the status becomes like this case, which please note.
When power is turned on without observing this condition, IC
internal circuit may not be reset, which please note.
POR circuit
This IC has a POR (Power On Reset) circuit as mistake write countermeasure.
After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF.
However, if CS is "H" at power ON/OFF, it may become write enable status owing to noises and the likes.
For secure actions, observe the following conditions.
1
2
Set CS = "L".
Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tR
tOFF
Vbot
10ms or below 10ms or higher 0.3V or below
100ms or below 10ms or higher 0.2V or below
tOFF
Vbot
0
Fig. 57 Rise waveform diagram
LVCC circuit
LVCC (Vcc - Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. = 1.2V) or below, it prevent data rewrite.
8) Noise countermeasures
Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach
a by pass capacitor (0.1µF) between IC Vcc and GND, At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
SK noise
When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit
displacement. To avoid this, a Schmitt trigger circuit is built in SK input. the hysteresis width of this circuit is set about 0.2V, if noises
exist at SK input, set the noise amplitude 0.2Vp-p or below.
And it is recommended to set the rise time (tR) of SK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient
noise countermeasures. Make the clock rise, fall time as small as possible.
Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In
the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static
characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute Maximum Ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be
destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute
maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum
ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that of GND
terminal in consideration of transition status.
(5) Heat design
In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in
the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be
destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
15/16
Selection of order type
BR
93
A
46
F
-
W
E2
ROHM
type name
BUS type
93 : Microwire
Operating
Capacity
Microwire BUS
46=1K
56=2K
66=4K
Package type
F : SOP8
FJ : SOP-J8
RF : SOP8
Double cell Taping type name
E2 : reel shape emboss taping
temperature
L : −40℃〜＋85℃
A : −40℃〜＋105℃
H : −40℃〜＋125℃
RFJ : SOP-J8
76=8K
86=16K
Package specifications
SOP8/SOP-J8/SSOP-B8
<External appearance>
<Package specifications>
Package type
Emboss taping
Package quantity 2500pcs
• SOP8
• SOP-J8
Package direction E2
4.9±0.2
(When the reel is gripped by the left hand, and the tape is pulled
out by the right hand, No.1 pin of the product is at the left top.)
5.0±0.2
8
7
6
5
8
5
1
2
3
4
1
4
0.2±0.1
0.1
+0.1
0.05
0.17
0.1
1.27
1.27
0.42±0.1
0.42±0.1
Pin No.1
Pulling side
Reel
(Unitꢀ:ꢀmm)
* For ordering, specify a number of multiples of the package quantity.
The contents described herein are correct as of October, 2005
The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.
Any part of this application note must not be duplicated or copied without our permission.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding
upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any
warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such
infringement, or arising from or connected with or related to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other
proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.
The products described herein utilize silicon as the main material.
The products described herein are not designed to be X ray proof.
Published by
Application Engineering Group
Catalog No. 05T818A '05.10 ROHM© 2000 TSU
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
THE AMERICAS / EUPOPE / ASIA / JAPAN
ROHM Customer Support System
Contact us : webmaster@ rohm.co.jp
www.rohm.com
TEL : +81-75-311-2121
FAX : +81-75-315-0172
Copyright © 2007 ROHM CO.,LTD.
21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
Appendix1-Rev2.0
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明