BU16028KV_技术文档

TECHNICAL NOTE

HDMI Switch ICs

3 for input 1 output switch with Termination sense

correspondence (Sync with HPD_SINK)

BU16028KV

●DESCRIPTION

BU16028KV is 3 for input 1 output HDMI/DVI switch LSI. Each port supports 2.25Gbps. (HDMI 1.3a)

This device control is simple. It requires only 3.3V source and a few GPIO controls.

Terminated resistors(50Ω) are integrated at input port. When channel is not selected, termination resistors are turned off.

TMDS inputs are high impedance.

This device is integrated equalization function and DDC buffer function, so it can adapt long cable.

●FEATURES

・ Supports 2.25 Gbps signaling rate for 480i/p, 720i/p, and 1080i/p resolution to 12-bit color depth

・ Compatible with HDMI 1.3a

・ 5V tolerance to all DDC and HPD_SINK inputs

・ Integrated DDC buffer

・ Integrated switchable 50Ωreceiver termination

・ Integrated equalizer circuit to adapt long cable

・ HBM ESD protection exceeds 10kV

・ 3.3V fixed supply to TMDS I/Os

・ 64Pin VQFP package

・ ROHS compatible

●APPLICATIONS

・ Digital TV

・ DVD Player

・ Set-Top-Box

・ Audio Video Receiver

・ Digital Projector

・ DVI or HDMI Switch Box

Jul. 2008

●OUTSIDE DIMENSION CHART

BU16028KV

1PIN MARK

Lot No.

Fig. 1-1 . Outside dimension chart

2/17

●BLOCK DIAGRAM

V_CC

R_INT

Y4

Z4

A24

B24

TMDS

R_X

TMDS

Drive

V_CC

R_INT

A23

B23

Y3

Z3

TMDS

R_X

TMDS

Drive

V_CC

R_INT

A22

B22

Y2

Z2

TMDS

R_X

TMDS

Drive

V_CC

R_INT

A21

B21

Y1

TMDS

R_X

TMDS

Drive

Z1

VSADJ

V_CC

R_INT

A34

B34

TMDS

R_X

V_CC

R_INT

A33

B33

TMDS

R_X

V_CC

R_INT

A32

B32

TMDS

R_X

V_CC

R_INT

A31

B31

TMDS

R_X

HPD1

HPD2

HPD3

S1

S2

HPD_SINK

SCL1

SDA1

SCL_SINK

SDA_SINK

Control Logic

SCL2

SDA2

SCL3

SDA3

Fig. 2-1. Block Diagram

3/17

●PIN EXPLANATION

1). PIN ASSIGNMENT

(TOP VIEW)

49

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Reserve2

S1

50

HPD2

HPD_SINK

SDA_SINK

SCL_SINK

GND

51

SDA2

52

SCL2

53

B21

54

A21

Z1

Y1

55

Vcc

56

B22

Vcc

Z2

BU16028KV

57

A22

(64-pin VQFP)

58

GND

Y2

59

B23

GND

Z3

60

A23

61

Vcc

Y3

62

B24

Vcc

Z4

63

A24

64

HPD3

Y4

1PIN

MARK

Fig3-1. Pin Location

4/17

2). PIN LIST

TERMINAL

I/O

DESCRIPTION

NAME

No.

A11, A12, A13, A14

A21, A22, A23, A24

A31, A32, A33, A34

B11, B12, B13, B14

B21, B22, B23, B24

B31, B32, B33, B34

39, 42, 45, 48

I

Source port 1 TMDS positive inputs

Source port 2 TMDS positive inputs

Source port 3 TMDS positive inputs

Source port 1 TMDS negative inputs

Source port 2 TMDS negative inputs

Source port 3 TMDS negative inputs

54, 57, 60, 63

5, 8, 11, 14

38, 41, 44, 47

53, 56, 59, 62

4, 7, 10, 13

3, 9, 15, 22, 28,

GND

-

Ground

43, 58

HPD1

HPD2

35

O

Source port 1 hot plug detector output (status pin)

Source port 2 hot plug detector output (status pin)

Source port 3 hot plug detector output (status pin)

Sink port hot plug detector input (status pin)

Set to HIGH/LOW/OPEN

50

HPD3

64

O

HPD_SINK

Reserve1

Reserve2

SCL1

31

I

34

I/O

I

49

Non Connect Pin

37

Source port 1 DDC I²C clock line

Source port 2 DDC I²C clock line

Source port 3 DDC I²C clock line

Sink port DDC I²C clock line

SCL2

52

SCL3

2

SCL_SINK

SDA1

29

36

Source port 1 DDC I²C data line

Source port 2 DDC I²C data line

Source port 3 DDC I²C data line

Sink port DDC I²C data line

SDA2

51

1

SDA3

SDA_SINK

S1, S2

30

32, 33

Source selector

6, 12, 19, 25,

40, 46, 55, 61

VCC

-

I

Power supply

TMDS compliant voltage swing control

(via 4.64kΩto GND)

VSADJ

16

Y1, Y2, Y3, Y4

Z1, Z2, Z3, Z4

26, 23, 20, 17

27, 24, 21, 18

O

Sink port TMDS positive outputs

Sink port TMDS negative outputs

5/17

●EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

TMDS Input Stage

V_DD

TMDS Output Stage

V_DD

HPD Output Stage

V_DD

50Ω

Ym

Zm

Anm

Bnm

HPDn

10mA

R-Side I²C Input/Output Stage

V_DD

T-Side I²C Input/Output Stage

V_DD

SCL_SINK

SDA_SINK

SCL

SDA

HPD_SINK

V_DD

※n=1,2,3 m=1,2,3,4

Fig. 4-1 . I/O pin schematic diagram

6/17

●SOURCE SELECTION LOOKUP TABLE

CONTROL PINS

I/O SELECTED

HOT PLUG DETECT STATUS

SCL_SINK

SDA_SINK

HPD_SINK

S1

S2

Y/Z

HPD1

HPD2

HPD3

A1/B1

Terminations of A2/B2

and A3/B3 are

disconnected

A2/B2

SCL1

SDA1

H

L

H

L

Terminations of A1/B1

and A3/B3 are

disconnected

A3/B3

SCL2

SDA2

L

H

L

H

L

H

L

H

L

H

L

Terminations of A1/B1

and A2/B2 are

disconnected

SCL3

SDA3

None (Z)

Are pulled HIGH by

external pull-up

termination

None (Z)

H

L

All terminations are

disconnected

Disallowed

(indeterminate)State

All terminations are

disconnected

SCL1

SDA1

H

L

Disallowed

(indeterminate)State

All terminations are

disconnected

SCL2

SDA2

L

Disallowed

(indeterminate)State

All terminations are

disconnected

SCL3

SDA3

L

None (Z)

Are pulled HIGH by

external pull-up

termination

None (Z)

L

H

L

All terminations are

disconnected

L

(1)H: Logic high; L: Logic low; X: Don't care; Z: High impedance

7/17

●ERECTRICAL SPECIFICATIONS

1.） ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

ITEM

Power supply voltage (Vcc)

DDC, HPD_SINK input voltage

Differential input voltage

S1, S2 input voltage

MIN.

-0.3

2.5

-0.3

-

TYP.

MAX.

4.0

UNIT

V

-

V

6.0

V

4.0

V

4.0

mW

℃

1250

125

Power dissipation

-55

Strage temperture range

※70mm×70mm×1.6mm glass epoxy board mount.（Reverse Cu occupation rate：15mm×15mm）

When it’s used by than Ta=25℃, it’s reduced by 12.5mW/℃.

2.） RECOMMENDED OPERATING CONDITIONS

SYMBOL

V_CC

PARAMETER

MIN.

TYP.

3.3

-

MAX.

UNIT

V

Supply voltage

Operating free-air temperature

3

0

3.6

70

T_A

℃

TMDS DIFFERENTIAL PINS

V_IC

Input common mode voltage

V_CC–0.6

-

V_CC+0.01

1560

4.68

3.6

V

mVp-p

kΩ

V_ID

Receiver peak-to-peak differential input voltage

Resistor for TMDS compliant voltage swing range

TMDS Output termination voltage, see Figure 5-1.

Termination resistance, see Figure 5-1.

Signaling rate

150

4.60

3

R_VSADJ

AV_CC

R_T

4.64

3.3

50

-

V

45

0

55

Ω

2.25

Gbps

CONTROL PINS (S1,S2)

VIH

VIL

LVTTL High-level input voltage

LVTTL Low-level input voltage

2

-

V_CC

0.8

V

GND

STATUS(HPD_SINK)

V_IH

V_IL

LVTTL High-level input voltage

LVTTL Low-level input voltage

2.4

-

5.5

0.8

V

GND

DDC I/O PINS Tx (SCL_SINK, SDA_SINK)

V_IH

V_IL

High-level input voltage

Low-level input voltage

2.1

-

5.5

V

-0.3

0.35

DDC I/O PINS Rx (SCLn, SDAn) n = 1, 2, 3

V_IH

V_IL

High-level input voltage

Low-level input voltage

2.4

-

5.5

0.8

V

-0.3

8/17

3.） ELECTRICAL CHARACTERISTICS

Over recommended operating conditions (unless otherwise noted)

LIMITS

TYP.⁽¹⁾

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN.

MAX.

V_IH- = Vcc,V_IL= Vcc-0.4V,R_VSADJ

4.64kΩ

=

R_T= 50Ω,AVcc = 3.3V

Icc

Supply current

Am/Bm = 2.25 Gbps HDMI data

pattern,

-

120

150

mA

m = 2,3,4

A1,/B1 = 225 MHz clock

V_IH= V_cc,V_IL= Vcc-0.4V,R_VSADJ

4.64kΩ

=

R_T= 50Ω,AVcc = 3.3V

P_D

Power dissipation

Am/Bm = 2.25Gbps HDMI data

pattern,

-

450

600

mW

m = 2,3,4

A1/B1 =255 MH_Zclock

TMDS DIFFERENTIAL PINS (A/B;Y/Z)

Single-ended high-level output

AVcc-

200

V_OH

-

Avcc-50

Avcc-400

460

mV

voltage

Single-ended low-level output

AVcc-

600

V_OL

voltage

Single-ended low-level swing

See Figure 5-2, AVcc = 3.3V,

V_SWING

voltage

300

-

mV

R_T= 50Ω

Overshoot of output differential

Vod_(O)

-

6%

12%

15%

2xV_swing

voltage

Undershoot of output

Vod_(U)

25%

differential voltage

See Figure 5-2,

Am/Bm = 250 Mbps HDMI data

pattern ,

Steady state output differential

V_OD(

600

-

920

mVp-p

)

ｐｐ

voltage

m = 2,3,4

A1/B1 = 25 MHz clock

V_IN= 2.9V

R_INT

⊿V_{OC SS}

Input termination resistance

Change in steady-state

common-mode output voltage

between logic states

45

-

50

5

55

-

Ω

mV

（

）

9/17

LIMITS

TYP.⁽¹⁾

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN.

MAX.

DDC Input and output

Tx

V_IH

V_IL

High-level input voltage

2.1

-

5.5

V

Low-level input voltage

-0.3

0.35

I_lKT

Input leak current,

VI=5.5V

-10

-

10

uA

V

①

I_lKT

Input leak current,

VI=Vcc

②

I_OHT

I_ILT

High-level output current

Low-level input current

Low-level output voltage

Low-level input voltage below

output low-level voltage

VO=3.6V

VIL=GND

RL=4.7kΩ

-10

-

10

-10

-

10

V_OLT

0.43

0.5

0.57

V_OLT-V_IL

20

100

190

mV

Rx

V_IH

V_IL

High-level input voltage

Low-level input voltage

Input leak current

2.4

-0.3

-10

-

5.5

0.8

10

V

I_lKR

VI=5.5V

uA

V

①

I_lKR

Input leak current

VI=Vcc

10

②

I_OHR

I_ILR

High-level output current

Low-level input current

Low-level output voltage

VO=3.6V

VIL=GND

Iout = 4mA

10

V_OLR

0.2

DDC Input and output

STATUS PINS (HPD 1, HPD 2, HPD 3)

V_OH(TTL)

V_OL(TTL)

CONTROL PINS (S1, S2 )

TTL High –level output voltage I_OH= -8mA

2.4

0

-

Vcc

0.4

V

TTL Low –level output voltage I_OL= 8mA

I_IH

I_IL

High –level digital input current V_IH= Vcc

-10

-

10

uA

Low –level digital input current

V_IL= GND

STATUS PINS (HPD_SINK)

I_IHHigh –level digital input current

I_ILLow –level digital input current

V_IH= 5.5V

V_IH= Vcc

10

5

50

30

100

80

uA

V_IL= GND

-10

-

10

uA

10/17

LIMITS

TYP.⁽¹⁾

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN.

MAX.

TMDS DIFFERENTIAL PINS (Y/Z)

Propagation delay time

t_PLH

-

480

500

150

-

ps

low-high-level output

Propagation delay time

t_PHL

low-high-level output

Differential output signal rise

t_r

time (20%-80%)

Differential output signal fall

See Figure 5-2, AV_CC= 3.3V,

t_f

-

150

20

-

ps

time (20%-80%)

R_T= 50Ω

t_sk(p)

t_sk(D)

Pulse skew (|t_PHL- t_PLH|)

Intra-pair differential skew,

see Figure 5-3.

50

Inter-pair channel-to-channel

output skew

t_sk(o)

-

50

-

ps

t_sk(pp)

Part to part skew

400

DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)

Propagation delay time,

t_pdLHTR

low-to-high-level output

-

650

200

500

350

-

ns

(DDC)

Tx to Rx

R_L= 4.7kΩ C_L= 100pF

Propagation delay time,

high-to-low-level output

Tx to Rx

t_pdHLTR

(DDC)

Propagation delay time,

low-to-high-level output

Rx to Tx

t_pdLHRT

(DDC)

R_L= 1.67kΩ C_L= 400pF

Propagation delay time,

high-to-low-level output

Rx to Tx

t_pdHLRT

(DDC)

tr Tx_(DDC)Tx output Rise time

tf Tx_(DDC)Tx output Fall time

tr Rx_(DDC)Rx output Rise time

tf Rx_(DDC)Rx output Fall time

-

800

150

950

50

8

-

ns

R_L= 4.7kΩ C_L= 100pF

R_L= 1.67kΩ C_L= 400pF

t_sx

t_dis

t_en

Select to switch output

Disable time

5

Enable time

7

Switch time from SCLn to

SCL_SINK

t_sx(DDC)

C_L=10pF

-

800

-

Ns

STATUS PINS (HPD1,HPD2,HPD3)

Propagation delay time,

t_pdLH(HPD)low-to-high-level output from C_L=10pF

HPD_SINK to HPDn(n=1,2,3)

-

5

-

ns

Propagation delay time,

t_pdHL(HPD)high-to-low-level output from C_L=10pF

HPD_SINK to HPDn(n=1,2,3)

-

5

8

-

ns

Switch time from port select to

t_sx(HPD)

C_L=10pF

the latest valid status of HPD

Note:

1. All typical values are at 25℃ and with a 3.3V supply.

11/17

●MEASUREMENT SYMBOL AND CIRCUIT

AVCC

RT

R^T

Zo = RT

TMDS

Receiver

TMDS

Driver

Figure 5-1. Termination for TMDS Output Driver

Vcc

RINT

R^INT

RT

Y

A

CL

TMDS

Driver

TMDS

Receiver

AVCC

VA

VID

VY

0.5pF

Z

B

VZ

VB

VID = VA - VB

Vswing = VY - VZ

DC Coupled AC Coupled

VA

Vcc V

Vcc+0.2 V

VB

Vcc-0.4 V

0.4 V

Vcc-0.2 V

VID

VIC

VID(pp)

0 V

-0.4 V

tPLH

80%

100%

Vswing

VOD(O)

0V Differential

0%

VOD(pp)

20%

tr

tf

VOD(U)

VOC

△VOC(SS)

Figure 5-2. Timing Test Circuit and Definitions

12/17

VY

VZ

VOH

50%

VOL

tsk(D)

Figure 5-3. Definition of Intra-Pair Differential Skew

Vcc V

Vcc-0.4 V

A

B

A

B

A

B

Port 1

Port 2

Port 3

Vcc-0.4 V

Vcc V

Vcc-0.4 V

Vcc V

VDD

2

VDD

S1

Clocking

S2

0V

tsx

75mV

Y

Z

Output

HI-Z

-75mV

tdis

ten

Figure 5-4.TMDS Outputs Control Timing Definitions

13/17

VDD

2

HPD_SINK

HPD1

VDD

2

tsx(HPD)

tpdHL(HPD)

tpdLH(HPD)

2.4V

0V

HPD2

HPD3

S1

Vcc

2

VDD

S2

t^pdHLRT(DDC)tpdLHRT(DDC)

tpdHLTR(DDC)

tpdLHTR(DDC)

t_SX(DDC)

SDA_SINK

80%

20%

1.5V

V_IL

SDA1

80%

20%

1.5V

0V

SDA2

SDA3

tfTX(DDC)

trTX(DDC)

tfRX(DDC)

trRX(DDC)

VDD

RX to TX

TX to RX

Figure 5-5. DDC and HPD Timing Definitions

14/17

1). Y and Z terminal ESD Diode notice.

Y and Z terminals are connected ESD diode.

When VCC＋0.4 < AVCC.

BU16028KV flow leak current from AVCC to VCC.

In order to minimize leak current.

Please use following application.

If you use “Repeater” or “output Buffer”

VCC

need more than

10mA load

Tx side

AVCC

Low Vsat TR

power down

controler

VCC

BU16028KV

10kΩ

GND(3pin)

HPD2

Figure 6-1. Ist mode application

2). HPD_SINK Pull down resistance.

HPD_SINK is a 5V tolerant structure shown in Fig6-2.

It needs some drive current to pull down HPD_SINK "H" to "L"(max10uA@HPD_SINK=2V).

So to pull down HPD_SINK, please use 10kΩ(or under 10kΩ) resistor.

VCC

BU16028KV

HPD_SINK

10kΩ

Figure 6-2. HPD_SINK I/O schematic

15/17

3). About don’t use terminal.

Unused TMDS input channel can be opened.

BU16028KV

Vcc

R_INT

R_T

A

Y

TMDS

Receiver

TMDS

Driver

AVcc

B

Z

R_T

Figure 6-3. TMDS Input Fail-Safe Recommendation

Unused DDC Buffers of R side pull up to Vdd .

VCC

4.7k

T

RSCL

RSDA

TSCL

TSDA

R

Figure 6-4. DDC Buffers in BU16028KV

4）. About serial connect notice.

When HDMI sw output connect to other HDMI sw input like following application.

There is possibility that. 1080p(12bit) image isn’t displayed. It‘s depend on receiver IC characteristic.

When system is required 1080p (12bit), Rohm doesn’t recommend serial connect application.

.

Vcc

R_INT

R_T

A

Y

Z

A

Y

Z

TMDS

Receiver

TMDS

Driver

TMDS

Receiver

TMDS

Driver

AVCC

B

R_T

Fig6-5 serial connect notice

16/17

Appendix

Notes

No technical content pages of this document may be reproduced in any form or transmitted by any

means without prior permission of ROHM CO.,LTD.

The contents described herein are subject to change without notice. The specifications for the

product described in this document are for reference only. Upon actual use, therefore, please request

that specifications to be separately delivered.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard

use and operation. Please pay careful attention to the peripheral conditions when designing circuits

and deciding upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams information, described herein

are intended only as illustrations of such devices and not as the specifications for such devices. ROHM

CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any

third party's intellectual property rights or other proprietary rights, and further, assumes no liability of

whatsoever nature in the event of any such infringement, or arising from or connected with or related

to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or

otherwise dispose of the same, no express or implied right or license to practice or commercially

exploit any intellectual property rights or other proprietary rights owned or controlled by

ROHM CO., LTD. is granted to any such buyer.

Products listed in this document are no antiradiation design.

The products listed in this document are designed to be used with ordinary electronic equipment or devices

(such as audio visual equipment, office-automation equipment, communications devices, electrical

appliances and electronic toys).

Should you intend to use these products with equipment or devices which require an extremely high level

of reliability and the malfunction of which would directly endanger human life (such as medical

instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers

and other safety devices), please be sure to consult with our sales representative in advance.

It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance

of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow

for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in

order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM

cannot be held responsible for any damages arising from the use of the products under conditions out of the

range of the specifications or due to non-compliance with the NOTES specified in this catalog.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact your nearest sales office.

THE AMERICAS / EUROPE / ASIA / JAPAN

ROHM Customer Support System

Contact us : webmaster@ rohm.co.jp

www.rohm.com

TEL : +81-75-311-2121

FAX : +81-75-315-0172

21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan

Appendix1-Rev2.0


型号：	BU16028KV
厂家：	ROHM
描述：	Consumer Circuit, PQFP64, ROHS COMPLIANT, VQFP-64 商用集成电路
文件：	总18页 (文件大小：836K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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