BU1852GXW-E2_技术文档

BU1852GUW

GPIO ICs

Keyencoder IC

BU1852GUW, BU1852GXW

No.11098EBT04

●Description

Keyencoder IC BU1852 can monitor up to 8x12 matrix (96 keys), which means to be adaptable to Qwerty keyboard. We

adopt the architecture that the information of the only key which status is changed, like push or release, is encoded into the

8 bits data. This can greatly reduce the CPU load which tends to become heavier as the number of keys increase.

(Previously, all key's status is stored in the registers.) When the number of keys is small, the extra ports can be used as

GPIO. Furthermore, auto sleep function contributes to low power consumption, when no keys are pressed. It is also

equipped with the various functions such as ghost key rejection, N-key Rollover, Built-in power on reset and oscillator.

●Features

1) Monitor up to 96 matrix keys.

2) Under 3µA Stand-by Current

3) Built-in Power on Reset.

4) Ghost key rejection.

5) Keyscan / GPIO selectable

6) 3 volt tolerant Input

●Absolute maximum ratings (Ta=25℃)

Parameter

Symbol

Ratings

-0.3 ~ +2.5

Unit

V

Conditions

VDD≦VDDIO

VDD

VDDIO

VI1

Supply Voltage

-0.3 ~ +4.5

V

1

-0.3 ~ VDD +0.3^※

V

XRST, XI, TW, PORENB

ADR

1

Input voltage

VI2

-0.3 ~ VDDIO +0.3^※

-0.3 ~ +4.5

V

XINT, SCL, SDA,

COL[11:0], ROW[7:0]

VIT

V

Storage temperature range

Package power

Tstg

PD

-55 ~ +125

℃

mW

2

272^※

※

This IC is not designed to be X-ray proof.

※1 It is prohibited to exceed the absolute maximum ratings even including +0.3 V.

※2 Package dissipation will be reduced each 2.72mW/℃ when the ambient temperature increases beyond 25℃.

●Operating conditions

Ratings

Parameter

Symbol

Unit

Conditions

Min.

1.65

Typ.

1.80

Max.

1.95

Supply voltage range

(VDD)

VDD

VDDIO

VI1

V

Supply voltage range

(VDDIO)

1.65

-0.2

-30

1.80

3.60

VDD+0.2

VDDIO+0.2

3.60

-

V

XRST, XI, TW, PORENB

ADR

Input voltage range

VI2

V

XINT, SCL, SDA,

COL[11:0], ROW[7:0]

VIT

-

V

Operating temperature range

Topr

25

+85

℃

www.rohm.com

2012.08 - Rev.B

1/25

Technical Note

BU1852GUW, BU1852GXW

●Electrical characteristics

1. DC characteristics (VDD=1.8V, VDDIO=1.8V, Ta=25℃)

Limits

Typ.

Parameter

Symbol

Unit

Conditions

Min.

Max.

3.6

1

2

※

Input H Voltage1

V_IH1

V_IH2

V_IH3

V_IH4

V_IL1

V_IL2

I_IH1

0.8xVDD

-

V

Input H Voltage2

Input H Voltage3

Input H Voltage4

Input L Voltage1

Input L Voltage2

Input H Current1

Input H Current2

Input L Current

0.8xVDD

0.8xVDDIO

-0.2

VDD+0.2

3.6

VDDIO+0.2

0.2xVDD

0.2xVDDIO

1.0

V

COL[11:0]

ADR

V

3

※

V

-0.2

V

ADR, COL[11:0]

4

V_IN=3.60V^※

-1.0

µA

V

Pull-down/up OFF

5

I_IH2

-1.0

1.0

V_IN=1.80V^※

V_IN=0V

I_IL

-1.0

1.0

Pull-down/up OFF

Output H Voltage1

Output H Voltage2

Output L Voltage1

Output L Voltage2

V_OH1

V_OH2

V_OL1

V_OL2

0.75xVDD

0.75xVDDIO

-

I_OH=-2mA, ROW[7:0]

I_OH=-2mA, COL[11:0]

-

V

6

0.25xVDD

0.25xVDDIO

V

I_OL=2mA, ^※

-

V

I_OL=2mA, COL[11:0]

※1 XINT,SCL,SDA,ROW[7:0]

※2 XRST,XI,TW,PORENB

※3 XINT,SCL,SDA,ROW[7:0],XRST,XI,TW,PORENB

※4 XINT,SCL,SDA,ROW[7:0],COL[11:0]

※5 XRST,XI,TW,PORENB,ADR

※6 XINT,SDA,ROW[7:0]

2. Circuit Current (VDD=1.8V, VDDIO=1.8V, Ta=25℃)

Limits

Typ.

Parameter

Symbol

Unit

Conditions

Min.

-

Max.

1.0

Power Down Current

(VDD)

I_PD

-

µA

XRST=VSS

Power Down Current

(VDDIO)

I_PDIO

-

1.0

3.0

1.0

110

Standby Current1

(VDD)

I_STBY1

I_STBYIO1

I_STBY2

XRST=VDD,

PORENB=VSS,

SCL=VDD, SDA=VDD

Standby Current1

(VDDIO)

Standby Current2

(VDD)

XRST=VDD,

PORENB=VDD,

SCL=VDD, SDA=VDD

Standby Current2

(VDDIO)

I_STBYIO2

-

µA

Operating Current

(VDD)

Internal oscillator is used.

one key is pressed.

I_OP

50

www.rohm.com

2012.08 - Rev.B

2/25

Technical Note

BU1852GUW, BU1852GXW

3. I²C AC Characteristics

(Repeated)

Condition

BIT6

BIT7

Ack

STOP

START

tSU;STA

1/fSCLK

tHIGH

t^LOW

SCL

SDA

tSU;STO

tSU;DAT

tHD;DAT

tBUF

tHD;STA

Fig.1 I²C AC timing

VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS

Limits

Parameter

Symbol

Unit

Conditions

Min.

Typ.

-

Max.

SCL Clock Frequency

Bus free time

f_SCL

t_BUF

-

400

kHz

µs

ns

µs

1.3

0.6

1.3

0.6

100

0

-

(Repeated) START Condition

Setup Time

t_SU;STA

t_HD;STA

t_LOW

(Repeated) START Condition

Hold Time

SCL Low Time

SCL High Time

t_HIGH

Data Setup Time

Data Hold Time

t_SU;DAT

t_HD;DAT

t_SU;STO

STOP Condition Setup Time

0.6

www.rohm.com

2012.08 - Rev.B

3/25

Technical Note

BU1852GUW, BU1852GXW

4. GPIO AC Characteristics

A

NA

State

BIT1

BIT0

SCL

GPIO[7:0](Output)

GPIO[7:0](Input)

tDV

tIV

t^IR

XINT

Fig.2 GPIO AC timing

VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS

Limits

Parameter

Symbol

Unit

Conditions

Min.

-

Typ.

-

Max.

0.8

Output Data Valid Time

Interrupt Valid Time

Interrupt Reset Time

t_DV

t_IV

µs

-

5

t_IR

www.rohm.com

2012.08 - Rev.B

4/25

Technical Note

BU1852GUW, BU1852GXW

5. Startup sequence

tVDD

VDD

tVDD

VDDIO

tRV

tRWAIT

XRST

SCL

tVDD

tI2CWAIT

SDA

Fig.3 Start Sequence timing

VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS

Limits

Typ.

Parameter

Symbol

Unit

Conditions

Min.

-

Max.

5

VDD and VDDIO are ON

at the same time.

VDD Stable Time

t_VDD

t_RWAIT

t_RV

-

ms

µs

1

Reset Wait Time

Reset Valid Time

I²C Wait Time

0

-

XRST controlling^※

10

t_I2CWAIT

※1 Even if XRST port is not used, it operates because Power On Reset is built in.

In this case, connect XRST port with VDD on the set PCB.

Note) At VDD=0V, when SCL port is changed from 0V to 0.5V or more, SCL port pulls the current. It is same in SDA, XINT,

and ROW[7:0] ports of 3V tolerant I/O. (VDDIO=0V in case of COL[11:0] ports)

VDD

0V

3V

0V

Port

(~2kΩPull-up)

0.1 1mA

～

Port

Pull Current

2

3ms

～

Fig.4 Port operating at VDD=0V

www.rohm.com

2012.08 - Rev.B

5/25

Technical Note

BU1852GUW, BU1852GXW

●Package Specification

U1852

Lot No.

Fig.5 Package Specification (VBGA035W040)

www.rohm.com

2012.08 - Rev.B

6/25

Technical Note

BU1852GUW, BU1852GXW

Lot No.

Fig.6 Package Specification (UBGA035W030)

www.rohm.com

2012.08 - Rev.B

7/25

Technical Note

BU1852GUW, BU1852GXW

●Pin Assignment

1

2

3

4

5

6

TESTM0

XI

ROW0

ROW2

ROW4

TW

A

B

C

D

E

F

XRST

VDD

ROW1

PORENB

VDDIO

COL8

ROW3

VSS

ROW6

ROW7

COL2

COL4

COL5

ROW5

COL0

COL1

COL3

ADR

XINT

SDA

VDD

VSS

SCL

COL10

COL11

COL6

COL7

TESTM1

COL9

Fig.7 Pin Diagram (Top View)

●Block diagram

XI

VDD

VDDIO

TESTM[1:0]

Oscillator

ADR

TW

COL[11:0]/

GPIO[19:8]

Key

Encoder

SCL

I²C /3wire

Input

Filter

+

Control

FIFO

Key Scan

/

SDA

GPIO

Control

Interrupt

Logic

XINT

Filter

ROW[7:0]/

GPIO[7:0]

Reset

Gen

XRST

PORENB

Power

on

Reset

VSS

Fig.8 Functional Block Diagram

www.rohm.com

2012.08 - Rev.B

8/25

Technical Note

BU1852GUW, BU1852GXW

●Pin Functional Descriptions

PIN name

I/O

Function

Init

Cell Type

VDD

VDDIO

VSS

-

I

Power supply (Core, I/O except for COL[11:0], ADR)

Power supply (I/O for COL[11:0], ADR)

GND

-

I

-

XRST

XI

Reset(Low Active)

A

I

External clock input (32kHz)

Select protocol

I

TW

I

H:

L:

original 3 wire

I

B

I²C

(TW=L) Select Device Address for I²C

(TW=H) H : Key scan rate 1/2

L : Key scan rate original

ADR

XINT

I

B

E

H(TW=H)

Hi-z(TW=L)

O

Key/GPIO Interrupt

SCL

SDA

I

Clock for serial interface

I

D

F

I/O

I

Serial data inout for serial interface

ROW0

ROW1

ROW2

ROW3

ROW4

ROW5

ROW6

ROW7

COL0

ROW0

ROW1

ROW2

ROW3

ROW4

ROW5

ROW6

ROW7

COL0

COL1

COL2

COL3

COL4

COL5

COL6

COL7

COL8

COL9

COL10

COL11

/ GPIO0

/ GPIO1

/ GPIO2

/ GPIO3

/ GPIO4

/ GPIO5

/ GPIO6

/ GPIO7

/ GPIO8

/ GPIO9

/ GPIO10

/ GPIO11

/ GPIO12

/ GPIO13

/ GPIO14

/ GPIO15

/ GPIO16

/ GPIO17

/ GPIO18

/ GPIO19

I

G

[100kΩ Pull-up]

COL1

COL2

COL3

COL4

L(TW=H)

COL5

I

H

COL6

[150kΩ Pull-down]

(TW=L)

COL7

COL8

COL9

COL10

COL11

PORENB

TESTM0

TESTM1

Power on reset enable (Low Active)

I

B

C

I

1

Test Pins^※

I

※1 Note: All these pins must be tied down to GND in normal operation.

www.rohm.com

2012.08 - Rev.B

9/25

Technical Note

BU1852GUW, BU1852GXW

●I/O equivalence circuit

A

E

I

B

C

D

F

G

H

Fig.9 Equivalent I/O circuit diagram

www.rohm.com

2012.08 - Rev.B

10/25

Technical Note

BU1852GUW, BU1852GXW

●Functional Description

1. Power mode

The device enters the state of Power Down when XRST=”0”. When XRST becomes High after powered, the device

enters the standby state.

Power On Reset

A Power On Reset logic is implemented in this device. Therefore, it will operate correctly even if the XRST port is not

used. In this case, the XRST port must be connected to “1” (VDD), and the PORENB port must be connected to “0”

(VSS). If you don’t want to use Power On reset, you must connect PORENB port to “1” (VDD).

Power Down State

The device enters Power Down state by XRST=”0”. An internal circuit is initialized, and key encoding and 3wire/I²C

interface are invalid. Power On Reset becomes inactive during this state.

Stand-by State

The device enters the stand-by state by setting XRST to "1". In this state, the device is waiting for keys pressed or

I²C communication (TW=”0”). When a key is pressed or I²C start condition, the state will change to operation. Power

On Reset is active in this state if PORENB = “0”.

Operating State

The device enters the operating state by pressing keys. The device will scan the key matrix and encode the key code,

and then the 3wire/I²C interface tries to start communication by driving XINT “0”. See next section for the details.

After communicating with host device, when no keys are pressed, the device returns to the stand-by state. Power On

Reset is active in this state if PORENB=”0”.

2. Protocol of serial interface

I²C

When set to TW=”0”, SCL and SDA are used for I²C communication. Any register shown in section 4 can be

accessed through I²C. Initially, all GPIO ports are set to GPI and pull-up/down ON. When the application requires

GPO or key scan, proper register setting should be done through I²C.

3 wire (Original)

When set to TW=”1”, SCL and SDA are used for original 3wire communication, which is not the standard interface.

Any register shown in section 4 cannot be accessed through 3wire. With TW=”1”, only keyscan and key encoding

are supposed to be performed. GPIO function is inactive. When the application needs kind of complex system (for

instance, GPO+keyscan or GPIO+keyscan…), I2C mode is recommended.

See appendix for the details.

www.rohm.com

2012.08 - Rev.B

11/25

Technical Note

BU1852GUW, BU1852GXW

3. I²C Bus Interface (TW=”0”)

Each function of GPIO is controlled by internal registers. The I²C Slave interface is used to write or read those internal

registers. The device supports 400kHz Fast-mode data transfer rate.

Slave address

Two device addresses (Slave address) can be selected by ADR port.

A7

0

A6

0

A5

0

A4

1

A3

0

A2

1

A1

0

R/W

1/0

ADR=0

ADR=1

0

1

0

1

Data transfer

One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should keep

the value. If SDA changes during SCL = “1”, START condition or STOP condition occur and it is interpreted as a

control signal.

SDA

SCL

Data is valid

SDA is

when SDA is stable variable

Fig.10 Data transfer

START・STOP・Repeated START conditions

When SDA and SCL are “1”, the data isn’t transferred on the I²C bus. If SCL remains “1” and SDA transfers from “1”

to “0”, it means “Start condition” is occurred and access is started. If SCL remains “1” and SDA transfers from “0” to

“1”, it means “Stop condition” is occurred and access is stopped. It becomes repeated START condition (Sr) the

START condition enters again although the STOP condition is not done.

SDA

SCL

S

Sr

P

STOP Condition

START Condition

Repeated START Condition

Fig.11 START・STOP・Repeated START conditions

www.rohm.com

2012.08 - Rev.B

12/25

Technical Note

BU1852GUW, BU1852GXW

Acknowledge

After start condition is occurred, 8 bits data will be transferred. SDA is latched by the rising edge of SCL. After 8 bits

data transfer is finished by the “Master”, “Master” opens SDA to “1”. And then, “Slave” de-asserts SDA to “0” as

“Acknowledge”.

SDA output

from “Master”

Not acknowledge

SDA output

from “Slave”

Acknowledge

SCL

1

2

8

9

S

Clock pulse

START condition

For Acknowledgs

Fig.12 Acknowledge

Writing protocol

Register address is transferred after one byte of slave address with R/W bit. The 3^rdbyte data is written to internal

register which defined by the 2^ndbyte. However, when the register address increased to the final address (18h), it will

be reset to (00h) after the byte transfer.

S

X

0

A

X

X A4 A3 A2 A1 A0 A D7D6D5D4D3D2D1D0 A

D7D6 D5 D4 D3D2D1D0 A

data

P

Slave address

Register address

data

R/W=0(write)

Register address

increment

Register address

increment

Transmit from master

Transmit from slave

A=acknowledge

=not acknowledge

A

S=Start condition

P=Stop condition

Fig.13 Writing protocol

www.rohm.com

2012.08 - Rev.B

13/25

Technical Note

BU1852GUW, BU1852GXW

Reading protocol

After Writing the slave address and Read command bit, the next byte is supposed to be read data. The reading

register address is the next of the previous accessed address. Reading address is incremented one by one. When

the incremented address reaches the last address, the following read address will be reset to (00h).

S X X X X X X X 1 A D7D6D5D4D3D2D1D0 A

D7D6D5D4D3D2D1D0 A P

Salve address

data

R/W=1(Read)

Register Address

increment

Register address

increment

A=acknowledge

Transmit from master

Transmit from slave

A=not acknowledge

S=Start condition

P=Stop condition

Fig.14 Readout protocol

Complex reading protocol

There is the complex reading protocol to read the specific address of registers that master wants to read.

After the specifying the internal register address as writing command, master occurs repeated START condition with

read command. Then, the reading access of the specified registers is supposed to start. The register address

increment is the same as normal reading protocol. If the address is increased to the last, it will be reset to (00h).

S X X X X X X X 0 A X X X A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A

Slave address

Register address

Slave address

R/W=0(write)

R/W=1(read)

D7D6D5D4D3D2D1D0 A

D7D6D5D4D3D2D1D0 A P

data

Register address

increment

Register address

increment

A=acknowledge

A=not aclnowledge

S=Start condition

Transmit from master

P=Stop condition

Sr=Repeated Start condition

Transmit from slave

Fig.15 Complex reading protocol

Illegal access of I²C

When illegal access happens, the data is annulled.

The illegal accesses are as follows.

・The START condition or the STOP condition is continuously generated.

・When the Slave address and the R/W bit are written, repeated START condition or the STOP condition are

generated.

・Repeated START condition or the STOP condition is generated while writing data.

www.rohm.com

2012.08 - Rev.B

14/25

Technical Note

BU1852GUW, BU1852GXW

4. Register configuration

Table1 shows the register map and Table2 indicates each function in the corresponding bit. Only when TW is “0”, these

registers can be accessed with I²C. By making XRST “0”, the setting register value will be initialized shown in following

register map.

Table1 Register map

Address Init

Type

R/W

-

D7

D6

D5

D4

D3

reserved

KS_RATE *¹

KS_C11

KS_C3

KS_R3

IOD19

D2

D1

D0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

00h

11h

00h

FFh

RESET

reserved

KS_C7

KS_R7

reserved

IOD15

reserved

CLKSEL

reserved

KS_C6

KS_R6

reserved

IOD14

reserved

KS_C5

KS_R5

reserved

IOD13

reserved

KS_C4

KS_R4

reserved

IOD12

KS_C10

KS_C2

KS_R2

IOD18

KS_C9

KS_C1

KS_R1

IOD17

IOD9

KS_C8

KS_C0

KS_R0

IOD16

IOD8

IOD11

IOD10

IOD7

IOD6

IOD5

IOD4

IOD3

IOD2

IOD1

IOD0

reserved

INTEN15

INTEN7

reserved

GPO15

GPO7

reserved

INTEN14

INTEN6

reserved

GPO14

GPO6

reserved

INTEN13

INTEN5

reserved

GPO13

GPO5

reserved

INTEN12

INTEN4

reserved

GPO12

GPO4

INTEN19

INTEN11

INTEN3

GPO19

GPO11

GPO3

INTEN18

INTEN10

INTEN2

GPO18

GPO10

GPO2

INTEN17

INTEN9

INTEN1

GPO17

GPO9

INTEN16

INTEN8

INTEN0

GPO16

GPO8

GPO1

GPO0

reserved

XPD15

XPU7

reserved

XPD14

XPU6

reserved

XPD13

XPU5

reserved

XPD12

XPU4

XPD19

XPD11

XPD18

XPD10

XPU2

XPD17

XPD9

XPD16

XPD8

XPU3

XPU1

XPU0

reserved

INTFLT

reserved

R

keycode

R

reserved

GPI15

reserved

GPI14

reserved

GPI13

Reserved

GPI12

reserved

GPI19

GPI11

GPI3

reserved

GPI18

GPI10

GPI2

fifo_ovf

GPI17

GPI9

fifo_ind

GPI16

GPI8

R

GPI7

GPI6

GPI5

GPI4

GPI1

GPI0

*1 Do not write more than 0x7F in KS_RATE

Do not write “1” in the reserved resisters. The write commands to 13h-18h addresses’ registers are ignored.

※

www.rohm.com

2012.08 - Rev.B

15/25

Technical Note

BU1852GUW, BU1852GXW

Table2 Register function

Symbol Address

Description

Software reset. All registers are initialized by writing "1".

This register value is returned to "0" automatically.

Exceptionally, GPIn register is not initialized.

RESET

CLKSEL

KS_RATE

KS_Cx

00h

01h

“1” : External clock from XI is used.

“0” : Internal CR oscillator is used.

02h

Key scan rate control

When set to “1”, port is used as COLx for key scan.

When set to “0”, it is used as GPIO port.

03h-04h

05h

When set to “1”, port is used as ROWy for key scan.

When set to “0”, it is used as GPIO port.

KS_Ry

GPIOn’s IO direction.

When set to “1”, GPIOn direction is output. When set to “0”, GPIOn direction is input.

IODn

06h-08h

INTENn 09h-0Bh Interrupt of GPIOn port is enabled by "1". It is masked by "0".

GPOn

XPDn

0Ch-0Eh Output value of GPIOn port.

0Fh-10h Pull-down of GPIOn port is on by "0" and off by "1". GPIOn should be input.

XPUn

11h

12h

14h

15h

Pull-up of GPIOn port is on by "0" and off by "1". GPIOn should be input.

“1” : interrupt filter ON (1us pulse rejection)

“0” : interrupt filter OFF (bypass)

INTFLT

keycode

fifo_ind

fifo_ovf

GPIn

Keycode that Host can read currently

When there are keycode data in FIFO, fifo_ind is set to “1”. “0” means fifo empty.

When FIFO overflow happens, fifo_ovf is set to “1”. Initially “0” is stored.

Input value of GPIOn port. Write command is ignored.

16h-18h When interrupt happens, these registers must be read.

Each bit is valid only when WRSELn=0(input). The bits at WRSELn=1(output) are fixed.

※"n" is the number of GPIO[19:0] ports. “x” is the number of COL[11:0]. “y” is the number of ROW[7:0].

www.rohm.com

2012.08 - Rev.B

16/25

Technical Note

BU1852GUW, BU1852GXW

5. GPIO function

GPIO configuration

When some ports of COL[11:0] and ROW[7:0] are needed to be used as GPIO, TW must be “0”. Then, set the proper

value in the appropriate registers through I²C. ROW[7:0] and COL[11:0] correspond to GPIO[7:0] and GPIO[19:8],

respectively. By default, GPIO[19:0] ports are set to input(IODn=0) and Pull-up/down ON(XPUn/XPDn=0).

(n is the number of GPIO[19:0] ports.)

Refer to the following for the configuration of GPIO.

Table3 GPIO configuration

Register

State of GPIO

GPOn

IODn

XPDn/XPUn

Input, Pull-up/down ON

Input, Pull-up/down OFF

Output, H drive

*

0

1

0

1

*

1

0

Output, L drive

*

1

Output, Hi-Z^※

1

※1 It is required to pull-up to more than VDD potential.

How to deal with GPIO ports which are not using

When set to output, GPIO port must be open.

When set to input, don’t make GPIO port open. It must be forced by "0" or Pull-up/down on.

Interrupt configuration

The initial XINT output is Hi-Z, so it should be pull-up. When interrupt is generated, XINT port outputs L. By default,

interrupt is masked with INTEN register "0". The bit to be used is made "1", and then the mask is released. In this

case, IOD register should be "0"(input).

Write to GPIO port

After master sets the internal register address for write, the data is sent from MSB.

After Acknowledge is returned, the value of each GPIO port will be changed.

Write Configuration Pulse, which is trigger of changing registers, is generated at the timing of Acknowledge.

SCL

SDA

1

2

3

4

5

6

7

8

9

S

X

0

Ack MSB

Reg Address

LSB Ack MSB

Data1 (GPO[7:0])

LSB Ack

P

Acknowledge From Slave

Stop Condition

Start Condition

Write

Acknowledge From Slave

Write Configuration

Pulse

Data1

Valid

GPIO[7:0]

tDV

SCL

SDA

1

2

3

4

5

6

7

8

9

S

X

0

Ack MSB

Reg Address

LSB Ack MSB

Data1 (GPO[7:0])

LSB Ack MSB

WRSEL = Write Mode

LSB Ack

P

Acknowledge From Slave

Stop Condition

Start Condition

Write

Acknowledge From Slave

Write Configuration

Pulse

Data1

Valid

GPIO[7:0]

tDV

Fig.16 Write to GPIO port

www.rohm.com

2012.08 - Rev.B

17/25

Technical Note

BU1852GUW, BU1852GXW

Read from GPIO port

After writing of the Slave address and R/W bits by master, reading GPIO port procedure begins.

All ports’ status that is set to the input by IOD registers are taken into the GPI register when ACK is sent.

SCL

SDA

1

2

3

4

5

6

7

8

9

D1 D1 D1 D1 D1 D1 D1 D1

[7] [6] [5] [4] [3] [2] [1] [0]

S

X

1

Ack

NA

P

Stop Condition

Start Condition

Read Acknowledge From Slave

No Acknowledge From Master

GPI[7:0] Reg

GPIO[7:0]

D1

D2

Fig.17 Read from GPIO port

Interrupt Valid/Reset

When the GPIO interrupt is used, some of INTEN registers are required to be written to "1".

When current GPIO port status becomes different from the value of the GPIn registers, XINT port is changed from

"1" to "0". After reading GPI register, it will return to "1".

When Master detects interrupt, Master must read all GPI registers that is set to input(IODn=0), even if XINT is

changed while reading. It is because BU1852 does not latch the XINT status. Fig.18 shows one of the example of

using only ROW[7:0] as GPI. In this case, Master reads only 18h register immediate after detecting XINT.

XINT cannot distinguish whether just one port is different or multi ports are different from the previous value. Master

is necessary to store the previous GPI register value and compare it with the current value after XINT is asserted.

SCL

SDA

1

2

3

4

5

6

7

8

9

S

X

1

Ack MSB

Data2 (GPI[7:0])

LSB NA

P

Stop Condition

Start Condition

Read

Acknowledge From Slave

No Acknowledge From Master

Data3

GPIOn

GPIn Reg

XINT

Data1

Data2

Data1

Data2

t

IV

t

IR

tIV

tIR

Fig.18 Interrupt Valid/Reset (Example : ROW[7:0] as GPI with interrupt)

www.rohm.com

2012.08 - Rev.B

18/25

Technical Note

BU1852GUW, BU1852GXW

6. Key code Assignment

Table 4 shows the key code assignment. These key codes are sent through 3wire or I²C corresponding to the pushed

or released keys.

Table4 Key codes

ROW0

0x01

0x81

0x02

0x82

0x03

0x83

0x04

0x84

0x05

0x85

0x06

0x86

0x07

0x87

0x08

0x88

ROW1

0x11

0x91

0x12

0x92

0x13

0x93

0x14

0x94

0x15

0x95

0x16

0x96

0x17

0x97

0x18

0x98

ROW2

0x21

0xA1

0x22

0xA2

0x23

0xA3

0x24

0xA4

0x25

0xA5

0x26

0xA6

0x27

0xA7

0x28

0xA8

ROW3

0x31

0xB1

0x32

0xB2

0x33

0xB3

0x34

0xB4

0x35

0xB5

0x36

0xB6

0x37

0xB7

0x38

0xB8

ROW4

0x41

0xC1

0x42

0xC2

0x43

0xC3

0x44

0xC4

0x45

0xC5

0x46

0xC6

0x47

0xC7

0x48

0xC8

ROW5

0x51

0xD1

0x52

0xD2

0x53

0xD3

0x54

0xD4

0x55

0xD5

0x56

0xD6

0x57

0xD7

0x58

0xD8

ROW6

0x61

0xE1

0x62

0xE2

0x63

0xE3

0x64

0xE4

0x65

0xE5

0x66

0xE6

0x67

0xE7

0x68

0xE8

ROW7

0x71

0xF1

0x72

0xF2

0x73

0xF3

0x74

0xF4

0x75

0xF5

0x76

0xF6

0x77

0xF7

0x78

0xF8

M

B

COL0

COL1

COL2

COL3

COL4

COL5

COL6

COL7

M

B

M

B

M

B

M

B

M

B

M

B

M

B

M

B

0x09

0x89

0x0A

0x8A

0x0B

0x8B

0x0C

0x8C

0x19

0x99

0x1A

0x9A

0x1B

0x9B

0x1C

0x9C

0x29

0xA9

0x2A

0xAA

0x2B

0xAB

0x2C

0xAC

0x39

0xB9

0x3A

0xBA

0x3B

0xBB

0x3C

0xBC

0x49

0xC9

0x4A

0xCA

0x4B

0xCB

0x4C

0xCC

0x59

0xD9

0x5A

0xDA

0x5B

0xDB

0x5C

0xDC

0x69

0xE9

0x6A

0xEA

0x6B

0xEB

0x6C

0xEC

0x79

0xF9

0x7A

0xFA

0x7B

0xFB

0x7C

0xFC

COL8

COL9

M

B

M

B

COL10

COL11

M

B

M : Make Key (the code when the key is pressed)

B : Break Key (the code when the key is released)

www.rohm.com

2012.08 - Rev.B

19/25

Technical Note

BU1852GUW, BU1852GXW

7. Ghost Key Rejection

Ghost key is an inevitable phenomenon as long as key-switch matrices are used. When three switches located at the

corners of a certain matrix rectangle are pressed simultaneously, the switch that is located at the last corner of the

rectangle (the ghost key) also appears to be pressed, even though the last key is not pressed. This occurs because the

ghost key switch is electrically shorted by the combination of the other three switches (Fig.19). Because the key

appears to be pressed electrically, it is impossible to distinguish which key is the ghost key and which key is pressed.

The BU1852 solves the ghost key problem to use the simple method. If BU1852 detects any three-key combination

that generates a fourth ghost key, and BU1852 does not report anything, indicating the ghost keys are ignored. This

means that many combinations of three keys are also ignored when pressed at the same time. Applications requiring

three-key combinations (such as <Ctrl><Alt><Del>) must ensure that the three keys are not wired in positions that

define the vertices of a rectangle (Fig. 20). There is no limit on the number of keys that can be pressed simultaneously

as long as the keys do not generate ghost key events.

PRESSED KEY

EVENT

GHOST-KEY

EVENT

KEY-SWITCH MATRIX

Fig.19 Ghost key phenomenon

EXAMPLES OF VALID THREE-KEY COMBINATIONS

KEY-SWITCH MATRIX

Fig.20 Valid three key combinations

www.rohm.com

2012.08 - Rev.B

20/25

Technical Note

BU1852GUW, BU1852GXW

8. Recommended flow

Fig.21 shows the recommended flow when TW=0(I²C protocol is selected).

Sequence

Related registers

power on

Reset release

clock select

01h : CLKSEL

02h : KS_RATE

determine key scan rate

03h-04h : KS_C[11:0]

05h : KS_R[7:0]

assign each port

to key scan and GPIO

06h-08h : IOD[19:0]

detemine GPIO direction

GPI interrupt setting

09h-0Bh : INTEN[19:0]

12h : INTFLT

Control GPO port

or

Monitor “XINT”

0Ch-0Eh : GPO[19:0]

14h-18h : Read registers

Fig.21 Recommended flow and related registers

Forbidden operation:

--- Dynamic change of TW (I²C/3wire protocol should be fixed)

--- Dynamic assignment change of keyscan and GPIO (should be determined initially)

--- Dynamic change of keyscan rate (should be determined initially)

--- Dynamic change of CLKSEL (should be determined initially)

www.rohm.com

2012.08 - Rev.B

21/25

Technical Note

BU1852GUW, BU1852GXW

●Application circuit example

1.8V

3.0V

0.1uF

1.8V

COL11

COL10

COL9

COL8

COL7

COL6

COL5

COL4

COL3

COL2

COL1

COL0

GPO

GPI

XRST

XI

from/to 3.0V device

INT

XINT

MPU

SCL

SDA

SCL

SDA

ROW0

ROW1

ROW2

ROW3

ROW4

ROW5

ROW6

ROW7

to Other I²C Devices

Fig.22 Application circuit example

www.rohm.com

2012.08 - Rev.B

22/25

Technical Note

BU1852GUW, BU1852GXW

●Appendix

1. 3wire Interface (TW=”1”)

XINT

SCL

invalid

Bit7

Bit6

Bit5

Bit0

SDA

Start bit

sent by host device

sent by BU1852

Fig.23 3wire protocol

Figure 23 shows the original 3wire protocol of BU1852. When this 3wire protocol is used, TW must be “1”. Note that

this 3wire interface is completely different from I²C and other standard bus interface.

Procedure

1. When BU1852 detects key events, XINT interrupt is generated to host with driving Low.

2. After the host detects XINT interrupt, the host is supposed to send start bit.

3. After BU1852 detects start bit, the 8bit data (key code) transmission on SDA will start synchronized with the

rising edge of SCL clock signal, which is sent from the host.

4. 8 bit data are followed by “0” (9^thbit is always “0”), and then BU1852 drives High on XINT line.

See also section “3wire interface AC characteristics”.

www.rohm.com

2012.08 - Rev.B

23/25

Technical Note

BU1852GUW, BU1852GXW

2. 3wire Interface AC characteristics

State

START

BIT 7

BIT 6

BIT 0

"0"

t_{TWLOW ;INT}

t_{TWS U;STA}

t_{TWHD ;INTE}

XINT

t_{TWH IGH ;}

CLK

1/f_{TWS CLK}

t_{TWL OW ;}

CLK

SCL

SDA

t_{TWH D;DAT}

Fig.24 3wire interface AC timing

VDD=1.8V, VDDIO=1.8V,Topr=25℃,TW=VDD

t_{TWH D;STA}

Limits

Typ.

Parameter

Symbol

Unit

Conditions

Min.

-

Max.

21.5

SCL Clock Frequency

f_TWSCLK

t_TWSU;STA

t_TWHD;STA

t_TWLOW;CLK

t_TWHIGH;CLK

t_TWHD;DAT

t_TWHD;INTE

t_TWLOW;INT

-

kHz

ms

µs

START Condition

Setup Time

0.030

20

-

500

START Condition

Hold Time

-

SCL Low Time

SCL High Time

Data Hold Time

XINT End Hold

XINT Low Time

23

-

µs

23

-

µs

0.1

-

1.0

10.2

1350

µs

1.35

500

µs

800

ms

www.rohm.com

2012.08 - Rev.B

24/25

Technical Note

BU1852GUW, BU1852GXW

●Ordering part number

B U

1

8

5

2

G U W

-

E

2

Part No.

Package

GUW: VBGA035W040

GXW: UBGA035W030

Packaging and forming specification

E2: Embossed tape and reel

VBGA035W040

4.0 ± ±0.1

1PIN MARK

Tape

Embossed carrier tape (with dry pack)

2500pcs

Quantity

E2

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

(

)

S

0.08

S

A

P=0.5×5

0.5

0.75 ± ±0.1

φ

35- 0.295± 0.05

F

φ

M

0.05

S AB

B

E

D

C

B

A

Direction of feed

1pin

1

2 3 4 5 6

Reel

(Unit : mm)

Order quantity needs to be multiple of the minimum quantity.

∗

UBGA035W030

1PIN MARK

3.0± 0.1

Tape

Embossed carrier tape (with dry pack)

Quantity

1000pcs

E2

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

S

(

)

0.08

0.5± 0.1

35- 0.2± 0.05

S

P=0.4×5

0.4

A

φ

0.05 A

B

F

E

D

C

B

A

Direction of feed

1pin

1

2 3 4 5 6

Reel

(Unit : mm)

Order quantity needs to be multiple of the minimum quantity.

∗

www.rohm.com

2012.08 - Rev.B

25/25

Notice

N o t e s

No copying or reproduction of this document, in part or in whole, is permitted without the

consent of ROHM Co.,Ltd.

The content speciﬁed herein is subject to change for improvement without notice.

The content speciﬁed herein is for the purpose of introducing ROHM's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the speciﬁcations,

which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein

illustrate the standard usage and operations of the Products. The peripheral conditions must

be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information speciﬁed in this document.

However, should you incur any damage arising from any inaccuracy or misprint of such

information, ROHM shall bear no responsibility for such damage.

The technical information speciﬁed herein is intended only to show the typical functions of and

examples of application circuits for the Products. ROHM does not grant you, explicitly or

implicitly, any license to use or exercise intellectual property or other rights held by ROHM and

other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the

use of such technical information.

The Products speciﬁed in this document are intended to be used with general-use electronic

equipment or devices (such as audio visual equipment, ofﬁce-automation equipment, commu-

nication devices, electronic appliances and amusement devices).

The Products speciﬁed in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard

against the possibility of physical injury, ﬁre or any other damage caused in the event of the

failure of any Product, such as derating, redundancy, ﬁre control and fail-safe designs. ROHM

shall bear no responsibility whatsoever for your use of any Product outside of the prescribed

scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or

system which requires an extremely high level of reliability the failure or malfunction of which

may result in a direct threat to human life or create a risk of human injury (such as a medical

instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-

controller or other safety device). ROHM shall bear no responsibility in any way for use of any

of the Products for the above special purposes. If a Product is intended to be used for any

such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology speciﬁed herein that may

be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to

obtain a license or permit under the Law.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact us.

ROHM Customer Support System

http://www.rohm.com/contact/

www.rohm.com

R1120A


型号：	BU1852GXW-E2
厂家：	ROHM
描述：	Keyencoder IC Keyencoder IC
文件：	总26页 (文件大小：492K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BU1852GXW-E2 [ROHM]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E