BU8254KVT [ROHM]
35bit LVDS Transmitter 35:5 Serializer; 35bit LVDS发射器35 ： 5串行
| 型号： | BU8254KVT |
| 厂家： | 
ROHM |
| 描述： | 35bit LVDS Transmitter 35:5 Serializer |
| 文件： | 总20页 (文件大小：939K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LVDS Interface ICs
35bit LVDS Transmitter
35:5 Serializer
BU8254KVT
●Description
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and
number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number
by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI.
●Features
■35bits data of parallel LVCMOS level inputs are converted to five channels of LVDS data stream.
■30bits of RGB data and 5bits of timing and control data(HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted
up to 784Mbps effective rate per LVDS channel.
■Support clock frequency from 8MHz up to 112MHz.
■Support consumer video format including 480i, 480P, 720P and 1080i as well.
■Clock edge selectable
■Power down mode
■Support spread spectrum clock generator.
■Support reduced swing LVDS for low EMI.
■30bit LVDS receiver is recommended to use BU8255KVT.
●Applications
Flat Panel Display
●Precaution
■This chip is not designed to protect from radioactivity.
■The chip is made strictly for the specific application or equipment.
Then it is necessary that the unit is measured as need.
■This document may be used as strategic technical data which subjects to COCOM regulations.
Status of this document
The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If there is any uncertainty in translation version of this document, official version takes priority.
Jun.2008
●Block Diagram
LVCMOS Input
LVDS Output
＋
－
CLKIN
(8～112MHz)
TCLK P/N
(8～112MHz)
PLL
7
7
7
7
7
＋
－
Parallel to Serial
Parallel to Serial
Parallel to Serial
Parallel to Serial
Parallel to Serial
TA P/N
TB P/N
TC P/N
TD P/N
TE P/N
TA6-TA0
TB6-TB0
TC6-TC0
TD6-TD0
TE6-TE0
＋
－
＋
－
＋
－
＋
－
RS
RF
XRST
Figure-1 Block Diagram
2 / 20
●TQFP64V Package Outline and Specification
Product No.
BU8254KVT
Lot No.
1PIN MARK
Figure–2 TQFP64V Package Outline and Specification
3 / 20
●Pin configuration
TB6
TC0
VDD
TC1
TC2
TC3
TC4
GND
TC5
TC6
TDO
RF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LVDS GND
TAN
32
31
30
29
28
27
26
25
TAP
TBN
TBP
LVDS VDD
LVDS GND
TCN
64-Pin TQFP
(Top View)
TCP
24
23
22
21
20
19
18
17
TCLKN
TCLKP
TDN
TDP
TD1
TD2
TD3
TD4
TEN
TEP
LVDS GND
Figure-3 Pin Diagram (Top View)
4 / 20
●Pin Description
Table 1 : Pin Description
Pin Name
Pin No.
30,31
Type
Descriptions
LVDS
OUT
LVDS
TAP, TAN
TBP, TBN
TCP, TCN
TDP, TDN
TEP, TEN
28,29
24,25
20,21
18,19
22,23
OUT
LVDS
OUT
LVDS
LVDS data out.
LVDS clock out.
Pixel data inputs.
OUT
LVDS
OUT
LVDS
TCLKP,
TCLKN
OUT
TA0～TA6 33,34,35,36,37,38,40
TB0～TB6 41,42,44,45,46,48,49
TC0～TC6 50,52,53,54,55,57,58
IN
IN
IN
IN
IN
IN
TD0～TD6
TE0～TE6
XRST
59,61,62,63,64,1,3
4,5,6,8,9,11,16
13
H : Normal operation,
L : Power down (all outputs are Hi-Z)
LVDS swing mode, VREF *1select.
Small Swing
LVDS
Swing
RS
Input
Support
N/A
RS-VREF
N/A
VDD
0.6～1.4V
GND
350mV
350mV
200mV
RS
43
IN
*1 VREF is Input Reference Voltage.
Input clock triggering edge select.
H : Rising edge, L : Falling edge.
Power supply pins for LVCMOS inputs and
digital core.
RF
60
IN
VDD
51,7
Power
IN
CLKIN
12
Clock input.
Ground pins for LVCMOS inputs and digital
core.
GND
2,10,39,47,56
Ground
Power
Ground
Power
Ground
LVDS VDD
LVDS GND
PLLVDD
PLLGND
27
17,26,32
15
Power supply pins for LVDS outputs.
Ground pins for LVDS outputs.
Power supply pin for PLL core.
Ground pins for PLL core.
14
5 / 20
●Electrical characteristics
■Rating
Table 2 : Absolute Maximum Rating
Parameter
Rating
Symbol
Units
Min
-0.3
-0.3
-0.3
-55
Max
4.0
Supply Voltage
Input Voltage
VDD
VIN
V
V
VDD+0.3
VDD+0.3
125
Output Voltage
VOUT
Tstg
V
Storage Temperature Range
℃
Table 3 : Package Power
PACKAGE
Power Dissipation (mW)
De-rating (mW/℃) *1
700
7.0
TQFP64V
1000*2
10.0*2
*1:At temperature Ta >25℃
*2:Package power when mounting on the PCB board.
The size of PCB board
:70×70×1.6（mm3）
The material of PCB board :The FR4 glass epoxy board.(3% or less copper foil area)
(It is recommended to apply the above package power requirement to PCB board
when the small swing input mode is used)
Table 4 : Recommended Operating Conditions
Rating
Units
Conditions
Symbol
Parameter
Min
3.0
Typ
3.3
Max
3.6
Supply Voltage
VDD
V
VDD,LVDSVDD,PLLVDD
-20
0
-
-
85
70
℃
℃
Clock frequency from 8MHz up to 90MHz
Cock frequency from 90MHz up to 112MHz
Operating
Topr
Temperature Range
6 / 20
■DC characteristics
Table 5 : LVCMOS DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～85℃）
Rating
Symbol
Parameter
Units
Conditions
Min
VDD×0.8
GND
Typ
Max
VDD
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Small Swing Voltage
V
V
-
exclude RS pin
-
VDD×0.2
VDD
VIHRS
VILRS
VDD×0.8
GND
1.2
-
RS pin
0.2
-
-
*1
VDDQ
2.8
V
VREF
Input Reference Voltage
VDDQ/2
Small Swing(RS=VDDQ/2)
VREF=VDDQ/2
-
-
-
-
Small Swing High Level
Input Voltage
VDDQ/2
+200mV
*2
VSH
V
-
Small Swing Low Level
Input Voltage
VDDQ/2
*2
VSL
V
VREF=VDDQ/2
0V≤VIN≤VDD
-
-
-
-200mV
IINC
Input Current
±10
μA
-
*1: VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage.
*2: Small swing signal is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0] TE[6:0], CLKIN.
Table 6 : LVDS Transmitter DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～85℃）
Rating
Symbol
Parameter
Units
Conditions
Min
250
Typ
350
Max
450
mV
mV
Normal swing RS=VDD
Differential Output Voltage
RL=100Ω
VOD
100
-
200
-
300
35
Reduced swing RS=GND
Change in VOD between
mV
V
ΔVOD
VOC
complementary output states
Common Mode Voltage
1.125
-
1.25
-
1.375
35
RL=100Ω
Change in VOC between
mV
mA
μA
ΔVOC
IOS
complementary output states
Output Short Circuit Current
Output TRI-STATE Current
-24
±10
-
-
VOUT=0V, RL=100Ω
XRST=0V,
VOUT=0V to VDD
IOZ
-
-
7 / 20
■Supply Current
Table 7 : Supply Current
Rating
Symbol
Parameter
Units
mA
Conditions
Typ
57
Max
-
RL=100Ω,CL=5pF
VDD=3.3V,RS=VDD
Gray Scale Pattern
RL=100Ω,CL=5pF
VDD=3.3V,RS=GND
Gray Scale Pattern
f=85MHz
f=85MHz
f=85MHz
f=85MHz
Transmitter Supply
Current
ITCCG
42
62
-
-
mA
mA
RL=100Ω,CL=5pF
VDD=3.3V,RS=VDD
Worst Case pattern
RL=100Ω,CL=5pF
VDD=3.3V,RS=GND
Worst Case pattern
Transmitter Supply
Current
ITCCW
45
-
mA
Transmitter Power Down
Supply Current
ITCCS
10
μA
XRST=L
-
8 / 20
Gray Scale Pattern
CLKOUT
Rx0
Rx1
Rx2
Rx3
Rx4
Rx5
Rx6
X=A,B,C,D,E
Figure-4 Gray scale pattern
Worst Case Pattern (Maximum Power condition)
CLKOUT
Rx0
Rx1
Rx2
Rx3
Rx4
Rx5
Rx6
X=A,B,C,D,E
Figure-5 Worst Case Pattern
9 / 20
■AC characteristics
Table 8 : Switching Characteristics
Parameter
Symbol
tTCIT
tTCP
tTCH
tTCL
Min
Typ
-
Max
5.0
Units
ns
CLK IN Transition time
CLK IN Period
-
8.93
0.35tTCP
0.35tTCP
-
-
125.0
0.65tTCP
0.65tTCP
-
ns
CLK IN High Time
0.5tTCP
0.5tTCP
tTCP
-
ns
CLK IN Low Time
ns
CLK IN to TCLK+/-Delay
LVSMOS Data Set up to CLK IN
LVCMOS Data Hold from CLK IN
LVDS Transition Time
tTCD
tTS
ns
2.5
-
ns
tTH
0
-
-
ns
tLVT
-
0.6
1.5
ns
tTOP1
Output Data Position 0
Output Data Position 1
-0.2
0.0
+0.2
ns
tTCP -0.2
7
tTCP +0.2
7
tTCP
7
tTOP0
tTOP6
tTOP5
tTOP4
tTOP3
ns
ns
ns
ns
ns
tTCP
Output Data Position 2
Output Data Position 3
Output Data Position 4
Output Data Position 5
2
3
4
5
6
tTCP -0.2
7
2
2
3
4
5
6
tTCP +0.2
7
7
tTCP
7
tTCP -0.2
7
3
4
5
6
tTCP +0.2
7
tTCP -0.2
7
tTCP +0.2
7
tTCP
7
tTCP -0.2
7
tTCP +0.2
7
tTCP
7
tTCP -0.2
7
tTCP +0.2
7
tTCP
7
tTOP2
tTPLL
Output Data Position 6
ns
Phase Locked Loop Set Time
-
-
10.0
ms
10 / 20
●AC Timing
■AC Timing Diagrams
LVCMOS Input
90%
10%
90%
10%
CLK IN
tTCIT
tTCIT
LVDS Output
Vdiff=(TAP)-(TAN)
80%
20%
80%
20%
TAP
Vdiff
CL
RL
TAN
tLVT
tLVT
LVDS Output Load
LVCMOS Input
tTCP
tTCH
RF=L
RF=H
CLKIN
VDD/2
VDD/2
VDD/2
tTCL
tTH
tTS
VDD/2
VDD/2
Tx0-Tx6
tTCD
TCLKP
TCLKN
VOC
Figure-6 AC Timing Diagrams
11 / 20
■Small Swing Inputs
tTCP
tTCH
RF=L
RF=H
CLKIN
VDDQ/2
V
DDQ/2
VDDQ/2
VREF
tTCL
tTH
tTS
VDDQ
VDDQ/2
VDDQ/2
VREF
GND
Tx0-Tx6
tTCD
TCLKP
TCLKN
VOC
Figure-7 Small Swing Inputs
12 / 20
■AC Timing Diagrams
LVDS Output
TCLK OUT
(Differential)
TA6
TB6
TC6
TD6
TE6
TA5
TB5
TC5
TD5
TE5
TA4
TB4
TC4
TD4
TE4
TA3
TB3
TC3
TD3
TE3
TA2
TB2
TC2
TD2
TE2
TA1
TB1
TC1
TD1
TE1
TA0
TB0
TC0
TD0
TE0
TAP/N
TBP/N
TCP/N
TDP/N
TEP/N
Previous Cycle
tTOP1
Next Cycle
tTOP0
tTOP6
tTOP5
tTOP4
tTOP3
tTOP2
Figure-8 AC Timing Diagrams
■Phase Locked Loop Set Time
2.0V
XRST
3.6V
3.0V
VDD
tTPLL
CLKIN
Vdiff=0V
TCLKP/N
Figure-9 Phase Locked Loop Set Time
13 / 20
●About the Power On Reset
Power On Reset is not mandatory for this device.
（The PD pin should be set to high level when Power On Reset procedure is not used.）
VDD
XRST
BU8254KVT
Figure–10 Terminal connection when Power On Reset
is not used
However, Power On Reset procedure is strongly recommend for internal logic initialization by following
two methods.
① The method of using CR circuit.
② The method of using external specific IC.
It is recommend to do enough examination for target application.
V DD
V DD
VDD
schottky barrier diode
10KΩ
+
V
T
XRST
220Ω
2.2μF
XRST
Be careful of temperature of
the capacitor especially over
and again.
Internal Reset
td
td is approximately equal to 20ms when the left RC coleus are applied.
B characteristic ceramics and
polymer aluminum
are recommended.
Figure–11 Power On Reset by external a CR circuit
V DD
V DD
Detection voltage
220KΩ
VDD
VDD
power on IC
(open drain
output)
XRST
+
V
T
XRST
VOUT
Internal Reset
0.1μF
GND
B Characteristic
ceramics.
td
Figure–12 Power On Reset by specific IC
14 / 20
●10bit LVCMOS Level Input
Example:
BU7986KUT ： Falling edge
Normal swing
Dual-in / Dual-out mode
VDD
0.1uF
0.01uF
VDD
LVDS VDD
LVDS GND
0.1uF
0.01uF
GND
R1[9:0]
R1[9:0]
G1[9:0]
B1[9:0]
R2[9:0]
G2[9:0]
B2[9:0]
HSYNC
G1[9:0]
B1[9:0]
R2[9:0]
G2[9:0]
TA1N
TA1P
TB1N
TB1P
TC1N
TC1P
TCLKN
TCLKP
TD1N
TD1P
TE1N
TE1P
TA2N
TA2P
TB2N
TB2P
TC2N
TC2P
TCLKN
TCLKP
TD2N
TD2P
TE2N
TE2P
B2[9:0]
HSYNC
VSYNC
DE
VSYNC
DE
CLK_IN
CLK_IN
CONT11
CONT12
CONT21
CONT22
BU7986KUT
CONT11
CONT12
CONT21
CONT22
TEST[3:0]
MODE0
MODE1
XRST
XRST
VDD
RS *1
R/F
100Otwist
pair Cable
or
PCB(Transmitter)
PCB trace
*1 :
If RS pin is tied to VDD, LVDS swing is 350m V.
If RS pin is tied to GND, LVDS swing is 200m V.
15 / 20
●10bit LVCMOS Level Input
Example:
BU7986KUT ： Falling edge
Normal swing
Dual-in / Single-out mode
VDD
0.1uF
0.01uF
VDD
LVDS VDD
LVDS GND
0.1uF
0.01uF
GND
R1[9:0]
R1[9:0]
G1[9:0]
B1[9:0]
R2[9:0]
G2[9:0]
B2[9:0]
HSYNC
G1[9:0]
B1[9:0]
R2[9:0]
G2[9:0]
TA1N
TA1P
TB1N
TB1P
TC1N
TC1P
TCLKN
TCLKP
TD1N
TD1P
TE1N
TE1P
TA2N
TA2P
TB2N
TB2P
TC2N
TC2P
TCLKN
TCLKP
TD2N
TD2P
TE2N
TE2P
B2[9:0]
HSYNC
VSYNC
DE
VSYNC
DE
CLK_IN
CLK_IN
CONT11
CONT12
CONT21
CONT22
BU7986KUT
CONT11
CONT12
CONT21
CONT22
TEST[3:0]
MODE0
VDD
MODE1
XRST
XRST
OPEN
VDD
RS *1
R/F
100Otwist
pair Cable
or
PCB(Transmitter)
PCB trace
*1 :
If RS pin is tied to VDD, LVDS swing is 350m V.
If RS pin is tied to GND, LVDS swing is 200m V.
16 / 20
●10bit LVCMOS Level Input
Example:
BU7986KUT ： Falling edge
Normal swing
Single-in / Dual-out mode
VDD
0.1uF
0.01uF
VDD
LVDS VDD
LVDS GND
0.1uF
0.01uF
GND
R1[9:0]
R1[9:0]
G1[9:0]
B1[9:0]
G1[9:0]
B1[9:0]
R2[9:0]
TA1N
TA1P
TB1N
TB1P
TC1N
TC1P
TCLKN
TCLKP
TD1N
TD1P
TE1N
TE1P
TA2N
TA2P
TB2N
TB2P
TC2N
TC2P
TCLKN
TCLKP
TD2N
TD2P
TE2N
TE2P
G2[9:0]
B2[9:0]
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
BU7986KUT
CLK_IN
CONT11
CONT12
CLK_IN
CONT11
CONT12
CONT21
CONT22
TEST[3:0]
MODE0
VDD
MODE1
XRST
XRST
VDD
RS *1
R/F
100Otwist
pair Cable
or
PCB(Transmitter)
PCB trace
*1 :
If RS pin is tied to VDD, LVDS swing is 350m V.
If RS pin is tied to GND, LVDS swing is 200m V.
17 / 20
●10bit LVCMOS Level Input
Example:
BU7986KUT ： Falling edge
Normal swing
Single-in / Single -out mode
VDD
0.1uF
0.01uF
VDD
LVDS VDD
LVDS GND
0.1uF
0.01uF
GND
R1[9:0]
R1[9:0]
G1[9:0]
B1[9:0]
G1[9:0]
B1[9:0]
R2[9:0]
TA1N
TA1P
TB1N
TB1P
TC1N
TC1P
TCLKN
TCLKP
TD1N
TD1P
TE1N
TE1P
TA2N
TA2P
TB2N
TB2P
TC2N
TC2P
TCLKN
TCLKP
TD2N
TD2P
TE2N
TE2P
G2[9:0]
B2[9:0]
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
BU7986KUT
CLK_IN
CONT11
CONT12
CLK_IN
CONT11
CONT12
CONT21
CONT22
TEST[3:0]
MODE0
VDD
VDD
MODE1
XRST
OPEN
XRST
VDD
RS *1
R/F
100Otwist
pair Cable
or
PCB(Transmitter)
PCB trace
*1 :
If RS pin is tied to VDD, LVDS swing is 350m V.
If RS pin is tied to GND, LVDS swing is 200m V.
18 / 20
●10bit Small Swing Input
Example:
BU8254KVT ： LVCMOS level input/Falling edge/Normal swing
BU8255KVT ： Falling edge
VDD
VDD
*3
*3
F.Bead
F.Bead
VDD
GND
VDD
GND
LVDS VDD
LVDD
LGND
0.1uF
0.1uF
0.01uF
0.01uF
0.1uF
0.01uF
0.1uF
0.01uF
CLKIN
R4
CLKIN
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TE0
TE1
TE2
TE3
TE4
TE5
TE6
CLKOUT
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RE0
RE1
RE2
RE3
RE4
RE5
RE6
CLKOUT
R4
LVDS GND
R5
R5
R6
R6
R7
R7
PLL VDD
PLL GND
PVDD
PGND
R8
R8
R9
R9
G4
G4
0.1uF
0.01uF
0.1uF
0.01uF
G5
G5
G6
G6
G7
G7
TAN
TAP
RA-
G8
G8
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
G9
G9
RA+
B4
B4
B5
B5
TBN
RB-
B6
B6
B7
B7
TBP
RB+
B8
B8
B9
B9
TCN
RC-
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
TCP
RC+
R2
R2
TCLKN
RCLK-
RCLK+
RD-
R3
R3
BU8254KVT
BU8255KVT
G2
G2
TCLKP
TDN
G3
G3
B2
B2
B3
B3
OPEN
TDP
RD+
R0
R1
G0
G1
B0
B1
R0
R1
G0
G1
B0
B1
TEN
RE-
TEP
RE+
OPEN
XRST
XRST
PD
OE
PD
OE
100Ωtwist
pair Cable
or
*4
RS
*4
PCB trace
DK
R/F
R/F
PCB(Transmitter)
PCB(Receiver)
*3 : Recommended Parts:
F.Bead : BLM18A-Series (Murata Manufacturing)
*4 : RS pin acts as VREF input pin when input voltage is set to half of high level signal input.
We recommend to locate by-pass condenser near the RS pin.
VDD
R1
R2
15k
RS pin.
C1=0.1uF
5.6k
Example for LVCMOS(1.8V input):(R1,R2)=(15kΩ,5.6kΩ)
19 / 20
TQFP64V
<Dimension>
<Packing information>
Container
Quantity
Tray(with dry pack)
12.0 0.3
10.0 0.2
1000pcs
Direction of product is fixed in a tray.
Direction
of feed
48
33
49
64
32
17
1
16
0.125 0.1
0.5
0.2 0.1
0.1
（Unit:mm)
※When you order , please order in times the amount of package quantity.
Catalog No.08T240A '08.6 ROHM ©
相关型号：
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