BU91R63CH-M [ROHM]
BU91R63CH-M3BW是1/4、1/3、1/2占空比、支持Static的COG型车载用通用LCD驱动器，最多可显示176段LCD。本产品支持高液晶电压驱动及高帧频率驱动，也可驱动高显示精度的VA液晶。还支持+105℃动作，符合车载应用要求的AEC-Q 100标准。内置显示用RAM，可减轻微控制器负荷，还无需外置部件，实现了低功耗。具备显示用RAM及寄存器的读取功能，可检测因噪声等导致的误动作。使用ITO电阻测量引脚，更方便进行COG贴装不良的管理。内置有EVR功能，可进行LCD对比度的调节。;
| 型号： | BU91R63CH-M |
| 厂家： | 
ROHM |
| 描述： | BU91R63CH-M3BW是1/4、1/3、1/2占空比、支持Static的COG型车载用通用LCD驱动器，最多可显示176段LCD。本产品支持高液晶电压驱动及高帧频率驱动，也可驱动高显示精度的VA液晶。还支持+105℃动作，符合车载应用要求的AEC-Q 100标准。内置显示用RAM，可减轻微控制器负荷，还无需外置部件，实现了低功耗。具备显示用RAM及寄存器的读取功能，可检测因噪声等导致的误动作。使用ITO电阻测量引脚，更方便进行COG贴装不良的管理。内置有EVR功能，可进行LCD对比度的调节。 驱动 控制器 CD 微控制器 驱动器 |
| 文件： | 总43页 (文件大小：2684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Low Duty LCD Segment Driver
For Automotive COG Application
BU91R63CH-M Max 176 segments (SEG44 x COM4)
General Description
Key Specifications
BU91R63CH-M is a 1/4, 1/3, 1/2 duty or Static COG type
LCD driver that can be used for automotive applications
and can drive up to 176 LCD segments.
Supply Voltage Range:
LCD Drive Power Supply Range:
Operating Temperature Range:
Max Segments:
+2.7 V to +6.0 V
+2.7 V to +6.0 V
-40 °C to +105 °C
176 Segments
It can support operating temperature of up to +105 °C and
compliant for AEC-Q100, as required for Automotive
Application. It has integrated display RAM for reducing
CPU load. Also, it is designed with low power
consumption and no external component needed. It
includes read function for display RAM and command
register, which make it possible to detect malfunction due
to noise. Also a defective mounting of COG can easily be
controlled by using pins to measure ITO resistance.
Display Duty:
Bias:
1/4, 1/3, 1/2, Static Selectable
1/2, 1/3 Selectable
Interface:
2-wire Serial Interface
Special Characteristics
ESD(HBM):
Latch-up Current:
±2,000 V
±100 mA
Features
Applications
AEC-Q100 Compliant (Note 1)
Instrument Clusters
Climate Controls
Car Audios / Radios
Metering
White Goods
Healthcare Products
1/4, 1/3, 1/2 Duty or Static Setting Selectable
1/4 Duty Drive: Max 176 Segments
1/3 Duty Drive: Max 132 Segments
1/2 Duty Drive: Max 88 Segments
Static Drive: Max 44 Segments
Integrated Buffer AMP for LCD Driving
Support Read Register and Display RAM Function
Support ITO Resistance Measurement
Integrated Oscillator Circuit
Battery Operated Applications
etc.
Integrated EVR Function to Adjust LCD Contrast
Integrated Power On Reset Circuit
No External Components
Package
Au BUMP Chip
Low Power Consumption Design
(Note 1) Quality Information:
There is data when LSI was put on a temporary package.
Please use it as reference data.
Typical Application Circuit
[LCD module]
44 x 4 dots
(Top view)
3
0
0
43
COM
BU91R63CH-M (Bottom view)
VLCD VSS VDD SCL SDA
(Note 2)
SEG
(Note 2) SDA of BU91R63CH-M needs pull-up
resistor because it is an open-drain output.
In case that SCL of MCU has open-drain structure,
it also needs pull-up resistor.
VLCD VSS VDD
MCU
SCL SDA
〇Product structure: Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays
.
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Block Diagram
---
Common
Driver
Segment
Driver
LCD Voltage Generator
VLCD
V0
LCD
BIAS
Blink
Timing
Generator
Common
Selector
Counter
DDRAM
Oscillator
Command
Register
Command
Data Decorder
OSCIN
VDD
Serial Interface
PowerOn
Reset
VSS
IF Filter
Terminal Description
Handling
when unused
Terminal Name
I/O
Function
POR enable setting
T0
T1
I
I
VDD: POR disable (Note)
VSS: POR enable
Test input (ROHM use only)
Must be connected to VSS.
Test input (ROHM use only)
Must be connected to VSS.
VSS
VSS
T2
I
-
-
VSS
DUMMY
Open
OPEN
OPEN
DUMMY1
DUMMY2
Can be used for COG resistance measurement.
External clock input
OSCIN
I
External clock and Internal clock can be selected by command
Must be connected to VSS when using internal oscillator
Serial data input-output terminal
VSS
SDA
SCL
VSS
I/O
I
I
-
-
-
Serial clock terminal
Ground
VDD
I
Power supply for logic
-
VLCD
I
Power supply for LCD driving circuit
SEGMENT output for LCD driving
COMMON output for LCD driving
-
SEG0 to SEG43
O
OPEN
OPEN
COM0 to COM3
O
(Note) Not 100 % tested. Software Reset is necessary to initialize IC in case of T0 = VDD.
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Recommended ITO Layout
LCD module terminals
Alignment Mark2
Test PADs on the glass (As needed)
ITO layout image
DUMMY
SEG0
83
1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
Internal
Wiring
80
SDA
SDA
SEG8
SEG9
SCL
SEG10
SEG11
OSCIN
SEG12
SEG13
SEG14
SEG15
70
10
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
VDD
60
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
20
VSS
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
50
VLCD
30
SEG40
SEG41
SEG42
SEG43
COM0
COM1
COM2
40
Internal
Wiring
COM3
DUMMY
34
33
Alignment Mark1
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Recommended ITO Layout – continued
Terminal Resistance
PAD No.
3, 4
Terminal Name
SDA
Maximum Resistance
1,500 Ω
1,500 Ω
1,500 Ω
1,500 Ω
1,500 Ω
1,500 Ω
400 Ω
5, 6
SCL
7, 8
OSCIN
T0
11, 12
13, 14
T1
15, 16
T2
17 to 20
9, 10, 21 to 27
28 to 31
VDD
VSS
400 Ω
VLCD
400 Ω
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
PAD Arrangement
Alignment Mark2
DUMMY
83
SEG0
DUMMY1
DUMMY1
1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
80
70
60
Size
Item
Chip size
Chip thickness
Bump height
Unit
X
650
Y
3560
µm
µm
µm
Hv
SDA
SDA
SCL
230
15 ± 3
50 ± 20
SEG8
Bump hardness
SEG9
SCL
SEG10
SEG11
OSCIN
OSCIN
VSS
Alignment Mark 1
81 µm
SEG12
SEG13
SEG14
SEG15
10
VSS
T0
T0
T1
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
T1
T2
81 µm
T2
SEG22
SEG23
VDD
VDD
(0, 0)
VDD
VDD
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
20
Markcenter coordinate
(X, Y) = (206.6,-1685.0)
VSS
VSS
VSS
VSS
VSS
Alignment Mark 2
VSS
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
50
27 µm 27 µm 27 µm
VSS
VLCD
VLCD
VLCD
27 µm
27 µm
27 µm
30
VLCD
DUMMY2
SEG40
SEG41
SEG42
SEG43
COM0
COM1
COM2
COM3
DUMMY
40
34
Mark center coordinate
(X, Y) = (206.6, 1685.0)
33
DUMMY2
Alignment Mark1
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Dimension
Table 1. Dimension (Completion Size)
Mark
Topic
Specification Limit
625 ± 40 μm
Chip Size X
Chip Size Y
Chip Size: X Direction
Chip Size: Y Direction
Chip Thickness
3,535 ± 40 μm
230 ± 20 μm
Chip Thickness
A (PAD1 to PAD33)
B (PAD1 to PAD33)
C (PAD1 to PAD33)
A’ (PAD34 to PAD83)
B’ (PAD34 to PAD83)
C’ (PAD34 to PAD83)
Bump Size: X Direction
Bump Size: Y Direction
Average of Bump Height
Bump Size: X Direction
Bump Size: Y Direction
Average of Bump Height
60.0 ± 3.0 μm
55.0 ± 3.0 μm
15.0 ± 3.0 μm
75.0 ± 3.0 μm
39.0 ± 3.0 μm
15.0 ± 3.0 μm
Input
PAD
Output
PAD
Table 2. Bump Specs and Dimensions
Topic
Specification Limit
Straight Bump
Bump Structure
Bump Co-planarity on Chip
3.0 μm or less
Bump Hardness (Microvicker’s Meter)
50 Hv ± 20 Hv
Bump Strength
7.25 mg/μm2 or more
Passivation opening
Input PAD
Output PAD
Y
Y’
Y
Au Bump
Y’
A
A’
B’
Aluminum
B
Au Bump
Bump height
Bump height
C
Passivation
C’
UBM(TiW/Au)
UBM (TiW/Au)
Y–Y´ cross section
Y–Y´ cross section
Aluminum
Figure 1. PAD / Bump Information
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
PAD Coordinates
Unit:µm
BUMP Center
BUMP Size
No
Terminal Name
X
Y
X
Y
1
2
3
4
5
6
7
8
DUMMY1
DUMMY1
SDA
SDA
SCL
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
-248.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
227.00
1340.00
1270.00
1045.00
975.00
905.00
835.00
765.00
695.00
625.00
555.00
485.00
415.00
345.00
275.00
205.00
135.00
65.00
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
SCL
OSCIN
OSCIN
VSS
VSS
T0
T0
T1
T1
T2
T2
VDD
VDD
VDD
VDD
VSS
VSS
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
-5.00
-75.00
-145.00
-215.00
-285.00
-355.00
-425.00
-495.00
-565.00
-635.00
-705.00
-775.00
-845.00
-915.00
-1005.00
-1636.00
-1496.55
-1442.55
-1388.55
-1334.55
-1280.55
-1226.55
-1172.55
-1118.55
-1064.55
-950.90
-896.90
-842.90
-788.90
-734.90
-680.90
-626.90
-572.90
-458.85
-404.85
-350.85
-296.85
-242.85
-188.85
-134.85
-80.85
VSS
VSS
VSS
VSS
VLCD
VLCD
VLCD
VLCD
DUMMY2
DUMMY2
DUMMY
COM3
COM2
COM1
COM0
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
DUMMY
33.20
87.20
141.20
195.20
249.20
303.20
357.20
411.20
525.25
579.25
633.25
687.25
741.25
795.25
849.25
903.25
1017.30
1071.30
1125.30
1179.30
1233.30
1287.30
1341.30
1395.30
1449.30
Refer to PAD Arrangement for the definition of X/Y coordinates.
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Absolute Maximum Ratings (VSS = 0 V)
Ratings
Parameter
Symbol
Unit
V
Remarks
Power Supply
Min
-0.5
Typ
-
Max
+7.0
Maximum Voltage1
VDD
Maximum Voltage2
LCD Drive Voltage
VLCD
VIN
-0.5
-0.5
-
-
+7.0
+7.0
-
V
V
Input Voltage Range
-
-
-
-
-
-
Human Body Model (HBM)(Note 1), (Note 2)
Latch-up Current(Note 1), (Note 3)
Maximum Junction Temperature
Storage Temperature Range
VESD
ILU
±2,000
V
-
±100
-
mA
°C
°C
Tjmax
Tstg
-55
-55
-
-
+125
+125
(Note 1) Please use as reference data.
(Note 2) Testing standards: JESD22-A114E
(Note 3) Testing standards: JESD78
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Recommend Operating Conditions (VSS = 0 V)
Ratings
Parameter
Symbol
Unit
Remarks
Min
-40
2.7
2.7
Typ
Max
+105
6.0
Operational Temperature
Power Supply Voltage 1
Power Supply Voltage 2
Topr
VDD
-
-
-
°C
V
-
Power Supply
VLCD
6.0
V
LCD Drive Voltage
Electrical Characteristics
DC Characteristics (Unless otherwise specified, Ta = -40 °C to +105 °C, VDD = 2.7 V to 6.0 V, VSS = 0 V)
Limits
Parameter
Symbol
Unit
Condition
Min
Typ
Max
“H” Level Input Voltage
“L” Level Input Voltage
“H” Level Input Current
“L” Level Input Current
SDA “L” Level Output Voltage
VIH
VIL
0.7VDD
-
-
VDD
V
SDA, SCL, OSCIN
VSS
0.3VDD
V
SDA, SCL, OSCIN
IIH
-
-1
0
-
-
1
-
µA
µA
V
SDA, SCL, OSCIN, T0, T1, T2
SDA, SCL, OSCIN, T0, T1, T2
ILOAD = -3 mA
IIL
-
VOLSDA
RON
RON
IVDD1
IVLCD1
-
0.4
-
SEG
3
3
-
kΩ
kΩ
µA
µA
LCD Driver
ILOAD = ±10 µA
On Resistance
COM
-
-
-
5.0
5.0
Standby Current
Display Off, Oscillation Off
-
-
VDD = 3.3 V, VLCD = 3.3 V,
Ta = 25 °C, Power save mode1,
1/3 bias, Frame inversion
IVDD2
-
-
2.0
5.5
10.0
20.0
µA
µA
Operating Current
IVLCD2
Frame Frequency = 80 Hz setting
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Electrical Characteristics – continued
Oscillation Characteristics (Unless otherwise specified,Ta = -40 °C to +105 °C, VDD = 2.7 V to 6.0 V, VSS = 0 V)
Limits
Parameter
Symbol
Unit
Condition
Min
56
Typ
Max
104
DISCTL 80 Hz setting,
VDD = 2.7 V to 6.0 V,
Ta = -40 °C to +105 °C
DISCTL 80 Hz setting,
VDD = 3.5 V, Ta = -40 °C to +105 °C
80
Frame Frequency 1
Frame Frequency 2
fCLK1
Hz
Hz
72
80
88
fCLK2
µs
µs
Hz
%
-
-
-
-
0.3
0.3
External Clock Rise Time
External Clock Fall Time
External Clock Frequency
External Clock Duty
trCLK
tfCLK
fCLK3
TDTY
External Clock Mode
30,000
30
-
300,000
70
50
Keep external clock frequency range from 30,000 Hz to 300,000 Hz.
The calculation formula for frame frequency at external clock mode is shown in Set IC Operation (ICSET).
[Reference Data]
110
100
VDD = 6.0 V
90
VDD = 5.0 V
VDD = 3.3 V
80
VDD = 2.7 V
70
60
50
-40 -20
0
20
40
60
80 100
Temperature °C
Figure 2. Frame Frequency Typical Temperature Characteristics
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Electrical Characteristics - continued
MPU Interface Characteristics (Unless otherwise specified, Ta = -40 °C to +105 °C, VDD = 2.7 V to 6.0 V, VSS = 0 V)
Limits
Parameter
Symbol
Unit
Condition
Min
-
Typ
Max
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
-
-
-
-
-
-
-
-
-
-
-
0.3
Input Rise Time
tr
tf
-
0.3
Input Fall Time
2.5
0.6
1.3
100
100
1.3
0.6
0.6
0.6
-
-
-
-
-
-
-
-
-
SCL Cycle Time
tCYC
tHW
“H” Level SCL Pulse Width
“L” Level SCL Pulse Width
SDA Setup Time
tLW
tSDS
tSDH
tBUF
tHD;STA
tSU;STA
tSU;STO
SDA Hold Time
Bus Free Time
START Condition Hold Time
START Condition Setup Time
STOP Condition Setup Time
SDA
SCL
SDA
tf
tCYC
tLW
tBUF
tHD;STA
tr
tSDH
tHW
tSDS
tSU;STO
tSU;STA
Figure 3. Interface Timing
I/O Equivalence Circuit
VLCD
VDD
VSS
VSS
SDA
SCL, T0, T1, T2,
OSCIN
VSS
VSS
DUMMY1
VLCD
DUMMY1
DUMMY2
SEG0 to SEG43
COM0 to COM3
DUMMY2
VSS
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Functional Descriptions
Command / Data Transfer Method
BU91R63CH-M transfers command or data by 2-wire signal (SDA, SCL).
SDA
SCL
START Condition
STOP Condition
Figure 4. 2-wire Command/Data Transfer Format
It is necessary to generate START and STOP Condition when transferring command or display data through the 2-wire
serial interface.
Slave Address
A
Display Data
A P
Command
S
0
1
1
1
1
1
0
M
A
C
R/W
Acknowledge
Command or data judge bit
STOP Condition
START Condition
Figure 5. Interface Protcol
The following procedure shows how to transfer Command and Display Data.
(1) Generate “START Condition”.
(2) Issue Slave Address.
(3) Transfer Command and Display Data.
(4) Generate “STOP Condition”
Acknowledge (ACK)
Data format is comprised of 8 bits, Acknowledge bit is returned after sending 8-bit data.
After the transfer of 8-bit data (Slave Address, Command, Display Data), release the SDA line at the 8th falling edge of
SCL. The SDA keeps “Low” output until the 9th falling edge of the SCL.
(Output cannot be pulled “High” because of open drain NMOS).
If acknowledge function is not required, keep SDA line at “Low” level from 8th falling edge to 9th falling edge
of SCL.
SDA
SCL
1 to 7
S
1 to 7
8
9
1 to 7
8
9
8
9
P
START Condition
STOP Condition
Slave Address
Ack
Data
Ack
Data
Ack
Figure 6. Acknowledge Timing
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Functional Descriptions – continued
Command Transfer Method
Issue Slave Address (“01111100”) after generating “START Condition”.
After issuing Slave address (“01111100”), the first byte is always command input.
MSB (Most Significant Bit) of command is the judgment bit for Command or Display Data.
When set “command or data judge bit” = “1”, commands can be input continuously.
When set “command or data judge bit” = “0”, next byte data is Display Data.
S
Slave Address
A
1
Command
A
1
Command
Display Data
A
Command
A
0
…
P
Command
A 1
Command cannot be accepted in once input state of display data.
In order to input command again it is necessary to generate “START Condition”.
If “START Condition” or “STOP Condition” is generated during command transfer, the command being transferred is
cancelled.
If Slave Address is issued continuously following “START Condition” during the transfer, it remains in command input state.
After generating “START Condition”, issue Slave Address at the first data transfer.
If Slave Address cannot be recognized in the first data transfer, Acknowledge bit is not returned and subsequent data
transfer is not accepted. When data is in invalid status, it is restored by generating “START Condition” again.
Consider the MPU interface characteristics such as Input rise time and Setup/Hold time when transferring command and
data (Refer to MPU Interface Characteristics).
Write Display Data and Transfer Method
For Write Mode set R/W bit to “0”.
BU91R63CH-M has Display Data RAM (DDRAM) of 44 x 4 = 176bit.
The relationship between data input and display data, DDRAM data and address are as follows.
Slave Address
0111110
Command
0000000
Command
1101000
S
0
A
0
A
1
A
a
b
c
d
e
f
g
h
A
i
j
k
l
m
n
o
p
A
… P
R/W = 0 (Write Mode)
Display Data
8-bit data is stored in DDRAM. ADSET command specifies the address to be written, and address is automatically
incremented in every 4-bit data.
Data can be continuously written in DDRAM by transmitting data continuously.
When DDRAM data is written successively, after writing DDRAM data to 2Bh (SEG43), the address is returned to 00h
(SEG0) by the auto-increment function.
DDRAM address
00h 01h 02h 03h 04h 05h 06h 07h
…
29h 2Ah 2Bh
a
b
c
d
e
f
i
j
m
n
0
1
2
3
COM0
COM1
BIT
g
h
k
l
o
COM2
COM3
p
SEG SEG SEG SEG SEG SEG SEG SEG
SEG SEG SEG
41 42 43
0
1
2
3
4
5
6
7
Display data is written to DDRAM every 4-bit data.
No need to wait for ACK bit to complete data transfer.
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Functional Descriptions – continued
Read Display and Transfer Method
For Read Mode set R/W bit to “1”.
The display data and command register value can be read during Read Mode.
The Read Mode sequence is shown below.
Slave Address
0111110
Command
0000000
Slave Address
0111110
Command
1101000
S
0
A
A
P
A
1
A
1
1
A
Data
…...
A
S
Data
R/W(Write Mode)
R/W(Read Mode)
In Read Mode, the display data and the register data can be read from the DDRAM through the SDA line.
Output data is output in synchronization with the SCL signal.
In order to access the DDRAM, it is necessary to set the address at first using the ADSET command in Write
Mode.
Note that if the address is not set before reading the display data, reading will start from the current address.
The address is automatically incremented by +2 for each 8-bit output data.
Master side should output ACK signal every 8bit data output.
BU91R63CH-M continues address increment and output data by receiving ACK. If ACK is not received, BU91R63CH-M
does not continue the above read operation so that input “STOP Condition”.
When receiving “STOP Condition”, BU91R63CH-M ends Read Mode.
The address automatically returns to 00h after 2Bh. (Not incremented to 2Ch or 2Dh.)
An example of the display data read sequence is shown below.
S
P
SDA
SCL
Slave Address (read)
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
Figure 7. Read Sequence
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Functional Descriptions – continued
Read Command Register and Transfer Method
The command registers can be read during Read Mode. The sequence for the command register read is shown below and
is similar to the display data read sequence.
Slave Address
Command
Command
Slave Address
NA
P
S
0111110
0
A
1
110 1100
A
ADSET
0111110 A
1
Data
A
S
Set ICSET [P2] = 1
R/W
R/W
Regarding address setting, refer to Address Set (ADSET) command.
The following register settings can be read in this mode by setting address to 2Ch, 2Dh, and 2Eh.
Address does not increment automatically after read the command register value.
Register
REG1
REG2
REG3
D7 D6 D5 D4 D3 D2 D1 D0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
Address
2Ch
2Dh
0
0
0
0
P3 P2 P1 P0
2Eh
REG1:
REG2:
REG3:
P7 = Duty setting
P6 = Duty setting
P5 = 1/2Bias / 1/3Bias setting
P4 = Internal clock / External clock setting
P3 = Software Reset setting
P2 to P0 = Blink setting
P7 to P6 = Frame Frequency setting
P5 to P4 = Power Save Mode setting
P3 = Frame/Line inversion setting
P2 = Display On/Off setting
P1 = All Pixels ON setting
P0 = All Pixels OFF setting
P3 = Contrast setting
P2 = Contrast setting
P1 = Contrast setting
P0 = Contrast setting
The ADSET and ICSET setting address map is shown below.
Write Mode
ADSET
ICSET
P7 P6 P5 P4 P3 P2(Note) P1 P0
RAM Address
D7 D6 D5
D[4:0]
0000 0000 to 0001 1111
0010 0000 to 0010 1011
0
0
0
0
0
0
0 0000 to 1 1111
0 0000 to 0 1011
1
1
1
1
1
1
0
0
1
1
0
1
0
0
0
0
Read Mode
ADSET
ICSET
RAM Address
D7 D6 D5
D[4:0]
P7 P6 P5 P4 P3 P2(Note) P1 P0
0000 0000 to 0001 1111
0010 0000 to 0010 1110
1
1
0
0
0
0
0 0000 to 1 1111
0 0000 to 0 1110
1
1
1
1
1
1
0
0
1
1
0
1
0
0
0
0
(Note) Please take care of ICSET [P2] setting.
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
OSC (Oscillator)
The clock required for internal operation and liquid crystal display operation is generated by an internal oscillation circuit or
an external clock. If internal oscillator circuit is used, OSCIN must be connected to VSS level.
When using external clock mode, input external clock from OSCIN terminal after ICSET command setting.
Clock input
OSCIN
BU91R63CH-M
OSCIN
BU91R63CH-M
VSS
VSS
Figure 8. Internal Clock Mode
Figure 9. External Clock Mode
LCD Driver Bias Circuit
This circuit generates the liquid crystal drive voltage. It also has a built-in buffer amplifier that can be driven with low power
consumption.
1/3 or 1/2 Bias can be set by MODESET command.
Line or frame inversion can be set by DISCTL command.
Refer to the LCD Driving Waveform for each LCD bias setting.
Blinker Timing Generator
BU91R63CH-M has Blink function.
Blink mode can be set by BLKCTL command.
The Blink frequency varies depending on fCLK characteristics at internal clock mode.
Refer to Oscillation Characteristics for fCLK
.
Reset Initialize Condition
Initial condition after executing Software Reset is as follows.
-
-
Display is OFF.
DDRAM address is initialized (DDRAM Data is not initialized).
Refer to Detailed Command Description for initial value of registers.
Command / Function List
Description List of Command / Function
No.
Command
Function
Software reset, internal/external clock setting
( P2 is MSB data of DDRAM address )
1
2
3
Set IC Operation (ICSET)
Display Control (DISCTL)
Address Set (ADSET)
Frame Frequency, Power Save Mode setting
DDRAM address setting
Register address setting
4
5
6
7
Mode Set (MODESET)
Blink Control (BLKCTL)
All Pixels Control (APCTL)
Contrast Setting (EVRSET)
Display ON/OFF, Bias, Duty
Blink off/0.5 Hz/1 Hz/2 Hz/0.3 Hz/0.2 Hz Blink setting
All Pixels ON/OFF during DISPON
Contrast Setting
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Detailed Command Description
D7 (MSB) is a command or data judgment bit.
Refer to Command / Data Transfer Method.
C = 0: Next byte is RAM write data.
C = 1: Next byte is command.
Set IC Operation (ICSET)
MSB
D7
C
LSB
D0
P0
D6
1
D5
1
D4
0
D3
1
D2
P2
D1
P1
P2: MSB data of DDRAM address. Please refer to Address Set (ADSET) command.
Set software reset execution.
Setup
P1
0
No operation
Software Reset Execute
1
When “Software Reset” is executed, BU91R63CH-M is reset to initial condition.
(Refer to Reset Initialize Condition)
Don’t set Software Reset (P1) with P2, P0 at the same time.
Set oscillator mode.
Setup
P0
0
Reset initialize condition
Internal Clock (internal oscillation circuit used)
External Clock
○
1
-
Internal Clock Mode: OSCIN must be connected to VSS level.
External Clock Mode: Input external clock from OSCIN terminal.
<Frame frequency Calculation at external clock mode>
DISCTL 80 Hz setting: Frame frequency = external clock / 512 [Hz]
DISCTL 130 Hz setting: Frame frequency = external clock / 315 [Hz]
DISCTL 64 Hz setting: Frame frequency = external clock / 648 [Hz]
DISCTL 200 Hz setting: Frame frequency = external clock / 205 [Hz]
Command
ICSET
OSCIN_EN
Internal Clock Mode
(Internal Signal)
External Clock Mode
Internal oscillation
(Internal Signal)
External Clock
(OSCIN)
Figure 14. OSC MODE Switch Timing
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Detailed Command Description – continued
Display Control (DISCTL)
MSB
D7
C
LSB
D0
P0
D6
0
D5
1
D4
P4
D3
P3
D2
P2
D1
P1
Set Frame Frequency.
Setup
80 Hz
P4
0
P3
0
Reset initialize condition
○
-
130 Hz
64 Hz
0
1
1
0
-
200 Hz
1
1
-
Set LCD Drive Waveform.
Setup
P2
0
Reset initialize condition
Line Inversion Mode
Frame Inversion Mode
○
1
-
Power consumption is reduced in the following order:
Line inversion > Frame inversion
Typically, when driving large capacitance LCD, Line inversion is more susceptible to crosstalk.
Regarding driving waveform, refer to LCD Driving Waveform.
Set Power Save Mode
Setup
P1
0
P0
0
Reset initialize condition
Power Save Mode 1
Power Save Mode 2
Normal Mode
-
-
0
1
1
0
○
-
High Power Mode
1
1
Power consumption is increased in the following order:
Power Save Mode 1 < Power Save Mode 2 < Normal Mode < High Power Mode
Address Set (ADSET)
MSB
D7
C
LSB
D0
P0
D6
0
D5
0
D4
P4
D3
P3
D2
P2
D1
P1
The range of address in the Write Mode can be set from 000000 to 101011(bin).
The range of address in the Read Mode can be set from 000000 to 101110(bin).
MSB
LSB
Internal
Address Address Address Address Address Address
Register
[5]
[4]
[3]
[2]
[1]
[0]
ICSET
P2
ADSET
P4
ADSET
P3
ADSET
P2
ADSET
P1
ADSET
P0
Command
Address [5:0]: MSB bit is specified in ICSET P2 and [4:0] are specified as ADSET P4 - P0.
Don’t set out of range address, otherwise address is set to 000000.
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Detailed Command Description – continued
Mode Set (MODE SET)
MSB
D7
C
LSB
D0
P0
D6
1
D5
0
D4
0
D3
P3
D2
P2
D1
P1
Set Display On and Off
Setup
P3
0
Reset initialize condition
Display Off (DISPOFF)
Display On (DISPON)
○
1
-
Display Off: Regardless of DDRAM data, all SEGMENT and COMMON outputs stop after writing OFF data of 1frame.
Display Off mode is disabled after Display On command.
Display On: SEGMENT and COMMON outputs become active, and reading operation from DDRAM to Display starts.
Set Bias Level
Setup
P2
0
Reset initialize condition
1/3 Bias
1/2 Bias
○
1
-
Please refer to LCD Driving Waveform, for example of SEG and COM output waveform
Set Duty
Setup
1/4 Duty
1/3 Duty
1/2 Duty
Static
P1
0
P0
0
Reset initialize condition
○
-
0
1
1
0
-
1
1
-
Blink Control (BLKCTL)
MSB
LSB
D7
C
D6
1
D5
1
D4
1
D3
0
D2
P2
D1
P1
D0
P0
Set Blink condition.
Blink mode (Hz)
P2
0
P1
0
P0
0
Reset initialize condition
OFF
0.5
1
○
-
0
0
1
0
1
0
-
2
0
1
1
-
0.3
0.2
1
0
0
-
1
0
1
-
The Blink frequency varies depending on fCLK characteristics at internal clock mode.
Refer to Oscillation Characteristics for fCLK
.
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Detailed Command Description – continued
All Pixels Control (APCTL)
MSB
D7
C
LSB
D0
P0
D6
1
D5
1
D4
1
D3
1
D2
P2
D1
P1
Set all pixels to be turned on and off simultaneously.
Setup
Normal
P1
0
Reset initialize condition
○
All Pixels ON
1
-
Setup
Normal
P0
0
Reset initialize condition
○
All Pixels OFF
1
-
All Pixels ON: All pixels are ON regardless of DDRAM data simultaneously.
All Pixels OFF: All pixels are OFF regardless of DDRAM data simultaneously.
This command is valid in Display On status. The data of DDRAM is not changed by this command.
If set both P1 and P0 = “1”, All Pixels OFF is selected.
P2 is used for P3 of Contrast Setting.
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Detailed Command Description – continued
Contrast Setting (EVRSET)
MSB
D7
C
LSB
D0
P0
D6
1
D5
1
D4
0
D3
0
D2
P2
D1
P1
BU91R63CH-M has an electronic volume of 16 gradations. This function allows setting the maximum potential (V0)
of the gradation voltage for LCD driving. In the initial state after reset, the electronic volume setting is “0000”. At this
time, the VLCD voltage becomes the V0 voltage. Set the electronic volume so that the V0 voltage is 2.7 V or higher.
Refer to the table below for V0 output voltage.
Contrast Setting
(V0 voltage)
P3(Note)
P2
P1
P0
Reset initialize condition
1.000 x VLCD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
○
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.975 x VLCD
0.950 x VLCD
0.925 x VLCD
0.900 x VLCD
0.875 x VLCD
0.850 x VLCD
0.825 x VLCD
0.800 x VLCD
0.775 x VLCD
0.750 x VLCD
0.725 x VLCD
0.700 x VLCD
0.675 x VLCD
0.650 x VLCD
0.625 x VLCD
(Note) P3 setting uses P2 of APCTL.
The relationship of LCD display contrast setting and VLCD voltage
VLCD
4.5
Formula
Unit
3.0
6.0
5.5
5.0
4.0
2.7
1.000 x VDD
0.975 x VDD
0.950 x VDD
0.925 x VDD
0.900 x VDD
0.875 x VDD
0.850 x VDD
0.825 x VDD
0.800 x VDD
0.775 x VDD
0.750 x VDD
0.725 x VDD
0.700 x VDD
0.675 x VDD
0.650 x VDD
0.625 x VDD
6.000 5.500 5.000
5.850 5.363 4.875
5.700 5.225 4.750
5.550 5.088 4.625
5.400 4.950 4.500
5.250 4.813 4.375
5.100 4.675 4.250
4.950 4.538 4.125
4.800 4.400 4.000
4.650 4.263 3.875
4.500 4.125 3.750
4.350 3.988 3.625
4.200 3.850 3.500
4.050 3.713 3.375
3.900 3.575 3.250
3.750 3.438 3.125
4.500
4.388
4.275
4.163
4.050
3.938
3.825
3.713
3.600
3.488
3.375
3.263
3.150
3.038
2.925
2.813
4.000
3.900
3.800
3.700
3.600
3.500
3.400
3.300
3.200
3.100
3.000
2.900
2.800
2.700
2.600
2.500
3.000
2.925
2.850
2.775
2.700
2.625
2.550
2.475
2.400
2.325
2.250
2.175
2.100
2.025
1.950
1.875
2.700
2.632
2.565
2.497
2.430
2.362
2.295
2.227
2.160
2.092
2.025
1.957
1.890
1.822
1.755
1.687
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Prohibited Setting
In the case of using EVR function, ensure “VLCD – V0 > 0.6 V” condition is satisfied.
IC output may become unstable if the above conditions are not satisfied.
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
LCD Driving Waveform
(1/4duty, 1/3bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
COM1
COM2
COM3
stateA
stateB
COM0
COM1
COM2
COM3
stateA
stateB
1frame
1frame
V0
V0
COM0
COM1
COM0
COM1
VSS
V0
VSS
V0
VSS
V0
VSS
V0
COM2
COM2
VSS
V0
VSS
V0
COM3
COM3
VSS
V0
VSS
V0
SEGn
SEGn
VSS
V0
VSS
V0
SEGn+1
SEGn+2
SEGn+3
SEGn+1
SEGn+2
SEGn+3
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
stateA
stateA
(COM0-SEGn)
(COM0-SEGn)
-V0
V0
-V0
V0
stateB
stateB
(COM1-SEGn)
(COM1-SEGn)
-V0
-V0
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
LCD Driving Waveform – continued
(1/4duty, 1/2bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
COM1
COM2
COM3
stateA
stateB
COM0
COM1
COM2
COM3
stateA
stateB
1frame
V0
1frame
V0
COM0
COM1
COM2
COM0
COM1
COM2
COM3
SEGn
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
COM3
VSS
V0
VSS
V0
SEGn
VSS
V0
VSS
V0
SEGn+1
SEGn+2
SEGn+1
SEGn+2
VSS
V0
VSS
V0
VSS
V0
VSS
V0
SEGn+3
stateA
SEGn+3
stateA
VSS
VSS
(COM0-SEGn)
(COM0-SEGn)
V0
V0
1/2 (V0)
1/2 (V0)
0
0
-1/2 (V0)
-V0
-1/2 (V0)
-V0
stateB
(COM1-SEGn)
V0
stateB
(COM1-SEGn)
V0
1/2 (V0)
1/2 (V0)
0
0
-1/2 (V0)
-V0
-1/2 (V0)
-V0
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
LCD Driving Waveform – continued
(1/3duty, 1/3bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
COM1
COM2
COM3
stateA
stateB
COM0
COM1
COM2
COM3
stateA
stateB
Save waveform as COM0
Save waveform as COM0
1frame
1frame
V0
V0
COM0
COM1
COM0
COM1
VSS
V0
VSS
V0
VSS
V0
VSS
V0
COM2
COM2
VSS
V0
VSS
V0
COM3
COM3
VSS
V0
VSS
V0
SEGn
SEGn
VSS
V0
VSS
V0
SEGn+1
SEGn+2
SEGn+3
SEGn+1
SEGn+2
SEGn+3
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
stateA
stateA
(COM0-SEGn)
(COM0-SEGn)
-V0
V0
-V0
V0
stateB
stateB
(COM1-SEGn)
(COM1-SEGn)
-V0
-V0
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
LCD Driving Waveform – continued
(1/3duty, 1/2bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
COM1
COM2
COM3
stateA
stateB
COM0
COM1
COM2
COM3
stateA
stateB
Same waveform as COM0
Same waveform as COM0
1frame
V0
1frame
COM0
COM1
COM2
V0
VSS
V0
COM0
VSS
V0
COM1
VSS
V0
VSS
V0
COM2
VSS
V0
VSS
V0
COM3
COM3
VSS
V0
VSS
V0
SEGn
SEGn
VSS
V0
VSS
V0
SEGn+1
SEGn+2
SEGn+1
SEGn+2
VSS
V0
VSS
V0
VSS
V0
VSS
V0
SEGn+3
stateA
SEGn+3
stateA
VSS
VSS
(COM0-SEGn)
(COM0-SEGn)
V0
V0
1/2 (V0)
1/2 (V0)
0
0
-1/2 (V0)
-V0
-1/2 (V0)
-V0
stateB
(COM1-SEGn)
V0
stateB
(COM1-SEGn)
V0
1/2 (V0)
1/2 (V0)
0
0
-1/2 (V0)
-V0
-1/2 (V0)
-V0
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24/40
TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
LCD Driving Waveform – continued
(1/2duty, 1/3bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
COM1
stateA
COM0
COM1
stateA
stateB
stateB
COM2, 3
Same waveform as COM0
COM2, 3
Same waveform as COM0
1frame
1frame
V0
V0
COM0
COM1
COM0
COM1
VSS
V0
VSS
V0
VSS
V0
VSS
V0
COM2
COM2
VSS
V0
VSS
V0
COM3
COM3
VSS
V0
VSS
V0
SEGn
SEGn
VSS
V0
VSS
V0
SEGn+1
SEGn+2
SEGn+3
SEGn+1
SEGn+2
SEGn+3
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
stateA
stateA
(COM0-SEGn)
(COM0-SEGn)
-V0
V0
-V0
V0
stateB
stateB
(COM1-SEGn)
(COM1-SEGn)
-V0
-V0
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
LCD Driving Waveform – continued
(1/2duty, 1/2bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
COM1
stateA
COM0
COM1
stateA
stateB
stateB
COM2, 3
Same waveform as COM0
COM2, 3
Same waveform as COM0
1frame
V0
1frame
V0
COM0
COM1
COM2
COM0
COM1
COM2
COM3
SEGn
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
V0
COM3
VSS
V0
VSS
V0
SEGn
VSS
V0
VSS
V0
SEGn+1
SEGn+2
SEGn+1
SEGn+2
VSS
V0
VSS
V0
VSS
V0
VSS
V0
SEGn+3
stateA
SEGn+3
stateA
VSS
VSS
(COM0-SEGn)
(COM0-SEGn)
V0
V0
1/2 (V0)
1/2 (V0)
0
0
-1/2 (V0)
-V0
-1/2 (V0)
-V0
stateB
(COM1-SEGn)
stateB
(COM1-SEGn)
V0
V0
1/2 (V0)
1/2 (V0)
0
0
-1/2 (V0)
-V0
-1/2 (V0)
-V0
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
LCD Driving Waveform – continued
(Static)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
stateA stateB
COM0
stateA stateB
COM1 to 3
Same waveform as COM0
COM1 to 3
Same waveform as COM0
1frame
1frame
V0
V0
COM0
COM0
(COM1 to 3)
(COM1 to 3)
VSS
V0
VSS
V0
SEGn
SEGn
VSS
V0
VSS
V0
SEGn+1
SEGn+2
SEGn+3
SEGn+1
SEGn+2
SEGn+3
VSS
V0
VSS
V0
VSS
V0
VSS
V0
VSS
VSS
V0
V0
stateA
stateA
0
0
-V0
V0
-V0
V0
stateB
stateB
0
0
-V0
-V0
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
Example of Display Data
When displaying a pattern as shown in Figure 12. Example Display Pattern on a panel with SEG / COM wiring patterns
shown in Figure 10. Example COM Line Pattern and Figure 11. Example SEG Line Pattern, the following DDRAM data
map is shown.
COM0
COM1
COM2
COM3
Figure 10. Example COM Line Pattern
SEG1 SEG3
SEG2
SEG5 SEG7
SEG4 SEG6 SEG8
SEG9
SEG10
Figure 11. Example SEG Line Pattern
Figure 12. Example Display Pattern
<DDRAM data mapping in Figure 12 display pattern>
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
9
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
10 11 12 13 14 15 16 17 18 19
COM0
COM1
COM2
D0
D1
D2
D3
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
0
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COM3
Address
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah0Bh0Ch0Dh0Eh 0Fh 10h 11h 12h 13h
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
Initialize Sequence
Follow the Power On sequence below to initialize condition.
Power On
↓
STOP Condition
↓
START Condition
↓
Issue Slave Address
↓
Execute Software Reset by sending ICSET command.
After Power On and before sending initialize sequence, each register value, DDRAM address and DDRAM data are random.
Start Sequence
Start Sequence Example1
No.
Input
D7 D6 D5 D4 D3 D2 D1 D0
Descriptions
VDD = 0 → 3.3 V (tr = 1 ms)
VLCD = 0 → 5.0 V
1
Power On
-
-
-
-
-
-
-
-
↓
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
3
Wait 100 µs
Initialize
↓
-
-
-
-
-
-
-
-
-
Stop
-
-
-
-
-
-
-
-
STOP Condition
↓
-
-
-
-
-
-
-
-
-
4
Start
-
-
-
-
-
-
-
-
START Condition
↓
-
-
-
-
-
-
-
-
-
5
Slave Address
0
-
1
-
1
-
1
-
1
-
1
-
0
-
0
-
Issue Slave Address
↓
-
6
ICSET
1
-
1
-
1
-
0
-
1
-
0
-
1
-
0
-
Software Reset
↓
-
7
BLKCTL
1
-
1
-
1
-
1
-
0
-
*
-
0
-
0
-
Blink OFF
↓
-
8
DISCTL
1
-
0
-
1
-
0
-
0
-
0
-
1
-
0
-
80 Hz, Line Inversion, Normal mode
↓
-
9
APCTL
1
-
1
-
1
-
1
-
1
-
0
-
0
-
0
-
Set MSB of EVRSET
↓
-
10
11
12
13
EVRSET
1
-
1
-
1
-
0
-
0
-
0
-
0
-
0
-
EVRSET V0 = 1.00 x VLCD
↓
ICSET
↓
-
1
-
1
-
1
-
0
-
1
-
*
-
0
-
0
-
RAM MSB address set
-
ADSET
↓
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
RAM address set
-
Display Data
Display Data
*
*
-
*
*
-
*
*
-
*
*
-
*
*
-
*
*
-
*
*
-
*
*
-
address
address
00h to 01h
02h to 03h
Display Data
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
address
-
2Ah to 2Bh
↓
14
15
16
17
Stop
-
-
-
-
-
-
-
-
STOP Condition
↓
-
-
-
-
-
-
-
-
-
Start
-
-
-
-
-
-
-
-
START Condition
↓
-
-
-
-
-
-
-
-
-
Slave Address
0
-
1
-
1
-
1
-
1
-
1
-
0
-
0
-
Issue Slave Address
↓
MODESET
↓
-
1
-
1
-
0
-
0
-
1
-
0
-
0
-
0
-
Display On, 1/4 Duty, 1/3 Bias
-
18
Stop
-
-
-
-
-
-
-
-
STOP Condition
(*: don’t care)
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
Start Sequence- continued
Start Sequence Example2
Initialize
Initialize Sequence
DISPON Sequence
RAMw rite Sequence
DISPOFF Sequence
DISPON
RAMwrite
DISPOFF
BU91R63CH-M is initialized with “Initialize Sequence”, starts to display with “DISPON Sequence”, updates Display data
with “RAM Write Sequence” and stops the display with “DISPOFF Sequence”.
Execute “DISPON Sequence” in order to restart display.
Initialize Sequence (In case of VDD≠VLCD)
Initialize Sequence (In case of VDD=VLCD)
DATE
D7 D6 D5 D4 D3 D2 D1 D0
DATE
D7 D6 D5 D4 D3 D2 D1 D0
Input
Description
Input
Description
VDD On
Wait 100 µs
STOP
VDD, VLCD On
Wait 100 µs
STOP
START
START
Slave Adress
0
1
1
1
1
1
1
0
1
1
1
0
0
1
0
0
Issue Slave Address
Slave Address
0
1
1
1
0
*
1
1
1
1
0
*
1
1
0
1
0
*
1
0
0
0
0
*
1
1
0
1
0
*
1
0
0
0
0
*
0
1
0
0
0
*
0
0
0
0
0
*
Issue Slave Address
Execute Software Reset
DisplayOff
ISECT
VLCD ON
STOP
Execute Software Reset
ICSET
MODESET
ICSET
Set MSB of RAMaddress
Set RAMaddress
Displaydata
START
ADSET
DisplayData
:
Slave Address
0
1
1
1
0
*
1
1
1
1
0
*
1
1
0
1
0
*
1
0
0
0
0
*
1
1
0
1
0
*
1
0
0
0
0
*
0
1
0
0
0
*
0
0
0
0
0
*
Issue Slave Address
Execute Software Reset
DisplayOff
ICSET
MODESET
ICSET
STOP
Set MSB of RAMaddress
Set RAMAddress
Displaydata
ADSET
DisplayData
:
STOP
DISPON Sequence
DATE
D7 D6 D5 D4 D3 D2 D1 D0
Input
Description
START
Slave Address
ICSET
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Issue Slave Address
Set Internal OSC mode
Set DisplayControl
Set BLKCTL
DISCTL
BLKCTL
APCTL
Set APCTL
EVRSET
MODESET
STOP
Set Contrast Setting
DisplayOn
RAM Write Sequence
DATE
D7 D6 D5 D4 D3 D2 D1 D0
Input
Description
START
Slave Address
0
1
1
1
1
1
1
0
*
1
0
1
1
1
1
1
0
*
1
1
1
1
1
0
1
0
*
1
0
1
1
0
0
0
0
*
1
0
0
1
0
1
1
0
*
1
0
0
1
0
0
0
0
*
0
1
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
*
Issue Slave Address
Set DisplayControl
Set BLKCTL
DISCTL
BLKCTL
APCTL
Set APCTL
EVRSET
MODESET
ICSET
Set Contrast Setting
DisplayOn
Set MSB of RAM address
Set RAM address
Displaydata
ADSET
DisplayData
:
STOP
DISPOFF Sequence
DATE
D7 D6 D5 D4 D3 D2 D1 D0
Input
Description
START
Slave Address
MODESET
STOP
0
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
Issue Slave Address
DisplayOff
Abnormal operation may occur in BU91R63CH-M due to the effect of noise or other external factor.
To avoid this phenomenon, it is highly recommended to input command according to sequence described above during
initialization, Display On/Off and refresh of RAM data.
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
Cautions in Power ON/OFF
To avoid unintended display errors, malfunctions and abnormal currents, use the following sequence when turning the
power On and Off.
Be sure to turn on the VDD power supply first before turning on the VLCD power supply.
When turning off the power, be sure to turn off the VLCD power supply first, and then turn off the VDD power supply.
Also, satisfy the conditions of t1 > 0 ns and t2 > 0 ns. Data transmission / reception may fail, so do not transfer data while
the power supply voltage is rising or falling.
t1
t2
VLCD
VDD
10 %
10 %
VDD min
VDD min
Figure 13. Recommended Power ON/OFF Sequence
BU91R63CH-M has a POR circuit (Power On Reset) and Software Reset function.
To ensure the operation, observe the following conditions when the power is turned on.
To operate the POR circuit, start up the VDD power supply so that the following recommended conditions for tR, tF, tOFF
and VBOT are satisfied.
,
To enable the POR circuit, T0 must be set to VSS.
tF
VDD
tR
Recommended condition of tR, tF, tOFF, VBOT (Ta = 25 °C)
(Note)
(Note)
(Note)
(Note)
tR
1 ms
tF
1 ms
tOFF
VBOT
tOFF
VBOT
Less than
0.1 V
Min 20 ms
to 500 ms to 500 ms
(Note) Not 100 % tested.
Figure 14. Power ON/OFF Waveform
If the above recommended conditions cannot be satisfied, execute the following sequence immediately after turning on the
power. When T0 = VDD, this sequence must also be executed, since the POR circuit is disabled. However, since the
command cannot be accepted when the power is turned off, Software Reset is not the same operation as POR.
1.Generate STOP Condition
VDD
SDA
SCL
STOP Condition
Figure 15. Stop Condition
2. Generate START Condition.
VDD
SDA
SCL
START Condition
Figure 16. Start Condition
3.Issue Slave Address
4.Execute Software Reset (ICSET) Command
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TSZ22111 • 15 • 001
BU91R63CH-M Max 176 segments (SEG44 x COM4)
Display Off Operation in External Clock Mode
BU91R63CH-M enters the DISPOFF sequence in synchronization with the frame after receiving the MODESET (Display
Off) command. All SEGMENT and COMMON outputs stop after writing 1 frame OFF level. Therefore, when using in
external clock mode, input of an external clock according to each frame frequency setting is required after completion of
MODESET (Display Off) transmission. The number of external clocks required for setting each frame frequency is as
follows according to the frame frequency setting of the DISCTL command.
Input the external clock as below.
DISCTL 80 Hz setting (Frame frequency = external clock / 512 [Hz]) , 1024 clk or more
DISCTL 130 Hz setting (Frame frequency = external clock / 315 [Hz]) , 630 clk or more
DISCTL 64 Hz setting (Frame frequency = external clock / 648 [Hz]) , 1296 clk or more
DISCTL 200 Hz setting (Frame frequency = external clock / 205 [Hz]) , 410 clk or more
Refer to the timing chart below.
Command
OSCIN
MODESET
To Input External Clock at Least 2
frame or more
Frame
SEG
VSS
VSS
VSS
VSS
VSS
COM0
COM1
COM2
COM3
Display On
Display Off
The last display
frame after receiving
MODESET
1 frame of OFF
data write
Figure 17. External Clock Stop Timing
In external clock mode, the clock signal must always be supplied to BU91R63CH-M. If the clock supply is stopped, the
display may freeze in a DC state that is not suitable for the LCD.
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Note on The Multiple Device Connection to 2-wire Serial Interface
Do not access other devices on the same bus with the BU91R63CH-M VDD Power Off.
MCU
BU91R63CH-M
Other Device
Figure 18. Example of BUS Connection
A capacitor is connected between the drain and gate of the SDA output NMOS transistor to control the slew rate (see the
figure below). When power (VDD) is not applied, the gate is in a high impedance state.
When the SDA pin transitions from Low to High while in this state, current is supplied via the slew rate control capacitor,
and the gate voltage (Vg) rises.
When this voltage (Vg) exceeds the threshold voltage (Vth), the output transistor is turned on and current (Ids) is drawn
from the SDA pin.
The SDA signal maintains the power supply voltage (VDD) by the external resistor (R), but if the voltage drop (R x Ids)
increases due to the current (Ids), is not possible to maintain “1” as the logical value of the SDA signal level.
Be sure to apply power (VDD) to BU91R63CH-M even when multiple devices are connected on the same bus.
Z = 1/jωC
VDD
SDA
Vg
internal circuit
Figure 19. SDA Output Cell Structure
Note in Case that the SDA is Stuck LOW
Normally, the state of SDA is controlled by the MCU, and BU91R63CH-M controls SDA to the VSS level only when “0” is
output during ACK and Read Mode. If the data line (SDA) is stuck at LOW unexpectedly, the MCU needs to send a dummy
byte with START and STOP conditions twice as shown below (Please set SDA to High at this time). This sequence returns
from the SDA stuck state.
SDA will be released in this sequence
Stuck
LOW
Normal
State
SDA status of BU91R63CH-M
SDA from MCU
SCL from MCU
Dummy Byte
Dummy Byte
(9 SCL pulses)
(9 SCL pulses)
START
Condition
STOP START
Condition Condition
STOP
Condition
Figure 20. Recovery sequence from SDA stuck
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Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
7. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
10. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation
of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage.
Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower
than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power supply
voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have voltages
within the values specified in the electrical characteristics of this IC.
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
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Operational Notes – continued
12. Disturbance Light
In a device where a portion of silicon is exposed to light such as in a WL-CSP and chip products, IC characteristics
may be affected due to photoelectric effect. For this reason, it is recommended to come up with countermeasures that
will prevent the chip from being exposed to light.
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Ordering Information
B
U
9
1
R
6
3
C
H - M 3 B W
Part Number
Product Rank
M: for Automotive
Minimum Order Quantity (MOQ)
Orderable Part Number
BU91R63CH-M3BW
Minimum Order Quantity
1,360 pcs
Back Marking Diagram
BU91R63CH-M
Product control number
Y
X
(Bump side down)
Refer to PAD Arrangement for the definition of X/Y coordinates.
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Packing Quantity
Packing QTY.
(Standard QTY)
Tray:
Block:
136 pcs / Tray
680 pcs / Block (1 block = 5 trays)
Vacuum Pack:
680 pcs / Vacuum pack (1 vacuum pack = 1 blocks)
Inner Box
Outer Box
1,360 pcs / inner Box (1 inner box = 2 vacuum packs)
2,720 pcs / outer Box (1 outer box = 2 inner boxes)
Pellet Drawing
PAD No.1
PAD No.83
Input Side
Output Side
Y
X
PAD No.33
PAD No.34
(Bump side up)
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BU91R63CH-M Max 176 segments (SEG44 x COM4)
Package Condition
Products should be aligned to the same direction with Bump side up.
“Chamfering” side is aligned with X/Y direction of the chip as shown in the following drawing.
C
RH20850376R-033A
X
Y
Refer to PAD Arrangement for the definition of X/Y coordinates.
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Physical Dimension Tray Information
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Revision History
Data
Revision
001
Changes
10 Feb. 2016
New Release
P5 Add Terminal Resistance
P6 Add Dimension
P8 Move Operational Temperature Range to Recommend Operating Conditions
P8 Add Maximum Junction Temperature
P20 Add The relationship of LCD display contrast setting and VLCD Voltage
P31 Add the description in Cautions in Power ON/OFF
(Transcription from Operational Notes)
P32 Add Display Off Operation in External Clock Mode
P33 Add Note on The Multiple Device Connection to 2-wire Serial Interface
P33 Add Note in case that the SDA is stuck LOW
15 Oct. 2019
002
P34 Delete Thermal Consideration
P35 Move Data transmission to Cautions in Power ON/OFF
P36 Change Minimum Order Quantity
P37 to P38 Add Packing Quantity, Pellet Drawing, Package Condition
-
-
Change Figure number
Correction of errors.
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
相关型号：
BU91R64CH-M
本产品支持高液晶电压驱动及高帧频率驱动，也可驱动高显示精度的VA液晶。而且，具备显示数据及指令寄存器读取功能，可检测出因噪声导致的误动作。除此之外，还支持MCU通信校验和、玻璃破碎、逻辑电路状态、SEG/COM端子拨动动作的异常检测。使用ITO电阻测量端子，更方便进行COG贴装不良的管理。还支持+105℃动作，符合车载应用要求的AEC-Q 100标准。
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本产品支持高液晶电压驱动及高帧频率驱动，也可驱动高显示精度的VA液晶。而且，具备显示数据及指令寄存器读取功能，可检测出因噪声导致的误动作。除此之外，还支持MCU通信校验和、玻璃破碎、逻辑电路状态、SEG/COM端子拨动动作的异常检测。使用ITO电阻测量端子，更方便进行COG贴装不良的管理。还支持+105℃动作，符合车载应用要求的AEC-Q 100标准。
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