BU95103SR [ROHM]

6bit RSDS Source Driver; 6bit的RSDS源驱动器


型号：	BU95103SR
厂家：	ROHM
描述：	6bit RSDS Source Driver 6bit的RSDS源驱动器驱动器
文件：	总15页 (文件大小：434K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Drivers for Large LCD Panels

6bit RSDS^TM

Source Driver

BU95303

No.10043EAT02

●Description

ROHMLCD drivers for large panels are display drivers optimized for large LCDs in a variety of applications, including

desktop PCs, laptops, and TVs. The broad lineup is offered in low amplitude differential transmission interface type

(RSDS^TM) featuring low EMI, 6bit gradation precision, and different output configurations (432 and up) for wide compatibility.

●Features

1) 384/414/420/432 output channels

2) 6bit 9pair RSDS^TMinputs

3) Dot & n-line inversion available

4) Built-in 2ch repair amplifiers

5) γcorrection is possible

6) Built-in input data reversing function (INV)

7) Output voltage range : AV_SS+0.1V ~ AV_DD-0.1V

8) High speed data transfer: f_CLK(MAX)=85MHz

9) Logic power supply voltage (DV_DD) : 2.7 ~ 3.6V

10) Driver power supply voltage (AV_DD) : 10.0 ~ 13.5V

11) Package: COF35

●Applications

TFT LCD Panels

●Line up matrix

BU95101

384

BU95303

BU95306

BU95408

Number of outputs

384 / 414 / 420 / 432

600 / 618 / 630 / 642

684 / 690 / 702 / 720

www.rohm.com

2010.10 - Rev.A

1/14

Technical Note

BU95303

●Absolute maximum ratings

Parameter

Symbol

DV_DD

AV_DD

V_I1

Ratings

Unit

Logic power supply voltage

Driver power supply voltage

Logic input voltage

-0.3 ~ +4.5

-0.3 ~ +14.0

-0.3 ~ DV_DD+0.3

-0.3 ~ AV_DD+0.3

-55 ~ +125

Logic output voltage

V_O1

Driver input voltage

V_I2

Driver output voltage

Storage temperature range

V_O2

T_stg

℃

●Recommended operating range

Parameter

Symbol

DV_DD

AV_DD

Ratings

+2.7 ~ +3.6

+10.0 ~ +13.5

0.5 AV_DD~ AV_DD-0.1

0.1 ~ 0.5 AV_DD

0.1 ~ AV_DD-0.1

Unit

Logic power supply voltage

Driver power supply voltage

V₀~ V₆

V₇~ V₁₃

V_O

γ-correction reference voltage

Driver output voltage

Output load capacitance

Maximum clock frequency

C_L

MHz

℃

f_CLK(MAX)

T_opr

Operating temperature range

-10 ~ +85

* AV_SS=DV_SS=0V

www.rohm.com

2010.10 - Rev.A

2/14

Technical Note

BU95303

●Electrical characteristics (DC)

(Unless otherwise noted, Ta=-10 ~ +85℃, DV_DD=2.7 ~ 3.6V, AV_DD=10.0 ~ 13.5V, DV_SS=AV_SS=0V)

Limits

Parameter

Logic Part

Symbol

Unit

Conditions

Min.

Typ.

Max.

DV_DD=3.3V, Data=00h-3Fh(dot),

fclk=65MHz, fstb=50kHz, 1Line-inverison

Logic supply current

Input “H” voltage

I_DDL

V_1H

R/L,SFTR,INV

,SFTL,

0.7DV_DD

DV_DD

POL,STB,SEL0,SEL1,

LPC0,

Input “L” voltage

V_1L

0.3DV_DD

LPC1

Input “H” current

Input “L” current

Input “H” current 2

Input “L” current 2

Input “H” current 3

Input “L” current 3

Output “H” voltage

I_1H1

I_1L1

I_1H2

I_1L2

I_1H3

I_1L3

-1

μA V_IN=DV_DD

μA V_IN=DV_SS

Dxx, SFTR, POL, INV,

SFTL,CLK,STB,R/L

V_IN=DV_DD

μA

SEL0,SEL1,

LPC1,LPC0,

Built-in Pull down R

DV_DD=3.3V

-3

-40

μA V_IN=DV_SS

μA V_IN=DV_DD

Built-in Pull up R

SFTR,SFTL

V_IN=DV_SS

μA

-20

DV_DD=3.3V

V_OHDV_DD-0.5

I_OH=-1.0mA

I_OL=1.0mA

Output “L” voltage

Driver part

V_OL

0.5

fCLK=85MHz,DATA=00h,

mA fSTB=56kHz,fPOL=28kHz, No Load

AVDD=12V,V0=11.9V, V13=0.1V

Driver supply current

I_DDA

R_γ

0.7Typ

11.88

1.3Typ

kΩ V0 ~ V6

γcorrection resistance

R_γ

kΩ V7 ~ V13

LOW

AV_DD=12V

Yout=0.1V ~ 1.5V,Yout=10.5V ~ 11.9V

±25

±15

±25

±5

±40

±25

±40

±10

±7.5

Output voltage deviation

V_OD1

mV AV_DD=12V, Yout=1.5V ~ 10.5V

AV_DD=12V,

Yout=0.1V ~ 1.5V,Yout=10.5V ~ 11.9V

Output swing voltage

Deviation

V_RMS

mV AV_DD=12V, Vout=1.5V ~ 10.5V

mV AV_DD=12V, Data=32-gray

Output voltage deviation 2

(between chips)

V_OD2

Repair input voltage

V_1NB

I_1BH

I_1BL

0.1

-1

AV_DD-0.1

Repair input “H” current

Repair input “L” current

μA V_IN=AV_DD=12 V

μA V_IN=AV_SS

IREP1,2

-1

I_VOHY

I_VOHR

I_VOLY

I_VOLR

-0.4

mA Y1 ~ Y432, AV_DD=12V, Vx=6 V, Yout=11V

mA OREP1,2 ,AV_DD=12V, Vx=6 V, Yout=11V

mA Y1 ~ Y432, AV_DD=12V, Vx=6 V,Yout=1V

mA OREP1,2 ,AV_DD=12V, Vx=6 V, Yout=1V

Driver output “H” current

-0.8

0.4

0.8

Driver output“L” current

RSDS^TMinput part

RSDS^TMinput “H” voltage

V_IHRSDS

V_ILRSDS

100

200

VCM_RSDS=+1.2V^*4

RSDS^TMinput “L” voltage

-200

-100

CLK_P/N,D_XXP/N

(X=0,1,2)

RSDS^TMcommon input

voltage

V_CMRSDS

0.4

DV_DD-1.2

V_DIFF=200mV^*5

V_OD1=measured output voltage - averaged output voltage of all outputs

_RMS=measured output swing voltage - averaged output swing voltage of all outputs

_OD2=averaged output voltage - target value

VCM _RSDS= (VCLK_P+VCLK_N)/2 or (VD_XXP+VD_XXN)/2

_DIFF= VCLK_P- VCLK_Nor VD_XXP-VD_XXN

www.rohm.com

2010.10 - Rev.A

3/14

Technical Note

BU95303

●Electrical characteristics (AC)

(Unless otherwise noted, Ta=-10 ~ +85℃, DV_DD=2.7 ~ 3.6V, AV_DD=10.0 ~ 13.5V, DV_SS=AV_SS=0V)

Limits

Parameter

Clock pulse width

Symbol

Unit

Conditions

Min.

Typ.

Max.

1/85MHz

Clock pulse "H" period

Clock pulse "L" period

Data setup time

tsu1

thd1

tsu2

thd2

t_WSFT

tdc

Data hold time

Start pulse setup time

Start pulse hold time

Start pulse width

CLK period

Carry output delay time

STB pulse width

C_L=15pF

t_WSTB

t_LDT

CLK period

Final data timing

Time between STB↑and start pulse↑

Time between STB↑and CLK↓

POL/STB setup time

t_STB-SFT

t_STB-CLK

tsp

*1*3

*2*3

*1*3

*2*3

μs

LPC:normal

Output delay time

tdout

LPC:low power

*1 The value is specified when the drive voltage value reaches the target output voltage level of 90%.

*2 The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.

*3 Output load condition:

R1=R2=R3=10kΩ, C1=C2=C3=20pF

Output

(Test Probe)

Vcom=AV^SS

www.rohm.com

2010.10 - Rev.A

4/14

Technical Note

BU95303

●Block diagram

・・・・・・・・・・・・・・・・・

LPC0, LPC1

Output Buffer

OREP2

IREP2

OREP1

IREP1

・・・・・・・・・・・・・・・・・

V0 V13

D/A Converter

～

POL

6 6 6

6 6

・・・・・・・・・・・・・・・・・

Level Shifter

6 6 6

6 6

・・・・・・・・・・・・・・・・・

Data Latch

STB

6 6 6

・・・・・・・・・・・・・・・・・

Data Register

00P/N

02P/N

～

D_10P/N～D_12P/N

20P/N

22P/N

～

INV

144bit Bi-directional Shift Register

CLK_{P/ N}

DV_DD

SFTL

SFTR R/L

SEL1, SEL0

Fig.1 Block diagram

www.rohm.com

2010.10 - Rev.A

5/14

Technical Note

BU95303

●Pin configuration

IREP2

OREP2

DV_DD

Y432

Y431

Y430

・

SFTL

D_22P

・

D_22N

D_21P

D_21N

D_20P

D_20N

D_12P

D_12N

D_11P

D_11N

D_10P

D_10N

DV_DD

LPC0

R/L

V13

V12

V11

V10

AV_DD

AV_SS

・

BU95303

Top View

・

DV_SS

CLK_P

CLK_N

STB

・

POL

・

INV

D_02P

D_02N

D_01P

D_01N

D_00P

・

D_00N

SEL1

SEL0

SFTR

OREP1

IREP1

↓

BUMP

Fig.2 Pin configuration (Top View)

www.rohm.com

2010.10 - Rev.A

6/14

Technical Note

BU95303

●Pin Descriptions

Pin Name

In/Out

Active

Descriptions

RSDS^TMinput terminals of display data

D_00P/N~ D_02P/N

D_10P/N~ D_12P/N

_20P/N~ D_22P/N

Differential The 3-bit differential input pairs generate the internal 6-bit data through the

comparison between D_XXPand D_XXN

The RSDS^TMclock input pair generate the internal shift clock through the

comparison between CLK_Pand CLK_N.

CLK_P/N

Differential

Y1 ~ Y432

Out

Driver outputs for D/A converted 64 gray scale analog voltage.

The shift direction of internal shift register is controlled by this pin as shown below.

R/L=H : Right shift SFTR→Y1→Y432→SFTL

R/L

R/L=L : Left shift SFTL→Y432→Y1→SFTR

The output channel number is controlled by this pin as shown below.

Number of effective

SEL1

SEL0

Invalid output terminal

output terminal

384

414

420

Y193 ~ Y240 become Hi-Z

Y208 ~ Y225 become Hi-Z

Y211 ~ Y222 become Hi-Z

SEL0

SEL1

432(default)

This pin is pulled down to the DV_SSinside the IC.

Low power control pin

LPC1

LPC0

power condition

Strong power

Normal power

Ultra-low power

Low power(default).

LPC0

LPC1

This pin is pulled down to the DV_SSinside the IC.

SFTR=H: Right shift start pulse input terminal in cascade connection.

SFTR=L: Carry output terminal in cascade connection.

SFTR

SFTL

STB

In/Out

SFTL=H: Carry output terminal in cascade connection.

SFTL=L: Left shift start pulse input terminal in cascade connection.

The data in the data register are transferred to the data latch at the rising edge of STB,

then the gray scale voltages are output from the buffer at the falling edge of STB.

Terminal to specify inverting or non-inverting of display data

INV:H : Input data are inverted in the IC.

INV:L : Input data are not inverted.

Input for the γ-correction reference voltage

The following external reference voltages are input.

INV

V0 ~ V13

At the rising edge of STB, the state of POL are transferred to the driver.

POL=H : The reference voltage for odd number outputs are V0 to V6 and those

for even number outputs are V7 to V13.

POL

POL=L : The reference voltage for odd number outputs are V7 to V13 and those

for even number outputs are V0 to V6

IREP1,2

OREP1,2

AV_DD

Out

Repair amplifier input

Repair amplifier output

Power supply for driver block

Ground for AV_DD

AV_SS

DV_DD

Power supply for digital block

Ground for DV_DD

DV_SS

www.rohm.com

2010.10 - Rev.A

7/14

Technical Note

BU95303

●Relationship between Input Data and Output Terminals

R/L=H (Right Shift)

First

→

…

Last

D_10P~ D_12N

Y431

Data

D_00P~ D_02N

D_10P~ D_12N

D_20P~ D_22N

D_00P~ D_02N

Y430

D_20P~ D_22N

Y432

Output

R/L=L (Left Shift)

First

D_10P~ D_12N

Y431

→

…

Last

D_10P~ D_12N

Data

D_00P~ D_02N

Y430

D_20P~ D_22N

Y432

D_00P~ D_02N

D_20P~ D_22N

Output

●Relationship between R/L , SFTR , SFTL and Output Direction

R/L pin controls the shift direction of the internal shift resistor as shown below.

Terminal Right Shift Mode Left Shift Mode

R/L

“H”

“L”

SFTR

Input

Output

Input

SFTL

Output direction

Y1,Y2,Y3→Y432,Y431,Y430

Y432,Y431,Y130→Y3,Y2,Y1

●Relationship between POL and Output Polarity

POL

“H”

“L”

・

Y427

Y428

Y429

Y430

Y431

Y432

+: The reference voltage are V0 ~ V6

-: The reference voltage are V7 ~ V13

www.rohm.com

2010.10 - Rev.A

8/14

Technical Note

BU95303

●Relationship between Input Data and Output Voltage

The LCD driver output voltages are determined by the input data and 14γ-corrected power supply.

0.1V≦V13≦V12≦V11≦V10≦V9≦V8≦V7≦0.5AV_DD

0.5 AV_DD≦V6≦V5≦V4≦V3≦V2≦V1≦V0≦AV_DD-0.1V

V0 (VH0)

V1 (VH1)

V2 (VH16)

V3 (VH32)

V4 (VH48)

V5 (VH62)

V6 (VH63)

V7 (VL63)

V8 (VL62)

V9 (VL48)

V10 (VL32)

V11 (VL16)

V12 (VL1)

V13 (VL0)

00 01

62 63

Fig.3 Input data - γcorrection curve

www.rohm.com

2010.10 - Rev.A

9/14

Technical Note

BU95303

●γcorrection Power Supply Circuit

14 external γ-corrected power supply is connected to ladder resistors inside IC.

IC internal circuit

RS0

RS1

RS2

RS3

External

γ correction

power supply

RS4

RS5

V10

RS6

V11

RS7

V12

V13

Fig.4 γcorrection power supply circuit

www.rohm.com

2010.10 - Rev.A

10/14

Technical Note

BU95303

●RSDS^TMdata timing

thd2

tsu2

thd1

tsu1

thd1

tsu1

CLK_P/N

SFTR

D_00P/N

(0)

(1)

(0)

(1)

(0)

(1)

(2)

(3)

(2)

(3)

(2)

(3)

D_01P/N

(4)

(5)

(4)

(5)

(4)

(5)

D_02P/N

(0)

(1)

(0)

(1)

D_10P/N

D_11P/N

D_12P/N

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(0)

(1)

D_20P/N

(2)

(3)

(2)

(3)

D_21P/N

(4)

(5)

(4)

(5)

(4)

(5)

D_22P/N

Fig.5 RSDS^TMdata timing

www.rohm.com

2010.10 - Rev.A

11/14

Technical Note

BU95303

●Timing chart

Fig.6 Timing chart

www.rohm.com

2010.10 - Rev.A

12/14

Technical Note

BU95303

●Start pulse timing

2CLK period over

CLKP

1^st

2^nd

SFTR input

(SFTL)

2(O)

Invalid

1(E) 1(O) 2(E)

DATA

When the start pulse (SFTR, SFTL) is input two times, the data is sampled based on the second start pulse.

●Power Supply Sequence

Maintain the following power supply order to prevent the device from being destroyed.

Turn on power order : DV_DD→Input signal →AV_DD, V0 ~ V13

Turn off power order : AV_DD, V0 ~ V13 →Input signal →DV_DD

AV_DD

V0～V13

DV_DD

Input signal

DV_SS, AV_SS

●Notes for use

1. When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may

flow instantaneously.

Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of

connections.

2. For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal

powering sequence and delays.

Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of

wiring.

www.rohm.com

2010.10 - Rev.A

13/14

Technical Note

BU95303

●Ordering part number

B U

S R

Part No.

Reel packing specification

SR: A pattern side is an inner arrow.

The output side is the right side.

SL: A pattern side is an inner arrow.

The output side is the left side.

BR: A pattern side is an outside arrow.

The output side is the right side.

BL: A pattern side is an outside arrow.

The output side is the left side.

COF35

www.rohm.com

2010.10 - Rev.A

14/14

Notice

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consent of ROHM Co.,Ltd.

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"Products"). If you wish to use any such Product, please be sure to refer to the speciﬁcations,

which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein

illustrate the standard usage and operations of the Products. The peripheral conditions must

be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information speciﬁed in this document.

However, should you incur any damage arising from any inaccuracy or misprint of such

information, ROHM shall bear no responsibility for such damage.

The technical information speciﬁed herein is intended only to show the typical functions of and

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implicitly, any license to use or exercise intellectual property or other rights held by ROHM and

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The Products speciﬁed in this document are intended to be used with general-use electronic

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While ROHM always makes efforts to enhance the quality and reliability of its Products, a

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Please be sure to implement in your equipment using the Products safety measures to guard

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R1010

BU95103SR [ROHM]

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