BU95106SL [ROHM]
6bit RSDS Source Driver; 6bit的RSDS源驱动器型号: | BU95106SL |
厂家: | ROHM |
描述: | 6bit RSDS Source Driver |
文件: | 总15页 (文件大小:292K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Drivers for Large LCD Panels
6bit RSDSTM
Source Driver
BU95306
No.10043EAT03
●Description
ROHMLCD drivers for large panels are display drivers optimized for large LCDs in a variety of applications, including
desktop PCs, laptops, and TVs. The broad lineup is offered in low amplitude differential transmission interface type
(RSDSTM) featuring low EMI, 6bit gradation precision, and different output configurations (642 and up) for wide compatibility.
●Features
1) 600/618/630/642 output channels
2) 6bit 9pair RSDSTM inputs
3) Dot & n-line inversion available
4) Built-in 2ch repair amplifiers
5) γ correction is possible
6) Built-in input data reversing function (INV)
7) Output voltage range : AVSS+0.1V~AVDD-0.1V
8) High speed data transfer: fCLK (MAX) =85MHz
9) Logic power supply voltage (DVDD) : 2.3~3.6V
10) Driver power supply voltage (AVDD) : 8.0~13.5V
11) Package: COF48
●Applications
TFT LCD Panels
●Line up matrix
BU95101
384
BU95303
BU95306
BU95408
Number of outputs
384 / 414 / 420 / 432
600 / 618 / 630 / 642
684 / 690 / 702 / 720
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.10 - Rev.A
1/14
Technical Note
BU95306
●Absolute maximum ratings
Parameter
Symbol
DVDD
AVDD
VI1
Ratings
Unit
V
-0.3 ~ +4.5
Logic power supply voltage
Driver power supply voltage
Logic input voltage
-0.3 ~ +14.0
V
-0.3 ~ DVDD+0.3
-0.3 ~ DVDD+0.3
-0.3 ~ AVDD+0.3
-0.3 ~ AVDD+0.3
-55~+125
V
VO1
V
Logic output voltage
VI2
V
Driver input voltage
VO2
V
Driver output voltage
Storage temperature range
Tstg
℃
●Recommended Operating Range
Parameter
Symbol
DVDD
AVDD
V0~V15
VO
Ratings
+2.3 ~ +3.6
+8.0 ~ +13.5
0.1 ~ AVDD-0.1
0.1 ~ AVDD-0.1
150
Unit
V
Logic power supply voltage
Driver power supply voltage
γ-correction reference voltage
Driver output voltage
V
V
V
CL
pF
MHz
℃
Output load capacitance
Maximum clock frequency
fCLK(MAX)
Topr
85
-30 ~ +85
Operating temperature range
* AVSS=DVSS=0V
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2010.10 - Rev.A
2/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Electrical characteristics (DC)
(Unless otherwise noted, Ta=-30~+85℃, DVDD=2.3~3.6V, AVDD=8.0~13.5V, DVSS=AVSS=0V)
Limits
Parameter
Logic Part
Symbol
Unit
Conditions
Min.
Typ.
Max.
DVDD=3.3V, Data=00h-3Fh(dot),
fclk=65MHz, fstb=50kHz, 1Line-inverison
Logic supply current
Input “H” voltage
Input “L” voltage
Input “H” current
Input “L” current
Input “H” current 2
Input “L” current 2
Output “H” voltage
IDDL
V1H
V1L
I1H1
I1L1
I1H2
I1L2
-
4
-
8
mA
V
R/L,SFTR,INV,SFTL,
POL,STB,SEL0,SEL1,
LPC0,
0.7DVDD
DVDD
0
-
-
0.3DVDD
V
LPC1 ,TEST0
-
+1
-
μA VIN=DVDD
μA VIN=DVSS
Dxx, SFTR, POL, INV,
SFTL,CLK,STB,R/L
-1
-
-
VIN=DVDD
μA
20
-
40
+3
-
SEL0,SEL1,
LPC0,LPC1,TEST0
Built-in Pull down R
DVDD=3.3V
-3
μA VIN=DVSS
VOH DVDD-0.5
-
V
V
IOH=-1.0mA
IOL=1.0mA
SFTR,SFTL
Output “L” voltage
Driver part
VOL
-
-
0.5
AVDD=12V, Data=00h-3Fh(dot),
mA fclk=65MHz, fstb=50kHz,1Line-inverison,
noLoad, LPC:normal
Driver supply current
IDDA
-
9
12
R
γ
10.9
10.8
15.5
15.4
20.2
20.0
kΩ V0~V7
kΩ V8~V15
UP
γ correction resistance
Rγ
LOW
AVDD=12V
Yout=0.1V~1.5V,Yout=10.5V~11.9V
mV AVDD=12V, Yout=1.5V~10.5V
-
-
-
-
-
±25
±10
±25
±3
-
mV
*1
Output voltage deviation
VOD1
±25
-
AVDD=12V
Yout=0.1V~1.5V,Yout=10.5V~11.9V
mV
Output swing voltage
Deviation
*2
VRMS
±10
±7.5
mV AVDD=12V, Vout=1.5V~10.5V
mV AVDD=12V, Data=32-gray
Output voltage deviation 2
(between chips)
*3
VOD2
-
Repair input voltage
V1NB
I1BH
I1BL
0.1
-1
-
-
-
AVDD-0.1
+1
V
Repair input “H” current
Repair input “L” current
μA VIN=AVDD=13.5V
μA VIN=AVSS
IREP1,2
-1
+1
IVOHY
IVOHR
IVOLY
IVOLR
-
-
-
-
-
-0.4
mA Y1~Y642, AVDD=12V, Vx=6 V,Yout=11V
mA OREP1,2 ,AVDD=12V, Vx=6 V, Yout=11V
mA Y1~Y642, AVDD=12V, Vx=6 V,Yout=1V
mA OREP1,2 ,AVDD=12V, Vx=6 V, Yout=1V
Driver output “H” current
-
-0.8
0.4
0.8
-
-
Driver output“L” current
RSDSTM input part
RSDSTM input “H” voltage
VIHRSDS
VILRSDS
100
-
200
-
mV
VCMRSDS=+1.2V*4
RSDSTM input “L” voltage
-200
-100
mV
CLKP/N,DXXP/N
(X=0,1,2)
RSDSTM common input
voltage
VCMRSDS
0.4
-
DVDD-1.2
V
VDIFF=200mV*5
*1
*2
*3
*4
*5
VOD1=measured output voltage - averaged output voltage of all outputs
V
V
RMS=measured output swing voltage - averaged output swing voltage of all outputs
OD2=averaged output voltage - target value
VCM RSDS = (VCLKP+VCLKN)/2 or (VDXXP+VDXXN)/2
DIFF = VCLKP- VCLKN or VDXXP-VDXXN
V
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2010.10 - Rev.A
3/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Electrical characteristics (AC)
(Unless otherwise noted, Ta=-30~+85℃, DVDD=2.3~3.6V, AVDD=8.0~13.5V, DVSS=AVSS=0V)
Limits
Parameter
Clock pulse width
Symbol
Unit
Conditions
Min.
Typ.
-
Max.
-
tw
th
1/85MHz
ns
Clock pulse "H" period
Clock pulse "L" period
Data setup time
5
5
2
0
1
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
tl
ns
tsu1
thd1
tsu2
thd2
tWSFT
tdc
-
ns
Data hold time
-
ns
Start pulse setup time
Start pulse hold time
Start pulse width
-
ns
ns
-
2
11
-
CLK period
ns
Carry output delay time
STB pulse width
CL=15pF
tWSTB
tLDT
1
1
6
4
14
CLK period
CLK period
CLK period
ns
Final data timing
-
Time between STB↑and start pulse↑ tSTB-SFT
-
Time between STB↑and CLK↓
tSTB-CLK
tsp
-
POL/STB setup time
-
ns
*1*3
*2*3
*1*3
*2*3
-
-
-
-
-
-
-
-
3
5
5
7
μs
μs
μs
μs
LPC:normal
LPC:normal
Output delay time
tdout
LPC:low power
LPC:low power
*1
*2
*3
The value is specified when the drive voltage value reaches the target output voltage level of 90%.
The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
Output load condition:
R1=R2=R3=10kΩ, C1=C2=C3=20pF
R1
R2
R3
Output
(Test Probe)
C1
C2
C3
Vcom=AVSS
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2010.10 - Rev.A
4/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Block diagram
・・・・・・・・・・・・・・・・・
AVDD
AVSS
LPC0,LPC1
2
Output Buffer
OREP2
IREP2
・・・・・・・・・・・・・・・・・
OREP1
IREP1
14
D/A Converter
V0 V13
~
POL
6
6 6
6 6 6
・・・・・・・・・・・・・・・・・
Level Shifter
6
6 6 6
6 6
・・・・・・・・・・・・・・・・・
Data Latch
・・・・・・・・・・・・・・・・・
STB
6 6 6
6 6
6
Data Register
00P/N
D
02P/N
D
~
D10P/N D12P/N
~
20P/N
D
22P/N
D
~
INV
214 bit Bi-directional Shift Register
2
CLKP/N
SEL1, SEL0
DVDD
SFTL
SFTR R/L
DVSS
Fig.1 Block diagram
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.10 - Rev.A
5/14
Technical Note
BU95306
●Pin configuration
IREP2
OREP2
AVSS
Y642
Y641
Y640
・
AVDD
DVSS
DVDD
・
・
SFTL
D22P
D22N
D21P
D21N
D20P
D20N
D12P
D12N
D11P
D11N
D10P
D10N
DVDD
LPC0
R/L
・
・
・
・
・
・
・
V15
V14
V13
V12
V11
V10
V9
V8
AVDD
AVSS
V7
・
・
・
・
BU95306
Top View
V6
V5
V4
V3
・
・
・
V2
V1
V0
DVSS
TEST0
CLKP
CLKN
STB
POL
INV
D02P
D02N
D01P
D01N
D00P
D00N
SEL1
SEL0
SFTR
DVDD
LPC1
DVSS
AVSS
AVDD
OREP1
IREP1
・
・
・
・
・
・
・
・
・
Y3
Y2
Y1
↓
BUMP
BUMP
IC
Fig.2 Pin configuration (Top View)
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2010.10 - Rev.A
6/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Pin Descriptions
Pin Name
In/Out
In
Active
Descriptions
RSDSTM input terminals of display data
D00P/N~D02P/N
10P/N~D12P/N
20P/N~D22P/N
D
D
Differential The 3-bit differential input pairs generate the internal 6-bit data through the
comparison between DXXP and DXXN
.
The RSDSTM clock input pair generate the internal shift clock through the
comparison between CLKP and CLKN.
CLKP/N
In
Differential
-
Y1~Y642
Out
Driver outputs for D/A converted 64 gray scale analog voltage.
The shift direction of internal shift register is controlled by this pin as shown below.
R/L=H : Right shift SFTR→Y1→Y642→SFTL
R/L=L : Left shift SFTL→Y642→Y1→SFTR
R/L
In
In
-
The output channel number is controlled by this pin as shown below.
Number of effective
output terminal
600
618
630
SEL1
SEL0
Invalid output terminal
H
H
L
H
L
H
L
Y301~Y342 become Hi-Z
Y310~Y333 become Hi-Z
Y316~Y327 become Hi-Z
-
SEL0
SEL1
-
L
642 (default)
This pin is pulled down to the DVSS inside the IC.
Low power control pin
LPC1
LPC0
H
L
H
L
power condition
Strong power
Normal power
Ultra-low power
Low power(default).
H
H
L
LPC0
LPC1
In
H
L
This pin is pulled down to the DVSS inside the IC.
SFTR=H:Right shift start pulse input terminal in cascade connection.
SFTR=L:Carry output terminal in cascade connection.
SFTR
SFTL
STB
In/Out
In/Out
In
H
H
SFTL=H:Carry output terminal in cascade connection.
SFTL=L:Left shift start pulse input terminal in cascade connection.
The data in the data register are transferred to the data latch at the rising edge of STB,
then the gray scale voltages are output from the buffer at the falling edge of STB.
Terminal to specify inverting or non-inverting of display data
INV:H : Input data are inverted in the IC.
INV:L : Input data are not inverted.
Input for the γ-correction reference voltage
The following external reference voltages are input.
INV
In
In
H
-
V0~V15
At the rising edge of STB, the state of POL are transferred to the driver.
POL=H : The reference voltage for odd number outputs are V0 to V7 and those for
even number outputs are V8 to V15.
POL
In
-
POL=L : The reference voltage for odd number outputs are V8 to V15 and those for
even number outputs are V0 to V7
IREP1,2
OREP1,2
AVDD
In
Out
In
-
-
-
-
-
-
Repair amplifier input
Repair amplifier output
Power supply for driver block
Ground for AVDD
AVSS
In
DVDD
In
Power supply for digital block
Ground for DVDD
DVSS
In
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2010.10 - Rev.A
7/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Relationship between Input Data and Output Terminals
R/L=H (Right Shift)
First
→
…
…
Last
D00P~D02N D10P~D12N D20P~D22N
Data
D00P~D02N D10P~D12N D20P~D22N
Output
Y1
Y2
Y3
Y640
Y641
Y642
R/L=L (Left Shift)
First
→
…
…
Last
Data
D00P~D02N D10P~D12N D20P~D22N
Y640 Y641 Y642
D00P~D02N D10P~D12N D20P~D22N
Y1 Y2 Y3
Output
●Relationship between R/L , SFTR , SFTL and Output Direction
R/L pin controls the shift direction of the internal shift resistor as shown below.
Terminal Right Shift Mode Left Shift Mode
R/L
“H”
“L”
SFTR
Input
Output
Output
Input
SFTL
Output direction
Y1,Y2,Y3→Y640,Y641,Y642
Y642,Y641,Y640→Y3,Y2,Y1
●Relationship between POL and Output Polarity
POL
Y1
Y2
Y3
Y4
Y5
Y6
“H”
“L”
*1
*1
+
-
+
-
+
-
-
+
-
+
-
+
・
・
・
・
・
・
Y637
Y638
Y639
Y640
Y641
Y642
+
-
+
-
+
-
-
+
-
+
-
+
*1
+: The reference voltage are V0~V7
: The reference voltage are V8~V15
-
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2010.10 - Rev.A
8/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Relationship between Input Data and Output Voltage
The LCD driver output voltages are determined by the input data and 16γ-corrected power supply.
0.1V≦V15≦V14≦V13≦V12≦V11≦V10≦V9≦V8≦0.5AVDD
0.5 AVDD≦V7≦V6≦V5≦V4≦V3≦V2≦V1≦V0≦AVDD -0.1V
V1(upper side:00)
V2(upper side:16)
V3(upper side:20)
V4(upper side:24)
V5(upper side:32)
V6(upper side:56)
V7(upper side:63)
V8(lower side:63)
V9(lower side:56)
V10(lower side:32)
V11(lower side:24)
V12(lower side:20)
V13(lower side:16)
V14(lower side:00)
00
16 20 24
32
56
63
Fig.3 Input data - γ correction curve
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.10 - Rev.A
9/14
Technical Note
BU95306
●γ correction Power Supply Circuit
16 external γ-corrected power supply is connected to ladder resistors inside IC.
IC Internal Circuit
V0
RS0 = 476Ω
V1
RS1 = 7,523Ω
V2
RS2 = 705Ω
V3
RS3 = 573Ω
V4
RS4 = 981Ω
V5
RS5 = 2,433Ω
V6
External
γ-corrected
power supply
RS6 = 2,819Ω
V7
V8
RS7 = 3,290Ω
V9
RS8 = 2,916Ω
V10
RS9 = 933Ω
V11
RS10 = 543Ω
V12
RS11 = 669Ω
V13
RS12 = 6,678Ω
V14
RS13 = 392Ω
V15
Fig.4 γ correction power supply circuit
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2010.10 - Rev.A
10/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●RSDSTM data timing
thd2
tsu2
thd1
tsu1
thd1
tsu1
CLKP/N
SFTR
D00P/N
Y1
(0)
Y1
(1)
Y7
(0)
Y7
(1)
Y4
(0)
Y4
(1)
Y1
(2)
Y1
(3)
Y4
(2)
Y4
(3)
Y7
(2)
Y7
(3)
D01P/N
Y4
(4)
Y4
(5)
Y7
(4)
Y7
(5)
Y1
(4)
Y1
(5)
D02P/N
Y5
(0)
Y2
(0)
Y2
(1)
Y5
(1)
Y8
(0)
Y8
(1)
D10P/N
D11P/N
D12P/N
Y8
(2)
Y2
(2)
Y2
(3)
Y5
(2)
Y5
(3)
Y8
(3)
Y2
Y8
(4)
Y8
(5)
Y2
(5)
Y5
(4)
Y5
(5)
(4)
Y6
(0)
Y3
(0)
Y9
(0)
Y9
(1)
Y3
(1)
Y6
(1)
D20P/N
Y9
(2)
Y9
(3)
Y3
(3)
Y3
(2)
Y6
(2)
Y6
(3)
D21P/N
Y3
(4)
Y3
(5)
Y6
(4)
Y6
(5)
Y9
(4)
Y9
(5)
D22P/N
Fig.5 RSDSTM data timing
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2010.10 - Rev.A
11/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Timing chart
Fig.6 Timing chart
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2010.10 - Rev.A
12/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Start pulse timing
2CLK period over
CLKP
1st
2nd
SFTR input
(SFTL)
2(O)
Invalid
1(E) 1(O) 2(E)
DATA
When the start pulse (SFTR, SFTL) is input two times, the data is sampled based on the second start pulse.
●Power Supply Sequence
Maintain the following power supply order to prevent the device from being destroyed.
Turn on power order : DVDD →Input signal →AVDD, V0~V15
Turn off power order : AVDD, V0~V15 →Input signal →DVDD
AVDD
V0~V15
DVDD
Input signal
DVSS, AVSS
t
●Notes for use
1. When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may
flow instantaneously.
Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of
connections.
2. For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal
powering sequence and delays.
Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of
wiring.
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2010.10 - Rev.A
13/14
© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BU95306
●Ordering part number
B U
9
5
3
0
6
-
S R
Part No.
Part No.
Reel packing specification
SR: A pattern side is an inner arrow.
The output side is the right side.
SL: A pattern side is an inner arrow.
The output side is the left side.
BR: A pattern side is an outside arrow.
The output side is the right side.
BL: A pattern side is an outside arrow.
The output side is the left side.
COF48
<Tape dimensions>
<Packing specifications>
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.10 - Rev.A
14/14
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The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
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R1010
A
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