BU9735KV-E2 [ROHM]
Liquid Crystal Driver, 18-Segment, PQFP32, ROHS COMPLIANT, VQFP-32;
| 型号： | BU9735KV-E2 |
| 厂家： | 
ROHM |
| 描述： | Liquid Crystal Driver, 18-Segment, PQFP32, ROHS COMPLIANT, VQFP-32 驱动 接口集成电路 |
| 文件： | 总26页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
LCD Segment Driver series
For 72/80/96 Segment type LCD
LCD Segment Driver
BU9735K, BU9796FS, BU9716BKV, BU9718KV
● Outline
This is LCD segment driver for 72-96 segment type display. There is a lineup which is suitable for multi
function display and is integrated display RAM and power supply circuit for LCD driving with 4 common
output type: BU9735K and BU9796FS. And 3 common output type: BU9716BKV and BU9718KV.
○ 72Segment (18SEG×4COM) Driver BU9735K
○ 80Segment (20SEG×4COM) Driver BU9796FS
○ 96Segment (32SEG×3COM) Driver BU9716BKV/BU9718KV
・・・・・・・P.1
・・・・・・・P.9
・・・・・・・P.19
BU9735K
72Segment (18SEG×4COM) Driver
● Feature
______________
__________
1) 4wire serial interface (SCK, SD, C/D, CS)
2) Integrated RAM for display data (DDRAM) ： 18 × 4bit (Max 72 Segment)
3) LCD driving port： 4 Common output, 18 Segment output
4) Display duty： 1/4 duty
5) Integrated Oscillator circuit (external resister type)
6) Integrated Power supply circuit for LCD driving (1/3 bias)
7) Low power/ Ultra low power consumption design： +2.5～5.5V
● Uses
DVC, Car audio, Telephone
● Absolute Maximum Ratings （Ta=25degree, VSS=0V） (BU9735K)
Parameter
Symbol
VDD
Limits
Unit
V
Remarks
Power Supply Voltage1
Power Supply Voltage2
-0.3 ～ +7.0
-0.3 ～ +7.0
Power supply
LCD drive voltage
VLCD
V
When use more than Ta=25C, subtract
4mW per degree.
Allowable loss
Pd
400
mW
Operational temperature range
Storage temperature range
Input voltage range
Topr
Tstg
-40 ～ +85
-55 ～ +125
Degree
Degree
VIN
-0.3 to VDD*0.3
-0.3 to VDD+0.3
V
V
Output voltage range
VOUT
*This product is not designed against radioactive ray.
● Recommend operating conditions (Ta=25degree, VSS=0V) (BU9735K)
Parameter
Symbol
VDD
VLCD
fOSC
MIN
2.2
2.5
-
TYP
MAX
5.5
5.5
-
Unit
V
V
Remarks
Power Supply Voltage1
Power Supply Voltage2
Oscillator frequency
-
-
VLCD≧VC≧VSS
36
KHz
Rf=470kΩ
This document is not delivery specifications.
Jun. 2008
● Electrical Characteristics (BU9735K)
DC Characteristics (VDD=2.5～5.5V, VSS=0V, Ta=25degree, unless otherwise specified)
Limit
Typ.
-
Symb
ol
Parameter
Unit
Condition
Terminal
Min.
Max.
VDD
SC1, SD, SCK,
VIH1
VIL1
RON
IIH
0.8×VDD
“H” level input voltage
“L” level input voltage
LCD Driver on resistance
______________ __________
V
C / D, CS
0
-
-
-
0.2×VDD
30
SEG1～18, COM1～4
KΩ
|△
VON|=0.1V
OSC1, SD, SCK,
-2
-
-
-
-
2
-
uA VIN=VDD
uA VIN=0
pF
“H” level input current
“L” level input current
Input capacitance
______________ __________
C / D, CS,
IIL
____ ___ ____
_________
CI
-
5
SD, SCK, C / D, CS
-
0.05
1
uA *2 Display OFF
uA *2 Display ON
uA *3 MPU Access
Power consumption
IDD
VDD
-
-
30
80
70
200
*1: LCD Driver on resistance is not included internal power supply impedance.
*2: VLCD=VDD, Rf=470Kohm, except of OSC1 terminals are connected to VDD or VSS.
*3: VLCD=VDD, Rf=470Kohm, fSCK=200KHz
AC Characteristics (VDD=2.5～5.5V, VSS=0V, Ta=25degree, unless otherwise specified)
Limit
Parameter
Symbol
Unit
Condition
Min.
-
Typ.
Max.
SCK rise time
tTLH
tTHL
tCYC
tWAIT
tWH1
tWL1
tSU1
tH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK fall time
-
100
SCK cycle time
800
800
300
300
100
100
300
6400
100
100
100
100
100
100
140
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Wait time for command
SCK pulse width H”
SCK pulse width ”L”
SD setup time
SD hole time
__________
CS pulse width ”H”
tWH2
tWL2
tSU2
tH2
__________
CS pulse width ”L”
__________
CS setup time
__________
CS hold time
______________
C / D setup time
tSU3
tH3
______________
C / D hold time
Based on SCK 8th clock rising
______________
__________
_________
C / D - CS time*4
tCCH
tSCH
tON
Based on CS rising
______________
C / D - SCK time*4
Based o SCK 8th clock falling
SCK 8th clock rising to display start
Display start delay time
*4: should satisfy either one condition
tWH2
tWL2
CS
tSU2
tTH2
tCYC
tWH1
tCYC
tWAIT
SCK
SCK
tWL1
tTLH
tH1
tTHL
SD
D7
D6
D0
D7
tSU1
SD
tCCH
tSCH
tSU3
tTH3
C/D
Fig. BU9735K-1 Interface timing
Fig. BU9735K-2 Command cycle
2/25
● Block Diagram （BU9735K）
●Pin Arrangement （BU9735K）
VLCD
VDD
VSS
SEG1
SEG
LCD
Segment
Driver
24
23
22
21
20
19
18
17
2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG2
SEG1
COM4
COM3
COM2
COM1
C/D
Display Data RAM
(DD RAM)
SD
SCK
C/D
CS
18bits
Address
Counter
Serial
Interface
SEG18
LCD Driver
Bias Circuit
V
C
Command/Data
Register
COM
1
LCD
Common
Driver
Timing
Common
Counter
CS
COM2
COM3
Generator
1
2
3
4
5
6
7
8
Command
Decoder
4bits
COM
4
Fig. BU9735K-3 Block diagram
Fig. BU9735KV-4 Pin arrangement
● Terminal description （BU9735K）
Terminal
No.
Type
Function
OSC1
OSC2
1
2
I
O
Int clock use mode, connect resister between OSC1 and OSC2.
Ext clock use mode, input clock from OSC1, OSC2 keep OPEN.
VSS
3
VSS terminal
VC
VLCD
4
5
Power supply for LCD driving
Please keep VLCD≧VC≧VSS condition
VDD
SCK
6
7
VDD terminal
I
I
I
Serial clock input
SD
__________
CS
8
9
Serial data input
Chip select input "L": active,
______________
Command data judgment input
“L”: display data, “H”: command
C/D
10
I
COM1～4
SEG1～18
11～14
15～32
O
O
LCD COMMON output
LCD SEGMENT output
3/25
● Block Description (BU9735K)
◯ ADDRESS COUNTER
An address counter shows the address of DDRAM. Address data are transferred to the address
counter automatically when an address set is written in the command/data register.
After data are written in DDRAM, +1 or +2 is done automatically with an address counter. The
choice of +1 or +2 is done automatically by the next condition.
DDRAM 8bit writing (in the 8 clock of SCK, C/D= "L")
→ +2
DDRAM 4bit rewriting (in the 8 clock of SCK, C/D= "H") → +1
And, when it is counted to 11H, an address becomes 00H with an address counter by the next count
up.
◯ DISPLAY DATA RAM (DDRAM)
A display data RAM (DDRAM) is used to store display data. That capacity is 18 address × 4 bits.
DDRAM and the relations of the display position are as the following.
DDRAM Address
00 01 02 03 04 05 06 07 ・・・・・ 0F 10 11
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
COM1
COM2
COM3
COM4
BIT
4bit
re-writing
8bit writing
・・・・・
◯ TIMING GENERATER
A built-in oscillator circuit does oscillated by connecting Rf between OSC1, OSC2, and an indication
timing signal is caused. And, it is possible that it is made to work by the external clock input, too.
1
1
OSC
OSC
EXTERNAL CLOCK INPUT
Rf
2
OSC
OSC
2
OPEN
(It is possible that Oscillating Frequency
is changed with Rf. )
Fig. BU9735K-5 Rf Oscillator Circuit
Fig. BU9735K-6 External Clock Input
◯ LCD DRIVE POWER SUPPLY
LCD drive power supply occurs by BU9735K.
LCD voltage is given by VC, and it causes V1=(2/3) VC, V2=(1/3) VC.
VDD
VLCD
VC
VSS
Fig. BU9735K-7 Internal Power Supply use
4/25
● DETAILS OF COMMANDS (BU9735K)
There is the following thing in the command (The 8×n clock of SCK is C/D= "H".) of BU9735K.
◯ ADDRESS SET
MSB
LSB
A
0
0
0
A
A
A
A
Address data shown as AAAAA by the binary system is set on the address counter.
Address does +2 every time indication data input (for 8bit) completes input.
◯ DISPLAY ON
MSB
LSB
*
0
0
1
*
*
*
*
*：Don't Care
There are no relations with the contents of the display data RAM (DDRAM).
And all display is turned on. In this case, the contents of DDRAM don't change.
◯ DISPLAY OFF
MSB
LSB
0
1
0
*
*
*
*
*
*：Don't Care
There are no relations with the contents of the display data RAM (DDRAM).
And all display is turned off. A built-in power supply circuit is turned off.
And an oscillation circuit stops. In this case, the contents of DDRAM don't change.
◯ DISPLAY START
MSB
LSB
0
1
1
*
*
*
*
*
*：Don't Care
Display is started in accordance with the contents of DDRAM.
◯ REWRITING OF THE DISPLAY DATA RAM (DDRAM)
MSB
LSB
1
0
0
*
D
D
D
D
*：Don't Care
The binary four bits data DDDD are written in DDRAM.
A writing address is address ordered by the address set command.
Then, after this command is carried out, an address does + 1 automatically.
◯ RESET
MSB
1
LSB
1
0
*
*
*
*
*
*：Don't Care
This command is to take precedence over all commands after POWER-on, and carry it out.
BU9735K is initialized in the following condition by this command.
・
・
・
Display off
Address counter resetting
Oscillation stop
5/25
● Recommendation circuit example (BU9735K)
VDD
*1 The value (840kΩ) of the built-in resistance
value in the figure is reference value. Value
varies according to terms of manufacture and
so on.
VLCD
*3
RC
VC
VC
*2 The maximum value of the signal of the control
isn't to use higher value than VDD. (Refer to the
regulation of the input voltage in the
specifications.)
*1
840kΩ
V1 BU9735K
*1
840kΩ
3.3V
5.0V
V2
*3 It can use as a resistance for the contrast
adjustment when variable resistance is given to
the VLCD-VC space. In this case, the
resistance of the outside and resistance with
built-in BU9735K become connections like a
left figure. The value of RC is to decide the
value, which met a system referring to the
circuit of the left figure.
*1
840kΩ
VSS
VSS
OSC1
OSC2
SCK
SD
CS
C/D
470kΩ
*2
From the controller
Fig. BU9735K-8 Power supply for control circuit and LCD driving is independent case
(Example: VLCD=5.0V and VDD=3.3V)
● INPUT OUTPUT CIRCUIT (BU9735K)
Name
I/O
Circuit
Name
I/O
O
Circuit
SD
I
SEG1
～
SEG18
VLCD
SCK
C/D
CS
VDD
GND
COM1
～
COM4
IN
GND
OUT
VLCD
GND
Name
I/O
Circuit
I
O
VDD
GND
OSC1
OSC2
OSC1
VDD
GND
OSC2
Fig.BU9735K-9 I/O circuit
6/25
● Cautions on use
(1) Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices,
thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings
is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
(2) Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed
under the conditions of each parameter.
(3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection,
such as mounting an external diode between the power supply and the IC’s power supply terminal.
(4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power
supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for
the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from
impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use
an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of
capacity dropout at a low temperature, thus determining the constant.
(5) GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure
no terminals are at a potential lower than the GND voltage including an actual electric transient.
(6) Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore,
if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal,
the ICs can break down.
(7) Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8) Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge
from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF
the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount
it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
(9) Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention
not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will
operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power
supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
(10) Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal
GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to
a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of
external parts as well.
(11) External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance
due to DC bias and changes in the capacitance due to temperature, etc.
(12) No Connecting input terminals
In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside
gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes
unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line.
(13) Rush current
When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow
instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.
7/25
● Order form name selection
－
B U
9
7 3 5
K
E 2
ROHM form name
Part No.
Package type
KV=VQFP
Packaging and forming specification
E2 =Reel-shaped emboss taping
QFP32
<Dimension>
<Packing information>
Tape
Embossed carrier tape
9.0 0.3
7.0 0.2
Quantity
1500pcs
E2
Direction
of feed
24
17
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
25
32
16
9
1
8
0.15 0.1
0.8
0.4 0.1
0.15
1Pin
Reel
（Unit:mm)
※When you order , please order in times the amount of package quantity.
8/25
BU9796FS
80Segment (20SEG×4COM) Driver
● Feature (BU9796FS)
1) 2wire serial interface
2) Integrated RAM for display data (DDRAM) ： 20 × 4bit (Max 80 Segment)
3) LCD driving port： 4 Common output, 20 Segment output
4) Display Duty: 1/4 duty
5) Integrated Oscillation circuit
6) Integrated Buffer AMP for LCD driving power supply circuit
7) Support 1/2bias, 1/3bias select
8) No external components
9) Low voltage / low power consumption design: 2.5～5.5V
● ● Uses (BU9796FS)
Telephone, FAX, Portable equipments （POS, ECR, PDA etc.）,
DSC, DVC, Car audio, Home electrical appliance, Meter equipment etc.
● Absolute Maximum Ratings （Ta=25degree, VSS=0V） (BU9796FS)
Parameter
Symbol
VDD
Limits
Unit
V
Remarks
Power Supply Voltage1
Power Supply Voltage2
-0.5 ～ +7.0
-0.5 ～ +7.0
Power supply
VLCD
V
LCD drive voltage
When use more than Ta=25C, subtract
6.4mW per degree.
Allowable loss
Pd
VIN
Topr
0.64
W
V
Input voltage range
Operational temperature
range
-0.5 ～ VDD+0.5
-40 ～ +85
degree
Storage
range
temperature
Tstg
-55 ～ +125
degree
*This product is not designed against radioactive ray.
● Recommend operating conditions (Ta=25degree, VSS=0V) (BU9796FS)
Parameter
Symbol
VDD
MIN
2.5
0
TYP
MAX
5.5
Unit
V
Remarks
Power Supply Voltage1
Power Supply Voltage2
-
-
Power supply
LCD drive voltage
VLCD
VDD-2.4
V
* Please use in the range of VDD-VLCD≧ 2.4V
9/25
● Electrical Characteristics (BU9796FS)
DC Characteristics (VDD=2.5～5.5V, VLCD=0V, VSS=0V, Ta=-40～85degree, unless otherwise specified)
Limit
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
VIH
VIL
0.7VDD
-
-
VDD
V
VSS
0.3VDD
V
IIH
-
-1
-
-
1
uA
uA
kΩ
kΩ
V
IIL
-
-
SEG
RON
RON
VLCD
IDD1
3
3
-
-
LCD Driver
Iload=±10uA
on resistance
COM
-
-
VDD-2.4
5
VDD-VLCD 2.4V
VLCD supply voltage
Standby current
0
-
-
uA
Display off, Oscillation off
VDD=3.3V, VLCD=0V, Ta=25degree
Power save mode SR = Power save mode1,
Power consumption
IDD2
-
12.5
30
uA
Power save mode FR = Power save mode1
1/3 bias, Frame inverse
56
80
104
Frame frequency
fCLK
Hz Power save mode FR = Normal mode
MPU interface Characteristics (VDD=2.5～5.5V, VLCD=0V, VSS=0V, Ta=-40～85degree, unless otherwise specified)
Limit
TYP.
Parameter
Input rise time
Symbol
Unit
Condition
MIN.
-
-
MAX.
0.3
0.3
tr
tf
-
-
-
-
-
-
-
-
-
-
-
us
us
us
us
us
ns
ns
us
us
us
us
Input fall time
2.5
0.6
1.3
100
100
1.3
0.6
0.6
0.6
SCL cycle time
“H” SCL pulse width
“L” SCL pulse width
SDA setup time
SDA hold time
tSCYC
tSHW
tSLW
tSDS
tSDH
tBUF
-
-
-
-
-
-
-
-
-
Buss free time
START condition hold time tHD;STA
START condition setup time tSU;STA
STOP condition setup time tSU;STO
SDA
tf
tr
tcyc
tLW
tBUF
SCL
SDA
tSDH
tHW
tSDS
tHD;STA
t r
tSU;STO
tSU;STA
Fig. BU9796FS-1 interface timing
10/25
●Block Diagram （BU9796FS）
● Pin Arrangement （BU9796FS）
COM0……COM3
SEG0……SEG19
VDD
LCD voltage generator
common
driver
Segment
driver
＋
－
LCD
BIAS
SELECTOR
common
counter
blink timing
generator
＋
－
DDRAM
VLCD
Command
register
Command
Data Decoder
OSCIN
OSCILLATOR
Power On Reset
serial inter face
IF FILTER
VSS
SDA
SCL
Fig. BU9796FS-2 block diagram
Fig. BU9796FS-3 Pin arrangement
●Terminal description （BU9796FS）
Terminal
Terminal
TEST1
I/O
Function
No.
Test input (ROHM use only)
Must be connect to VSS
Test input (ROHM use only)
26
I
I
TEST2=”L”: POR circuit enable
TEST2
27
28
TEST2=”H”: POR circuit disenable,
refer to “Cautions in Power ON/OFF”
External clock input
OSCIN
I
Ext clock and Int clock can be changed by command.
Must be connect to VSS when use internal oscillation circuit.
SDA
SCL
VSS
VDD
VLCD
30
29
25
24
23
I/O serial data in-out terminal
I
serial data transfer clock
GND
Power supply
Power supply for LCD driving
31,32
1-18
19-22
SEG0-19
COM0-3
O
O
SEGMENT output for LCD driving
COMMON output for LCD driving
11/25
● Command Description （BU9796FS）
D7 (MSB) is bit for command or data judgment.
Refer to Command and data transfer method.
C： 0： Next byte is RAM write data.
1： Next byte is command.
○ Display control (DISCTL)
MSB
D7
C
LSB
D0
P0
D6
0
D5
1
D4
P4
D3
P3
D2
P2
D1
P1
Set Power save mode FR
Setup
P4
0
0
1
1
P3
Reset initialize condition
Normal mode
0
1
0
1
○
Power save mode1
Power save mode2
Power save mode3
Set LCD drive waveform
Setup
P2
0
1
Reset initialize condition
Line inversion
Frame inversion
○
Set Power save mode SR
Setup
P1
0
0
P0
0
1
Reset initialize condition
Power save mode1
Power save mode2
Normal mode
1
0
○
High power mode
1
1
* Please keep condition VDD-VLCD≧3.0V in High power mode.
○ Mode Set (MODE SET)
MSB
D7
C
LSB
D0
*
D6
1
D5
0
D4
*
D3
P3
D2
P2
D1
*
(*: Don’t Care)
Set display ON and OFF
Setup
Display OFF
Display ON
P3
0
1
Reset initialize condition
○
Set bias level
Setup
P3
0
1
Reset initialize condition
1/3 Bias
1/2 Bias
○
12/25
○ Address set (ADSET)
MSB
D7
C
LSB
D0
P0
D6
0
D5
0
D4
P4
D3
P3
D2
P2
D1
P1
The range of address can be set as 00000 to 10011(2).
○ Set IC Operation (ICSET)
MSB
D7
C
LSB
D0
P0
D6
1
D5
1
D4
0
D3
1
D2
*
D1
P1
(*: Don’t Care)
Set software reset execution
Setup
P1
0
No operation
Software Reset execute
1
Set oscillator mode
setup
P0
0
1
Reset initialize condition
Internal oscillation
External clock input
○
○ Blink control (BLKCTL)
MSB
D7
C
LSB
D0
P0
D6
1
D5
1
D4
1
D3
0
D2
*
D1
P1
(*: Don’t Care)
Set blink mode
Blink mode (Hz)
P1
0
0
P0
0
1
Reset initialize condition
OFF
0.5
1
○
1
0
2
1
1
○ All Pixel control (APCTL)
MSB
LSB
D7
C
D6
1
D5
1
D4
1
D3
1
D2
1
D1
P1
D0
P0
All display set ON, OFF
APON P1
Normal
Reset initialize condition
0
1
○
All pixel ON
APOFF
Normal
P0
0
Reset initialize condition
○
All pixel OFF
1
13/25
● Function description （BU9796FS）
○ Command transfer method
1byte after Slave Address always becomes command input.
MSB (“command or data judge bit”) of command decide to next data is command or display data.
When set “command or data judge bit”=‘1’, next byte will be command.
When set “command or data judge bit”=‘0’, next byte data is display data.
S
Slave address
Display Data
A
A
1 Command
A
1
Command
Command
A 1
A
0
…
P
Command
Once it becomes display data transfer condition, it cannot input command.
When want to input command again, please generate “START condition” once.
○ Write display and transfer method
This device has Display Data RAM (DDRAM) of 50×4=200bit.
The relationship between data input and display data, DDRAM data and address are as follows;
Slave address
Command
S
01111100
A
0 0000000
A
a
b
c
d
e
f
g
h
A
i
j
k
l
m
n
o
p
A
…
P
Display Data
DDRAM address
00
01
02
03
m
n
04
05
06
07
・・・
2Fh
30h
31h
0
1
2
3
a
e
i
j
COM0
COM1
COM2
COM3
b
c
f
g
BIT
k
l
o
d
h
p
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG47
SEG48
SEG49
Data transfer to DDRAM happens every 4bit data. So It will be finished to transfer with no need
to wait ACK.
○ Reset initialize condition
Initial condition after execute Software Reset is as follows.
・ Display is OFF.
・ DDRAM address is initialized (DDRAM Data is not initialized).
・ Refer to Command Description about initialize value of register.
14/25
● Cautions in Power ON/OFF (BU9796FS)
This device has “P.O.R” (Power-On Reset) circuit and Software Reset function.
Please keep the following recommended Power-On conditions in order to power up properly.
Please set power up conditions to meet the recommended tR, tF, tOFF, and Vbot spec
below in order to ensure P.O.R operation
* It has to set TEST2=”L” to be valid in POR circuit.
tF
VDD
Recommendation condition of tR, tF, tOFF, Vbot (Ta=25℃)
tR
tR
tF
tOFF
More than
100ms
Vbot
Less than 1ms Less than 1ms
Less than 0.1V
tOFF
Vbot
Fig. BU9796FS-4 Power ON/OFF waveform
If it is difficult to meet above conditions, execute the following sequence after Power-On.
* It has to keep the following sequence in the case of TEST2=”H”. As POR circuit is invalid status.
But it is not able to accept Command input in Power off status, it has to take care that
software reset is not perfectly alternative method of POR function.
(1) Generate STOP condition
VDD
SDA
SCL
STOP condition
Fig. BU9796FS-5 Stop condition
(2) Generate START condition.
(3) Issue slave address
(4) Execute Software Reset (ICSET) command
15/25
● IO Equivalent Circuit (BU9796FS)
VDD
VLCD
VSS
SDA
VSS
SCL
VSS
VDD
TEST1
VSS
VDD
TEST2
VSS
VDD
OSCIN
VSS
VLCD
SEG/COM
VSS
Fig. BU9796FS-6 I/O equivalent circuit
16/25
● Cautions on use
(1) Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices,
thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings
is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
(2) Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed
under the conditions of each parameter.
(3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection,
such as mounting an external diode between the power supply and the IC’s power supply terminal.
(4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power
supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for
the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from
impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use
an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of
capacity dropout at a low temperature, thus determining the constant.
(5)
GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure
no terminals are at a potential lower than the GND voltage including an actual electric transient.
(6)
Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore,
if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal,
the ICs can break down.
(7)
Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8) Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge
from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF
the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount
it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
(9) Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention
not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will
operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power
supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
(10) Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal
GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to
a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of
external parts as well.
(11) External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance
due to DC bias and changes in the capacitance due to temperature, etc.
(12) No Connecting input terminals
In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside
gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes
unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line.
(13) Rush current
When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow
instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.
17/25
● Order form name selection
－
B U
9
7 9 6
F S
E 2
Part No.
ROHM form name
Package type
Packaging and forming specification
E2 =Reel-shaped emboss taping
FS: SSOP-A32
SSOP-A32
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2000pcs
E2
13.6 0.2
Direction
of feed
32
17
16
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
1
0.15 0.1
0.1
0.8
0.36 0.1
Direction of feed
1pin
Reel
※When you order , please order in times the amount of package quantity.
（Unit:mm)
18/25
BU9716BKV／BU9718KV 96SEGMENT (32SEG×3COM) Driver
● Features (BU9716BKV/BU9718KV)
1) LCD driving port : 3 Common output, 32 Segment output
2) Display duty: 1/3duty
3) Each 1/2 or 1/3 can be selected for power supply for LCD display.
● Uses (BU9716BKV/BU9718KV)
Portable equipments （POS, ECR, PDA etc.）
DSC, DSC, Telephone etc.
● Line up (BU9716BKV/BU9718KV)
Parameter
Recommended operating voltage
Package
BU9716BKV
4.5～5.5V
VQFP-48C
BU9718KV
2.7～3.5V
VQFP-48C
● ABSOLUTE MAXIMUM RATINGS (Ta=25degree, Vss=0V) (BU9716BKV/BU9718KV)
Parameter
Maximum Supply Voltage
Input Voltage
Symbol
VDD
VIN
Pin
Ratings
Unit
V
VDD
-0.3～+7.0
OSC,CS,CK,DI,RES -0.3～VDD+0.3
V
Output Voltage
VOUT
ISO
OSC
-0.3～VDD+0.3
V
S1～S32
300
3
mA
mA
Output Current
ICO
COM1～COM3
Power Dissipation
Pd
－
－
400
mW
Storage Temperature Range
Tstg
-55～+125
degree
Note: Derating decreases at -4mW/degree for operation above Ta=25degree.
● RECOMMENDED OPERATING CONDITIONS
◎ BU9716BKV
Parameter
Symbol
VDD
Pin
VDD
VDD1
VDD2
－
MIN
+4.5
0
TYP
MAX
+5.5
VDD
VDD
+85
Unit
Supply Voltage
V
V
VDD1
VDD2
Topr
2/3VDD
1/3VDD
Input Voltage
0
V
Operating Temperature
-40
degree
◎ BU9718KV
Parameter
Symbol
VDD
VDD1
VDD2
fOSC
R
Pin
MIN
TYP
-
MAX
+3.5
Unit
V
Supply Voltage
VDD
VDD1
VDD2
OSC
OSC
OSC
－
+2.7
0
0
2/3VDD VDD
1/3VDD VDD
V
Input Voltage
V
External Input wave frequency
Recommended external resistor
Recommended external capacitor
Operating Temperature
-
38
47
100
kHz
kΩ
-
-
-
C
-
1000
-
pF
Topr
-40
+85
degree
* This product is not designed to be protected against radiation.
19/25
● ERECTRICAL CHARACTERISTICS
◎ BU9716BKV (VDD=4.5V-5.5V, Ta=25degree)
Parameter
Symbol
VIH
Pin
Condition
MIN
TYP
-
MAX
VDD
Unit
V
CS,CK,DI,RES
0.8VDD
“H” Level Input Voltage
CS,CK,DI,RES
CS,CK,DI,RES
CS,CK,DI,RES
VIL
IIH
IIL
0
0
0
-
-
-
0.2VDD
6.0
V
“L” Level Input Voltage
“H” Level Input Current
“L” Level Input Current
VI=VDD
VI=VSS
uA
uA
6.0
VSOH
VCOH
VSOL
VCOL
VCM1
VSM1
VCM2
VSM2
VCM3
IQ
S1～S32
COM1～COM3
S1～S32
IO=-20mA
IO=-100mA
IO=20mA
IO=100mA
1/2bias
-
-
-
-
-
-
-
-
-
-
-
VDD-1.0
VDD-1.0
1.0
-
V
V
“H” Level Output Voltage
“L” Level Output Voltage
-
-
V
COM1～COM3
COM1～COM3
S1～S32
1.0
-
V
1/2 VDD
2/3 VDD
2/3 VDD
1/3 VDD
1/3 VDD
30
-
V
1/3bias
-
-
V
Center-Level Output
Voltage
COM1～COM3
S1～S32
1/3bias
V
1/3bias
-
V
COM1～COM3
1/3bias
-
V
Low Power Mode
fOSC=38kHz
70
500
uA
uA
Supply Current
IDD
200
◎ BU9718KV (VDD=2.7-3.5V, Ta=25degree)
Parameter
Symbol
VIH
Pin
Condition
MIN
TYP
-
MAX
VDD
Unit
CS,CK,DI,RES
0.8VDD
V
V
“H” level Input Voltage
CS,CK,DI,RES
CS,CK,DI,RES
CS,CK,DI,RES
VIL
IIH
IIL
0
0
0
-
-
-
0.2VDD
6.0
“L” Level Input Voltage
“H” Level Input Current
“L” Level Input Current
VI=VDD
VI=VSS
uA
uA
6.0
VSOH
VCOH
VSOL
VCOL
VCM1
VSM1
VCM2
VSM2
VCM3
IQ
S1～S32
COM1～COM3
S1～S32
IO=-20mA
IO=-100mA
IO=20mA
IO=100mA
1/2bias
-
-
-
-
-
-
-
-
-
-
-
VDD-1.0
VDD-1.0
1.0
-
V
V
“H” Level Output Voltage
“L” Level Output Voltage
-
-
V
COM1～COM3
COM1～COM3
S1～S32
1.0
-
V
1/2 VDD
2/3 VDD
2/3 VDD
1/3 VDD
1/3 VDD
0.1
-
V
1/3bias
-
-
V
Center-Level Output
Voltage
COM1～COM3
S1～S32
1/3bias
V
1/3bias
-
V
COM1～COM3
1/3bias
-
V
Low Power Mode
fOSC=38kHz
30
300
uA
uA
Supply Current
IDD
100
20/25
●
AC ERECTRICAL CHARACTERISTICS
◎ BU9716BKV (VDD=4.5-5.5V, Ta=25degree)
MIN
-
TYP
MAX
Unit
kΩ
pF
kHz
ns
Parameter
Symbol
Pin
OSC
R
C
47
-
Recommended External Resistance
Recommended External Capacitance
Oscillator frequency guaranteed range
Data Setup Time
OSC
-
1000
-
fOSC
tDS
tDH
tCS
tCH
tCKH
tCKL
tr
OSC
19
100
100
100
100
100
100
-
38
-
76
CK,DI
CK,DI
CS,CK
CS,CK
CK
-
Data Hold Time
-
-
ns
CS Setup Time
-
-
ns
CS Hold Time
-
-
-
ns
CK High-Level Pulse width
CK Low-Level Pulse width
Rise Time
-
ns
CK
-
-
ns
CS,CK,DI
CS,CK,DI
-
300
300
ns
Fall Time
tf
-
-
ns
◎ BU9718KV (VDD=2.7V-3.5V, Ta=25degree)
MIN TYP
MAX
Unit
Condition
Parameter
Symbol
fOSC
Pin
OSC
10
38
80
kHz R=47kΩ,C=1000pF
Oscillator frequency guaranteed range
fOSC
tDS
tDH
tCS
tCH
tCKH
tCKL
tr
OSC
-
-
-
-
-
-
-
-
-
-
100
kHz External Input case
Operating frequency
Data Setup Time
Data Hold Time
CK,DI
CK,DI
CS,CK
CS,CK
CK
200
200
200
200
200
200
-
-
ns
ns
ns
ns
ns
ns
ns
ns
-
CS Setup Time
-
CS Hold Time
-
-
CK High-Level Pulse width
CK Low-Level Pulse width
Rise Time
CK
-
CS,CK,DI
CS,CK,DI
100
100
Fall Time
tf
-
Fig. BU9716BKV/BU9718KV-2 CK: Normal Low Level case
0.8VDD
CS
0.2VDD
tCKH
tCKL
tCH
tCS
0.8VDD
0.8VDD
0.2VDD
0.5VDD
0.5VDD
tDH
CK
DI
tr
tf
tDS
Fig. BU9716BKV/BU9718KV-3 CK: Normal High Level case
0.8VDD
CS
0.2VDD
tCKH
tCKL
tCH
tCS
0.8VDD
0.8VDD
0.2VDD
0.5VDD
0.5VDD
tDH
CK
DI
tr
tf
tDS
21/25
◎ BU9716BKV
● Block Diagram
● Terminal description
VDD1
LCD drive voltage
occurrence circuit
VDD2
Pin No, Terminal I/O
1-11
Description
Unused
OPEN
RES
CS
DI
Segment output pins. It output the
proper LCD voltage levels
corresponding to the input data
multiplexed with COM1 to CPM3.
Common driver output pins.
Frame frequency:
Control logic
Data latch
CK
13-23
26-35
S1-S32
O
OSC
Oscillation circuit
36
37
38
COM1
COM2
COM3
Common driver
Segment driver
O
OPEN
fO＝（fOSC／384）Hz
Active low reset input. Used for
resetting all latches.
_____________
39
44
RES
I
VDD
VSS
Fig. BU9716BKV /BU9718KV-3
BU9716BKV Block Diagram
(Include Control Code.)
Internal Oscillator connection for
an external resister and capacitor
which determines fOSC.
Chip select. Used for serial data
transfer. Active high.
Input data clock. Used for serial
data transfer.
Data input. Used for serial data
transfer.
Internal voltage reference
connection.
Connect to VDD2 at 1/2 bias
mode.
Internal voltage reference
connection.
Connect to VDD1 at 1/2 bias
mode.
OSC
-
● Pin assignment
45
46
47
CS
CK
DI
I
I
I
VSS
VSS
VSS
36
35
34
33
32
31
30
29
28
27
26
25
COM2
N.C.
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
COM3
RES
VDD
VDD1
VDD2
VSS
OSC
CS
VQFP-48C
41
42
VDD1
VDD2
-
-
OPEN
OPEN
CK
DI
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
Fig. BU9716BKV /BU9718KV-4
BU9716BKVPin assignment
◎ BU9718KV
● Block Diagram
● Terminal description
VDD1
LCD drive voltage
occurrence circuit
VDD2
Pin
No,
RES
CS
DI
Terminal
S1-S32
I/O
O
Description
Unused
OPEN
Control logic
Data latch
Segment output pins. It output the
proper LCD voltage levels
corresponding to the input data
multiplexed with COM1 to CPM3.
Common driver output pins.
1-11
13-23
26-35
CK
OSC
Oscillation circuit
Common driver
Segment driver
36
37
38
COM1
COM2
COM3
Frame frequency: fO＝（fOSC／
O
OPEN
384）Hz
Active low reset input. Used for
resetting all latches.
Fig. BU9716BKV /BU9718KV-5
BU9718KV Block Diagram
___________
39
44
RES
I
VDD
VSS
(Include Control Code.)
Internal Oscillator connection for
an external resister and capacitor
which determines fOSC.
Chip select. Used for serial data
transfer. Active high.
Input data clock. Used for serial
data transfer.
Data input. Used for serial data
transfer.
Internal voltage reference
connection.
Connect to VDD2 at 1/2 bias
mode.
Internal voltage reference
connection.
Connect to VDD1 at 1/2 bias
mode.
● Pin assignment
OSC
-
36
35
34
33
32
31
30
29
28
27
26
25
45
46
47
CS
CK
DI
I
I
I
VSS
VSS
VSS
COM2
COM3
RES
VDD
VDD1
VDD2
VSS
OSC
CS
N.C.
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VQFP-48C
41
42
VDD1
VDD2
-
-
OPEN
OPEN
CK
DI
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
Fig. BU9716BKV /BU9718KV-6
BU9718KV Pin assignment
22/25
● Timing chart
◎ Command / data Input
1. CK: Normal Low level case
CS
CK
DI
D1
D2
D3
D96
0
0
0
0
0
BM
LC
OE
Display Data
Control Code
2. CK: Normal High level case
CS
CK
DI
D1
D2
D3
D96
0
0
0
0
0
BM
LC
OE
Display Data
Control Code
Data transfer is enabled when CS is asserted high. The value of DI is shifted into the shift register on the
rising edge of CK. After all of the data in DI is sifted in, CS must be asserted low. The new display data
and control code takes effect after the falling edge of CS.
◎ Control Code
OE
0
Output-Enable Control
Normal Operation
1
Blank Display-as if all display data =0(Oscillator is active.)
LC
0
Low-power Mode Control
Normal Operation
1
Low-power Mode: Oscillator is stopped, segment /common outputs=”L”
BM
0
Bias Mode Control
1／3 Bias
1
1／2 Bias
◎ DISPLAY DATA
SEGMENT
COM3
COM2
COM1
SEGMENT
COM3
COM2
COM1
S1
S2
D1
D2
D3
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D86
D89
D92
D95
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
D4
D5
D6
S3
D7
D8
D9
S4
S5
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
23/25
● Cautions on use
(1)
Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices,
thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings
is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
(2)
Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed
under the conditions of each parameter.
(3)
Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection,
such as mounting an external diode between the power supply and the IC’s power supply terminal.
(4)
Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power
supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for
the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from
impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use
an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of
capacity dropout at a low temperature, thus determining the constant.
(5)
GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure
no terminals are at a potential lower than the GND voltage including an actual electric transient.
(6)
Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore,
if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal,
the ICs can break down.
(7)
Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8)
Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge
from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF
the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount
it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
(9)
Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention
not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will
operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power
supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
(10)
Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal
GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to
a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of
external parts as well.
(11)
External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance
due to DC bias and changes in the capacitance due to temperature, etc.
(12)
No Connecting input terminals
In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside
gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes
unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line.
(13) Rush current
When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow
instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.
24/25
● Order form name selection
B U
9
7 1 8
K V
ROHM form name
Package type
KV: VQFP
Part No.
BU9716B: 4.5V-5.5V
BU9718: 2.7V-3.5V
VQFP48C
<Packing information>
<Dimension>
Container
Tray
Quantity
9.0 0.2
7.0 0.1
1000pcs
Direction of product is fixed in a tray.
Direction
of feed
36
25
37
48
24
13
1
0.75
12
+0.05
−0.03
0.145
+6°
−4°
°
4
0.08
S
0.5 0.1
+0.05
0.22
−0.04
M
0.08
（Unit:mm)
When you order , please order in times the amount of package quantity.
Catalog No.08T197A '08.6 ROHM ©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no re-
sponsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no re-
sponsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, elec-
tronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intend-
ed to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
THE AMERICAS / EUROPE / ASIA / JAPAN
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Contact us : webmaster@ rohm.co.jp
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Copyright © 2009 ROHM CO.,LTD.
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Appendix-Rev4.0
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