ML22825 [ROHM]
P2ROM™内置型;
| 型号： | ML22825 |
| 厂家： | 
ROHM |
| 描述： | P2ROM™内置型 |
| 文件： | 总73页 (文件大小：2040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL228XX-06
Issue Date: Sep. 1, 2017
ML2282X-XXX/ML2286X-XXX
Speech Synthesis LSI with Built-in P2ROM Including 2-Channel Mixing Function
GENERAL DESCRIPTION
ML2282X(ML22825/ML22824/ML22823-XXX) and ML2286X (ML22865/ML22864/ML22863-XXX) are
voice synthesis LSIs with built-in P2ROM that stores speech data.
These LSIs include edit ROM, ADPCM2 decoder, 16-bit DA converter, low pass filter and monaural speaker
amplifier. Also, ML2282X supports the synchronous serial interface and ML22865/ML22864/ML22863
supports the I2C interface.
By integrating all the functions required for voice output into a single chip, these LSIs can be more easily
incorporated in compact portable devices.
•Built-in memory capacity and maximum vocal reproduction time:
(at the case of 4-bit ADPCM2 algorithm)
Maximum vocal reproduction time (sec)
Product name
ROM capacity
FS = 4.0 kHz
1,044
FS = 8.0 kHz
522
FS = 16 kHz
ML22825-XXX/ML22865
ML22824-XXX/ML22864
ML22823-XXX/ML22863
16 Mbits
8 Mbits
4 Mbits
261
130
64
520
260
258
129
•Voice synthesis method:
4-bit ADPCM2
8-bit Nonlinear PCM
8-bit PCM , 16-bit PCM
Can be specified for each phrase.
•Sampling frequency(Fs):
4.0 / 5.3 / 6.4 / 8.0 / 10.6 / 12.0 / 12.8 / 16.0 / 21.3 / 24.0 / 25.6 / 32.0 /
48.0 kHz
fs can be specified for each phrase.
•Built-in low-pass filter and 16-bit DA converter
•Speaker driving amplifier:
0.7 W (when 8Ω , DVDD=5 V, Ta=25°C)
2ch analog input (internal: 1ch; external: 1ch)
3-wired serial clock-synchronized (ML2282X)
I2C interface (ML2286X)
•CPU command interface:
•Maximum number of phrases:
•Memory bank switching:
•Volume control:
4,096 phrases from 000h to 3FFh (1024 phrases/bank)
Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins
32 levels (OFF is included) can be set by CVOL command.
50 levels (OFF is included) can be set by AVOL command
LOOP commands
•Repeat function:
•2-channel mixing function:
•Source oscillation frequency:
•Power supply voltage:
•Operating temperature range:
•Package:
Available except case using 32kHz as sampling frequencys
4.096 MHz
2.7 to 3.6V / 4.5 to 5.5 V
–40 to +85°C
30-pin plastic SSOP (P-SSOP30-56-0.65-ZK6-MC)
ML22825-xxxMB, ML22824-xxxMB, ML22823-xxxMB
ML22865-xxxMB, ML22864-xxxMB, ML22863-xxxMB
(xxx: ROM code No.)
•Product name:
1/72
FEDL2283X-07
ML2283X/ ML2287X
The following table shows the differences among the other speech synthesis LSIs.
ML22825/ML22824/
ML22823-XXX
←
ML22865/ML22864/
ML22863-XXX
I2C
Parameter
ML2216
ML22800 series
CPU interface
Serial
←
4-bit ADPCM2
8-bit nonlinear PCM
8-bit straight PCM
16-bit straight PCM
Playback method
←
1,024 (256/bank)
←
←
←
←
←
Maximum number
of phrases
256
4,096 (1,024/bank)
4.0/5.3/6.4/8.0/
10.6/12.0/12.8/
16.0/21.3/24.0/
25.6/32.0/48.0
4.0/5.3/6.4/
8.0/10.6/12.8
16.0
Sampling
frequency (kHz)
4.096MHz
(with a built-in crystal
oscillator circuit)
12 bits
Clock frequency
←
←
←
DA converter
Low-pass filter
Speaker driving
amplifier
12 bits
16 bits
←
←
3rd order comb filter 3rd order comb filter FIR interpolation filter
Built-in 0.3W
(8Ω, DVDD = 5 V)
Yes
Built-in 0.7W
(8Ω, DVDD = 5 V)
←
No
←
←
Edit ROM function
Simultaneous
sound production
function (mixing
function)
←
No
←
2-channel
←
Volume control
16 levels
Yes
20 ms to 1024 ms
(4 ms/step)
Yes
←
←
←
32 levels
←
←
←
Silence insertion
←
←
Repeat function
Interval at which a
seam is silent
during continuous
playback (Note)
Memory bank
switching
No
No
←
←
←
Yes
←
←
Power supply
voltage
2.7 to 3.6V
4.5 to 5.5 V
←
2.7 to 3.6V
4.5 to 5.5 V
←
2.7 V to 5.5 V
44-pin QFP
2.7 V to 3.6 V
30-pin SSOP
Package
*1: Continuous playback as shown below is possible.
(Playback method: 8-bit straight PCM, 8-bit non-linear PCM, 16-bit straight PCM)
1 phrase
1 phrase
No silence interval
2/72
FEDL2283X-07
ML2283X/ ML2287X
BLOCK DIAGRAMS
(ML22825/ML22824/ML22823-XXX : Synchronous serial interface)
DVDD
Multiplexer
16/8/4Mbit ROM
Address Controller
DGND
VDDL
VDDR
Phrase Address
Latch
ADPCM Synthesizer
PCM Synthesizer
LPF
Address Counter
CSB
SCK
SI
SO
CBUSYB
DIPH
I/O
Interface
Timing
Controller
SEL0
SEL1
16bit DAC
TESTI0,1
TESTO
RESETB
SP-AMP
XT
OSC
PLL
XTB
SPM SPP
AIN
SPVDD SPGND
(ML22865/ML22864/ML22863-XXX : I2C interface)
DVDD
Multiplexer
16/8/4Mbit ROM
Address Controller
DGND
VDDL
VDDR
Phrase Address
Latch
ADPCM Synthesizer
PCM Synthesizer
LPF
Address Counter
SDA2-0
SCL
SDA
CBUSYB
SEL0
I/O
Interface
Timing
Controller
SEL1
TESTI0,1
TESTO
16bit DAC
RESETB
SP-AMP
XT
OSC
PLL
XTB
SPM SPP
AIN
SPVDD SPGND
3/72
FEDL2283X-07
ML2283X/ ML2287X
PIN CONFIGURATIONS (TOP VIEW)
(ML22825/ML22824/ML22823-XXXMB : Synchronous serial interface)
AIN
TESTI0
RESETB
TESTO
DIPH
SEL0
SEL1
DGND
CSB
SCK 10
SI 11
1
2
3
4
5
6
7
8
9
30 SPM
29 SPP
28 SPGND
27 SPVDD
26 DGND
25 SG
24 TESTI1
23 VDDR
22 DVDD
21 VDDL
20 NC
SO 12
19 DGND
18 NC
17 DVDD
16 XTB
CBUSYB 13
DGND 14
XT 15
NC: No Connection
30-Pin Plastic SSOP
(ML22865/ML22864/ML22863-XXXMB : I2C interface)
AIN
TESTI0
RESETB
TESTO
SAD0
SEL0
30 SPM
29 SPP
28 SPGND
27 SPVDD
26 DGND
25 SG
1
2
3
4
5
6
SEL1
24 TESTI1
23 VDDR
22 DVDD
21 VDDL
20 NC
19 DGND
18 NC
17 DVDD
16 XTB
7
8
9
10
11
12
13
14
15
DGND
SAD1
SCL
SDA
SAD2
CBUSYB
DGND
XT
NC: No Connection
30-Pin Plastic SSOP
4/72
FEDL2283X-07
ML2283X/ ML2287X
PIN DESCRIPTION (COMMON TO ALL PRODUCTS)
Initial value
Pin
1
Symbol
AIN
I/O
I
Description
(*1)
0
Input pin for speaker amplifier.
Input pin for testing.
2
TESTI0
I
0
Fix this pin to “L” level (DGND level). This pin has a pull-down resistor
built in.
Input pin for reset.
At the “L” level, the LSI enters initial state. During reset, the entire
circuitry stops and enters power down state. Input “L” level when power is
supplied. After the power supply voltage is stable, drive this pin to “H”
level. Then the entire circuitry can be powered up.
This pin has a pull-up resistor built in.
0
(*2)
3
RESETB
TESTO
I
Output pins for testing.
Leave these pins open.
4
O
I
Hi-Z
0
SEL0
SEL1
Memory bank switching pins.
Fix these pins to “L” level when the memory bank function is not used.
6, 7
8, 14,
19, 26
DGND
—
—
Digital ground pin. Also serves as a ground pin for the internal memory.
Output pin for command processing status.
13
15
16
CBUSYB
O
I
1
0
1
This pin outputs “L” level during command processing. Any command
should be entered when this pin is “H” level.
Connect to the crystal or ceramic resonator.
A feedback resistor around 1 MΩ is built in between this pin and the XTB
pin. Use this pin if need to use an external clock.
If the resonator is used, connect it as close to this pin as possible.
Connect to the crystal or ceramic resonator.
When to use an external clock, leave this pin open.
If the resonator is used, connect it as close to this pin as possible.
Power supply pins for logic circuitry.
XT
XTB
O
17, 22
18, 20
21
DVDD
N.C
—
—
—
—
—
0
Connect a capacitor of 0.1µF or more between these pins and DGND pins.
Non connected pins. Leave these pins open.
Regulator output pin for internal logic circuitry.
Connect a capacitor recommended between this pin and DGND pin.
Regulator output pin for Built-in ROM.
Connect a capacitor recommended between this pin and DGND pin.
Test pin. Fix this pin to a DGND level.
VDDL
23
24
25
VDDR
TESTI1
SG
—
—
—
0
0
0
Reference voltage output pin for the speaker amplifier built-in.
Connect a capacitor recommended between this pin and DGND pin.
Power supply pin for the speaker amplifier.
27
SPVDD
—
—
Connect a bypass capacitor of 0.1µF or more between this pin and SPGND
pin.
28
29
30
SPGND
SPP
—
O
O
—
0
Ground pin for the speaker amplifier.
Positive(+) output pin of the speaker amplifier built-in.
Serves as the LINE output (*3), if built-in speaker amplifier is not used.
Negative(-) output pin of the speaker amplifier built-in.
SPM
Hi-Z
*1: Indicates the initial value during reset input or power down.
*2: “H” during power down.
*3: Outputs a voice signal before amplified by the speaker amplifier built-in.
5/72
FEDL2283X-07
ML2283X/ ML2287X
PIN DESCRIPTION (FOR ML2282X SYNCHRONOUS SERIAL INTERFACE)
Initial value
(*1)
Pin
Symbol
I/O
Description
Set pin of the SCK clock edge.
When this pin is “L” level, rising edge is available for input(SI) and falling
edge is available for output(SO).
5
DIPH
I
0
When this pin is “H” level, falling edge is available for input(SI) and rising
edge is available for output(SO).
Chip select pin.
9
CSB
SCK
I
I
1
0
At the “L” level, data input/output is available.
Synchronous clock input pin for serial interface.
Input pin of synchronous serial data.
10
When the DIPH pin is “L” level, data is shifted in at the rising edges of
the SCK clock pulses.
When the DIPH pin is “H” level, data is shifted in at the falling edges of
the SCK clock pulses.
11
12
SI
I
0
Output pin of synchronous serial data.
When the DIPH pin is “L” level, data is output at the falling edges of the
SCK clock pulses.
When the DIPH pin is “H” level, data is output at the rising edges of the
SCK clock pulses.
SO
O
Hi-Z
When the CSB pin is “H” level, this pin is Hi-Z state.
*1: Indicate the initial value during reset or power down.
PIN DESCRIPTION (FOR ML2286X I2C INTERFACE)
Initial value
Pin
Symbol
SAD0
I/O
Description
(*1)
5, 9, 12 SAD1
SAD2
I
I
0
Set pin of the slave address.
Clock input pin for I2C serial interface.
This pin should be connected to pull-up resistor.
Input/output pin for I2C serial data.
Use for setting the mode of write/read and writing address, writing data
or reading data.
This pin should be connected to pull-up resistor.
(N-ch MOS) open drain, when output mode.
High impedance(Hi-Z), when input mode.
10
SCL
SDA
1
11
IO
1
*1: Indicate the initial value during reset or power down.
6/72
FEDL2283X-07
ML2283X/ ML2287X
ABSOLUTE MAXIMUM RATINGS
(DGND = SPGND = 0 V, Ta = 25°C)
Parameter
Symbol
DVDD
SPVDD
VIN
Condition
—
Rating
Unit
,
Power supply voltage
−0.3 to +7.0
V
Input voltage
−0.3 to DVDD+0.3
V
—
Power dissipation
PD
938
mW
Applies to all pins except
SPM, SPP, VDDL, and VDDR
10
mA
mA
.
Output short-circuit
current
Applies to SPM and SPP
pins.
IOS
300
Applies to VDDL and VDDR
50
mA
°C
pins.
—
Storage temperature
TSTG
−55 to +150
RECOMMENDED OPERATING CONDITIONS
(DGND = SPGND = 0 V)
Range Unit
Parameter
Symbol
DVDD
SPVDD
TOP
Condition
,
2.7 to 3.6
4.5 to 5.5
Power supply voltage
Operating temperature
—
—
V
−40 to +85
Typ.
°C
Min.
3.5
Max.
4.5
Master clock frequency
fOSC
—
—
MHz
pF
4.096
External capacitors for
crystal oscillator
Cd, Cg
15
30
45
7/72
FEDL2283X-07
ML2283X/ ML2287X
ELECTRICAL CHARACTERISTICS
DC Characteristics (for the 3V applications)
DVDD = SPVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = −40 to +85°C
Parameter
“H” input voltage
“L” input voltage
Symbol
VIH
Condition
—
Min.
Typ.
—
Max.
DVDD
0.14×DVDD
—
Unit
V
0.86×DVDD
VIL
—
0
DVDD−0.4
DVDD−0.4
—
—
V
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
“L” output voltage 2 (*1)
“L” output voltage 3 (*2)
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
“L” input current 2 (*3)
“L” input current 3 (*5)
“H” output leak current 3
(*6)
VOH1
VOH2
VOL1
VOL2
VOL3
IIH1
IOH = −1 mA
IOH = −50 µA
IOL = 2 mA
IOL = 50 µA
IOL = 3 mA
VIH = DVDD
VIH = DVDD
VIH = DVDD
VIL = GND
VIL = GND
VIL = GND
—
V
—
—
V
—
0.4
V
—
—
0.4
V
—
—
0.4
V
—
—
10
µA
µA
µA
µA
µA
µA
IIH2
0.3
2.0
30
—
15
IIH3
2
200
—
IIL1
−10
−15
−200
IIL2
−2.0
−30
−0.3
−2
IIL3
IILOH
IILOL
IDD
VOH = DVDD
VOL = GND
—
−10
—
—
—
—
10
—
20
µA
µA
“L” output leak current 3
(*6)
Supply current during
playback
f
OSC = 4.096 MHz
No output load
mA
Ta = −40 to +40°C
Ta = −40 to +85°C
—
—
1
1
10
20
µA
µA
Power-down supply
current
IDDS
*1: Applies to the XTB pin.
*2: Applies to the SCL, SDA pin.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 pin.
*5: Applies to the RESETB pin.
*6: Applies to the TESTO pin.
8/72
FEDL2283X-07
ML2283X/ ML2287X
DC Characteristics (for the 5V applications)
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
“H” input voltage
“L” input voltage
Symbol
VIH
Condition
—
Min.
0.8×DVDD
0
Typ.
—
Max.
DVDD
0.2×DVDD
—
Unit
V
VIL
—
—
V
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
“L” output voltage 2 (*1)
“L” output voltage 3 (*2)
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
“L” input current 2 (*3)
“L” input current 3 (*5)
“L” output leak current 2
(*6)
VOH1
VOH2
VOL1
VOL2
VOL3
IIH1
IOH = −1 mA
IOH = −50µA
IOL = 2 mA
IOL = 50 µA
IOL = 3 mA
VIH = DVDD
VIH = DVDD
VIH = DVDD
VIL = GND
VIL = GND
VIL = GND
DVDD−0.4
DVDD−0.4
—
—
V
—
—
V
—
0.4
V
—
—
0.4
V
—
—
0.4
V
—
—
10
µA
µA
µA
µA
µA
µA
IIH2
0.8
5.0
100
—
20
IIH3
20
400
—
IIL1
−10
−20
−400
IIL2
−5.0
−100
−0.8
−20
IIL3
IILOH
IILOL
IDD
VOH = DVDD
VOL = GND
—
−10
—
—
—
—
10
—
25
µA
µA
“L” output leak current 3
(*6)
Supply current during
playback
f
OSC = 4.096 MHz
No output load
mA
Power-down supply
current
Ta = −20 to +40°C
Ta = −20 to +85°C
—
—
1
1
15
30
µA
µA
IDDS
*1: Applies to the XTB pin.
*2: Applies to the SCL and SDA pins.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 pin.
*5: Applies to the RESETB pin.
*6: Applies to the TESTO pin.
9/72
FEDL2283X-07
ML2283X/ ML2287X
Characteristics of Analog Circuitry (for the 3V applications)
DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
AIN input resistance
AIN input voltage range
LINE output load
resistance
Symbol
RAIN
Condition
Min.
15
Typ.
20
Max.
25
Unit
kΩ
Vp-p
VAIN
DVDD×2/3
RLA
VAO
During 1/2 DVDD output
No output load
10
kΩ
LINE output voltage
range
DVDD/6
DVDD×5/6
V
SG output voltage
SG output resistance
SPM, SPP output load
resistance
VSG
RSG
0.95×VDDL/2
VDDL/2
96
1.05×VDDL/2
V
During power down
57
135
kΩ
RLSP
PSPO
8
Ω
Speaker amplifier output
power
SPVDD = 3.3V, f = 1kHz
RSPO = 8Ω, THD≥10%
100
300
mW
Output offset voltage
between SPM and SPP
with no signal present
SPIN–SPM gain = 0dB
VOF
−50
+50
mV
With a load of 8Ω
Characteristics of Analog Circuitry (for the 5V applications)
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −20 to +85°C
Parameter
AIN input resistance
AIN input voltage range
LINE output load
resistance
Symbol
RAIN
Condition
Min.
15
Typ.
20
Max.
25
Unit
kΩ
Vp-p
VAIN
DVDD×2/3
RLA
VAO
During 1/2 DVDD output
No output load
10
kΩ
LINE output voltage
range
DVDD/6
DVDD×5/6
V
SG output voltage
SG output resistance
SPM, SPP output load
resistance
VSG
RSG
0.95×VDDL/2
VDDL/2
96
1.05×VDDL/2
V
During power down
57
135
kΩ
RLSP
8
Ω
SPVDD = 5.0V, f = 1kHz
Speaker amplifier output
power
PSPO
RSPO = 8Ω, THD≥10%
500
700
mW
Ta=25°C
Output offset voltage
between SPM and SPP
with no signal present
SPIN–SPM gain = 0dB
VOF
−50
+50
mV
With a load of 8Ω
10/72
FEDL2283X-07
ML2283X/ ML2287X
AC Characteristics (Common to All Products)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C,
Applicable
command
Parameter
Symbol
Condition
Min. Typ. Max. Unit
Master clock duty cycle
fduty
tRST
—
—
—
40
100
—
50
—
—
60
—
%
µs
µs
RESETB input pulse width
Reset noise rejection pulse width
tNRST
0.1
STOP, SLOOP,
CLOOP, CVOL,
AVOL
tINT
2
—
—
ms
Command input interval time
Command input enable time
fOSC = 4.096 MHz
PUP
tINTP
10
—
—
—
—
ms
RDSTAT
(After status read)
SLOOP
Continuous play
by PLAY/MUON
tINTRD
500
µs
tcm
fOSC = 4.096 MHz
—
—
10
ms
PUP
tPUP1
tPD1
fOSC = 4.096 MHz
fOSC = 4.096 MHz
2.0
—
2.5
—
3.0
20
ms
PDWN
µs
2nd byte of AMODE
(POP = “0”
tPOPA1
fOSC = 4.096 MHz
fOSC = 4.096 MHz
58
60
62
ms
SPEN = “0”,
DAEN = “0” →”1”)
2nd byte of AMODE
(POP = “1”
tPOPA2
tPOPA3
tPDA1
90
93
95
ms
ms
ms
SPEN = “0”,
DAEN = “0” →”1”)
2nd byte of AMODE
(SPEN = “0” →”1”)
2nd byte of AMODE
(POP = “0”
f
OSC = 4.096 MHz
46*2
108
60*3
110
70*4
112
CBUSYB “L” level output time
AVOL=“0Eh~3Fh”
fOSC = 4.096 MHz
SPEN = “0”,
DAEN = “1” →”0”)
2nd byte of AMODE
(POP = “1”
tPDA2
fOSC = 4.096 MHz
140
142
144
ms
SPEN = “0”,
DAEN = “1” →”0”)
2nd byte of AMODE
(SPEN = “1” →”0”)
(*1)
f
OSC = 4.096 MHz
tPDA3
tCB1
0.2*2 6.5*3 17*4
ms
ms
AVOL=“0Eh~3Fh”
fOSC = 4.096 MHz
—
—
2
Note: Output pin load capacitance = 45 pF
*1: Applies to cases where a command is input except after a PUP, PDWN, or 2nd byte of AMODE command
input.
*2: The value when AVOL=”0Eh” is set.
*3: The value when AVOL=”23h” is set.
*4: The value when AVOL=”3Fh” is set.
11/72
FEDL2283X-07
ML2283X/ ML2287X
AC Characteristics of Synchronous Serial Command Interface (Applied to ML2282X)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Applicable
command
Parameter
Symbol
Condition
Min. Typ. Max. Unit
SCK input enable time from CSB fall edge
SCK hold time from CSB rise edge
Data floating time from CSB rise edge
Data setup time from SCK rise edge
Data hold time from SCK rise edge
Data output delay time from SCK fall edge
Data setup time from SCK fall edge
Data hold time from SCK fall edge
Data output delay time from SCK rise edge
SCK “H” level pulse width
tESCK
tCSH
—
100
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
tDOZ
RL = 3 kΩ
DIPH = “0”
DIPH = “0”
RL = 3 kΩ
DIPH = “1”
DIPH = “1”
RL = 3 kΩ
—
100
—
tDIS1
50
tDIH1
50
—
tDOD1
tDIS2
—
80
—
50
tDIH2
50
—
tDOD2
tSCKH
tSCKL
tDBSY1
tDBSY2
—
80
—
100
100
—
SCK “L” level pulse width
—
—
CBUSYB output delay time from SCK rise edge
CBUSYB output delay time from SCK fall edge
DIPH = “0”
DIPH = “1”
150
150
—
Note: Output pin load capacitance = 45 pF
12/72
FEDL2283X-07
ML2283X/ ML2287X
AC Characteristics of I2C Command Interface (Applied to ML2286X)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
(High-speed mode)
Parameter
Symbol
tSCL
Unit
kHz
µs
Min.
0
Max.
400
SCL clock frequence
Hold time (repeated) START condition
After this period, the first clock pulse is generated.
SCL “L” level pulse width
tHD;STA
0.6
—
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
1.3
0.6
—
—
µs
µs
µs
µs
ns
ns
ns
µs
µs
PF
SCL “H” level pulse width
Setup time for repeated START condition
Data hold time: For I2C bus devices
Data setup time
0.6
—
0
0.9
—
100
20
SDA and SCL signal rise time
300
300
—
SDA and SCL signal fall time
tf
20
STOP condition setup time
tSU;STO
tBUF
0.6
Bus free time between STOP condition and START condition
Capacitive load for each bus line
Noise margin at a “L” level in each device connected (including
hysteresis)
1.3
—
Cb
—
400
0.1×
DVDD
0.1×
DVDD
VnL
VnH
tsp
—
—
50
V
V
Noise margin at a “H” level in each device connected (including
hysteresis)
Pulse width of spikes which must be suppressed by the input
filter
0
ns
Note: Output pin load capacitance = 45 pF
13/72
FEDL2283X-07
ML2283X/ ML2287X
TIMING DIAGRAMS ( 3-WIRED SERIAL CLOCK-SYNCHRONIZED (ML2282X) )
Power-On Timing
5V
5V
SPVDD
DVDD
RESETB
Status
tRST
VIH
VIL
Performing a
reset
Power-down
Oscillation is stopped after power-on.
Power-Up Timing
CSB
SCK
SI
tPUP1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
Oscillation stopped
Power-down
Oscillating
XTXTB
Command is being
processed
Oscillation stabilized
Awaiting command
Status
14/72
FEDL2283X-07
ML2283X/ ML2287X
Power-Down Timing (At the PDWN command Input)
CSB
SCK
SI
tPD1
CBUSYB VOH
VOL
VOH
NCR
(internal)
VOL
VOH
BUSYB
(internal)
VOL
Oscillation
stopped
Oscillating
XT•XTB
Command is
Awaiting command
Power-down
Status
being processed
Power-Down Timing (At the RESETB Input)
RESETB
tRST
Oscillating
Oscillation stopped
XTXTB
V
DDLSG
GND
Hi-Z
SPM
GND
SPP
Playing
Power-down
Status
Note: The same timing is applied in the case that the RESETB signal is input during command waiting.
15/72
FEDL2283X-07
ML2283X/ ML2287X
Playback Start Timing by the PLAY Command
PLAY command
st byte
PLAY command
2nd byte
1
CSB
SCK
SI
tCB1
tCB1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
(*1)
VOH
VOL
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Address is being
controlled
Command standby
Awaiting command
Playing
Awaiting command
Status
Command is being
processed
Note: The length of the “L” interval of BUSYB is tCB1 + voice reproduction time.
Playback Stop Timing
STOP command
CSB
SCK
SI
tCB1
VOH
CBUSYB
VOL
VOH
NCR
(internal)
VOL
VOH
BUSYB
(internal)
VOL
1/2SPVDD
SPM
1/2SPVDD
SPP
Status
Playing
Awaiting command
Command is being processed
16/72
FEDL2283X-07
ML2283X/ ML2287X
Continuous Playback Timing by the PLAY Command
PLAY command
2nd byte
PLAY command PLAY command
1st byte 2nd byte
CSB
SCK
SI
tcm
tCB1
tCB1
tCB1
CBUSYB VOH
VOL
VOH
NCR
(*1)
(internal)VOL
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Awaiting command
Playing phrase 1
Playing phrase 2
Status
Address is being controlled
Address is being controlled
*1: The time length of “L” level of the NCR signal during playback varies depending on the input timing of
command.
*2: The following PLAY command must be inputted within tcm. When it cannot, please input the
phrase 2 PLAY command after checking that BUSYB became “H”(phrase 1 playback has been finished).
Continuous Playback Timing by the START Command
START command
START command
CSB
SCK
SI
tcm
(*2)
tCB1
tCB1
CBUSYB
NCR
(*1)
(internal)
BUSYB
(internal)
1/2SPVDD
1/2SPVDD
SPM
SPP
Awaiting command
Playing phrase 1
Playing phrase 2
Status
Address is being controlled
Address is being controlled
*1: The time length of “L” level of the NCR signal during playback varies depending on the input timing of
command.
*2: The following START command must be inputted within tcm. When it cannot, please input the
phrase 2 START command after checking that BUSYB became “H”(phrase 1 playback has been finished).
17/72
FEDL2283X-07
ML2283X/ ML2287X
Silence Insertion Timing by the MUON Command
PLAY command
2nd byte
MUON command MUON command
PLAY command PLAY command
1st byte 2nd byte
1st byte
2nd byte
CSB
SCK
SI
tcm
tcm
(*2)
(*2)
tCB1
tCB1
tCB1
tCB1
tCB1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
(*1)
(*1)
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Awaiting command
Playing
Silence is being inserted
Playing
Status
Address is being controlled
*1: The time length of “L” level of the NCR signal during playback or silence insertion varies depending on the
input timing of command.
*2: The following MUON commnad or PLAY command must be inputted within tcm. When it
cannot, please input the MUON commnad or PLAY command after checking that BUSYB
became “H”(playback has been finished).
Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands
SLOOP command
CLOOP command
PLAY command
2nd byte
VIH
VIL
CSB
SCK
SI
tINT
tcm
tCB1
tCB1
tCB1
VOH
VOL
CBUSYB
NCR
(*1)
VOH
VOL
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Awaiting command
Playing
Playing
Awaiting command
Status
Address is being
controlled
Address is being
controlled
Command is being processed
*1: The SLOOP commnad must be inputted within tcm.
18/72
FEDL2283X-07
ML2283X/ ML2287X
Timing of Volume Change by the CVOL Command
CVOL command
1st byte
CVOL command
2nd byte
CSB
SCK
SI
tCB1
tCB1
CBUSYB VOH
VOL
VOH
NCR
(internal)
VOL
VOH
BUSYB
(internal)
VOL
Awaiting command
Awaiting command
Awaiting command
Status
Command is being
processed
Command is being
processed
Timing of Volume Change by the AVOL Command
AVOL command
1st byte
AVOL command
2nd byte
CSB
SCK
SI
tCB1
tCB1
CBUSYBVOH
VOL
VOH
NCR
(internal)
VOL
VOH
BUSYB
(internal)
VOL
Awaiting command
Awaiting command
Awaiting command
Status
Command is being
processed
Command is being
processed
19/72
FEDL2283X-07
ML2283X/ ML2287X
TIMING DIAGRAMS ( I2C INTERFACE (ML2286X) )
Power-On Timing
5V
SPVDD
5V
DVDD
tRST
VIH
RESETB
VIL
Performing a
Power-down
Status
reset
Oscillation is stopped after power-on.
Power-Up Timing
SCL
A
6
A
5
A
4
SDA
W A
A
tPUP1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
Oscillation stopped
Power-down
Oscillationg
XT・XTB
Command is being
processed
Oscillation stabilized
Awaiting command
Status
20/72
FEDL2283X-07
ML2283X/ ML2287X
Power-Down Timing (At the PDWN command Input)
SCL
A
6
A
5
A
4
SDA
W A
A
tPD1
CBUSYBVOH
VOL
VOH
NCR
(internal)VOL
VOH
BUSYB
(internal) VOL
Oscillating
Oscillation stopped
Power-down
XT・XTB
Command is being
processed
Awaiting command
Status
Power-Down Timing (At the RESETB Input)
RESETB
tRST
Oscillating
Oscillation stopped
XT・XTB
V
DDL・SG
GND
Hi-Z
SPM
GND
SPP
Playing
Power-down
Status
Note: The same timing is applied in the case that the RESETB signal is input during command waiting.
21/72
FEDL2283X-07
ML2283X/ ML2287X
Playback Start Timing by the PLAY Command
PLAYcommand
PLAY command
2ndbyte
1stbyte
SCL
A
6
A
5
A
4
SDA
W A
A
A
tCB1
tCB1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
(*1)
VOH
VOL
BUSYB
(internal)
1/2SPVDD
1/2SPVDD
SPM
SPP
Command standby
Command is being processed
Awaiting command
Playing
Awaiting command
Status
Address is being
contorolled
Note: The length of the “L” interval of BUSYB is tCB1 + voice reproduction time.
Playback Stop Timing
STOP command
SCL
A
6
A
5
A
4
SDA
W A
A
tCB1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSY
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Playing
Awaiting command
Status
Command is being processed
22/72
FEDL2283X-07
ML2283X/ ML2287X
Continuous Playback Timing by the PLAY Command
PLAYcommand
2nd byte
PLAYcommand
1st byte
PLAYcommand
2nd byte
SCL
SDA
A
6
A
5
A
4
W A
A
A
A
tCM
（*2）
tCB1
tCB1
tCB1
CBUSYB VOH
VOL
VOH
NCR
（*1）
(internal)VOL
BUSYB
(internal)
1/2SPVDD
1/2SPVDD
SPM
SPP
Awaiting command
Playing phrase1
Playing phrase2
Status
Address is being
controlled
Address is being
controlled
*1:The time length of “L” level of the NCR signal during playback varies depending on the input timing of
command.
*2: The following PLAY command must be inputted within tcm. When it cannot, please input the
phrase 2 PLAY command after checking that BUSYB became “H”(phrase 1 playback has been finished).
Continuous Playback Timing by the START Command
START command
START command
SCL
SDA
A
6
A
5
A
4
W A
A
A
tcm
(*2)
tCB1
tCB1
CBUSYB VOH
VOL
VOH
NCR
(*1)
(internal)VOL
BUSYB
(internal)
1/2SPVDD
1/2SPVDD
SPM
SPP
Awaiting command
Playing phrase 1
Playing phrase 2
Status
Address is being controlled
Address is being controlled
*1: The time length of “L” level of the NCR signal during playback varies depending on the input timing of
command.
*2: Please input the following START command within tcm. When it cannot, please input the
phrase 2 START command after checking that BUSYB became “H”(phrase 1 playback has been finished).
23/72
FEDL2283X-07
ML2283X/ ML2287X
Silence Insertion Timing by the MUON Command
PLAYcommand
2nd byte
MUONcommand
1st byte
MUONcommand
2nd byte
SCL
SDA
A
6
A
5
A
4
W A
A
A
A
tCM
tCM
（*2）
（*2）
tCB1
tCB1
tCB1
CBUSYB VOH
VOL
VOH
（*1）
NCR
(internal)VOL
BUSYB
(internal)
1/2SPVDD
1/2SPVDD
SPM
SPP
Awaiting command
Playing
Silence is being inserted
Status
Address is being
controlled
PLAYcommand
1st byte
PLAYcommand
2nd byte
SCL
SDA
A
6
A
5
A
4
W A
A
A
tCB1
tCB1
VOH
CBUSYB
VOL
VOH
NCR
(internal)
（*1）
VOL
VOH
BUSYB
(internal)
VOL
1/2SPVDD
1/2SPVDD
SPM
SPP
Silence is being insserted
Playing
Status
Address is being controlled
*1: The time length of “L” level of the NCR signal during playback or silence insertion varies depending on the
input timing of command.
*2: Please input the following MUON commnad or PLAY command within tcm. When it cannot, please input
the MUON commnad or PLAY command after checking that BUSYB became “H”(playback has been
finished).
24/72
FEDL2283X-07
ML2283X/ ML2287X
Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands
PLAYcommand
2nd byte
SLOOPcommand
SCL
SDA
A
6
A
5
A
4
W A
A
A
tCM
tCB1
tCB1
VOH
CBUSYB
VOL
VOH
VOL
NCR
(internal)
BUSYB
(internal)
1/2SPVDD
1/2SPVDD
SPM
SPP
Awaiting command
Playing
Playing
Status
Address is being
controlled
Command is being processed
CLOOP command
SCL
SDA
A
6
A
5
A
4
W A
A
tCB1
CBUSYB VOH
VOL
VOH
NCR
(internal) VOL
BUSYB
(internal)
1/2SPVDD
SPM
SPP
1/2SPVDD
Playing
Playing
Awaiting command
Status
Command is being processed
*1: The SLOOP commnad must be inputted within tcm.
25/72
FEDL2283X-07
ML2283X/ ML2287X
Timing of Volume Change by the CVOL Command
CVOLcommand
1st byte
CVOLcommand
2nd byte
SCL
SDA
A
6
A
5
A
4
W A
A
A
tCB1
tCB1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
Awaiting command
Awaiting command
Awaiting command
Status
Command is being processed
Command is being processed
Timing of Volume Change by the AVOL Command
AVOL command
1st byte
AVOL command
2nd byte
SCL
SDA
A
6
A
5
A
4
W A
A
A
tCB1
tCB1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
Awaiting command
Awaiting command
Awaiting command
Status
Command is being processed
Command is being processed
26/72
FEDL2283X-07
ML2283X/ ML2287X
Serial Command Interface Timing (Applied to ML2282X)
when DIPH pin is “L” level (Rise edge for input, fall edge for output)
VIH
CSB
VIL
tCSH
tESCK
tSCKH
VIH
VIL
SCK
tDIS1
tDIH1
tSCKL
VIH
VIL
SI
tDOD1
tDOZ
VIH
VIL
SO
tDBSY1
CBUSYB VOH
VOL
Serial Command Interface Timing (Applied to ML2282X)
when DIPH pin is “H” level (Fall edge for input, rise edge for output)
VIH
CSB
VIL
tCSH
tESCK
tSCKL
VIH
VIL
SCK
tDIS2
tDIH2
tSCKH
VIH
VIL
SI
tDOD2
tDOZ
VIH
VIL
SO
tDBSY2
CBUSYB VOH
VOL
I2C Command Interface Timing (Applied to ML2286X)
27/72
FEDL2283X-07
ML2283X/ ML2287X
FUNCTIONAL DESCRIPTION
Synchronous Serial Command Interface
The CSB, SCK, SI, and SO pins are used to input the command data or to read the status. Driving the CSB pin
to “L” level enables the serial CPU interface.
After the CSB pin is driven to “L” level, the command data are input through the SI pin from the MSB
synchronized with the SCK clock. The command data shifts in through the SI pin at the rising or falling edge
of the SCK clock pulse. Then, a command is executed at the rising or falling edge of the eighth pulse of the
SCK clock.
As for status reading, status is output from the SO pin, synchronized with the SCK clock after the CSB pin is
driven to “L” level.
The SCK clock edge is specified by the input level of the DIPH pin.
- When the DIPH pin is “L” level, rising edge is available for input from SI pin and falling edge is available
for output from SO pin.
- When the DIPH pin is “H” level, falling edge is available for input from SI pin and rising edge is available
for output from SO pin.
It is possible to input command data, even if the CSB pin is fixed by “L” level. However, if unexpected pulses
caused by noise are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a failure in
normal recognition of command. Then it is recommended that the CSB pin is “L” level only for command
input.
The count of the SCK clock pulse is initialized when the CSB pin goes to “H” level.
Command Data Input or Status Read Timing
• When DIPH pin is “L” level
CSB
SCK
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
SI
(
)
(
)
SO
• When DIPH pin is “H” level
CSB
SCK
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
SI
(
)
(
)
SO
28/72
FEDL2283X-07
ML2283X/ ML2287X
The following table shows the contents of each data output at a status read.
Output status signal
MSB
7SB
6SB
5SB
4SB
3SB
2SB
LSB
Channel 2 BUSYB output (BUSYB1)
Channel 1 BUSYB output (BUSYB0)
Channel 2 NCR output (NCR1)
Channel 1 NCR output (NCR0)
The BUSYB output is “L” level when a command is being processed or the playback of a particular channel is
going on. In other states, the BUSYB output is “H” level. The NCR output is “L” level when a command is
being processed or particular channel is in standby for playback. In other states, the NCR output is “H” level.
29/72
FEDL2283X-07
ML2283X/ ML2287X
I2C Command Interface (Applies to ML2286X)
The I2C Interface built-in is an serial interface (: slave side) that is compliant with I2C bus specification. It
supports Fast mode and enables data transmission/reception at 400 kbps. The SCL and SDA pins are used to
input the command data or to read the status. Pins (:SAD0, 1 and 2) are used to set the slave address.
Pull-up resister should be connected to SCL pin and SDA pin.
For the master on the I2C bus to communicate with this device (: slave), input the slave address with the first
seven bits after setting the start condition. The upper three bits of the slave address can be set using the SAD0
to 2 pins. The eighth bit of slave address is used to set the direction (: write or read) of communication. If the
eighth bit is “0” level, it is write mode from master to slave. And, if the eighth bit is “1” level, it is read mode
from master.
The communication is made in the unit of byte. And acknowledge is needed for each byte.
The protocol of I2C communication is shown below.
− Command flow at data write( 1byte command )
START condition
Slave address +W (0)
Write address (ex. 1st byte of a command)
STOP condition
Data write timing( 1byte command )
SCL
A6 A5 A4 A3 A2A1 A0 W A D7 D6D5 D4 D3D2 D1 D0 A
SDA
P
Slave Address
A
1st Command Data
A
S
CBUSYB
− Command flow at data write( 2byte command )
START condition
Slave address +W (0)
Write address (ex. 1st byte of a command)
Write data (ex. 2nd byte of a command)
STOP condition
Data write timing( 2byte command )
SCL
A6 A5 A4 A3 A2A1 A0 W A D7 D6D5 D4 D3D2 D1 D0 A D7 D6D5 D4 D3D2 D1 D0 A
SDA
P
A
Slave Address
A
1st Command Data
A
2nd Command Data
S
30/72
FEDL2283X-07
ML2283X/ ML2287X
− Command flow at data read
Start condition
Slave address +W(0)
Write address (RDSTAT command)
STOP condition
Start condition
Slave address +R(1)
Read data (ex. Status read)
STOP condition
Data read timing
SCL
A6 A5 A4 A3 A2A1 A0 W A D7 D6D5 D4 D3D2 D1 D0 A
SDA
P
Slave Address
A
RDSTAT Command
A
S
CBUSYB
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R
Slave Address
A
D7D6D5 D4 D3D2 D1 D0 A
Read Data
A
A
P
S
CBUSYB
31/72
FEDL2283X-07
ML2283X/ ML2287X
Setting of the slave address using the SAD0 to 2 pins
SAD2 SAD1 SAD0
Lower 4 bits
0101
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0101
0101
0101
0101
0101
0101
0101
The following table shows the contents of each data output at a status read. Status is updated by the
RDSTAT command; therefore, be sure to input the RDSTAT command in order to read status.
Output status signal
MSB
7SB
6SB
5SB
4SB
3SB
2SB
LSB
Channel 2 BUSYB output (BUSYB1)
Channel 1 BUSYB output (BUSYB0)
Channel 2 NCR output (NCR1)
Channel 1 NCR output (NCR0)
The BUSYB signal is “L” level when either a command is being processed or the playback of a particular
channel is going on. In other states, the BUSYB signal is “H” level.
The NCR signal is “L” level when either a command is being processed or a particular channel is in standby for
playback. In other states, the NCR signal is “H” level.
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Command List
Each command is configured by the unit of byte (8-bit). The following commands, AMODE, AVOL FADR,
PLAY, MUON, and CVOL, use two bytes.
Command
PUP
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
S1
D0
S0
Description
Power-up command.
Shifts from the power down state to
the command waiting state. Also,
sets the number of memory banks.
Power-down command.
PDWN
RDSTAT
AMODE
0
0
1
0
0
0
0
0
Shifts form the command waiting
state to the power down state.
Status read command.
Reads the command status on each
channel.
1
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
Control command of analog circuitry.
Setoperation of
and input/output.
power-up/dpwn
FAD DAG1 DAG0 AIG1 AIG0 DAEN SPEN POP
Playback start command.
0
F7
0
1
F6
1
0
F5
1
0
F4
0
F9
F3
0
F8
F2
0
0
CH
F0
Use the data of the 2nd byte to
specify a phrase number. Can be
specified for each channel.
PLAY
F1
Playback stop command.
Can be set for each channel.
STOP
FADR
CH1 CH0
Set command of playback phrase.
Can be set for each channel.
Use START command to start.
Playback start command without
phrase spec. Use FADR command
to set phrase.Can start playback on
0
0
1
1
F9
F3
F8
F2
0
CH
F0
F7
F6
F5
F4
F1
START
0
1
0
1
0
0
CH1 CH0 multiple channels simultaneously.
After played back by PLAY
command, the same phrase can be
played back with this command.
Silence insertion command.
CH1 CH0
0
1
1
1
0
0
Set the silent time length for each
MUON
SLOOP
CLOOP
channel using M7 to M0 bits in the
2nd byte.
M7
M6
M5
M4
M3
M2
M1
M0
Set command of repeat playback.
CH1 CH0 Setting is enabled during playback.
Can be specified for each channel.
1
1
0
0
0
0
0
0
Stop command of repeat playback.
Can be specified for each channel.
Also, repeat playback is released by
STOP command automatically.
0
1
1
0
0
0
0
0
CH1 CH0
1
0
0
0
CH1 CH0 Volume control command.
Set volume for each channel using
CV4 CV3 CV2 CV1 CV0 CV4 to CV0 bits in the 2nd byte.
CVOL
AVOL
0
0
Analog volume control command.
Set volume after channel mixing
using AV5 to AV0 bits.
0
0
0
0
0
1
0
0
0
AV5 AV4 AV3 AV2 AV1 AV0
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Voice Synthesis Algorithm
Four types of voice synthesis algorithm are supported. They are 4-bit ADPCM2, 8-bit non-linear PCM, 8-bit
straight PCM and 16-bit straight PCM. Select the best one according to the characteristics of playback voice.
The following table shows key features of each algorithm.
Voice synthesis
Applied waveform
Feature
algorithm
Up version of LAPIS Semiconductor’s specific voice
4-bit ADPCM2
Normal voice waveform synthesis algorithm (: 4-bit ADPCM).
Voice quality is improved.
Algorithm, which plays back mid-range of waveform as
8-bit Nonlinear PCM
Waveform including
high frequency signals
(sound effect, etc.)
10-bit equivalent voice quality.
Normal 8-bit PCM algorithm
Normal 16-bit PCM algorithm
8-bit straight PCM
16-bit straight PCM
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Memory Allocation and Creating Voice Data
The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM
area.
The voice control area manages the voice data in the ROM. It contains data for controlling the start/stop
addresses of voice data for 1,024 phrases, use/non-use of the edit ROM function and so on.
The test area contains data for testing.
The voice area contains actual waveform data.
The edit ROM area contains data for effective use of voice data. For the details, refer to the section of “Edit
ROM Function.”
The edit ROM area is not available if the edit ROM is not used.
The ROM data is created using a dedicated tool.
Configuration of ROM data
0x00000
Voice control area
(Fixed 64 Kbits)
0x01FFF
0x02000
Test area
0x0205F
0x02060
Voice area
max: 0x1FFFFF
Edit ROM area
Depends on creation
of ROM data.
max: 0x1FFFFF
Playback Time and Memory Capacity
The playback time depends on the memory capacity, sampling frequency, and playback method.
The equation to know the playback time is shown below. But this is not applied if the edit ROM function is
used.
1.024 × (Memory capacity – 64.75 [Kbits]
Playback time [sec] =
Sampling frequency [kHz] × Bit length
(Bit length is 4 at the 4-bit ADPCM2 and 8/16 at the PCM.)
Example) In the case that the sampling frequency is 16 kHz, algorithm is 4-bit ADPCM2 and ROM capacity
is 16 Mbits, the playback time is approx. 261 seconds, as shown below.
1.024×(16834 – 64.75) [Kbits]
≅ 261 [sec]
Playback time =
16 [kHz] × 4 [bits]
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Edit ROM Function
The edit ROM function makes it possible to play back multiple phrases in succession. The following functions
are set using the edit ROM function:
Continuous playback:
There is no limit to set the number of times of continuous playback. It
depends on the memory capacity only.
Silence insertion function:
20ms to 1,024 ms (4ms/step)
It is possible to use voice ROM effectively to use the edit ROM function.
Below is an example of the ROM structure, case of using the edit ROM function.
Example 1) Phrases using the Edit ROM Function
Phrase 1
Phrase 2
Phrase 3
Phrase 4
Phrase 5
A
A
E
E
A
B
C
D
D
B
C
D
D
B
D
Silence
E
C
D
Example 2) Structure of the ROM that contents of Example 1 are stored
Address control area
A
B
C
D
E
Editing area
Mixing Function
It is possible to perform mixing of two channels simultaneously. And also, it is possible to specify PLAY,
STOP, and CVOL commands for each channel respectively. The mixing function is available if the sampling
frequency (FS) is 32 kHz or less.
- Precautions for Waveform Clamp
Adjust the volume of each channel using the CVOL command, if the waveform clamp is increased by channel
mixing.
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Memory Bank Switching Function
The memory bank switching function enables the the built-in ROM area that is divivided into up to four banks to
be used. When four banks are used, the maximum number of phrases per bank is 1,024 so that up to 4096
phrases can be played back.
Using this function, multiple ROM codes can be grouped into one code.
The settings of SEL1 pin and SEL0 pin determines which memory bank is used. To playback phrases, the
number of memory banks must be specified in PUP.
When using a memory bank switching function, data must be divided and saved in the specified areas at ROM
data creation.
− When the number of memory banks is 1
SEL1 SEL0
ML22825
ML22865
ML22824
ML22864
ML22823
ML22863
0
0
00000h – 1FFFFFh
00000h – FFFFFh
00000h -7FFFFh
− When the number of memory banks is 2
SEL1 SEL0
ML22825
ML22865
ML22824
ML22864
ML22823
ML22863
0
0
0
1
00000h – FFFFFh
00000h – 7FFFFh
80000h – FFFFFh
00000h – 3FFFFh
40000h – 7FFFFh
100000h – 1FFFFFh
− When the number of memory banks is 4
ML22825
SEL1 SEL0
ML22824
ML22864
ML22823
ML22863
ML22865
0
0
1
1
0
1
0
1
00000h – 7FFFFh
80000h – FFFFFh
100000h – 17FFFFh
180000h – 1FFFFFh
00000h – 3FFFFh
40000h – 7FFFFh
80000h – BFFFFh
C0000h – FFFFFh
00000h – 1FFFFh
20000h – 3FFFFh
40000h – 5FFFFh
60000h – 7FFFFh
The memory (16 Mbits) in the ML22825 is divided as shown below.
Bank 1
Bank 1
Bank 1
Capacity: 16 Mbits
Max. Phrase count: 1024
Capacity: 8 Mbits
Max. Phrase count: 1024
Capacity: 4 Mbits
Max. Phrase count: 1024
0-7FFFFh
80000-FFFFFh
Bank 2
Capacity: 4 Mbits
Max. Phrase count: 1024
Bank 2
Bank 3
Capacity: 8 Mbits
Max. Phrase count: 1024
Capacity: 4 Mbits
Max. Phrase count: 1024
100000-17FFFFh
180000-1FFFFFh
Bank 4
Capacity: 4 Mbits
Max. Phrase count: 1024
Memory divide count: 1
Memory divide count: 2
Memory divide count: 4
16 Mbits × 1 area
8 Mbits × 2 areas
4 Mbits × 4 areas
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Description of Command Functions
1. PUP command
command
0
0
0
0
0
0
S1
S0
The PUP command is used to shift from the power down state to the command waiting state.
This command is only available at the power down state .
Conditions are as follows to enter the power down state.
1) When power is turned on
2) When the RESETB input is “L” level (: rest input).
3) When CBUSYB pin goes to “H” level after inputting the power down command(:PDWN).
The relationship between S1/S0 and the memory banks is as follows:
S1
0
S0
0
Overall memory area is used.
The internal memory is divided into 2 areas. The 2 memory areas are
switched with the SEL0 pin.
0
1
The internal memory is divided into 4 areas. The 4 memory areas are
switched with the SEL1 and SEL0 pins.
1
1
0
1
Prohibited (The operation is the same as above.)
CSB
SCK
SI
tINTP
TPUP1
CBUSYB
Oscillation stopped
Oscillating
XT•XTB
Status
Power-down
Awaiting command
Oscillation stabilized /
Command is being processed
The regulator output starts operating after the PUP command is entered. Any command will be ignored if
entered while oscillation is stabilized. However, if a “L” level is input to the RESETB pin, the LSI enters a
power down state immediately.
The built-in amplifier is not powered up by this command. It is powered up by the AMODE command.
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2. PDWN command
command
0
0
1
0
0
0
0
0
The PDWN command is used to shift from the command waiting state (:both NCR and BUSYB are “H” level) to
the power down state.
Any setting is initialized by this command, so it is necessary to set again after power up.
This command is not available during playback.
To resume playback after the entering power down state, input the AMODE and the PLAY command after
input the PUP command.
CSB
SCK
SI
CBUSYB
NCR
(internal)
BUSYB
(internal)
Oscillation
Oscillating
stopped
XT•XTB
Command is being
processed
Status
Awaiting command
Power down
The regulator and the speaker amplifier stop operation after a lapse of command processing time after the
PDWN command is input. At this time, the SPM output of the speaker amplifier goes to a Hi-Z state to prevent
troubles by pop noise.
Initial stauts at reset input and status during power down
The status of each output pin is as follows:
Analog
State
output pin
VDDL
VDDR
SG
GND
GND
GND
HiZ
SPM
SPP
GND
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3. RDSTAT command
command
1
0
1
1
0
0
0
0
The RDSTAT command is used to read the NCR and BUSYB signals that indicate the status of internal
operation.
The NCR signal is “L” level while command are processed, and goes to “H” level at the command waiting state.
The BUSYB signal is “L” level during playback voices.
The command interval time ( : tINTRD) is needed to input the next command after reading status using this
command.
The following table shows the contents of each bit of data output.
Output status signal
MSB
7SB
6SB
5SB
4SB
3SB
2SB
LSB
Channel 2 BUSYB output (BUSYB1)
Channel 1 BUSYB output (BUSYB0)
Channel 2 NCR output (NCR1)
Channel 1 NCR output (NCR0)
RDSTAT command
CSB
SCK
SI
tINTRD
SO
tCB1
VOH
VOL
CBUSYB
NCR
(internal)
VOL
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Explanation of NCR/BUSYB is shown in the following figure.
PLAY command
1st byte
PLAY command
2nd byte
CSB
SCK
SI
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Address is being
controlled
Command standby
Awaiting command
Playing
Awaiting command
状態
Command is being
processed
When RDSTAT is inputted to this timing,
NCR="H" and BUSYB="L" are outputted.
NCR outputs "L" during command processing and address administration, and outputs "H" in other state.
BUSYB outputs "L" during command processing and reproduction, and outputs "H" in other state.
NCR/BUSYB at the time of inputting the RDSTAT command is read as the serial output from SO
terminal.
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4. AMODE command
command
0
0
0
0
0
1
0
0
1st byte
2nd byte
FAD DAG1 DAG0 AIG1 AIG0 DAEN SPEN POP
The AMODE command uses 2 bytes. This command is used to perform various settings for analog circuitry.
This command is not available during power-down state, transition to power-up state, transition to power down
state or playback state.
In the case of performing power down using PDWN command during power up of analog circuitry, the setting of
power up by AMODE command is retained. Use the AMODE command to perform power down, if need to
use different conditions from power up of analog circuitry.
In the case of power up of analog circuitry, input the AMODE command after setting the CVOL command to
“00h” (: initial value).
The settings of each bit is shown below.
The setting is initialized by reset release or power-up.
The FAD bit specifies whether to perform fade-out processing when the STOP command is input. If the bit is
set to “1”, fade-out processing is performed during a period of approx. 3 ms after the STOP command is input.
The BUSYB signal goes to “H” level after fade-out processing.
FAD
Fade-out processing
0
1
Not available (initial value)
Available
The DAG1, 0 bits are used to set the gain of the internal DAC signal. The AIG1, 0 bits are used to set the gain
of an analog input signal from the AIN pin. They are available only when using the speaker amplifier.
DAG1 DAG0
Volume
0
0
1
1
0
1
0
1
Input OFF
Input ON (–6 dB)
Input ON (0 dB) (initial value)
Prohibited (input ON (0 dB))
AIG1
AIG0
Volume
Input OFF (initial value)
Input ON (–6 dB)
Input ON (0 dB)
Prohibited (input ON (0 dB))
0
0
1
1
0
1
0
1
The DAEN bit controls power-up and power-down of the DAC circuitry.
DAEN
0
1
Status of the DAC section
Power-down state (initial value)
Power-up state
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The SPEN bit takes power-up and power-down of the speaker circuitry.
When the SPEN bit is “0”, SPP pin is the LINE output.
SPEN
0
1
Status of the speaker circuitry
Power-down state (initial value)
Power-up state
The POP bit sets whether to suppress the “pop” noise of the LINE output.
− In the case of setting the POP bit to “0”
If the DAEN bit is “1”, LINE output rises from the GND level to the SG level during a period of the
specified time (:tPOPA1) . If the DAEN bit is “0”, LINE output falls from the SG level to the GND level
during a period of the specified time (:tPDA1).
− In the case of setting the POP bit to “1”
If the DAEN bit is “1”, LINE output rises from the GND level to the SG level during a period of the
specified time (:tPOPA2). If the DAEN bit is “0”, LINE output falls from the SG level to the GND level
during a period of the specified time (:tPDA2).
POP
Pop noise suppression
0
1
Not available (initial value)
Available
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• When POP bit is “0”, SPEN bit is “0” and DAEN bit goes to “1”
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB1
tPOPA1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
1/2SPVDD
SPP
GND
(LINE output)
Command is being
processed
Awaiting command
Status
Awaiting command
Awaiting command
Command is being
processed
• When POP bit is “1”, SPEN bit is “0” and DAEN bit goes to “1”
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB1
tPOPA2
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
1/2SPVDD
GND
SPP
(LINE output)
Awaiting command
Command is being
POP noise suppressed
Status
Awaiting command
Awaiting command
Command is being
processed
processed
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• When SPEN bit goes to “1”
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB1
tPOPA3
VOH
CBUSYB
VOL
VOH
NCR
(internal)
VOL
VOH
BUSYB
(internal)
VOL
AOUT
GND
(internal)
1/2SPVDD
1/2SPVDD
Hi-Z
SPM
GND
SPP
Command is being
processed
Awaiting command
Status
Awaiting command
Awaiting command
Command is being
processed
• When POP bit is “0”, SPEN bit is “0” and DAEN bit goes to “0”
AMODE command
2nd byte
AMODE command
1st byte
CSB
SCK
SI
tCB1
tPDA1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
1/2SPVDD
SPP
GND
(LINE output)
Command is being
processed
Status
Awaiting command
Awaiting command
Awaiting command
Command is being
processed
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• When SPEN bit goes to “0”
AMODE command
2nd byte
AMODE command
1st byte
CSB
SCK
SI
tCB1
tPDA3
VOH
CBUSYB
VOL
VOH
NCR
(internal)
VOL
VOH
BUSYB
(internal)
VOL
1/2SPVDD
1/2SPVDD
1/2SPVDD
AOUT
(internal)
GND
Hi-Z
SPM
SPP
GND
Command is being
processed
Status
Awaiting command
Awaiting command
Awaiting command
Command is being
processed
• When POP bit is “1”, SPEN bit is “0” and DAEN bit goes to “0”
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB1
tPDA2
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
1/2SPVDD
SPP
GND
(LINE output)
POP noise suppressed
Status
Awaiting command
Awaiting command
Awaiting command
Command is being
processed
Command is being
processed
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5. PLAY command
command
0
1
0
0
F9
F3
F8
F2
0
CH
F0
1st byte
2nd byte
F7
F6
F5
F4
F1
The PLAY command uses 2 bytes. This command is used to start playback phrase. This command is able to
input by each channel when the NCR signal is “H” level. The channel to be played back is specified by the CH
bit.
For the phrase to be played back, set the phrase address of voice data in the ROM using the F9 to F0 bits.
The following figure shows the timing of playback phrase (F9 to F0 is 01h) .
PLAY command
1st byte
PLAY command
2nd byte
CSB
SCK
SI
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Address is being
controlled
Awaiting command
Awaiting command
Playing
Awaiting command
Status
Command is being processed
When the 1st byte of the PLAY command is input, the device enters a state awaiting input of the 2nd byte of the
PLAY command after a lapse of command processing time.
When the 2nd byte of PLAY command is input, the device starts reading the external ROM to get the address
information of the phrase to be played back after a lapse of command processing time.
Thereafter, playback starts and the playback is performed up to the specified ROM address, then the playback
stops automatically.
The NCR1 signal is “L” level during address control, and goes “H” level when the address control is completed.
Then it is possible to input the PLAY command for the next playback phrase.
The BUSYB signal is “L” level during address control and playback, and goes to “H” level when playback is
completed. Then it is possible to knowwhether the playback is going on by the BUSYB signal.
- Channel settings mothod
CH
0
Channel
Channel 1
Channel 2
1
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The PLAY Command Input Timing for Continuous Playback
In the case of continuous playback, input the PLAY command for the next phrase within the command input
enable time (:tcm) after NCR goes to “H” level. Then it is possible to start playback the next phrase without any
silent interval between phrases.
PLAY command
2nd byte
PLAY command PLAY command
1st byte 2nd byte
CSB
SCK
SI
tcm
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Awaiting command
Playing phrase 1
Playing phrase 2
Status
Address is being controlled
Address is being controlled
As shown in the diagram above, if continuous playback is carried out, input the PLAY command for the second
phrase (tcm) after NCR goes “H”. This will make it possible to start playing the second phrase immediately
after the playback of the first phrase finishes. Phrases can thus be played continuously without inserting silence
between phrases.
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6. STOP command
command
0
1
1
0
0
0
CH1 CH0
The STOP command is used to stop playback for each channel. This command can be set to each channel and
also to multiple channels simultaneously. The channels are specified by setting CH0 to CH1 bits to “1” state
respectively.
If the playback is stopped, the NCR and BUSYB signals go to “H” level.
Although it is possible to input this command regardless of the status of NCR during playback, a prescribed
command interval time (:tINT) is needed.
The STOP command is not available during power down, transition to power-up or transition to power-down.
The playback related command (:PLAY, START or MUON) is not available during STOP command processing.
STOP command
CSB
SCK
SI
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Status
Playing
Awaiting command
Command is being processed
- Channel settings method
Channel
CH0
CH1
Channel 1
Channel 2
The playback related command (:PLAY, START or MUON), used on the same channel after the STOP
command, should be input after confirming the completion (: NCRn is “H” and BUSYBn is “H”, n is the related
number of channel concerned) of this command processing by the RDSTAT command, or waiting for 12ms from
transition of the CBUSYB to “H” level.
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7. FADR command
command
0
0
1
1
F9
F3
F8
F2
0
CH
F0
1st byte
2nd byte
F7
F6
F5
F4
F1
The FADR command used 2 bytes. This command is used to specify phrase to be played. The channel and
phrase to be played back are set by this command.
The channel for playback is specified by CH bit.
Playback will be started by START command after the phrase for each channel is specified.
For the phrase to be played back, set the phrase address of voice data in the ROM using the F9 to F0 bits.
The setting values of the FADR command are initialized at power-down.
- Channel settings method
CH
0
Channel
Channel 1
Channel 2
1
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8. START command
command
0
1
0
1
0
0
CH1 CH0
The START command is used to start playback on the channel specified. It is necessary to specify a playback
phrase using the FADR command before inputting this command.
Usually, use this command when starting playback on multiple channels simultaneously.
The channels to be player back are specified by setting CH0 to CH1 bits to “1” starts respectively.
The following figure shows the timing when starting playback on channel 1 and channel 2 simultaneously.
CSB
SCK
SI
tCB1
CBUSYB
NCR0,1
(internal)
BUSYB0,1
(internal)
1/2SPVDD
SPP output
1/2SPVDD
SPM output
Address is being
controlled
Awaiting
command
Awaiting
command
Playing
Status
- Channel settings method
Channel
Channel 1
Channel 2
CH 0
CH 1
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The START Command Input Timing for Continuous Playback
The START command input timing in the case of reproducing the following phrase succeeding the one phrase
playback is shown.
START command
START command
CSB
SCK
SI
tcm
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2SPVDD
1/2SPVDD
SPM
SPP
Awaiting command
Playing phrase 1
Playing phrase 2
Address is being controlled
Status
Address is being controlled
As shown in the diagram above, if continuous playback is carried out, input the START command for the second
phrase (tcm) after NCR goes “H”. When it cannot, please input the phrase 2 START command after checking
that BUSYB became "H"(phrase 1 playback has been finished).
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9. MUON command
command
0
1
1
1
0
0
CH1 CH0
M1 M0
1st byte
2nd byte
M7
M6
M5
M4
M3
M2
The MUON command uses 2 bytes. This command is used to insert the silence between two playback phrases.
This command can be set to each channel and also to multiple channels simultaneously. The channels are
specified by setting CH0 to CH1 bits to “1” state respectively.
This command can be input when the NCR signal is “H” level. Set the silent time value after inputting this
command.
The silent time length to be specified by M7 to M0 bits is able to be set by 256 steps at 4 ms interval between 20
ms and 1,024 ms.
The silent time length (tmu) is calculated by equation as below.
The silent time length should be set to 04h or higher (:tmu is 20ms or more).
tmu = (27×(M7) + 26×(M6) + 25×(M5) + 24×(M4) + 23×(M3) + 22×(M2) + 21×(M1) + 20×(M0) + 1) × 4ms
The following figure shows the timing of inserting the silence of 20 ms between the repetitions of a phrase (F7 to
F0 is 01h).
PLAY command
MUON command MUON command
PLAY command PLAY command
2nd byte
1st byte 2nd byte
1st byte 2nd byte
CSB
SCK
SI
tcm
tcm
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Awaiting command
Playing
Silence is being inserted
Playing
Status
Waiting for playback to be finished
Waiting for silence insertion
to be finished
Address is being controlled
When the playback starts after the PLAY command is input and the address control of phrase-1 is over, the
CBUSYB and NCR signals go to “H” level. Input the MUON command after this CBUSYB signal changes to
“H” level. After the MUON command input, the NCR signal remains at “L” level until the end of phrase-1
playback. This status is the waiting for the phrase-1 playback to be finished.
When the phrase-1 playback is finished, the silence playback starts and the NCR signal goes to “H” level. Then,
input the PLAY command again to playback phrase-1. Then, the NCR signal goes to “L” level again and the
device enters a state of the waiting for the end of silence playback.
When the silence playback is finished and then the phrase-1 playback starts, the NCR signal goes to “H” level,
and the device enters a status where it is possible to input the next PLAY or MUON command.
The BUSYB signal remains “L” level until the end of a series of playback.
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10. SLOOP command
command
1
0
0
0
0
0
CH1 CH0
The SLOOP command is used to set the repeat playback mode for each channel. This command can be set to
each channel and also to multiple channels simultaneously. The channels are specified by setting CH0 to CH1
bits to “1” state respectively.
Use the CLOOP command to release repeat playback mode.
Since the SLOOP command is only valid during playback, be sure to input the SLOOP command while the NCR
signal is “H” level after the PLAY command is input. The NCR signal is “L” level during repeat playback
mode.
Once repeat playback mode is set, the current phrase is repeatedly played until the repeat playback setting is
released by the CLOOP command or until playback is stopped by the STOP command. In the case of a phrase
that was edited by the edit function, the edited phrase is repeatedly played.
The repeat playback mode is released if playback is stopped by the STOP command, therefore input the SLOOP
command again if need to repeat playback again.
The following shows the SLOOP command input timing.
PLAY command
2nd byte
SLOOP command
CLOOP command
CSB
SCK
SI
CBUSYB
NCR
(internal)
tcm
BUSYB
(internal)
1/2SPVDD
SPM
1/2SPVDD
SPP
Awaiting command
Playing
Playing
Awaiting command
Status
Address is being controlled
Address is being controlled
Command is being processed
Effective Range of SLOOP Command Input
After the PLAY command is input, input the SLOOP command within the command input enable time (: tcm)
after NCR goes “H”. Then, the SLOOP command is available to repeat playback.
- Channel settings method
Channel
CH 0
CH 1
Channel 1
Channel 2
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11. CLOOP command
command
1
0
0
1
0
0
CH1 CH0
The CLOOP command is used to release the repeat playback mode for each channel. This command can be set
to each channel and also to multiple channels simultaneously. The channels are specified by setting CH0 to
CH1 bits to “1” state respectively.
When the repeat playback mode is released, the NCR signal goes “H” level.
It is possible to input this command regardless of the NCR signal status during playback, but a prescribed
command interval time (:tINT) is needed.
- Channel setting method
Channel
CH 0
CH 1
Channel 1
Channel 2
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12. CVOL command
command
1
0
0
0
1
0
0
0
0
CH1 CH0
1st byte
2nd byte
CV4 CV3 CV2 CV1 CV0
The CVOL command uses 2bytes. This command is used to adjust the playback volume of each channel.
This command can be set to each channel and also to multiple channels simultaneously. The channels are
specified by setting CH0 to CH1 bits to “1” state respectively.
It is possible to input this command regardless of the NCR status. This command is not available during power
down, transition to the power-up state or transition to the power-down state.
This command can adjust volume by 32-levels as shown in the table below. The initial value is set to 0 dB
after the reset is released. Also, the setting of this command is initialized after the reset is released or during
power-up,
CV4-0
00
Volume
0dB
(initial value)
CV4-0
10
Volume
-6.31
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
-0.28
-0.58
-0.88
-1.20
-1.53
-1.87
-2.22
-2.59
-2.98
-3.38
-3.81
-4.25
-4.72
-5.22
-5.74
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
-6.90
-7.55
-8.24
-9.00
-9.83
-10.74
-11.77
-12.93
-14.26
-15.85
-17.79
-20.28
-23.81
-29.83
OFF
- Channel setting method
Channel
CH 0
CH 1
Channel 1
Channel 2
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13. AVOL command
command
0
0
0
0
0
0
1
0
0
0
1st byte
2nd byte
AV5 AV4 AV3 AV2 AV1 AV0
The AVOL command uses 2 bytes. This command is used to adjust the playback volume. It is possible to
input this ommand regardless of the NCR status.. This command is not available during power down state,
transition to power-up state or transition to power-down state.
This command can adjust volume by 50-level as shown in the table below. The initial value is set to -4.0 dB
after the released. When the STOP command is input, the value set by the AVOL command is retained.
When powered down, the value set by the AVOL command is initialized.
AV5-0
Volume(dB)
AV5-0
Volume (dB) AV5-0 Volume (dB) AV5-0 Volume (dB)
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
+12.0
+11.5
+11.0
+10.5
+10.0
+9.5
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
+4.0
+3.5
+3.0
+2.5
+2.0
+1.5
+1.0
+0.5
+0.0
-1.0
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
-8.0
-9.0
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
-34.0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
-10.0
-11.0
-12.0
-13.0
-14.0
-16.0
-18.0
-20.0
-22.0
-24.0
+9.0
+8.5
+8.0
+7.5
+7.0
-2.0
+6.5
-3.0
-4.0
(initial value)
33
+6.0
23
13
-26.0
03
OFF
32
31
30
+5.5
+5.0
+4.5
22
21
20
-5.0
-6.0
-7.0
12
11
10
-28.0
-30.0
-32.0
02
01
00
OFF
OFF
OFF
To know the volume controls more
Three commands (: CVOL, AVOL and AMODE) can control volume. CVOL
sets volume of each channel. AVOL sets volume of signal after mixing. And
AMODE sets input gain of amplifier.
CVOL setting
DAG bits on AMODE
AVOL setting
Channel1
Channel2
DAC
Filter
GAIN
AMP
MIXING
SPP
SPM
AMP
GAIN
AMP
AIG bit on AMODE
AIN
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Command Flow Charts
1-Byte Command Input Flow (applied to the PUP, PDWN, STOP, START, SLOOP, and CLOOP commands)
Start
CBUSYB “H”?
N
Y
Input command
CBUSYB “H”?
N
Y
End
2-Byte Command Input Flow (applied to the AMODE, PLAY, FADR, MUON, CVOL, and AVOL commands)
Start
CBUSYB “H”?
N
Y
Input the 1st byte of command
CBUSYB “H”?
N
Y
Input the 2nd byte of command
CBUSYB “H”?
N
Y
End
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Status Read Flow
RDSTAT command
CBUSYB “H”?
Y
N
Read status (SI=”L”)
Power-On Flow
Apply power, Drive RESETB “L”
Waited for
100 µs?
N
Y
Drive RESETB “H”
Example of Power-Up Flow
Power-down state
PUP command
AMODE command
Example of Playback Start Flow
Power-up state
Idle (not playback)?
Y
N
Single-channel playback
PLAY command
Multi-channel playback
FADR command
START command
Example of Playback Stop Flow
Playing
STOP command
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Continuous Playback Start Flow
Playback start
Playing
Within 10mS
PLAY/START/MUON command
Loop Start Flow
Playback start
Playing
Within 10mS
SLOOP command
Loop Stop Flow
Looping
Stop after playback is finished all the
way through the phrase
Stop playback forcibly
CLOOP command
STOP command
Power-Down Flow
Power-up state
PDWN command
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Detailed Flow of “Power-Up ⇒ Playback ⇒ Power-Down”
Power-down state
A
CBUSYB “H”?
Y
N
N
N
N
CBUSYB “H”?
Y
PUP command
RDSTAT command
CBUSYB “H”?
Y
CBUSYB “H”?
Y
N
1st byte of AMODE command
Read status
CBUSYB “H”?
BUSYB “H”?
Y
N
Y
2nd byte of AMODE command
1st byte of AMODE command
CBUSYB “H”?
Y
N
N
CBUSYB “H”?
Y
1st byte of PLAY command
2nd byte of AMODE command
CBUSYB “H”?
Y
N
CBUSYB “H”?
Y
N
2nd byte of PLAY command
PDWN command
A
N
CBUSYB “H”?
Y
Power-down state
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TERMINATION OF THE SG PIN
The SG pin is the signal ground for the built-in speaker amplifier. Connect a capacitor between this pin and the
analog ground (:DGND) pin to prevent the trouble caused by noise.
Recommended capacitance value is shown below; however, it is important to evaluate and decide using the own
board.
Also, start playback after each output voltage is stabilized.
Recommended
capacitance value
Pin
SG
Remarks
The time to stabilize voltage of the speaker output (:SPM and
SPP) is longer, if use the larger capacitance.
0.1 µF ±20%
TERMINATION OF THE VDDL AND VDDR PINS
The VDDL pin is the regulator output that is power supply pin for the internal logic circuits and the VDDL pin is the
power supply pin for the P2ROM. Connect a capacitor between this pin and the ground in order to prevent
noise generation and power fluctuation.
The recommended capacitance value is shown below. However, it is important to evaluate and decide using the
own board.
Also, start the next operation after each output voltage is stabilized.
Recommended
capacitance value
Pin
Remarks
The larger the connection capacitance, the longer the settling
time.
VDDL, VDDR
10 µF ±20%
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POWER SUPPLY WIRING
The power supplies of this LSI are divided into the following two:
• Power supply for logic circuitry (: DVDD
)
• Power supply for speaker amplifier (: SPVDD
)
As shown in the figure below, supply DVDD and SPVDD from the same power supply, and separate them into
analog and logic power supplies in the wiring.
DVDD
DGND
5V
SPVDD
SPGND
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ML2283X/ ML2287X
RECOMMENDED CERAMIC OSCILLATION
Recommended ceramic resonators for oscillation and conditions are shown below for reference.
KYOCERA Corporation
Optimal load capacity
Freq [Hz]
Type
C1
C2
Rf
Rd Supply voltage Operating Temperature
[pF]
[pF] [Ohm] [Ohm]
Range [V]
Range [°C]
2.7 to3.3
4.5 to5.5
4.096M PBRC4.096MR50X000 15(internal)
---
--
-20 to +85
Note: C1 and C2 are capacitors built-in resonator.
Circuit diagram
GND
VDD
C2
C1
TDK Corporation
Optimal load capacity
C1 Supply voltage Operating Temperature
Freq [Hz]
Type
C1
CL2
Rf
[pF]
[pF] [Ohm] [pF]
Range [V]
2.7 to3.6
4.5 to5.5
2.7 to3.6
Range [°C]
FCR4.0MXC5
FCR4.0MXC5
FCR4.09MXC5
4.000M
4.096M
30 (internal)
30 (internal)
---
---
---
---
-40 to +85
-40 to +85
FCR4.09MXC5
4.5 to5.5
Note: C1 and C2 are capacitors built-in resonator.
Circuit diagram
GND
VDD
CL2
CL1
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FEDL2283X-07
ML2283X/ ML2287X
MURATA Corporation
Optimal load capacity
Supply
voltage
Range [V]
Operating
Temperature
Range [°C]
Freq [Hz]
Type
C1
[pF]
C2
Rf
Rd
[pF] [Ohm] [Ohm]
SMD
CSTCR4M00G55-R0
CSTLS4M00G56-B0
CSTCR4M00G55-R0
CSTLS4M00G56-B0
CSTCR4M09G55-R0
CSTLS4M09G56-B0
CSTCR4M09G55-R0
39 (Built-in)
47 (Built-in)
39 (Built-in)
47 (Built-in)
39 (Built-in)
47 (Built-in)
39 (Built-in)
47 (Built-in)
2.7 to 3.6
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
Leaded
4.000M
---
---
0
0
SMD
Leaded
SMD
-40 to +85*
Leaded
4.096M
SMD
Leaded CSTLS 4M09G56-B0
Note: C1 and C2 are capacitors built-in resonator.
Circuit diagram
GND
VDD
C2
C1
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FEDL2283X-07
ML2283X/ ML2287X
APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 5V)
RESETB
MCU
CSB
SCK
SPM
SPP
SI
SO
CBUSYB
Speaker
0.1µF
DIPH
SG
TESTI1
0.1µF
AIN
TESTI0
VDDL
VDDR
DVDD
10µF
10µF
33pF
4.096MHz
33pF
XT
SPVDD
0.1µF
0.1µF
5V
XTB
DGND
SPGND
APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 3V)
RESETB
MCU
CSB
SCK
SI
SPM
SPP
SO
Speaker
CBUSYB
0.1µF
SG
DIPH
TESTI1
0.1 µF
AIN
TESTI0
VDDL
VDDR
DVDD
10µF
33pF
SPVDD
XT
0.1µF
0.1µF
4.096MHz
0.1µF
3V
DGND
XTB
33pF
SPGND
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ML2283X/ ML2287X
APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=5V)
7kΩ
7kΩ
SCL
SDA
MCU
(CBUSYB)
SPM
SPP
Speaker
0.1µF
SG
SAD2-0
0.1µF
AIN
TESTI0
TESTI1
VDDL
VDDR
DVDD
10µF
10µF
33pF
XT
SPVDD
0.1µF
4.096MHz
33pF
0.1µF
5V
XTB
DGND
SPGND
APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=3V)
7kΩ
MCU
7kΩ
SCL
SDA
(CBUSYB)
SPM
SPP
Speaker
0.1µF
0.1µF
SG
SAD2-0
AIN
TESTI0
TESTI1
VDDL
VDDR
33pF
DVDD
XT
SPVDD
10µF
0.1µF
0.1µF
4.096MHz
33pF
0.1µF
3V
XTB
DGND
SPGND
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ML2283X/ ML2287X
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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REVISION HISTORY
Page
Previous
Edition
Document No.
Date
Description
Current
Edition
PEDL2282XFULL-01 Dec. 17, 2007
FEDL228XXFULL-01 Apr. 18, 2008
FEDL228XXFULL-02 May. 29, 2008
–
–
–
–
Preliminary edition 1
–
–
Final edition 1
Final edition 2
2-channel mixing function
48kHz-> 32kHz
1
1
Power supply voltage
2.7 to 5.5V -> 2.7 to 3.6V / 4.5 to 5.5 V
2
2
LINE output voltage range
10
10
10
10
10
10
MAX. DVDD x 4/6 -> DVDD x 5/6
SG output resistance
Min 52 -> Min 57
AIN input voltage range(for the 5V app..)
Max. DVDD x 2/4 -> DVDD x 2/3
CBUSYB “L” level output time
PUP: (Min= - /Typ= - /Max=10) ->
(Min=2.0/Typ=2.5/Max=3.0)
11
11
FEDL228XXFULL-03 Mar. 24, 2009
CBUSYB “L” level output time
tCB1: Max= 2µs -> Max= 2ms
11
13
11
13
(Ta = -40 to +70) -> (Ta = -40 to +85)
12,24,32,
33,34,35
12,24,32,
33,34,35
PUP(AMODE) -> POP(AMODE)
26
44, 45
45
26
44, 45
45
Correct ROM address and calculation
Modify volume table
Add volume setting information
Modify application circuit
50,51
45
50,51
45
Correct value for AVOL
6
6
Modify SCL/SDA initial value.(0 -> 1)
Add “Pulse width of spikes which must be
suppressed by the input filter”.
-
13
FEDL228XXFULL-04 Jun. 20, 2011
-
-
19-25
29-30
53
Add timing chart( I2C interface )
Add timing chart( I2C interface )
Modify AVOL table
53
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ML2283X/ ML2287X
Page
Previous
Edition
Document No.
FEDL228XX-05
Date
Description
Current
Edition
Modify tDOD1.
Oct. 10, 2013
12
12
( SCK rise edge -> SCK fall edge )
1
2
1
2
Package is changed.
Add Playback method.
tPOPA3 and tPDA3 is added to CBUSYB “L” level
output time in AC Characteristics(Common to
All Products).
11
11
t
POPA2 is modified to CBUSYB “L” level output
time in AC Characteristics(Common to All
Products).
14,19
15,20
14,20
15,21
Time chart of tPUP1 is modified.
Time chart of tPD1 is modified.
Explanation of the playback start timing by
the PLAY command is added.
16,21
16,21
17,22
16,22
16,22
17,23
Explanation of the playback stop timing is
added.
Explanation of the continuous playback
timing by the PLAY command is added.
FEDL228XX-06
Sep. 01, 2017
“Continuous Playback Timing by the START
command” is added.
- , -
17,23
18,24
18,25
19,26
Explanation of the silence Insertion timing by
the MUON command is modified.
17,23
18,24
18,25
“Repeat Playback Set/Release Timing by the
SLOOP and CLOOP Commands” is added.
Explanation of the timing of volume change
by the CVOL command is modified.
“Timing of Volume Change by the AVOL
Command” is added.
- , -
35
-
19,26
36
Add Silence step.
Explanation of NCR/BUSYB is added to the
time chart of RDSTAT.
41
Time chart of tPOPA3 and tPDA3 is added.
Time chart of tPOPA1, tPOPA2, tPDA1 and tPDA2 is
modified.
42,43
44-46
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ML2283X/ ML2287X
Page
Previous
Edition
Document No.
Date
Description
Current
Edition
"The START Command Input Timing for
Continuous Playback" is added.
-
52
-
58-61
68
Add Command Flow Charts.
Change of the package.
60
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FEDL228XX-06
ML2282X-XXX/ ML2286X -XXX
NOTES
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from
failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire
prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for
any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to
illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when
designing circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property
rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this
document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights
owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and
power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have
no responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright 2007 – 2017 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
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