ML5204 [ROHM]
电池电压和电流值监控器过充电和过放电电压检测充放电过电流检测短路电流检测唤醒检测内置电池均衡开关MCU接口：I2C;
| 型号： | ML5204 |
| 厂家： | 
ROHM |
| 描述： | 电池电压和电流值监控器过充电和过放电电压检测充放电过电流检测短路电流检测唤醒检测内置电池均衡开关MCU接口：I2C 电池 开关 监控 |
| 文件： | 总36页 (文件大小：2008K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL5204-02
1, December, 2020
ML5204
Analog Front-End IC for 4 to 5-Serial-Cell Lithium-Ion Rechargeable Battery Protection
■ General Description
The ML5204 is an analog front-end type battery monitoring LSI for a host controller in 4- to 5-cell Li-ion
rechargeable battery packs. It outputs individual analog cell voltages and pack current equivalent voltage, while
cell balancing, overvoltage/undervoltage detection, and overcurrent detection functions are integrated for
configuring high-precision/high-reliability battery management systems.
■ Features
• Supported number of cells: 4 to 5 cells
• Analog cell voltage output: Individual analog cell voltage is divided by 2 and output on the VMON pin.
• Analog pack current output: The voltage across the shunt resistor is amplified by x12 or x24 and output
on the IMON pin
• Cell balancing function: Built-in cell balancing switches with a 6Ω (typ) ON resistance
• Overvoltage/undervoltage detection function:
Overvoltage detection accuracy
2nd overvoltage detection accuracy
Undervoltage detection accuracy
: ±20 mV (25 °C)
: ±35 mV (25 °C)
: ±50 mV (25 °C)
Zero voltage (0-V) charge inhibit detection accuracy : ±50 mV (25 °C)
• Charge/discharge overcurrent detection function
Discharge overcurrent detection accuracy
Charge overcurrent detection accuracy
: ±10 mV (25 °C)
: ±10 mV (25 °C)
• Short-Circuit detection function:
Short-circuit detection accuracy
: ±10 mV (25 °C)
• Wake-up detection function: Asserts an interrupt signal to the external MCU when a predefined discharge
current is detected.
• Cell count, detection thresholds and delay times can be redefined and supplied under a separate product
code
• MCU interface: I2C compatible serial interface
• Low current consumption
Cell voltage/current monitor active
Cell voltage/current monitor inactive
:
:
14 μA (typ), 50 μA (max)
6 μA (typ), 10 μA (max)
• High voltage supply input
• Operating power supply range
• Operating temperature
• Package
:
:
:
:
+53 V (absolute maximum rating)
+3.3 V to +42 V
-40 °C to +85 °C
20-pin TSSOP
Note) This product is not intended for automotive use and for any equipment, device, or system that requires a
specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace
machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether
your application corresponds to such special purposes, please contact your local ROHM sales
representative in advance.
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FEDL5204-02
ML5204
■ Block Diagram
VDD
V5
VREG
Voltage
Regulator
SDA
SCL
V4
V3
V2
V1
/INTO
Reference
Voltage
Generator
Control
Logic
/ERR
CELLOP
/SCDET
/PUPIN
Cell Voltage
Detector
Clock
Generator
V0
Cell Voltage
Monitor
Clock Stop
Detector
GND
Current
Detector
Output
Buffer
VMON
IMON
ISM
ISP
Current
Monitor
■ Pin Configuration (Top View)
1
2
3
4
5
6
20
VDD
V5
VREG
19
SCL
18
V4
SDA
V3
17
/INTO
V2
16 /ERR
V1
15 /SCDET
V0 7
GND 8
14
13
12
11
CELLOP
VMON
IMON
ISP
/PUPIN 9
ISM
10
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FEDL5204-02
ML5204
■ Pin Description
Pin No.
Pin name
I/O
Description
Power supply.
Configure an external CR noise filter circuit.
1
VDD
—
2
3
4
5
6
7
8
V5
V4
I
I
I
I
I
I
I
Cell 5 positive input.
Cell 5 negative input and Cell 4 positive input.
Cell 4 negative input and Cell 3 positive input.
Cell 3 negative input and Cell 2 positive input.
Cell 2 negative input and Cell 1 positive input.
Cell 1 negative input.
V3
V2
V1
V0
GND
Ground pin.
Power-up trigger input. The device wakes up with an "L" level input.
Internally pulled up to VDD through a 1 M resistor.
9
/PUPIN
I
Connect a 0.1 F capacitor between this pin and GND.
Current sense negative input. Connected to the negative terminal of the
lowest battery cell.
Current sense positive input. The ISP pin level should be higher than the ISM
pin level in discharge state.
10
11
ISM
ISP
I
I
Analog current monitor output. The input voltage difference between the ISP
and ISM pins is amplified by 12-/24-fold on output.
Analog cell voltage output. The specified cell voltage is divided by 2 on output.
2nd overvoltage alarm output. Output type is NMOS open drain, and the "L"
level is asserted at 2nd overvoltage conditions.
12
13
14
IMON
VMON
O
O
O
CELLOP
Short-circuit alarm output. Output type is NMOS open drain, and the "L" level
is asserted if short-circuit is detected.
Error state alarm output. Output type is NMOS open drain, and the "L" level is
asserted if any error is detected.
Interrupt signal to an external MCU. Output type is NMOS open drain, and the
"L" level is asserted when an interrupt request occurs.
15
16
17
/SCDET
/ERR
O
O
O
/INTO
18
19
SDA
SCL
IO
I
Serial data input/output pin. Connect an external pull-up resistor.
Serial clock input pin. Connect an external pull-up resistor.
Internal 3.3 V regulator output pin. Connected to GND through a 1 F or
larger capacitor. Do not use as a power supply for external circuit.
20
VREG
O
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FEDL5204-02
ML5204
■ Absolute Maximum Ratings
GND= 0 V, Ta = +25 °C
Rating Unit
Item
Symbol
VDD
Conditions
Applied to VDD pin
Supply voltage
-0.3 to +53
V
Applied to V5 to V0 pins
VIN1
Voltage difference between Vn+1
and Vn pins (Note 1)
-0.3 to +6.5
V
Input voltage
VIN2
VIN3
VIN4
Applied to /PUPIN pin
-0.3 to VDD+0.3
-0.3 to VREG+0.3
-0.3 to +6.5
V
V
V
Applied to ISM and ISP pins
Applied to SCL and SDA pins
Applied to /SCDET, CELLOP,
/ERR, /INTO, SDA, VREG pins
VOUT1
VOUT2
ICB
-0.3 to +6.5
-0.3 to VREG+0.3
200
V
V
Output voltage
Applied to VMON and IMON pins
Cell balancing
current
Per cell balancing switch
mA
W
Power dissipation
PD
—
1.0
Applied to /SCDET, CELLOP,
/ERR, /INTO, SDA, VREG, VMON,
IMON pins
Short-circuit
output current
IOS
10
mA
Storage
temperature
TSTG
—
-55 to +150
°C
Note 1: When connecting or removing a battery cell, the Vn+1-to-Vn pin voltage may exceed the specified
rating, leading to destruction of the device. Make a full and detailed evaluation before usage.
■ Recommended Operating Conditions
GND= 0 V
Unit
Item
Symbol
VDD
Conditions
Applied to VDD pin
—
Range
3.3 to 42
-40 to +85
Supply voltage
V
Operating temperature
TOP
°C
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FEDL5204-02
ML5204
■ Electrical Characteristics
● DC Characteristics
VDD=3.3 V to 42 V, GND=0 V, Ta=-40 to +85 °C
Item
Symbol
Conditions
—
Min.
Typ.
—
Max.
Unit
V
"H" input voltage (Note 1)
"L" input voltage (Note 1)
"H" input current (Note 1)
"L" input current (Note 1)
VIH
VIL
IIH
0.7×VREG
3.6
—
0
—
0.3×VREG
V
VIH = 3.3 V
—
–2
—
2
µA
µA
IIL
VIL = GND
—
—
In normal operation
Cell voltage monitor
inactive
Cell balancing switch
OFF
Cell voltage monitor pin
input current 1
IINV1
—
0.1
1.5
3.5
µA
µA
Each cell voltage = 4 V
Cell voltage monitor
active
Cell balancing switch
OFF
Cell voltage monitor pin
input current 2
IINV2
–0.5
—
Cell voltage monitor pin
input leakage current
"L" output voltage (Note 2)
Output leakage current
(Note 2)
IILVC
VOL
IOLK
In power-down
IOL = 1 mA
–0.5
—
—
—
—
0.5
0.2
2
µA
V
VOUT= 0 V to 4 V
–2
µA
/PUPIN pin
"H" input voltage
/PUPIN pin
"L" input voltage
/PUPIN pin
"H" input current
/PUPIN pin
VIHP
VILP
IIHP
—
—
0.8×VDD
—
—
VDD
0.2×VDD
5
V
V
0
VIH = VDD
—
—
µA
µA
VDD=18 V
VIL = GND
IILP
–36
–18
–9
"L" input current
VDD=5 V to 42 V
Output load current
< 0.5 mA
VREG1
3.0
3.3
3.6
V
VREG pin output voltage
VDD=3.3 V to 5 V
Output load current <
100 µA
VREG2
3.0
3
3.3
6
3.6
12
V
Cell balancing switch
ON resistance
VDD=15 V to 42 V
VDS=0.6 V
RCB
Note 1: Applied to SCL and SDA pins.
Note 2: Applied to SDA, /SCDET, CELLOP, /ERR, /INTO pins.
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FEDL5204-02
ML5204
● Supply Current Characteristics
VDD = 3.3 to 42 V, GND = 0 V, Ta = -40 to +85 °C, no output load, /PUPIN = "H"
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Cell voltage/current
monitor output active
Ta=0 to +60 °C
Supply current during
operation 1
IDD1
—
14
50
µA
Cell voltage/current
monitor output inactive
Ta=0 to +60 °C
Supply current during
operation 2
IDD2
—
—
6
10
µA
µA
Current consumption during
powered-down
IDDS
—
0.1
1.0
● Code 001: Detection Threshold Characteristics (Ta = 25 °C)
VDD=18 V, GND=0 V, Ta=+25 °C
Item
Overvoltage detection
threshold
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
—
4.205
4.225
4.245
V
Overvoltage release
threshold
VOVR
VSOV
VUV
—
—
—
3.975
4.265
1.55
4.025
4.30
1.6
4.075
4.335
1.65
V
V
V
2nd overvoltage detection
threshold
Undervoltage detection
threshold
Undervoltage release
threshold
VUVR
VCNG
VOCU
—
—
—
2.925
0.95
110
3.000
1.00
120
3.075
1.05
130
V
V
0-V charge inhibit threshold
Discharge overcurrent
detection threshold
Charge overcurrent
detection threshold
Short-circuit detection
threshold
mV
VOCO
VSC
—
—
-50
190
2.5
-40
200
5
-30
210
7.5
mV
mV
mV
Wake-up detection
threshold
When current monitoring
is stopped
VWK
6/36
FEDL5204-02
ML5204
● Code 001: Detection Threshold Characteristics (Ta = 0 to 60 °C)
VDD=18 V, GND=0 V, Ta=0 °C to +60 °C
Item
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
Overvoltage detection
threshold
Ta=10 °C to 45 °C
4.200
4.225
4.250
V
Overvoltage release
threshold
VOVR
VSOV
VUV
—
—
—
3.955
4.25
1.5
4.025
4.30
1.6
4.095
4.35
1.7
V
V
V
2nd overvoltage detection
threshold
Undervoltage detection
threshold
Undervoltage release
threshold
VUVR
VCNG
VOCU
—
—
—
2.9
0.95
105
3.0
1.00
120
3.1
1.05
135
V
V
0-V charge inhibit threshold
Discharge overcurrent
detection threshold
Charge overcurrent
detection threshold
Short-circuit detection
threshold
mV
VOCO
VSC
—
—
-55
185
2
-40
200
5
-25
215
8
mV
mV
mV
Wake-up detection
threshold
When current monitoring
VWK
is stopped
VREG drop threshold
VREG recovery threshold
VUREG
VRREG
—
—
2.2
2.4
2.5
2.7
2.8
3.0
V
V
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ML5204
● Code 001: Detection/Release Delay Time Characteristics (Ta = 25 °C)
VDD=18 V, GND=0 V, Ta=+25 °C
Item
Symbol
tDET
Conditions
Min.
0.32
Typ.
0.40
Max.
0.48
Unit
sec
Cell voltage monitor cycle
Overvoltage detection delay
time (Note)
tOV
tOVR
tSOV
tUV
—
—
—
—
—
—
—
—
—
—
—
—
3.8
0.6
12.8
3.8
0.6
6.9
0.6
40
4.8
0.8
16
5.8
1.0
19.2
5.8
1.0
9.5
1.0
60
sec
sec
sec
sec
sec
sec
sec
ms
ms
ms
ms
µs
Overvoltage release delay time
(Note)
2nd overvoltage detection
delay time (Note)
Undervoltage detection delay
time (Note)
4.8
0.8
8
Undervoltage release delay
time (Note)
tOVR
tCNG
tCNGR
tOCU
tOCUR
tOCO
tOCOR
tSC
0-V charge inhibit delay time
(Note)
0-V charge enable delay time
(Note)
0.8
50
Discharge overcurrent
detection delay time
Discharge overcurrent release
delay time
80
100
25
120
30
Charge overcurrent detection
delay time
20
Charge overcurrent release
delay time
80
100
100
120
180
Short-circuit detection delay
time
60
Short-circuit release delay time
Wake-up detection delay time
tSCR
tWK
—
—
80
100
2
120
2.6
ms
ms
1.6
(Note)
The actual detection delay time may include the time lag incorporated by the cell voltage monitor
cycle.
8/36
FEDL5204-02
ML5204
● Code 001: Detection/Release Delay Time Characteristics (Ta = 0 to 60 °C)
VDD=18 V, GND=0 V, Ta=0 to +60 °C
Item
Symbol
tDET
Conditions
Min.
0.3
Typ.
0.4
Max.
0.5
Unit
sec
Cell voltage monitor cycle
Overvoltage detection delay
time (Note)
tOV
tOVR
tSOV
tUV
—
—
—
—
—
—
—
—
—
—
—
—
3.6
0.6
12
4.8
0.8
16
6.0
1.0
20
sec
sec
sec
sec
sec
sec
sec
ms
ms
ms
ms
µs
Overvoltage release delay time
(Note)
2nd overvoltage detection
delay time (Note)
Undervoltage detection delay
time (Note)
3.6
0.6
6.6
0.6
37
4.8
0.8
8
6.0
1.0
9.8
1.0
63
Undervoltage release delay
time (Note)
tOVR
tCNG
tCNGR
tOCU
tOCUR
tOCO
tOCOR
tSC
0-V charge inhibit delay time
(Note)
0-V charge enable delay time
(Note)
0.8
50
Discharge overcurrent
detection delay time
Discharge overcurrent release
delay time
74
100
25
126
32
Charge overcurrent detection
delay time
18
Charge overcurrent release
delay time
74
100
100
126
200
Short-circuit detection delay
time
50
Short-circuit release delay time
Wake-up detection delay time
tSCR
tWK
—
—
74
100
2
126
2.8
ms
ms
1.4
(Note)
The actual detection delay time may include the time lag incorporated by the cell voltage monitor
cycle.
9/36
FEDL5204-02
ML5204
● Cell Voltage Monitor Output Characteristics (Ta = 0 to 60 °C)
VDD = 18 V, GND = 0 V, Ta = 0 to +60 °C, no VMON output load
Item
Symbol
VVMR
Conditions
Min.
0.1
Typ.
Max.
4.5
Unit
V
Cell voltage monitor range
—
—
When cell voltage
VCELO4
VCELO1
VECEL4
VECEL1
1.96
0.4
2.00
0.5
—
2.04
0.6
V
= 4 V
VMON output voltage
When cell voltage
V
= 1 V
When cell voltage
-25
-30
+25
+30
mV
mV
= 4 V
Cell voltage measurement
error (Note)
When cell voltage
—
= 1 V
VMON output current
VMON output disable period
VMON output enable period
VMON output stabilization time
IOVM
tINHVM
tENVM
tSVM
—
-100
40
—
50
+100
65
µA
ms
ms
ms
—
—
290
—
350
—
450
1
No output load
(Note)
Cell voltage is corrected in the following formula with the VGAIN and OFFSET register values:
Corrected cell voltage = VGAIN × [VMON output voltage] + OFFSET
SCL
Hi-Z
Hi-Z
VMON
State
0V
0V
tINHVM
tINHVM
tSVM
tSVM
tSVM
tENVM
VMON output enable period
Initial
state
VMON output
enable period
VMON output
disable period
(Internal cell voltage
measurement in
progress)
VMON output
disable period
(Internal cell voltage
measurement in
progress)
10/36
FEDL5204-02
ML5204
● Code 001: Current Monitor Output Characteristics (Ta = 0 to 60 °C)
VDD = 18 V, GND = 0 V, Ta = 0 to +60 °C, no IMON output load
Item
Symbol
VIMON0
Conditions
ISP-to-ISM voltage
difference = 0 V
GIM bit = "0"
Min.
Typ.
Max.
Unit
0.5
0.6
0.7
V
IMON output voltage
ISP-to-ISM voltage
difference = 0 V
GIM bit = "1"
VIMON1
0.4
0.6
0.8
V
GIM0
GIM1
GIM bit = "0"
11.4
22.8
12
24
12.6
25.2
V/V
V/V
IMON output gain
(Note)
GIM bit = "1"
GIM bit = "0"
Shunt resistor RIS = 0.5 m
GIM bit = "1"
Shunt resistor RIS = 0.5 m
—
RIM0
-365
—
+63
A
Current measurement
range
(Note)
RIM1
IOIM
-174
-100
—
—
+23
A
IMON output current
ISP and ISM pin input
current
+100
µA
ISP=ISM=0 V
OUT bit = "1"
IIS
0.25
0.46
0.8
µA
(Note)
GIM bit = "0"
tSIM0
tSIM1
GIM bit = "0"
—
—
—
—
1
3
ms
ms
IMON output
stabilization time
GIM bit = "1
(Note)
A shunt resistor is connected to the ISP and ISM pins via a 1 k resistor each.
SCL
0V
ISP-ISM
IMON
0V
0V
tSIM1
tSIM0
12-fold gain
OUT bit = "1"
GIM bit = "0"
24-fold gain
OUT bit = "1"
GIM bit = "1"
State
OUT bit = "0"
OUT bit = "0"
11/36
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ML5204
● I2C Compatible Serial Interface
VDD=3.3 to 42 V, GND=0 V, Ta=-40 to +85 °C
Item
Symbol
fSCL
Conditions
Min.
Typ.
Max.
400
Unit
kHz
SCL clock frequency
SCL hold time
—
—
—
tHD:STA
—
0.6
—
—
µs
(Start condition)
SCL "L" hold time
SCL "H" hold time
SDA hold time
SDA setup time
SDA setup time
(Stop condition)
Bus free time
tLOW
tHIGH
tHD:DAT
tSU:DAT
—
—
—
—
1.3
0.6
0
—
—
—
—
—
—
—
—
µs
µs
µs
µs
0.1
tSU:STO
tBUF
—
—
0.6
1.3
—
—
—
—
µs
µs
Start
Stop
condition
condition
SDA
SCL
tSU:DAT tHD:DAT tSU:STO tBUF
tLOW tHIGH
tHD:STA
● Power-up Timing
VDD=3.3 to 42 V, GND=0 V, Ta=-40 to +85 °C
Item
Symbol
Conditions
Min.
1
Typ.
Max.
Unit
ms
/PUPIN "L" pulse width
tPUP
—
—
—
/PUPIN
tPUP
VREG
VRREG
Hi-Z
Hi-Z
Hi-Z
VMON
0V
0V
tDET
tINHVM
I2C Communication enabled
State
Reset
Power down
12/36
FEDL5204-02
ML5204
■ Functional Description
● I2C Compatible Serial Interface
The ML5204 is equipped with an I2C compatible serial interface.
Configurations can be done by reading/writing corresponding addresses in the control register.
Address
Data
SCL
SDA
MSB
LSB
MSB
LSB
D2
A6
A4 A3
D5 D4 D3
D1
D0 ACK
A5
A2 A1
R/W ACK D7 D6
A0
Start
condition
Stop
condition
Set the RW bit to "0" for data write or "1" for data read.
● Control Register
The control register map is shown below.
Address
Register name
R/W
Default
Description
00H
01H
02H
03H
04H
05H
06H
07H
08H
NOOP
VMON
IMON
R/W
R/W
R/W
R/W
R/W
R
R
R
R
00H
00H
00H
00H
00H
00H
02H
—
No function is assigned.
Cell voltage monitor control
Current monitor control
Cell balancing switch control
Power-down/Wake-up control
Interrupt request flags
CBAL
POWER
INTREQ
ERROR
VGAIN
OFFSET
Error state flags
VMON output voltage gain
VMON output voltage offset
Detection delay time reduction for tests
CELLOP state control
—
09H
TEST
R/W
R/W
00H
00H
Reserved for IC production test
(Do not use)
Others
NOT_USE
13/36
FEDL5204-02
ML5204
1. NOOP Register (Adrs = 00H)
7
6
5
4
3
2
1
0
Bit
NO7
NO6
NO5
NO4
NO3
NO2
NO1
R/W
0
NO0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default
No function is assigned to the NOOP register. Read/write access to this register does not change the
LSI state. The written data can be read as it is.
2. VMON Register (Adrs = 01H)
7
6
5
4
3
2
1
0
Bit
—
—
—
—
—
CN2
CN1
CN0
R/W
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Default
The VMON register specifies the battery cell to monitor on the VMON pin.
The CN0, CN1, and CN2 bits select the battery cell.
CN2
CN1
CN0
Selected cell
None (default)
VMON output = Hi-Z
V1 cell (lowermost)
V2 cell
V3 cell
V4 cell
V5 cell (uppermost)
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
None
VMON output = Hi-Z
Data write to the VMON register during the VMON output disable period is ignored, thus the present
register value is kept.
Invalid write
Valid write
SCL
VMON
State
Hi-Z
Hi-Z
0V
0V
tINHVM
tINHVM
tENVM
VMON output
enable period
VMON output enable period
VMON output
disable period
(Internal cell
voltage
measurement
in progress)
VMON output
disable period
(Internal cell
voltage
measurement
in progress)
Initial state
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3. IMON Register (Adrs = 02H)
7
6
5
4
3
2
1
0
Bit
—
—
—
OUT
—
—
ZERO
R/W
0
GIM
R/W
R
0
R
0
R
0
R/W
0
R
0
R
0
R/W
0
Default
The IMON register specifies various conditions for pack current monitor output.
The GIM bit selects the voltage gain of the current amplifier.
GIM
0
1
Voltage gain GIM
12 times (default)
24 time
The ZERO bit selects input levels on the ISP and ISM pins to perform zero current compensation on
the current amplifier.
ZERO
ISP pin input level ISM pin input level
0
1
Pin input level
GND level
Pin input level
GND level
The OUT bit enables the current amplifier output on the IMON pin. The OUT bit should be set to "1"
when zero current compensation is performed as well.
OUT
0
1
IMON pin output level
0V(default)
Current amplifier output
Pack current is obtained as the voltage across the current sensing shunt resistor RIS, which is tied to the
ISP and ISM pins.
The voltage difference between the ISP and ISM pins is converted and centered to 0.6 V (typ), which
is asserted on the IMON pin. The IMON pin output voltage VIMON is given by the following formula
using the shunt resistance RIS and the pack current ISENSE
:
VIMON = (ISENSE × RIS)×GIM+0.6
The circuit configuration of the current amplifier is shown below.
ML5204
PACK(+)
GIM＝R2/(R1+1kΩ)
R2
1kΩ
1kΩ
ISM
ISP
R1
R1
ZERO
RIS
IMON
PACK(-)
R2
0.6V
VIMON = 0.6 V for zero current, VIMON > 0.6 V for discharge current, and VIMON < 0.6 V for charge
current.
When ZERO bit = "1", the ISM and ISP pins are fixed to the GND level inside the device so that the
input voltage difference of the current amplifier becomes zero. By using this IMON level as the
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reference for zero current, internal reference deviation from 0.6 V and offset of the current amplifier
can be corrected.
The charge/discharge overcurrent, short-circuit, wake-up detection characteristics are irrelevant to
IMON register values.
4. CBAL Register (Adrs = 03H)
7
6
5
4
3
2
1
0
Bit
—
—
—
—
—
SW2
SW1
SW0
R/W
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Default
The CBAL register controls cell balancing switches.
The SW0, SW1, and SW2 bits select the cell balancing switch to turn ON.
When changing switches, all switches should be turned OFF first, then select a new switch to turn ON.
SW2
SW1
SW0
Switched ON cell
All OFF (default)
V1 cell (lowermost)
V2 cell
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V3 cell
V4 cell
V5 cell
All OFF
During the VMON output disable period, all the cell balancing switches are autonomously turned OFF
regardless of the CBAL register setting. During the VMON output enable period, the cell balancing
switch specified with the CBAL register is turned ON. Data write to the CBAL register during the
VMON output disable period is ignored, thus the present register value is kept.
If a cell balancing switch is kept turned ON all the way along, it is autonomously turned OFF at the
beginning of the VMON output disable period. But if the time constant of the RC input filter is too
large, cell voltage recovery may be slow enough to create a false overvoltage or undervoltage
condition. It is thus recommended that RCELL and CCELL values are carefully selected so that the time
constant of the RC filter is 1.5 ms or shorter.
Invalid
write
Valid write
SCL
Hi-Z
Hi-Z
0V
0V
VMON
tINHVM
tENVM
tINHVM
VMON output enable period
VMON output
disable period
(Internal cell
voltage
measurement
in progress)
VMON output
enable period
VMON output
disable period
(Internal cell
voltage
measurement
in progress)
State Initial state
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5. POWER Register (Adrs = 04H)
7
6
5
4
3
2
1
0
Bit
PUPIN
—
—
PD
—
—
—
R
0
WKUP
R/W
R
0
R
0
R
0
R/W
0
R
0
R
0
R/W
0
Default
The POWER register specifies wake-up detection and power-down conditions.
The WKUP bit starts or stops the wake-up detection circuit. It is autonomously reset to “0” when a
wake-up condition is detected.
WKUP
Wake-up circuit operation
Inactive (default)
Active
0
1
The PD bit controls transition to the power-down state. In the power-down state, all circuit operations
are halted for reducing current consumption.
PD
Power-down control
None
0
(Default)
1
Transition to Power-down
The PUPIN bit indicates the /PUPIN pin input level.
PUPIN
/PUPIN pin input level
0
1
"H"
"L"
If the PD bit is set to "1" while the /PUPIN pin input level is "L", transition to the power-down state is
not enabled until the /PUPIN pin input level becomes "H". Therefore, make sure that the /PUPIN pin
level is “H” by reading the PUPIN bit before writing “1” to the PD bit.
Writing “0” to the PD bit during power-down does not power up the device. For power-up, assert the
"L" level on the /PUPIN pin.
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6. INTREQ Register (Adrs = 05H)
7
6
5
4
3
2
1
0
Bit
QWK
QSC
QOCC
QOCD
QSOV
QZV
QUV
R
QOV
R/W
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
0
The INTREQ register shows the existing interrupt requests to MCU. The INTREQ register is cleared
by reading it, and the /INTO output autonomously returns to “Hi-Z”.
Data write to the INTREQ register is ignored.
QUV
0
1
Undervoltage IRQ
None (default)
Present
QOV
0
1
Overvoltage IRQ
None (default)
Present
QSOV
2nd overvoltage IRQ
None (default)
Present
QZV
0
1
0-V charge inhibit IRQ
None (default)
Present
0
1
QOCC
Charge overcurrent IRQ
None (default)
Present
QOCD
Discharge overcurrent IRQ
None (default)
0
1
0
1
Present
QWK
0
1
Wake-up IRQ
None (default)
Present
QSC
0
1
Short-circuit IRQ
None (default)
Present
All bits are set to "1" when clock halt is detected.
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7. ERROR Register (Adrs = 06H)
7
6
5
4
3
2
1
0
Bit
CKER
SC
OCC
OCD
SOV
ZV
UV
R
OV
R/W
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
1
The ERROR register indicates present error states. If any one bit is set to "1", the "L" level is asserted
on the /ERR pin. Each bit is autonomously reset to "0" when corresponding error condition is resolved.
The /ERR pin output becomes “Hi-Z” when all the bits are "0". Data write to the ERROR register is
ignored.
UV
0
1
Undervoltage condition
Not detected
OV
0
1
Overvoltage condition
Not detected (default)
Detected
Detected (default)
SOV
0
1
2nd overvoltage condition
Not detected (default)
Detected
ZV
0
1
0-V charge inhibit condition
Not detected (default)
Detected
Discharge overcurrent
condition
Charge overcurrent
condition
OCD
OCC
0
1
Not detected (default)
Detected
0
1
Not detected (default)
Detected
CKER
Clock halt condition
Not detected (default)
Detected
SC
0
1
Short-circuit condition
Not detected (default)
Detected
0
1
The "L" level is asserted on the CELLOP pin at 2nd overvoltage condition.
CELLOP pin level
SOV
0
1
2nd overvoltage state
Not detected (default)
Detected
“Hi-Z”
"L"
The "L" level is asserted on the /SCDET pin at short-circuit condition.
/SCDET pin level
SC
0
1
Short-circuit state
Not detected (default)
Detected
“Hi-Z”
"L"
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8. VGAIN Register (Adrs = 07H)
7
6
5
4
3
2
1
0
Bit
—
VG6
VG5
VG4
VG3
VG2
VG1
R
VG0
R/W
R
R
R
R
R
R
R
Default
—
—
—
—
—
—
—
—
The VGAIN register specifies a calibrated gain value for VMON output.
Calibrated cell voltage is given by the following equation using an A/D converted value of analog
VMON output:
Cell voltage = VGAIN × [VMON output voltage] + OFFSET
, where VGAIN is a calibrated gain, and OFFSET is a deviation from zero voltage.
The following table shows the relationship between the VGAIN register value and the calibrated gain.
Register value
Register value
Calibrated Gain
Calibrated Gain
[Hex]
40
41
42
43
44
45
46
47
[Hex]
00
01
02
03
04
05
06
07
1.936
1.937
1.938
1.939
1.940
1.941
1.942
1.943
2.000
2.001
2.002
2.003
2.004
2.005
2.006
2.007
4F
50
5F
60
1.951
1.952
1.967
1.968
0F
10
1F
20
2.015
2.016
2.031
2.032
6F
70
1.983
1.984
2F
30
2.047
2.048
7F
1.999
3F
2.063
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9. OFFSET Register (Adrs = 08H)
7
6
5
4
3
2
1
0
Bit
OF7
OF6
OF5
OF4
OF3
OF2
OF1
R
OF0
R/W
R
R
R
R
R
R
R
Default
—
—
—
—
—
—
—
—
The OFFSET register specifies the voltage offset on the VMON output. Calibrated cell voltage is
given by the following equation using an A/D converted value of analog VMON output:
Cell voltage = VGAIN × [VMON output voltage] + OFFSET
, where VGAIN is a calibrated gain, and OFFSET is a deviation from zero voltage.
The following table shows the relationship between the VOFFSET register value and the offset value.
Register value [Hex]
Offset [mV]
+0
00
01
02
03
+1
+2
+3
7F
80
81
82
83
FD
FE
FF
+127
-128
-127
-126
-125
-3
-2
-1
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10. TEST Register (Adrs = 09H)
7
6
5
4
3
2
1
0
Bit
OPC
—
—
RCVD
SOVD
ZVD
UVD
R/W
0
OVD
R/W
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Default
The TEST register controls detection delay times. Production test time can be reduced significantly in
battery pack assembly.
The OVD bit selects overvoltage detection delay time.
OVD
0
1
Overvoltage detection delay time
4.8 second (default)
100 ms (internal timer used)
The UVD bit selects undervoltage detection delay time.
UVD
0
1
Undervoltage detection delay time
4.8 second (default)
100 ms (internal timer used)
The ZVD bit selects 0-V charge inhibit delay time.
ZVD
0
1
0-V charge inhibit delay time
16 second (default)
100 ms (internal timer used)
The SOVD bit selects 2nd overvoltage detection delay time.
SOVD 2nd overvoltage detection delay time
0
1
16 second (default)
100 ms (internal timer used)
The RCVD bit selects recovery delay time from the overvoltage, undervoltage and 0-V charge inhibit
states.
RCVD
Recovery delay time
0.8 second (default)
100 ms (internal timer used)
0
1
The OPC bit resets the 2nd overvoltage detection state. Writing data "1" to the OPC bit resets the SOV
bit of the ERROR register to "0", with resetting the CELLOP pin output to Hi-Z as well.
OPC
0
1
2nd overvoltage state reset
None (default)
Reset
(Note)
After writing data "1" to the OPC bit, it is autonomously restored to the ‘0’ level. You do
not have to write ‘0’ again.
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● Power-on/Power-off Sequence
Battery cells can be connected in any order, but the recommend sequence is connecting the GND and VDD
pins first, followed by Vn pins from the bottom to the top of the battery cell stack. When disconnecting cells
the opposite sequence is recommended, in which Vn pins are disconnected from the top to the bottom of the
cell stack, and then cut off VDD and GND. If this sequence is not observed, the Vn+1-to-Vn pin voltage
may exceed the absolute maximum rating, resulting in destruction of the device. This is also true in
performing evaluation or inspection with battery simulators, where the power-on/power-off sequence
should be observed so that the Vn+1-to-Vn pin voltage does not exceed the absolute maximum rating.
For surge protection, a 150 or higher external input resistor RCELL is recommended. Battery cells should
be stacked before connected to Vn pins. Never try to connect single battery cells one-by-one, because the
Vn+1-to-Vn pin voltage may exceed the absolute maximum rating.
There are no restrictions on the power supply voltage rise time at power-on and power-off, and power
supply voltage fall time at power-off.
● False Overvoltage Conditions at Power-up
Immediately after the power-on sequence, the ML5204 usually enters the normal state. But due to
chattering noise or other reasons at power-up, it may enter the power-down state. The power-down state is
cleared by asserting the "L" level on the /PUPIN pin.
During battery pack assembly, overvoltage or 2nd overvoltage condition may be detected if battery pack
assembly is not completed soon enough. After completing pack assembly, the overvoltage state is released
autonomously, while the 2nd overvoltage state needs to be reset by one of the following methods.
To reset the 2nd overvoltage state, you can either:
(1)Set the OPC bit of the TEST register to "1", and then the CELLOP pin is restored to Hi-Z.
(2)Set the PD bit of the POWER register to "1" to transition to the power-down state, and then assert “L”
on the /PUPIN pin to power up. This procedure resets the ML5204 so the CELLOP output is
restored to Hi-Z accordingly.
(3)Assert a voltage which is lower than the VREG drop detection threshold VUREG for 100 ms or longer
on the VREG pin. It resets the ML5204 and the CELLOP pin output is restored to Hi-Z.
● Cell Voltage Monitor Function
During battery pack assembly if VREG pin voltage reaches the VREG recovery threshold VRREG, cell
voltage monitoring is started at an interval tDET of 0.4 sec. Because the initial state of the device is the
undervoltage state by default, the UV bit of the ERROR register is "1", and "L" is asserted on the /ERR pin.
After battery pack assembly is completed, if all the cell voltages exceed the undervoltage release threshold
VUVR for longer than the undervoltage release delay time tUVR, the UV bit is set to "0" and the /ERR pin
level becomes Hi-Z, transitioning to the normal state.
VDD
VRREG
VREG
VUVR
Cell voltage
/ERR
tUVR
Hi-Z
tDET
0V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VMON
State
0V
0V
0V
Undervoltage state
Normal state
Reset
After VREG recovery if battery pack assembly is not completed within the corresponding detection delay
time, an overvoltage or 2nd overvoltage condition may be detected. In this case, the /INTO pin output
becomes "L" asserting an interrupt signal to the microcontroller. Confirm the interrupt requests by reading
the INTREQ register and control the device accordingly.
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1. Overvoltage Detection and Release
Overvoltage detection and release timing is shown in the following diagram.
INTREQ register reading
SCL
VOV
VOVR
Cell voltage
tDET + tOVR
tDET + tOV
Hi-Z
Hi-Z
Hi-Z
/INTO
/ERR
0V
Hi-Z
0V
Normal state
Overvoltage
state
Normal state
State
If one or more battery cell voltage exceeds the overvoltage detection threshold VOV for longer than the
overvoltage detection delay time tOV, the ML5204 enters the overvoltage state and the "L" level is asserted
on the /INTO pin to interrupt the microcontroller. By reading the INTREQ register, the microcontroller can
confirm the interrupt request, where the QOV bit "1" denotes overvoltage condition. The INTREQ register
is autonomously cleared after readout, and the /INTO pin level is set to Hi-Z. In parallel, the OV bit of the
ERROR register is set to "1", and the "L" level is asserted on the /ERR pin to notify the microcontroller of
the error.
If all the battery cell voltages fall below the overvoltage release voltage VOVR for longer than the
overvoltage release delay time tOVR, the ML5204 returns to the normal state. The /ERR pin level returns to
Hi-Z if no other errors are present. When returning to the normal state, no interrupt signal is asserted on the
/INTO pin.
2. Undervoltage Detection and Release
Undervoltage detection and release timing is shown in the following diagram.
INTREQ register reading
SCL
VUVR
VUV
Cell voltage
tDET + tUVR
tDET + tUV
Hi-Z
Hi-Z
Hi-Z
/INTO
/ERR
0V
Hi-Z
0V
Normal state
Normal state
Undervoltage
state
State
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ML5204
If one or more battery cell voltage falls below the undervoltage detection threshold VUV for longer the
undervoltage detection delay time tUV, the ML5204 enters the undervoltage state and the "L" level is
asserted on the /INTO pin to interrupt the microcontroller. By reading the INTREQ register, the
microcontroller can confirm the interrupt request, where the QUV bit "1" denotes undervoltage condition.
The INTREQ register is autonomously cleared after readout, and the /INTO pin level is set to Hi-Z. In
parallel, the UV bit of the ERROR register is set to "1", and the "L" level is asserted on the /ERR pin to
notify the microcontroller of the error.
If all the battery cell voltages exceed the undervoltage release threshold VUVR for longer than the
undervoltage release delay time tUVR, the ML5204 returns to the normal state. The /ERR pin level returns to
Hi-Z, if no other errors are present. When returning to the normal state, no interrupt signal is asserted on the
/INTO pin.
The ML5204 does not transition to the power-down state autonomously even if it detects an undervoltage
condition. To enter the power-down state, set the PD bit of the POWER register to "1". Refer to the
POWER register section for details.
3. 2nd Overvoltage Detection
2nd overvoltage detection timing is shown in the following diagram.
INTREQ register reading
SCL
VSOV
VOV
Cell voltage
tDET + tSOV
tDET + tOV
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
/INTO
/ERR
0V
0V
0V
CELLOP
0V
Normal state
State
Overvoltage state
2nd overvoltage state
If one or more battery cell voltage exceeds the 2nd overvoltage detection threshold VSOV for longer than the
2nd overvoltage detection delay time tSOV, the ML5204 enters the 2nd overvoltage state and the "L" level is
asserted on the CELLOP pin to notify the microcontroller of the 2nd overvoltage state. In parallel, the SOV
bit of the ERROR register is set to "1", and the "L" level is asserted on the /ERR pin. Also, the "L" level is
asserted on the /INTO pin as well. By reading the INTREQ register, the microcontroller can confirm the
interrupt requests, where the QSOV bit s "1" denotes 2nd overvoltage condition. The INTREQ register is
autonomously cleared after readout, and the /INTO pin level is set to Hi-Z.
If 2nd overvoltage is detected, a permanent failure is suspected where charge current cannot be turned off
due to C-FET breakdown, for example. Fuse the current path immediately to permanently disable the
battery pack.
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Even if all the battery cell voltages come back to the normal range, the 2nd overvoltage state is held. To
reset the 2nd overvoltage state, you can either:
(1)Set the OPC bit of the TEST register to "1", and the CELLOP output is restored to Hi-Z.
(2)Set the PD bit of the POWER register to "1" to transition to the power-down state, and then assert “L”
on the /PUPIN pin to power up. This procedure resets the ML5204 so the CELLOP output is
restored to Hi-Z accordingly.
(3)Assert a voltage which is lower than the VREG drop detection threshold VUREG for 100 ms or longer
on the VREG pin. It resets the ML5204 and the CELLOP pin output is restored to Hi-Z.
4. 0-V Charge Inhibit and Enable
0-V charge inhibit and enable timing is shown in the following diagram.
INTREQ register reading
SCL
VCNG
Cell voltage
tDET + tCNGR
tDET + tCNG
Hi-Z
0V
Hi-Z
/INTO
/ERR
0V
Undervoltage
state
Undervoltage
state
0-V charge inhibit
state
State
If one or more battery cell voltage falls below the 0-V charge inhibit threshold VCNG for longer than the 0-V
charge inhibit delay time tCNG, the ML5204 enters the 0-V charge inhibit state and the "L" level is asserted
on the /INTO pin to interrupt the microcontroller. By reading the INTREQ register, the microcontroller can
confirm the interrupt request, where the QZV bit "1" denotes 0-V charge inhibit condition. The INTREQ
register is autonomously cleared after readout, and the /INTO pin is set to Hi-Z. In parallel, the ZV bit of the
ERROR register is set to "1", and the "L" level is asserted on the /ERR pin to notify the microcontroller of the
error.
If all the battery cell voltages exceed the 0-V charge inhibit threshold VCNG for longer than the 0-V charge
enable delay time tCNGR, the 0-V charge inhibit state is released, and the ZV bit of the ERROR register is
reset to "0". Immediately after 0-V charge enable, the cell voltage is usually below the undervoltage
threshold, thus undervoltage condition is remaining and the /ERR level is still "L". If 0-V charge inhibit
condition is cleared, no interrupt signals are asserted on the /INTO pin.
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● Current Monitor Function
If the VREG pin voltage exceeds the VREG recovery threshold VRREG, overcurrent monitor is initiated after
a 6 ms stabilization time, where voltage difference between the ISP and ISM pins is analyzed for
overcurrent detection. Overcurrent monitor is always running except in the power-down state, the VREG
drop state and the stabilization time after the VREG recovery, regardless of the analog current monitor
configurations on the IMON register.
VDD
VRREG
VRREG
VREG
State
VUREG
Stabilization time
6 ms
Stabilization time
6 ms
Reset
Overcurrent
monitoring
Overcurrent
monitoring
Reset
1. Discharge Overcurrent Detection and Release
Discharge overcurrent detection and release timing is shown in the following diagram.
INTREQ register reading
SCL
VOCU
ISP-ISM voltage
difference
tOCU
tOCUR
Hi-Z
Hi-Z
Hi-Z
/INTO
/ERR
0V
Hi-Z
0V
Normal state
Normal state
Discharge
State
overcurrent state
When a load is connected to the battery pack, if the ISP-to-ISM voltage exceeds the discharge overcurrent
detection threshold VOCU for longer than the discharge overcurrent detection delay time tOCU, the ML5204
enters into the discharge overcurrent state and asserts the "L" level on the /INTO pin to interrupt the
microcontroller, regardless of cell voltage monitoring. By reading the INTREQ register, the microcontroller
can confirm the interrupt request, where the QOCU bit "1" denotes discharge overcurrent condition. The
INTREQ register is autonomously cleared after readout, and the /INTO pin level is set to Hi-Z. In parallel,
the OCU bit of the ERROR register is set to "1", and the "L" level is asserted on the /ERR pin to notify the
microcontroller of the error.
If the ISP-to-ISM pin voltage falls below the discharge overcurrent detection threshold VOCU for longer than
the discharge overcurrent release delay time tOCUR, the discharge overcurrent state is released, and the OCU
bit of the ERROR register is reset to "0". The /ERR pin returns to the Hi-Z state if no other errors are
present. When returning to the normal state, no interrupt signals are asserted on the /INTO pin.
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2. Charge Overcurrent Detection and Release
Charge overcurrent detection and release timing is shown in the following diagram.
INTREQ register reading
SCL
VOCO
ISP-ISM voltage
difference
tOCO
tOCOR
Hi-Z
Hi-Z
Hi-Z
/INTO
/ERR
0V
Hi-Z
0V
Normal state
Normal state
Charge
State
overcurrent state
When a charger is connected to the battery pack, if the ISP-to-ISM pin voltage exceeds the charge
overcurrent detection threshold VOCO for longer than the charge overcurrent detection delay time tOCO, the
ML5204 enters into the charge overcurrent state, and asserts the "L" level on the /INTO pin to interrupt the
microcontroller, regardless of cell voltage monitoring. By reading the INTREQ register, the microcontroller
can confirm the interrupt request, where the QOCO bit "1" denotes charge overcurrent condition. The
INTREQ register is autonomously cleared after readout, and the /INTO pin level is set to Hi-Z. In parallel,
the OCO bit of the ERROR register is set to "1", and the "L" level is asserted on the /ERR pin to notify the
microcontroller of the error.
If the ISP-to-ISM pin voltage falls below the charge overcurrent detection threshold VOCO for longer than
the charge overcurrent release delay time tOCOR, the charge overcurrent state is released, and the OCO bit of
the ERROR register is reset to "0". The /ERR pin returns to the Hi-Z state if no other errors are present.
When returning to the normal state, no interrupt signals are asserted on the /INTO pin.
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3. Short-Circuit Detection and Release
Short-circuit detection and release timing is shown in the following diagram.
INTREQ register reading
SCL
VSC
ISP-ISM voltage
difference
tSC
tSCR
Hi-Z
Hi-Z
/INTO
/ERR
0V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0V
/SCDET
0V
Normal state
Normal state
State
Short-circuit state
When a heavy load is connected to the battery pack, if the ISP-to-ISM pin voltage exceeds the short-circuit
detection threshold VSC for longer than the short-circuit detection delay time tSC, the ML5204 enters the
short-circuit state and asserts the "L" level on the /SCDET pin to interrupt the microcontroller, regardless of
cell voltage monitoring. By reading the INTREQ register, the microcontroller can confirm the interrupt
request, where the QSC bit "1" denotes short-circuit condition. The INTREQ register is autonomously
cleared after readout, and the /INTO pin level is set to Hi-Z. In parallel, the SC bit of the ERROR register is
set to "1", and the "L" level is asserted on the /ERR pin. Also, the "L" level is asserted on the /INTO pin.
If the ISP-to-ISM pin voltage falls below the short-circuit detection threshold VSC for longer than the
short-circuit release delay time tSCR, the short-circuit state is released, and the SC bit of the ERROR register
is reset to "0". The /ERR pin returns to the Hi-Z state if no other errors are present. When returning to the
normal state, no interrupt signals are asserted on the /INTO pin.
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● Wake-up Detection
If the VREG pin voltage reaches the VREG recovery threshold VRREG, wake-up detection is available after
a 6ms stabilization time, where voltage difference between the ISP and ISM pins is analyzed for wake-up
detection. Wake-up detection is controlled by the WKUP bit of the POWER register. Refer to the POWER
register section for details.
INTREQ register reading
SCL
VWK
ISP-ISM voltage
difference
tWK
Hi-Z
Hi-Z
Hi-Z
/INTO
/ERR
0V
Idle state
Discharge current
detection state
State
When wake-up detection is enabled, if a load is connected and the ISP-to-ISM pin voltage exceeds the
wake-up detection threshold for longer than the wake-up detection delay time tWK, the "L" level is asserted
on the /INTO pin to interrupt the microcontroller. By reading the INTREQ register, the microcontroller can
confirm the interrupt request, where the QWKUP bit "1" denotes wake-up condition and presence of
discharge current. The INTREQ register is autonomously cleared by readout, and the /INTO pin level is
restored to Hi-Z. Wake-up detection does not change the /ERR pin or the ERROR register state.
● VREG Drop Detection
If the VREG pin voltage falls below VREG drop threshold VUREG, ML5204 internal state is initialized, in
which the UV bit of the ERROR register is set to “1”, and the "L" level is asserted on the /ERR pin. At this
time, the /INTO pin output level is Hi-Z and no interrupt signals are asserted.
If the VREG voltage exceeds the VREG recovery threshold VRREG, individual cell voltage monitoring is
started. If all the battery cell voltages exceed the undervoltage release threshold VUVR for longer than the
undervoltage release delay time tUVR, the UV bit is reset to "0", making the /ERR pin level Hi-Z.
VRREG
VREG
/ERR
VUREG
tUVR
Hi-Z
0V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VMON
State
0V
0V
Undervoltage state
0V
Normal state
Normal state
Reset
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● Handling VDD Pin and V0 to V5 Pins
Since the VDD pin is power supply input, a noise elimination RC filter is recommended for stability.
The V0 to V5 pins are cell voltage sense inputs. Connect each battery cell via a noise elimination RC filter
to prevent false alarms. For surge protection, 150 or larger value is recommended for the external
resistance RCELL
.
● Handling VREG Pin
The VREG pin outputs internally regulated power, which is also used for internal circuits. Connect a 1 µF
or larger capacitor between this pin and GND for stability. Do not source power to external circuits since
supply capacity of the internal regulator is limited.
● Unused Pins Treatment
The following table shows how to handle unused pins.
Unused pins
V0
Recommended treatment
Connected to GND
ISM, ISP
VMON
Connected to GND
Open
IMON
Open
SCL, SDA
/SCDET
CELLOP
/INTO
Connected to VREG
Open
Open
Open
/ERR
Open
/PUPIN
VREG
Connected to GND through a 0.1 μF or larger capacitor
Connected to GND through a 1 μF or larger capacitor
● Supported Cell Counts
Supported serial cell count is 4 or 5.
In a 4-cell system, the V0 input pin should not be used and should be tied to GND.
● Redefinition of Detection Thresholds
Detection thresholds are selectable and can be redefined in the range and step shown in the following
table. Some combinations may not be available due to conflicts.
Detection threshold
Overvoltage detection
threshold
Settable range
3.65 V to 4.35 V
3.5 V to 4.25 V
3.65 V to 4.35 V
Step voltage
25 mV
Overvoltage release threshold
2nd overvoltage detection
threshold
25 mV
25 mV
Undervoltage detection
threshold
1.6 V to 3 V
100 mV
Undervoltage release threshold
0-V charge inhibit threshold
Discharge overcurrent
threshold
Charge overcurrent threshold
Short-circuit detection
threshold (Note 1)
2.3 V to 3.6 V
0.1 V to 1.2 V
100 mV
50 mV
50 mV to 200 mV
-60 mV to -20 mV
100 mV to 500 mV
5 mV to 10 mV
10 mV
10 mV
10 mV
2.5 mV
Wake-up detection threshold
(Note 1) Detection accuracy is aggravated twice for a threshold value exceeding 200 mV.
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● Redefinition of Detection Delays
Detection delay times are selectable and can be redefined in the range shown below.
Detection delay time
Configurable time
Unit
Overvoltage detection
delay time
Overvoltage release delay
time
2nd overvoltage detection
delay time
Undervoltage detection
delay time
Undervoltage release
delay time
0-V charge inhibit delay
time
0-V charge enable delay
time
Discharge overcurrent
detection delay time
Discharge overcurrent
release delay time
Charge overcurrent
detection delay time
Charge overcurrent
release delay time
Short-circuit detection
delay time
1.6
0.4
6.4
1.6
0.4
1.6
0.4
12.5
25
3.2
0.8
11.2
3.2
0.8
3.2
0.8
25
4.8
6.4
―
8
―
9.6
―
11.2
―
sec
sec
sec
sec
sec
sec
sec
ms
ms
ms
ms
μs
1.6
12.8
4.8
1.6
4.8
1.6
50
14.4
6.4
―
16
8
17.6
9.6
―
19.2
11.2
―
―
6.4
―
8
9.6
―
11.2
―
―
100
200
100
200
800
200
16
200
―
―
―
50
100
50
―
―
12.5
25
25
200
―
50
100
400
100
8
―
―
―
―
―
―
―
―
100
25
200
50
―
Short-circuit release delay
time
Wake-up detection delay
time
―
ms
ms
2
4
―
● Redefinition of Current Amplifier Gain/IMON Level at Zero Current
Current amplifier gain and IMON Level at zero current are selectable and can be redefined in the range
shown below. Some combinations may not be available due to conflicts.
Item
Configurable value
Unit
Factor
Factor
V
Gain (GIM = 0)
Gain (GIM = 1)
IMON level at zero current
8
10
20
0.5
12
24
0.6
14
28
0.7
16
32
0.8
16
0.4
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■ Application Circuit Example
Pack(+)
3.3V
RVDD
1
20
19
18
17
VDD
VREG
SCL
RI2C
CREG
RCELL
CVDD
VDD
2
V5
SCL
SDA
CCELL
3
V4
SDA
/INT_in
/INT_in
4
V3
/INTO
5 V2
/ERR 16
CDET 15
CELLOP 14
VMON 13
/INT_in
/INT_in
6
7
V1
V0
8 GND
9 /PUPIN
10 ISM
AD_in
AD_in
IMON
ISP
12
11
CPUP
PWR_up
RDWN
GND
CIS
RIS
RISIN
RISIN
Pack(-)
■ Recommended Values for External Components
Component Recommended value
Component
Recommended value
0.5 m
RVDD
CVDD
RCEL
CCEL
CREG
CPUP
RIS
RISIN
CIS
RI2C
510
2.2 µF or larger
150 to 10 k
0.1 µF or larger
1 µF
1 k
10 nF
5.1 k to 47 k
100 k
RDWN
0.1 µF
(Note 1) When cell balancing is performed, false overvoltage and/or undervoltage conditions may be detected
if the time constant of RC input filter is too large. It is thus recommended that RCELL and CCELL are
carefully selected so that the time constant is 1.5 ms or shorter.
(Note 2) Example of application circuit and the recommended values to parts list shall not guarantee
performance under all conditions. Full and detailed tests are suggested on your actual application.
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■ Package Dimensions
Caution regarding surface mount type packages
Surface mount type packages are susceptible to applied heat in solder reflow or moisture absorption during
storage. Please contact your local ROHM sales representative for the recommended mounting conditions (reflow
sequence, temperature and cycles) and storage environment.
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■ Revision History
Page
Before
Document No.
Issue date
Revision description
After
revision
revision
FEDL5204-01
FEDL5204-02
30 Oct, 2017
1 Dec, 2020
-
-
-
-
Initial release
Changed Company name
36
36
Changed “Notes”
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Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating
conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products
outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within
such usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.
Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of
LAPIS Technology Products, please take safety at your own risk measures such as complying with the derating
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe
procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate
the standard operation of semiconductor products and application examples. You are fully responsible for the
incorporation or any other use of the circuits, software, and information in the design of your product or system.
And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS
Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising
from the use of these circuits, software, and other related information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of
LAPIS Technology or any third party with respect to LAPIS Technology Products or the information contained
in this document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and
application examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any
dispute, concerning such rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer
systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our
Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a
LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,
trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical
systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all
liability for any losses and damages incurred by you or third parties arising by using the Product for purposes
not intended by us. Do not use our Products in applications requiring extremely high reliability, such as
aerospace equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this
document. However, LAPIS Technology does not warrant that such information is error-free and LAPIS
Technology shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the
RoHS Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting
non-compliance with any applicable laws or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide
by the procedures and provisions stipulated in all applicable export laws and regulations, including without
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this
document or LAPIS Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2020 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
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