ML5205 [ROHM]
支持3～5节电池、具有电池电压和断线检测、电池连接节数识别功能的电池监控保护LSI电池电压检测断线检测电池连接节数识别功能省时测试模式;
| 型号： | ML5205 |
| 厂家： | 
ROHM |
| 描述： | 支持3～5节电池、具有电池电压和断线检测、电池连接节数识别功能的电池监控保护LSI电池电压检测断线检测电池连接节数识别功能省时测试模式 电池 监控 测试 |
| 文件： | 总13页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL5205-02
27. Sep., 2021
ML5205
5 seris cell Li-ion Rechargeable Battery Protection IC
■ General Description
The ML5205 is a protection IC for the 3- to 5-cell Li-ion rechargeable battery pack. It detects individual
cell overvoltage and battery cell open-wire, and alerts by alarm output signal.
■ Features
• 3 to 5 cell high precision overvoltage detection function
Overvoltage detection threshold : 4.0V to 4.4V(5mV step), accuracy:±25mV (0 °C to 60 °C)
Overvoltage release threshold
: 3.8V to 4.2V(10mV step), accuracy:±50mV (0 °C to 60 °C)
Overvoltage detection delay time : 0 sec to 5.6 sec(typ)
• Open-wire detection function
Open-wire detection threshold
: 0.6V(typ)
Open-wire detection sink current : ±0.8µA(typ)
Open-wire detection delay time
: 0 sec to 5.6 sec(typ)
• Three types of alarm output
Selected from CMOS / Nch open drain / Pch open drain
• Number of connected battery cells detection function
By connecting batteries in order from the top and unused pins are connected to VDD, number of
connected cells (3 to 5 cells) is automatically detected.
• Low current consumption
• Power supply voltage
: 3A(typ), 5A(max) (0℃ to 60℃)
: +5V to +25V
• Operating temperature
• Package
: -20℃ to +85℃
: 8 pin VSSOP
FEDL5205-02
ML5205
■ Block Diagram
VDD
V5
V4
Reset
Clock
Generator
Generator
V3
V2
Cell
Voltage
detector
Reference
Generator
Control
Logic
/ALARM
Number
of cells
detector
V1
GND
■ Pin Configuration (top view)
8
1
2
/ALARM
VDD
V5
7
6
5
GND
V1
V4
V3
3
4
V2
2/13
FEDL5205-02
ML5205
■ Pin Description
Pin No
Pin
I/O
Description
Power supply input pin
Battery cell 5 high voltage input pin
1
2
3
4
VDD
V5
―
I
I
I
V4
Battery cell 5 low voltage input pin and Battery cell 4 high voltage input pin
Battery cell 4 low voltage input pin and Battery cell 3 high voltage input pin
Battery cell 3 low voltage input pin and Battery cell 2 high voltage input pin
Should be connected to positive terminal of the highest battery cell for the 3 cell
series connected battery pack application
V3
5
V2
I
Battery cell 2 low voltage input pin and Battery cell 1 high voltage input pin
Should be connected to positive terminal of the highest battery cell for the 3 or 4
cell series connected battery pack application
6
7
V1
I
GND
―
Ground pin
Alarm signal output pin.
・If CMOS output : Output level is “L“ level(GND level) if overvoltage/
open-wire is detected, else “H“ level (VDD power supply level). The reverse
is selectable.
・If Nch open drain output : Output level is “L“ level(GND level) if
overvoltage/ open-wire is detected, else “Hi-Z“ level. The reverse is
selectable.
8
/ALARM
O
・If Pch open drain output： Output level is “H“level (VDD power supply level)
if overvoltage/open-wire is detected, else “Hi-Z“ level. The reverse is
selectable.
■ Absolute Maximum Ratings
（GND= 0 V, Ta = 25 ℃）
Item
Symbol
VDD
Condition
Applied to VDD pin
Rating
Unit
V
Supply Voltage
Input Voltage
－0.3 to +32
VIN
Applied to V5 to V1 pins
Applied to /ALARM pin（CMOS, Pch
open drain）
－0.3 to VDD＋0.3
V
VOUT1
VOUT2
－0.3 to VDD＋0.3
－0.3 to +32
V
V
Output Voltage
Applied to /ALARM pin（Nch open
drain）
Short-circuit
output current
Power dissipation
Storage
IOS
PD
Applied to /ALARM pin
10
730
mA
mW
℃
—
—
TSTG
-55 to +150
temperature
■ Recommended Operating Conditions
（GND= 0 V）
Item
Symbol
VDD
Condition
Range
5 to 25
Unit
V
Supply Voltage
—
—
Operating temperature
TOP
－20 to +85
℃
3/13
FEDL5205-02
ML5205
■ Electrical Characteristics
● DC Characteristics
VDD=5 to 25V，GND=0 V，Ta=-20 to +85℃
Item
Symbol
IVC12
Condition
Each cell voltage=
3.6V
Min.
Typ.
Max.
Unit
V1, V2 pins input current
－1.0
－0.8
－0.6
µA
Ta=25℃
Each cell voltage=
3.6V
V3, V4 pins input current
IVC34
0.6
0.8
1.0
µA
Ta=25℃
V5 pin input current
/ALARM pin
“H” output voltage
/ALARM pin
“L” output voltage
/ALARM pin
output leakage current
IVC5
Cell voltage= 3.6V
-0.3
―
―
0.3
µA
V
VOHA
IOH= -100A
V
DD－0.2
VDD
IOL=500A
VDD=8 to 25V
VOLA
IOLKA
VIH
0
－2
―
―
―
―
0.5
2
V
A
V
Output state is Hi-Z
3cell, 4cell
configuration
4cell, 5cell
V1,V2 pin “H” input voltage
V
DD－0.3
0
VDD
V1,V2 pin “L” input voltage
VIL
V
DD－3
V
configuration
● Supply Current Characteristics
VDD=5 to 25V，GND=0 V，Ta=-20 to +85℃
Item
Symbol
IDD
Condition
Each cell voltage=3.6V
No output load
Min.
Typ.
Max.
Unit
―
3
5
µA
Ta=0 to 60℃
Current consumption in
normal operation
Each cell voltage=3.6V
No output load
IDDT
―
3
7
µA
Ta=‐20 to 85℃
(Note) VDD pin current consumption. V5 to V1 pin input current and /ALARM pin output current is not
included.
4/13
FEDL5205-02
ML5205
● Detection Threshold Characteristics (Ta=0 to 60℃)
VDD=18V，GND=0 V，Ta=0 to 60℃
Item
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
Overvoltage detection
threshold
―
VOV-25m
VOV
VOV+25m
V
Overvoltage release
threshold
VOVR
VOW
―
―
VOVR-50m
0.5
VOVR
0.6
VOVR+50m
0.7
V
V
Open-wire detection /
release threshold
Quick test mode
transition VDD-V5 pin
voltage difference
Quick test mode release
VDD-V5 pin voltage
difference
VTSTT
Ta=25℃
Ta=25℃
10
0
―
―
―
V
V
VTSTR
3
● Detection delay time Characteristics (Ta=0 to 60℃)
VDD=18V，GND=0 V，Ta=0 to 60℃
Item
Symbol
tDET
Condition
Min.
300
Typ.
Max.
単位
Cell voltage monitoring
cycle
―
400
500
ms
Overvoltage detection
delay time setting range
Open-wire detection /
release delay time
Quick test mode cell
voltage monitoring cycle
Quick test mode
Defined with
detection cycle
Defined with
tOV
tOW
0
0
―
―
14
14
Cycle
Cycle
ms
detection cycle
tDETT
Ta=25℃
75
100
125
overvoltage detection
delay time,
Open-wire detection /
release delay time
Defined with
detection cycle time.
tDOVW
―
―
1
Cycle
● Code 001: Setting Parameters
VDD=18V, GND=0V, Ta=0 to 60℃
Items
Symbols
VOV
Condition
Min.
Typ.
Max.
Unit
Overvoltage detection
threshold
―
4.175
4.200
4.225
V
Overvoltage release
threshold
VOVR
tOV
―
4.10
2
4.15
―
4.20
3
V
Overvoltage detection
delay time
Defined with
detection cycle
Defined with
cycle
cycle
Open-wire detection /
release delay time
tOW
2
―
3
detection cycle
5/13
FEDL5205-02
ML5205
■ Functional Description
● Selecting the number of battery cells
By connecting batteries in order from the top and unused pins are connected to VDD, number of
connected cells (3 to 5 cells) is automatically detected.
Connected
V5 pin
V4 pin
V3 pin
V2 pin
V1 pin
cells
3 cells
4 cells
5 cells
Cell
Cell
Cell
Cell
Cell
Cell
Cell
Cell
Cell
VDD
Cell
Cell
VDD
VDD
Cell
● /ALARM output pin
/ALARM pin output status for overvoltage/open-wire detected state.
/ALARM pin output
Nch open drain
CMOS
Pch open drain
(code 001)
Overvoltage/open-wire
“L” level
“H” level
“L” level
“Hi-Z”
“H” level
“Hi-Z”
detected state
Undetected state
(Note) The /ALARM pin output for detected state and undetected state is selectable the reverse.
● Handling VDD pin and V1 to V5 pins
Since the VDD pin is the power supply input, put a noise elimination RC filter in front of the VDD
input for stabilization. The resistor value of this noise filter should be adjusted so that the voltage drop
across the resistor is smaller than 0.3 V.
The V1 to V5 pins are the monitor pins for individual cell voltages. Put a noise elimination RC filter
in front of each battery cell to prevent false detection.
● Power-on / Power-off sequence
Battery cells can be connected in any order, but it is recommend that the lowest voltage cell is
connected first, and then connection continues from lower to higher voltage cells, and the highest
voltage cell is connected last. There are no restrictions on the power supply voltage rise time at
power-on, and power-off sequence or power supply voltage fall time at power-off.
It may transition to the open-wire detection or overvoltage detection state if it takes long time to
connect all cells.
6/13
FEDL5205-02
ML5205
● Overvoltage detection function (if the overvoltage detection delay time =5 detection
cycles)
After power-on, voltage monitoring is started with cycle of cell voltage monitoring cycle tDET 400ms(typ) .
When any one or more battery cell voltages reach or exceed the overvoltage detection threshold VOV for
series six times, it detects overvoltage state. And in case of CMOS output, /ALARM pin output changes
from “H” level to “L” level.
If the state in which cell voltage of all cell is lower than overvoltage detection threshold VOV is detected
only one time, detection delay time counting is not initialized, but if detected for series two times, detection
delay time counting is initialized.
After the overvoltage detection, if the cell voltage of all cell is lower than overvoltage release threshold
VOVR , and in case of CMOS output, /ALARM pin output changes from “L” level to “H” level.
VOV
Cell monitor pin voltage
VOVR
difference (Vn+1-Vn)
tDET tDET tDET tDET tDET tDET tDET
tDET tDET tDET tDET tDET
tDET
③
④
①
②
⑤
⑥
tOV
VDD
VDD
/ALARM
Status
0V
Detection delay
counting
Overvoltage is
detected
Overvoltage is not
detected
Overvoltage is
not detected
VOV
Cell monitor pin voltage
VOVR
difference (Vn+1-Vn)
tDET tDET tDET tDET
tDET tDET tDET tDET
tDET
tDET tDET tDET tDET
②
③
④
⑥
⑤
①
tOV
VDD
VDD
/ALARM
Status
0V
Detection delay
counting
Overvoltage is
detected
Overvoltage is not
detected
Overvoltage is
not detected
VOV
Cell monitor pin voltage
VOVR
difference (Vn+1-Vn)
tDET tDET tDET tDET tDET tDET tDET tDET tDET tDET tDET tDET tDET
⑤
①
②
③
④
⑥
①
tOV
VDD
VDD
/ALARM
Status
0V
Detection delay
counting
Overvoltage is not
detected
Overvoltage is
Detection delay
counting
Initialize Detection
delay counting
Overvoltage is
not detected
detected
7/13
FEDL5205-02
ML5205
● Open-wire detection function(if the open-wire detection delay time =8 detection cycles)
After power-on, voltage monitoring is started with cycle of cell voltage monitoring cycle tDET 400ms(typ).
When any one or more battery cell voltages reach or below the open-wire detection threshold VOW for
series nine times, it detects open-wire. And in case of CMOS output, /ALARM pin output changes from “H”
to “L” level
If the state in which cell voltage of all cell is higher than open-wire detection threshold VOW is detected
one time, detection delay counting is initialized.
After the open-wire detection, if the state in which cell voltage of all cell is higher than open-wire
detection threshold VOW is detected for series nine times, and in case of CMOS output, /ALARM pin output
changes from “L” level to “H” level. If the state in which cell voltage of one or more cell is lower than
open-wire detection threshold VOW for once, detection time counting is initialized.
Cell monitor pin voltage
VOW
difference (Vn+1-Vn)
tDET tDET
tDET
tDET
tDET tDET tDET
tDET tDET tDET
①
⑧
⑧
⑨
⑨
①
tOW
tOW
VDD
VDD
/ALARM
Status
0V
Open-wire is not
detected
Open-wire is
detected
Open-wire is not
detected
● Quick test mode
In the Quick test mode, overvoltage/open wire detection cycle time is set 100ms(typ), overvoltage
detection delay time and 0V battery detection delay time are set equal or shorter than one detection cycle.
If the voltage of VDD pin is more than 10V higher than V5 pin, the state change into this quick test mode.
For recovering from quick test mode to normal mode, set the voltage of VDD pin lower than “the voltage
of V5 + 3V”.
This test mode can decrease the test time after board mounting.
VDD
VTSTT
VTSTR
VDD
V5
V5
Status Monitoring state
Quick test mode
Monitoring state
8/13
FEDL5205-02
ML5205
● Definition of overvoltage detection/release threshold voltage range and step
The overvoltage detection/release thresholds can be defined as shown in the following table.
Since some combinations are unavailable, contact us for detail.
Detection threshold
Overvoltage detection threshold VOV
Overvoltage release
Setting range
4.0V to 4.4V
Step voltage
5mV
VOV – (0 to 200mV)
10mV
threshold VOVR
● Definition of overvoltage detection delay time and open-wire detection/release delay
time range
The overvoltage detection delay time and open-wire detection delay time can be defined as shown in the
following table.
Delay time
Settable time (detection cycle time)）
Unit
0
to
1
1
to
2
2
to
3
3
to
4
4
to
5
5
to
6
6
to
7
7
to
8
8
to
9
9
to
10 11 12 13
to to to to
Overvoltage detection
delay time
Cycle
10 11 12 13 14
Open-wire
detection/release
delay time
0
to
1
1
to
2
2
to
3
3
to
4
4
to
5
5
to
6
6
to
7
7
to
8
8
to
9
9
to
10 11 12 13
to to to to
Cycle
10 11 12 13 14
Delay time
Settable time(detection cycle =400ms)
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.0 3.6 4.0 4.4 4.8 5.2
to to to to to to to to to to to to to
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
Unit
sec
Overvoltage
detection delay
time
0
to
Open-wire
detection/release
delay time
0
to
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.0 3.6 4.0 4.4 4.8 5.2
to to to to to to to to to to to to to
sec
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
9/13
FEDL5205-02
ML5205
■ Application Circuit Example (3 cell system)
PACK(+)
RVDD
VDD
CVDD
V5
RCELL
RCELL
CCELL
CCELL
V4
V3
To Controller
/ALARM
RCELL
RCELL
RCELL
CCELL
CCELL
CCELL
V2
V1
GND
PACK(-)
PACK(+)
■ Application Circuit Example (4 cell system)
RVDD
VDD
CVDD
V5
RCELL
RCELL
CCELL
CCELL
V4
V3
To Controller
/ALARM
RCELL
RCELL
RCELL
CCELL
CCELL
CCELL
V2
V1
GND
PACK(-)
■ Recommended values for External Components
Recommended
Component
Value
RVDD
CVDD
RCELL
CCELL
1kΩ
4.7F
330Ω
0.22F
10/13
FEDL5205-02
ML5205
■ Package Dimensions
Caution regarding surface mount type packages
Surface mount type packages are susceptible to heat applied in solder reflow and moisture absorbed during
storage. Please contact your local ROHM sales representative for recommended mounting conditions (reflow
sequence, temperature and cycles) and storage environment
11/13
FEDL5205-02
ML5205
■ Revision History
Page
Before
Document No.
Issued date
Revision Description
After
revision
―
revision
―
FEDL5205-01
FEDL5205-02
2021.03.23
2021.07.27
Frist edition issued
Change Block Diagram
2
2
12/13
FEDL5205-02
ML5205
Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Semiconductor Products, refer to the latest product information (data sheets, user’s manuals,
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating
conditions, etc.) are within the ranges specified. LAPIS Semiconductor disclaims any and all liability for any
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Semiconductor Products outside
of such usage conditions specified ranges, or without observing precautions. Even if it is used within such usage
conditions specified ranges, semiconductors can break down and malfunction due to various factors. Therefore, in
order to prevent personal injury, fire or the other damage from break down or malfunction of LAPIS Semiconductor
Products, please take safety at your own risk measures such as complying with the derating characteristics,
implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. You are
responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the
standard operation of semiconductor products and application examples. You are fully responsible for the incorporation
or any other use of the circuits, software, and information in the design of your product or system. And the peripheral
conditions must be taken into account when designing circuits for mass production. LAPIS Semiconductor disclaims
any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits,
software, and other related information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS
Semiconductor or any third party with respect to LAPIS Semiconductor Products or the information contained in this
document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and application
examples、etc.). Therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning
such rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,
gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in
applications requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS
Semiconductor representative and must obtain written agreement: transportation equipment (cars, ships, trains, etc.),
primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers,
solar cells, and power transmission systems, etc. LAPIS semiconductor disclaims any and all liability for any losses
and damages incurred by you or third parties arising by using the Product for purposes not intended by us. Do not use
our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control
systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall
have no responsibility for any damages arising from any inaccuracy or misprint of such information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS
Directive. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with
any applicable laws or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or
LAPIS Semiconductor's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Semiconductor.
(Note) “LAPIS Semiconductor” as used in this document means LAPIS Semiconductor Co., Ltd.
Copyright 2021 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
13/13
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