ML5241 [ROHM]
电池电压检测断线检测警报输出睡眠功能省时测试模式;
| 型号： | ML5241 |
| 厂家： | 
ROHM |
| 描述： | 电池电压检测断线检测警报输出睡眠功能省时测试模式 电池 测试 |
| 文件： | 总14页 (文件大小：880K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL5241-02
1 December, 2020
ML5241
5 series Cell Li-ion Rechargeable Battery Protection IC
■ General Description
The ML5241 is a protection IC for the 3- to 5-cell Li-ion rechargeable battery pack. It detects individual
cell overvoltage and battery cell open-wire, and alerts by alarm output signal. And the ML5241 has a SLEEP
pin to reduce and minimize current consumption.
■ Features
• 3 to 5 cell high precision overvoltage detection function
Overvoltage detection threshold and detection accuracy : 4.225V±25mV (0 °C to 60 °C)
Overvoltage detection delay time
: 2 sec(typ)
• Open-wire detection function
Open-wire detection voltage
Open-wire detection sink current
Open-wire detection delay time
: 0.6V(typ)
: 100nA(typ)
: 3.2sec(typ)
• Sleep function
Set the SLEEP pin “H” and stop all functions for low power consumption.
• 3 types of alarm output
Selected from CMOS / Nch open drain / Pch open drain
• Setting number of connected battery cells : defined with part-number
5 cells = ML5241-001, 4 cells =ML5241-001A, 3 cells=ML5241-001B
• Low current consumption
Operating
: 1A(typ), 2A(max） (0°C to 60°C)
Sleep mode
: 0.1A(typ), 0.4A(max) (-20°C to 85°C)
• Power supply voltage
: +5V to +25V
• Operating temperature
• Package
: -20°C to +85°C
: 10 pin WSON
FEDL5241-02
ML5241
■ Block Diagram
VDD
V5
SLEEP
OV
detector
V4
V3
V2
V1
/ALARM
OW
detector
GND
■ Pin Configuration (top view)
N.C.
1
2
3
4
SLEEP
10
9
VDD
/ALARM
V5
V4
8 GND
7 V1
6 V2
V3 5
2/14
FEDL5241-02
ML5241
■ Pin Description
Pin No.
Pin
I/O
Description
Power supply input pin.
2
3
4
5
VDD
V5
―
I
I
I
Battery cell 5 high voltage input pin
V4
Battery cell 5 low voltage input and Battery cell 4 high voltage input pin.
V3
Battery cell 4 low voltage input and Battery cell 3 high voltage input pin.
Battery cell 3 low voltage input and Battery cell 2 high voltage input pin.
Should be connected to GND for the 3 cell series connected battery pack
application.
6
V2
I
Battery cell 2 low voltage input and Battery cell 1 high voltage input pin.
Should be connected to GND for the 3 or 4 cell series connected battery pack
application.
7
8
V1
I
Ground pin.
GND
―
Alarm signal output pin.
・If CMOS output : Output level is ”L” level(GND level) if overvoltage/
open-wire is detected, else ”H” level (VDD power supply level).
・If Nch open drain output : Output level is ”L” level(GND level) if overvoltage/
open-wire is detected, else ”Hi-Z” level.
9
/ALARM
O
・If Pch open drain output： Output level is ”H”level (VDD power supply level) if
overvoltage/open-wire is detected, else ”Hi-Z” level.
Sleep control input pin. For setting the sleep status, input Hi-Z level, else input
GND level. In sleep status, pulled-up with 500kΩ(typ) resisitor. In operating
status, pulled up with 0.1μA(typ) constant current.
10
1
SLEEP
N.C.
I
―
No connect. Leave them electrically unconnected.
■ Absolute Maximum Ratings
（GND= 0 V, Ta = 25 °C）
Item
Symbol
VDD
Condition
Applied to VDD pin
Rating
Unit
V
Supply Voltage
Input Voltage
Output Voltage
Short-circuit
output current
Power dissipation
Storage
－0.3 to +33
VIN
Applied to V5 to V1 and SLEEP pins
Applied to /ALARM pin
－0.3 to VDD+0.3
－0.3 to VDD+0.3
V
VOUT
V
IOS
PD
Applied to /ALARM pin
10
690
mA
mW
°C
—
—
TSTG
－55 to +150
temperature
■ Recommended Operating Conditions
（GND= 0 V）
Item
Supply Voltage
Operating temperature
Symbol
VDD
TOP
Condition
Range
5 to 25
-20 to +85
Unit
V
°C
—
—
3/14
FEDL5241-02
ML5241
■ Electrical Characteristics
● DC Characteristics
VDD=5 to 25V，GND=0 V，Ta=-20 to +85°C
Item
Symbol
Condition
Each cell voltage =
3.6V
Min.
Typ.
Max.
Unit
V5 to V1 pins
Input leakage current
IVCL
-1
―
1
A
SLEEP pin = “H”
/ALARM pin
“H” output voltage
/ALARM pin
“L” output voltage
/ALARM pin
IOHA
VOLA
IOLKA
VIH2
VIL2
IIH2
IOH = -100A
VDD-0.2
―
―
VDD
0.2
V
V
IOL = 100A
0
-2
Output state is Hi-Z
―
2
A
Output leakage current
SLEEP pin
―
0.8×VDD
0
—
VDD
"H" input voltage
SLEEP pin
"L" input voltage
SLEEP pin "H" input
current
―
VIH = VDD
—
0.2×VDD
2
—
—
µA
nA
SLEEP pin "L" input
current
IIL2
VDD = 18V, VIL = GND
―
–300
200
–100
500
–20
SLEEP pin
Pull-up resistor
RSLP
1000
kΩ
● Supply Current Characteristics
VDD=5 to 25V，GND=0 V，Ta=-20 to +85°C
Item
Symbol
IDD
Condition
Each cell voltage=3.6V
No output load
Min.
Typ.
Max.
Unit
―
1
2
µA
Ta=0 to 60°C
Current consumption
in normal operation
Each cell voltage=3.6V
No output load
IDDT
―
―
1
3
µA
µA
Ta=‐20 to 85°C
Each cell voltage=3.6V
No output load
Current consumption
in sleep mode
IDDS
0.1
0.4
Ta=‐20 to 85°C
(Note) VDD pin current consumption. V5 to V1 pin input current, /ALARM pin output current is not included.
4/14
FEDL5241-02
ML5241
● Code 001: Detection Threshold Chracteristics（Ta=0°C to 60°C）
VDD=18V，GND=0 V，Ta=0 to 60°C
Item
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
Overvoltage detection
threshold
―
4.200
4.225
4.250
V
Overvoltage release
threshold
VOVR
VOW
IOW
―
―
―
3.975
0.5
4.025
0.6
4.075
0.7
V
V
Open-wire detection /
release threshold
Open-wire detection sink
current
50
150
300
nA
Quick test mode
transition/release
VDD-V5 pin voltage
difference
VTST
Ta=25°C
3
―
10
V
● Code 001: Detection delay time characteristtics（Ta=0°C to 60°C）
VDD=18V，GND=0 V，Ta=0 to 60°C
Item
Symbol
tOV
Condition
Min.
300)
Typ.
Max.
Unit
Overvoltage/open-wire
detection cycle
Overvoltage detection
delay time
―
400
500
ms
Defined with
detection cycle
tDOV
5
8
―
―
6
9
cycle
cycle
Open-wire
detection/release delay
time
Defined with
detection cycle
tDOW
Quick test mode
Overvoltage/open-wire
detection cycle
Quick test mode
Overvoltage detection
delay time,
tOVW
Ta=25°C
75
100
125
1
ms
Defined with
detection cycle
tDOVW
―
―
time
open-wire
detection/release delay
time
5/14
FEDL5241-02
ML5241
■ Functional Description
● Selecting the number of battery cells
Number of battery cells is determined by part number.
5-cells=ML5241-001, 4-cells=ML5241-001A, 3-cells=ML5241-001B
● /ALARM output pin
/ALARM pin output status for overvoltage/open-wire detected state.
/ALARM pin output status
CMOS
Nch open drain
Code 001
Pch open drain
Overvoltage/open-wire
“L” level
“H” level
“L” level
“H” level
detected state
Undetected state
“Hi-Z” level
“Hi-Z” level
● Handling VDD pin and V1 to V5 pins
Since the VDD pin is the power supply input, put a noise elimination RC filter in front of the VDD input
for stabilization. The resistor value of this noise filter should be adjusted so that the voltage drop across the
resistor is smaller than 0.3 V.
The V1 to V5 pins are the monitor pins for individual cell voltages. Put a noise elimination RC filter in
front of each battery cell to prevent false detection.
● Unused pin Treatment
The followtin table shows how to handle unused pins
Unused pins
V1 , V2
Recommended treatment
Connected to GND pin
Connected to GND pin
SLEEP
● Power-on/Power-off sequence
Battery cells can be connected in any order, but it is recommend that the lowest voltage cell is connected
first, and then connection continues from lower to higher voltage cells, and the highest voltage cell is
connected last. There are no restrictions on the power supply voltage rise time at power-on, and power-off
sequence or power supply voltage fall time at power-off.
It may transition to the open-wire or overvoltage detection state if it takes long time to connect all cells.
6/14
FEDL5241-02
ML5241
● Overvoltage detection function
After power-on, overvoltage detection is started with cycle of 400ms(typ) (overvoltage detection cycle
tOV ). When any one or more battery cell voltages reach or exceed the overvoltage detection threshold VOV
for series six times, it detects overvoltage state. And if /ALARM pin output type is CMOS output,
/ALARM pin output changes from “H” level to “L” level.
If the state in which cell voltage of all cell is lower than overvoltage detection threshold VOV is detected
for series two times, detection delay time counting is initialized.
After the overvoltage detection, if the cell voltage of all cell is lower than overvoltage relase threshold
VOVR , and if /ALARM pin output type is CMOS output, /ALARM pin output changes from “L” level to “H”
level.
VOV
Cell monitor pin voltage
VOVR
difference (Vn+1-Vn)
tOV tOV tOV
tOV tOV tOV tOV
tOV tOV
tOV
tOV tOV tOV
③
⑤
⑥
①
②
④
tDOV
VDD
VDD
/ALARM
Status
0V
Detection delay
counting
Overvoltage is
detected
Overvoltage is not
detected
Overvoltage is
not detected
VOV
Cell monitor pin voltage
VOVR
difference (Vn+1-Vn)
tOV tOV tOV
tOV tOV tOV tOV
tOV tOV
tOV
tOV tOV tOV
③
tDOV
④
①
②
⑤
⑥
VDD
VDD
/ALARM
Status
0V
Detection delay
counting
Overvoltage is
detected
Overvoltage is not
detected
Overvoltage is
not detected
VOV
Cell monitor pin voltage
VOVR
difference (Vn+1-Vn)
tOV tOV tOV tOV tOV tOV
tOV tOV tOV tOV tOV tOV tOV
③
tDOV
④
①
②
⑤
⑥
①
VDD
VDD
/ALARM
Status
0V
Overvoltage is not
detected
Detection delay
counting
Overvoltage is
detected
Detection delay
counting
Initialize Detection
delay counting
Overvoltage is
not detected
7/14
FEDL5241-02
ML5241
● Open-wire detection function
After power-on, open-wire detection is started with cycle of 400ms(typ) (open-wire detection cycle tOW ).
When any one or more battery cell voltages reach or below the open-wire detection threshold VOW for series
nine times. It detects open-weire state. And if /ALARM output type is CMOS output, /ALARM pin output
changes from “H” level to “L” level.
If the state in which voltage of all cell is higher than open-wire detection threshold VOW is detected for
once, detection delay time counting is initialized.
After the open-wire detection, if the state in which cell voltage of all cell is higher than open-wire
detection threshold VOW is detected for series nine times, and if /ALARM output type is CMOS output,
/ALARM pin output changes from “L” level to “H” level.
If the state in which cell voltage of one or more cell is lower than open-wire detection threshold VOW is
detected for once, detection delay time counting is initialized.
Cell monitor pin voltage
VOW
difference (Vn+1-Vn)
tOW tOW
tDOW
tOW
tOW
tOW tOW tOW
tDOW
tOW tOW tOW
⑧
⑨
①
⑧
①
⑨
VDD
VDD
/ALARM
Status
0V
Open-wire is not
Open-wire is detected
detected
Open-wire is not
detected
● Sleep function
Set the SLEEP pin input “H” level and all function is stopped, and ML5241 is in the low power
consumtion sleep mode.
In the sleep mode, the SLEEP pin is pulled up with 500kΩ(typ) resistor and the /ALARM pin is in the
same state as overvoltage/open-wire detection shown below..
/ALARM pin outpout in sleep mode
CMOS
Nch open drain
Pch open drain
Code 001
“L” level
“L” level
“H” level
If the SLEEP pin is set ”L” level, the ML5241 powe-ups and its state changes from sleep mode to
normal operation, and overvoltage and open-wire detection are started. In the normal operation state, 500k
Ω(typ) pull-up resistor is disconnected and pulled up with 100nA(typ) current source.
8/14
FEDL5241-02
ML5241
● Quick test mode
In the Quick test mode, overvoltage/open-wire detection cycle time is set 100ms(typ), overvoltage
detectin delay time and openwire detection/release delay time are set equal or shorter than one detection
cycle.
If the voltage of VDD pin is more than 10V higher than V5 pin, the state change into this quick test mode.
For recovering from quick test mode to normal mode, set the voltage of VDD pin lower than “the voltage
of V5 + 3V”.
This test mode can decrease the test time after board mounting.
VDD
VDD
VTST
V5
V5
Status Monitoring state
Quick test mode
Monitoring state
9/14
FEDL5241-02
ML5241
● Redefinition of overvoltage Detection/Release threshold Range and Step
The overvoltage detection/release thresholds can be redefined as shown in the following table.
Since some combinations are unavailable, contact us for details
Detection voltage
Overvoltage detection voltage
Overvoltage release voltage
Setting range
4.0V to 4.4V
3.8V to 4.2V
Step voltage
25mV
25mV
● Redefinition of overvoltage Detection Delay time and open-wire Detection/Relase Delay
Time Range
The overvoltrage detection delay time and open-wire detection/release delay time can be redefined as
shown in the following table.
Delay time
Settable time (detection cycle time)
Unit
1
to
2
1
to
2
3
to
4
3
to
4
5
to
6
5
to
6
7
to
8
7
to
8
9
11
to
12
11
to
13
to
4
13
to
14
Overvoltage detection delay
time
to
10
9
To
10
cycle
Open-wire detection/release
cycle
delay time
12
Delay time
Settable time (detection cycle=400ms)
Unit
sec
0.4
to
1.2
to
2.0
to
2.8
to
3.6
to
4.4
to
5.2
to
5.6
5.2
to
Overvoltage detection delay
time
0.8
0.4
to
1.6
1.2
to
2.4
2.0
to
3.2
2.8
to
4.0
3.6
to
4.8
4.4
to
Open-wire detection/release
sec
delay time
0.8
1.6
2.4
3.2
4.0
4.8
5.6
10/14
FEDL5241-02
ML5241
■ Application Circuit Example (5-cell system)
PACK(+)
RVDD
VDD
CVDD
V5
SLEEP
RCELL
RCELL
RCELL
CCELL
V4
V3
CCELL
CCELL
From Controller
V2
V1
RCELL
RCELL
CCELL
CCELL
To Controller
/ALARM
GND
PACK(-)
■ Recommended values for External Components
Recommended
Component
Value
RVDD
CVDD
RCELL
CCELL
1kΩ
4.7F
1kΩ
0.1F
11/14
FEDL5241-02
ML5241
■ Package Dimensions
Caution regarding surface mount type packages
Surface mount type packages are susceptible to heat applied in solder reflow and moisture absorbed during
storage. Please contact your local ROHM sales representative for recommended mounting conditions (reflow
sequence, temperature and cycles) and storage environment.
12/14
FEDL5241-02
ML5241
■ Revision History
Page
Before
Document No.
Issue date
Revision Description
After
rvision
―
revision
FEDL5241-01
FEDL5241-02
2019.07.23
2020.12.01
―
―
14
Initial release.
―
Changed Company name
14
Changed “Notes”
13/14
FEDL5241-02
ML5241
Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating
conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products
outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within
such usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.
Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of
LAPIS Technology Products, please take safety at your own risk measures such as complying with the derating
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe
procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate
the standard operation of semiconductor products and application examples. You are fully responsible for the
incorporation or any other use of the circuits, software, and information in the design of your product or system.
And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS
Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising
from the use of these circuits, software, and other related information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of
LAPIS Technology or any third party with respect to LAPIS Technology Products or the information contained
in this document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and
application examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any
dispute, concerning such rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer
systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our
Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a
LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,
trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical
systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all
liability for any losses and damages incurred by you or third parties arising by using the Product for purposes
not intended by us. Do not use our Products in applications requiring extremely high reliability, such as
aerospace equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this
document. However, LAPIS Technology does not warrant that such information is error-free and LAPIS
Technology shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the
RoHS Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting
non-compliance with any applicable laws or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide
by the procedures and provisions stipulated in all applicable export laws and regulations, including without
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this
document or LAPIS Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2020 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
14/14
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