ML5810A [ROHM]

ML5810A是用于工业设备电池组充电/放电高边开关Nch功率MOSFET的栅极驱动器。另外，搭载Pch MOSFET驱动器，可在电池过放电时以低电流进行预充电。;


型号：	ML5810A
厂家：	ROHM
描述：	ML5810A是用于工业设备电池组充电/放电高边开关Nch功率MOSFET的栅极驱动器。另外，搭载Pch MOSFET驱动器，可在电池过放电时以低电流进行预充电。电池开关栅极驱动驱动器
文件：	总13页 (文件大小：562K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FEDL5810A-06

9, June. 2023

ML5810A

High-Side Switch Driver IC for Battery Pack

■General Description

ML5810A is charge/discharge high-side switch Nch power MOSFET gate driver for battery pack. ML5810A

assert external input reference voltage(CFS, DFS)+12V(typ) as the voltage for drive by charge pump. And also,

built-in PchMOSFET gate driver for low current precharge in battery over-discharge state.

■Features

•High-side switch Nch power MOSFET gate driver for battery pack protection

•Built-in Pch MOSFET gate driver for low current precharge/predischarge

•80V breakdown voltage applicable to 48V battery system

•Built-in charge pump

•Gate driver for charge/discharge ”H” output voltage

•Gate driver for precharge/predischarge ”L” output voltage

: Reference voltage(CFS, DFS)+10V (min)

: Reference voltage (PCFS)-9V (min)

• Current consumption

• Power supply voltage range

: 210uA(typ), 480uA(max)

+6.5V to +64V

(Absolute Maximum Rating: 80V)

• Operating temperature range

• Package

: -40℃ to +105℃

: 20pin TSSOP

• Application

: 12V to 48V Battery pack for industrial

eBikes, Energy Storage Systems (ESS) and

Uninterruptible Power Supplies (UPS)

Note) This product is not intended for automotive use and for any equipment, device, or system that requires a

specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace

machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether

your application corresponds to such special purposes, please contact your local ROHM sales

representative in advance.

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FEDL5810A-06

ML5810A

■Block Diagram

CPHD

CPLC

CPLD

CPHC

VDD

Charge Pump

VREG

OSC

PCFS

PCFETON

PC_FET

I/O

CFETON

DFETON

C_FET

CFS

D_FET

DFS

GND

2/13

FEDL5810A-06

ML5810A

■Pin Configuration(Top View)

VDD

CFS

C_FET

CPHC

CPLC

PCFS

DFETON

PCFETON

CFETON

TEST_N

PC_FET

CPLD

CPHD

D_FET

TEST1

TEST2

GND

VREG

DFS

3/13

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ML5810A

■Pin Description

Pin No.

I/O

Description

Power supply.

VDD

―

Connect an external CR filter for noise rejection.

―

DFETON

D_FET enable input.(pulldown resistance:1M)

PCFETON

CFETON

PC_FET enable input.(pulldown resistance:1M)

C_FET enable input.(pulldown resistance:1M)

TEST_N input.

TEST_N

TEST1

Should be fixed to VDD.

TEST1 input.(pulldown resistance:1M)

Should be fixed to GND.

TEST2 input.(pulldown resistance:1M)

Should be fixed to GND.

TEST2

GND

―

Ground.

Built-in 3.3V regurator output. Connect a 4.7F capacitor between this pin

and GND.

VREG

Reference voltage input for the D_FET drive charge pump. Connect to the

source pin of the discharge FET.

DFS

Discharge Nch-FET gate drive. Connect to the gate pin of the external

Nch-FET. In the ON state, the DFS level +12V (typ) is asserted.In the OFF

state DFS level is asserted.

D_FET

CPHD

CPLD

Charge pump capacitor input for D_FET drive. Connect a capacitor which

approximately 8-times of the discharge FET gate capacitance, between the

CPHD and CPLD pins.

Precharge/predischarge Pch-FET gate drive. Connected to the gate pin of

the external Pch-FET. In the ON state, the PCFS level -12V (typ) is asserted,

PC_FET

while the PCFS level is asserted in the OFF state.

Reference voltage input for the PC_FET drive charge pump. Connected to

the source pin of the precharge/predischarge FET.

PCFS

CPLC

CPHC

Charge pump capacitor input for C_FET drive. Connect a capacitor with

approximately twice the gate capacitance of the charge FET between the

CPHC and CPLC pins.

Charge Nch-FET gate drive. Connected to the gate pin of the external

Nch-FET. In the ON state, the CFS level +12V (typ) is asserted, while the

C_FET

CFS

CFS level is asserted in the OFF state.

Reference voltage input for the C_FET drive charge pump. Connected to the

source pin of the charge FET.

4/13

FEDL5810A-06

ML5810A

■Absolute Maximum Ratings

GND=0V, Ta=25°C

Unit

Parameter

Symbol

V_DD

Condition

Applied to VDD pin

Rating

Supply voltage

-0.3 to +86.5

Applied to CFS,DFS, and

PCFS pins

V_IN1

-0.3 to +86.5

-0.3 to VDD+0.3

V_DFS-0.5 to +86.5

Input voltage

Applied to CFETON,

DFETON,PCFETON,TEST1, and

TEST2,TEST_N pins

Applied to D_FET pin

V_DFS=DFS pin voltage

Applied to C_FET pin

V_CFS=CFS pin voltage

V_IN2

V_OUT1

Output voltage

V_OUT2

V_OUT3

I_OS1

V_CFS-0.5 to +86.5

-0.5 to +71.5

Applied to PC_FET pin

VDD=50V

Applied to VREG pin

VDD=50V

Applied to C_FET and D_FET pins

VDD=50V

Applied to PC_FET pin

Short circuit

output current

I_OS2

I_OS3

P_D

Power dissipation

Ta=25℃

2.3

33.7

Package thermal

resistance

θja

JEDEC double-side board mounted

℃/W

Storage

temperature

T_STG

—

-55 to +150

°C

5/13

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ML5810A

■Recommended Operating Conditions

（GND= 0 V）

Parameter

Symbol

V_DD

Condition

Applied to VDD pin

No VREG output load

Range

6.5～64

Unit

Power supply voltage

Operating temperature

－40～＋105

°C

■Electrical Characteristics

V_DD=6.5～64V,GND=0V,Ta=-40 to +105°C, no VREG output load

Parameter

Digital ”H” input

voltage(*1)

Symbol

Condition

Min.

Typ.

Max.

Unit

V_IH

V_IL

―

2.15

—

VDD+0.3

Digital ”L” input

voltage(*1)

―

—

―

0.35

130

—

µA

Digital ”H” input

current(*1)

I_IH

V_IH= VDD

V_IL= GND

—

-2

Digital ”L” input

current(*1)

I_IL

I_OH=-1.5µA

(V_DD*0.95)≧10V

V_OH11

V_OH12

V_OL21

V_OL22

C_FET / D_FET output

voltage( C_FET-CFS,

D_FET-DFS )

I_OH=-1.5µA

(V_DD*0.93)＜10V

V_DD*0.93

V_DD

I_OL=+1.5µA

(V_DD*0.8)≧9V

PC_FET output voltage

( PCFS-PC_FET )

I_OL=+1.5µA

(V_DD*0.8)＜9V

V_DD*0.8

V_DD

Ccp=80nF,

Rg=1k, Rfs=100,

FET gate capacitance=10nF

From FET-on to 80% of

output voltage V_OH11, V_OH12

Ccp=80nF,

Rg=1k, Rfs=100,

FET gate capacitance=10nF

From FET-off to 20% of

output voltage V_OH11, V_OH12

Ccp=80nF,

Rg=1k, Rfs=1k,

FET gate capacitance=1nF

From FET-on to 80% of

output voltage V_OL21, V_OL22

Ccp=80nF,

Rg=1k, Rfs=1k,

FET gate capacitance=1nF

From FET-off to 20% of

output voltage V_OL21, V_OL22

C_FET / D_FET

rise time

Tfetr1

Tfetf1

Tfetf2

Tfetr2

―

150

350

C_FET / D_FET

fall time

PC_FET

fall time

110

400

PC_FET

rise time

Current consumption in

operation

( charge and discharge ）

(*2)

CFETON=1 & DFETON=1 &

PCFETON=0

VDD=CFS=DFS=PCFS

IDD1

IDD2

―

210

135

480

380

Current consumption in

operation

( precharge or

predischarge ）(*2)

CFETON=0 & DFETON=0 &

PCFETON=1

VDD=CFS=DFS=PCFS

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ML5810A

V_DD=6.5V～64V

Output load current＜1mA

VREG output voltage

V_REG1

F_CPCD

F_CPPC

3.0

3.3

3.6

9.4

1.2

C_FET / D_FET

charge pump frequency

PC_FET

―

6.25

0.78

7.8125

0.9766

kHz

charge pump frequency

*1：Applied to CFETON,DFETON,PCFETON,TEST1,TEST2 and TEST_N pins

*2：Current consumption are sum of VDD,CFS,DFS, and PCFS currents

7/13

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ML5810A

■Functional Description

Operating state of ML5810A in each input status of 3 control input(PCFETON, DFETON, CFETON) is

indicated in the following table.

“Charge pump ON, FET stand-by” is in which a charge pump powers up and each FET gate voltage output

enable. The wait time is required at transition from power-up, and please refer to the “■ Timing diagram”

mentioned later for details.

”FET ON state” is the state in which each FET gate voltage is asserted by a relevant pin actually. Please

refer to “■ electrical characteristic” about rise and fall time of gate voltage.

Input

ML5810A

Operating status

PCFETON DFETON

CFETON

Charge pump ON, FET stand-by

FET ON

More than one is ”1”

C_FET and D_FET can be turn on at the same time, but PC_FET is exclusively other FETs and can’t be

turn on at the same time. A truth table of FET ON/OFF is following. As it's shown on the table, CFETON,

DFETON is priority more than PCFETON .

Input

Output

D_FET

OFF

PCFETON DFETON CFETON

PC_FET

OFF

C_FET

OFF

0 or 1

OFF

8/13

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ML5810A

■Timing diagram

C_FET / D_FET timing

VDD

6.5V

VREG

CFETON

DFETON

Twait（*）

CFS+12V（typ） or DFS+12V（typ）

80%

C_FET

D_FET

20%

CFS

Tfetf1

Tfetr1

DFS

PC_FET timing

VDD

6.5V

VREG

Twait（*）

PCFETON

PCFS

20%

PC_FET

80%

PCFS-12V（typ）

Tfetr2

Tfetf2

（*）Twait must be more than 50ms, when CFETON, DFETON, and PCFETON are set to H from L (0v).

9/13

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ML5810A

■Application Circuit Example

_RPC(*3)

PACK(+)

RVDD

CPHC

CPLC

VDD

CVDD

CCP

TEST_N

VREG

CPLD

CPHD

CREG

CCP

RFS2

PCFS

PCFETON

RG2

RFS1

RG1

PC_FET

CFETON

DFETON

TEST1

CFS

C_FET

D_FET

DFS

RG1

TEST2

RFS1

GND

PACK(-)

Recommended Values for External Components

Recommended

Component

value

R_VDD(*1)

C_VDD

C_REG

R_G1

510 to 1.5k

2.2F to 10F

4.7F

1k

R_FS1

R_G2

100

1k

R_FS2

R_GS

1k

10M

C_CP

82nF (*2)

(*1) Recommended R_VDD=1.5k for C_VDD=2.2F.

(*2) Set 80nF to 100nF, when gate capacitance of external Nch-FET is 10nF.

Set about 8-times of gate capacitance of external Nch-FET to C_CP.

(*3) Set R_PCaccording to current of Pch-FET.

Notice: Example of application circuit and the recommended values to parts list shall not guarantee

performance under all conditions. Full and detailed tests are suggested on your actual application.

10/13

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ML5810A

■ Package Dimensions

Causion regarding surface mount type packages

Surface mount type packages are susceptible to applied heat in solder reflow or moisture absorption during

storage. Please contact your local ROHM sales representative for the recommended mounting conditions (reflow

sequence, temperature and cycles) and storage environment.

11/13

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ML5810A

■ Revision History

Page

Document No.

Issue date

Descriptions

New

―

Version-02

Version-03

2019.07.18

2019.07.19

2019.07.25

―

English version first edition issued

Error in writing corrected

Error in Pin Configuration corrected (pin

2,8,15,16)

5,10

Version-04

2020.06.05

■Application Circuit Example

Added TEST1, TEST2, TEST_N pin.

Version-04

2020.06.05

Version-05

Version-06

2020.10.30

2023.06.09

―

Changed Company name and “notes” page.

Changed "Package Dimensions".

12/13

FEDL5810A-06

ML5810A

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application

notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are

within the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident

arising out of or in connection with the use of LAPIS Technology Products outside of such usage conditions specified

ranges, or without observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors

can break down and malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other

damage from break down or malfunction of LAPIS Technology Products, please take safety at your own risk measures such

as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups

and fail-safe procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard

operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other

use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be

taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any

losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related

information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS

Technology or any third party with respect to LAPIS Technology Products or the information contained in this document

(including but not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.).

Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by

third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in

applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS

Technology representative: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic

lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems, etc.

LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by

using the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high

reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,

LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility

for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable

laws or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US

Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or

LAPIS Technology’s Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

13/13

ML5810A [ROHM]

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