ML62Q1555 [ROHM]
ML62Q1500/ML62Q1800系列是内置16位CPU nX-U16/100、并集成了程序存储器（FLASH存储器）、数据存储器（RAM）、DATA FLASH、乘除法运算器、CRC运算器、DMA控制器、时钟发生电路、定时器、通用端口、简易RTC、UART、同步串行端口、I2C总线（主/从）、蜂鸣器、电压电平检测功能（VLS）、逐次比较型A/D转换器、D/A转换器、模拟比较器、安全功能等丰富外围功能的高性能CMOS 16位微控制器。16位CPU nX-U16/100可通过流水线架构的并行处理实现一个时钟周期一个指令的高效指令执行。ML62Q1500/ML62Q1800系列具有片上调试功能，可在开发板上进行软件调试及软件改写。另外还具有ISP（In-System Programming）功能，可轻松实现在量产生产线上的FLASH写入功能。;
| 型号： | ML62Q1555 |
| 厂家： | 
ROHM |
| 描述： | ML62Q1500/ML62Q1800系列是内置16位CPU nX-U16/100、并集成了程序存储器（FLASH存储器）、数据存储器（RAM）、DATA FLASH、乘除法运算器、CRC运算器、DMA控制器、时钟发生电路、定时器、通用端口、简易RTC、UART、同步串行端口、I2C总线（主/从）、蜂鸣器、电压电平检测功能（VLS）、逐次比较型A/D转换器、D/A转换器、模拟比较器、安全功能等丰富外围功能的高性能CMOS 16位微控制器。16位CPU nX-U16/100可通过流水线架构的并行处理实现一个时钟周期一个指令的高效指令执行。ML62Q1500/ML62Q1800系列具有片上调试功能，可在开发板上进行软件调试及软件改写。另外还具有ISP（In-System Programming）功能，可轻松实现在量产生产线上的FLASH写入功能。 时钟 生产线 控制器 微控制器 存储 比较器 转换器 |
| 文件： | 总71页 (文件大小：3059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL62Q1500-07
Issue Date: May 19, 2022
ML62Q1500/1800 Group
16-bit micro controller
GENERAL DESCRIPTION
ML62Q1500/1800 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the
multiplier/divider, CRC generator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports, UART,
Synchronous serial port, I2C bus interface unit (Master, Slave), Buzzer, Voltage Level Supervisor(VLS), Successive
approximation type A/D converter, D/A converter , Analog comparator, Safety function(IEC60730/60335 Class B) and so on.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel
processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The ML62Q1500/1800 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte).
Table 1 ML62Q1500/1800 Group Product List
48pin
52pin
TQFP52
64pin
QFP64
TQFP64
80pin
100pin
QFP100
TQFP100
Data memory
(RAM)
Program
memory
Data Flash
8Kbyte
TQFP48
QFP80
512Kbyte
384Kbyte
256Kbyte
192Kbyte
160Kbyte
－
－
ML62Q1859
ML62Q1858
ML62Q1557
ML62Q1556
ML62Q1555
－
ML62Q1869
ML62Q1868
ML62Q1567
ML62Q1566
ML62Q1565
ML62Q1564
－
ML62Q1879
ML62Q1878
ML62Q1577
ML62Q1576
ML62Q1575
ML62Q1574
－
32Kbyte
16Kbyte
－
－
－
－
－
－
－
－
16Kbyte
8Kbyte
16Kbyte
8Kbyte
－
－
128Kbyte
96Kbyte
ML62Q1534
－
ML62Q1544
－
ML62Q1554
－
4Kbyte
ML62Q1563
－
ML62Q1573
－
ML62Q1533
ML62Q1532
ML62Q1531
ML62Q1530
ML62Q1543
ML62Q1542
ML62Q1541
ML62Q1540
ML62Q1553
ML62Q1552
ML62Q1551
ML62Q1550
64Kbyte
48Kbyte
32Kbyte
－
－
8Kbyte
－
－
－
－
Please see the page 70 “Notes for product usage” and the page 71 “Notes” in this document on use with this ML62Q1500/1800
group.
FEATURES
• CPU
− 16-bit RISC CPU: nX-U16/100(A35 core)
− Instruction system: 16-bit length instructions
‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒ Built-in On-chip debug function
‒ Built-in ISP (In-System Programming) function
‒ Minimum instruction execution time
Approximately 30.5 μs (at 32.768 kHz system clock)
Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock)
FEDL62Q1500-07
• Coprocessor for multiplication and division
− Multiplication
: 16bit × 16bit (operation time : 4 cycles)
: 32bit ÷ 16bit (operation time : 8 cycles)
: 32bit ÷ 32bit (operation time : 16 cycles)
− Division
− Division
− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)
− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)
− Signed or Unsigned is selectable
• Operating voltage and temperature
‒ Operating voltage: VDD = 1.6 to 5.5 V (VDD should be 1.8V or over at Power-on)
‒ Operating temperature: -40 °C to +105 °C
• Internal memory
‒ Program memory area
Rewrite count: 100 cycles
Write unit: 32bit(4byte)
Erase unit: 16Kbyte/1Kbyte
Erase/Write temperature: 0 °C to +40 °C
‒ Data Flash memory area
Rewrite count 10,000 cycles
Write unit: 8bit(1byte)
Erase unit: all area/128byte
Erase/Write temperature: -40 °C to +85 °C
Back Ground Operation(CPU can work while erasing and rewriting)
This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc.
Super Flash® is a registered trademark of Silicon Storage Technology, Inc.
‒ Data RAM area
Rewrite unit: 8bit/16bit (1byte/2byte)
Parity check function is available (interrupt / reset are generatable at Parity error)
• Clock Generation Circuit
‒ Low-speed clock (LSCLK)
Internal low-speed RC oscillation: Approximately 32.768 kHz
External low-speed clock input: Approximately 32.768 kHz
External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable
3 selectable crystal oscillation mode (Tough, Normal, and Low current consumption)
⋅
⋅
⋅
Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins
Normal mode: Normal oscillation allowance and current consumption
Low current consumption mode: Smallest oscillation allowance to make lower current consumption
‒ High-speed clock (HSCLK)
PLL oscillation: 2 selectable oscillation frequency (24MHz and 16MHz) by code option
‒ Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1kHz)
• Reset
‒ Reset by reset input pin
‒ Reset by Power-On Reset
‒ Reset by WDT overflow
‒ Reset by WDT invalid clear
‒ Reset by RAM parity error
‒ Reset by unused ROM area access (instruction access)
‒ Reset by voltage level supervisor (VLS)
‒ Software reset by BRK instruction (reset CPU only)
‒ Reset the peripherals individually
‒ Collective reset to the all control pins and peripheral circuits
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FEDL62Q1500-07
• Power management
‒ HALT mode: CPU stops executing instruction, peripheral circuits continue working
‒ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits continue
working with low-speed clock
‒ STOP mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed
oscillation stop.
‒ STOP-D mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed
oscillation stop. The internal logic voltage (VDDL) goes down to reduce the current consumption (RAM data is retained).
‒ Clock gear: High-speed system clock frequency can be changed (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of HSCLK)
‒ Block Control Function: Powers down the unused function blocks (reset the block or stop supplying the clock)
• Interrupt controller
− External interrupt ports : max 12
− Non-maskable interrupt source: 1 (Internal source: WDT)
− Maskable interrupt sources: max.51
− Four step interrupt levels
• Watchdog timer(WDT)
‒ Selectable Operating clock : select RC1K or LSCLK by code option
‒ Overflow period: 8selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2s and 8s)
‒ Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow period)
‒ Selectable WDT operation : select Enable or Disable by code option
‒ Readable WDT counter : WDT counter monitor function
• DMA(Direct Memory Access) controller
− Channel: 2channel
− Transfer unit: 8bit/16bit
− Transfer count: 1 to 1024
− Transfer cycle: 2 cycle transfer
− Transfer address: Fixed addressing mode, inclement addressing mode, and decrement addressing mode
− Transfer target: Special Function Register (SFR)/RAM SFR/RAM (Transfer from/to Flash is not supported)
− Transfer request: External pins, Serial communication unit, Successive approximation type A/D converter, 16bit timer,
and Functional timer
• Low-speed Time base counter
− Generate 8 frequency (128Hz to1Hz) internal pulse signals by dividing the Low-speed clock (LSCLK)
− Selectable 3 interrupts from eight frequency internal pulse signals
− 1Hz or 2Hz output from general purpose port
− Built-in Frequency adjust function : Adjust range: Approximately -488ppm to +488ppm, adjust resolution:
Approximately 0.119ppm
• Simplified RTC
− Channel: 1channel
− Count by a unit for one second from "00 min. 00 sec" to "59 min. 59 sec"
− Selectable Periodical interrupt request from four periods (0.5s, 1s, 30s or 60s)
− Built-in minute and second writing error protraction function
3/71
FEDL62Q1500-07
• Functional timer
− Channel: Max. 8 channel
− Built-in timer, capture, and PWM function by 16bit counter
− Built-in Repeat mode, One shot mode is available
− Two types of PWM output with the same period and different duties, and complementary PWM output with the dead time
− Monitor input signal duty and the period by capture function
− Generate periodical interrupts, duty interrupts, and interrupts coincided with set value
− Counter Start, Stop, Counter clear triggered by an external inputs or Timer
− Generate Emergency stop and emergency stop interrupt triggered by an external input
− Same start/stop among different channels of the functional timer
− Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels
• 16-bit General timers
− Channel: Max. 8channel
‒ 8 bits timer mode and 16-bit timer mode
− Same start/stop among different channels of 16bit (8bit) timer
‒ Timer output (toggled by overflow)
− Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels
• Serial communication unit
− Synchronous Serial Port (SSIO) mode or UART mode is selectable
− Channel: Max. 6channel
< Synchronous Serial Port mode>
‒ Selectable from Master and Slave
‒ Selectable from LSB first or MSB first
‒ Selectable 8-bit length or 16-bit length
< UART mode>
‒ Full-duplex communication mode and half-duplex communication mode
‒ 5 to 8bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits
‒ Selectable from Positive logic or Negative logic
‒ Selectable from LSB first or MSB first
‒ Configurable wide range communication speed
32.768kHz operation clock: 1 bps to 4,800 bps
24MHz operation clock: 600 bps to 3 Mbps
16MHz operation clock: 300 bps to 2 Mbps
‒ Built-in baud rate generator
• I2C bus unit (Master / Slave)
‒ Selectable from Master mode or Slave mode
‒ Channel: 1 channel
< Master function >
‒ Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbps)
‒ Handshake (Clock synchronization)
‒ 7bit address format (10bit address format is supported)
< Slave function >
‒ Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbp)
‒ Clock stretch function
‒ 7bit address format
• I2C bus Master
‒ Channel: 2channel
‒ Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbps)
‒ Handshake (Clock synchronization)
‒ 7bit address format (10bit address format is supported)
4/71
FEDL62Q1500-07
• General-purpose ports (GPIO)
‒ I/O port: Max. 92 (Including one pin for on-chip debug and pins for other shared functions)
‒ Input port: Max. 2(Including a shared function)
‒ External interrupt port: Max. 12
‒ LED driver port: Max. 91
‒ Carrier frequency output function (used for IR communication)
• Successive approximation type A/D converter (SA-ADC)
‒ Channel: Max.16channel
‒ Resolution: 10bit
‒ Conversion time: Min. 2.25μs /channel (When the conversion clock speed is 8MHz)
‒ Reference voltages are selectable
(VDD pin / Internal reference voltage (VREFI = Approximately 1.55V) / External reference voltage (VREF pin))
‒ Selected channel repeat conversion
‒ Dedicated result register for each channel
‒ Interrupt determining by upper limit or lower limit threshold of conversion result
•
•
Voltage Level Supervisor (VLS)
‒ Accuracy: ±4%
‒ Threshold voltage: 12 selectable (from 1.85V to 4.00V)
‒ Functional Voltage level detection reset (VLS reset)
‒ Functional Voltage level detection interrupt (VLS0 interrupt)
Analog comparator
‒ Channel: Max. 2 channel
‒ Selectable interrupt from the comparator output (rising edge or falling edge)
‒ Selectable from sampling or without sampling
‒ Comparable with external 2 inputs
‒ Comparable with external input and internal reference voltage (0.8V)
•
•
•
D/A converter
‒ Channel: Max. 2 channel
‒ Resolution: 8bit
‒ Output impedance: 6k ohm (Typ.)
‒ R-2R ladder type
Buzzer
‒ 4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2)
‒ 8frequencies (4.096kHz to 293Hz)
‒ 15 step duty (1/16 to 15/16)
‒ Selectable from positive logic buzzer output or negative logic buzzer output
CRC (Cyclic Redundancy Check) generator
‒ Generation equation: X16+X12+X5+1
‒ Selectable from LSB first or MSB first
‒ Built-in Automatic program memory CRC calculation mode in HALT mode
5/71
FEDL62Q1500-07
•
Safety Function (IEC60730/60335 Class B)
‒ Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation stopped
‒ RAM/SFR guard
‒ Automatic program memory CRC calculation
‒ RAM parity error detection
‒ ROM unused area access reset (instruction access)
‒ Clock mutual monitoring
‒ WDT counter monitoring
‒ SA-ADC test
‒ UART test
‒ Synchronous serial I/O test
‒ I2C bus test
‒ GPIO test
• Shipping package
48 pin plastic TQFP
−
−
−
−
−
−
−
ML62Q1530/1531/1532/1533/1534 - xxxTB
（Blank part: ML62Q1530/1531/1532/1533/1534-NNNTB）
52 pin plastic TQFP
ML62Q1540/1541/1542/1543/1544 - xxxTB
（Blank part: ML62Q1540/1541/1542/1543/1544-NNNTB）
64 pin plastic TQFP
ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859 - xxxTB
（Blank part: ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859-NNNTB）
64 pin plastic QFP
ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859 - xxxGA
（Blank part: ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859-NNNGA）
80 pin plastic QFP
ML62Q1563/1564/1565/1566/1567 /1868/1869- xxxGA
（Blank part: ML62Q1563/1564/1565/1566/1567/1868/1869-NNNGA）
100 pin plastic TQFP
ML62Q1573/1574/1575/1576/1577/1878/1879 - xxxTB
（Blank part: ML62Q1573/1574/1575/1576/1577/1878/1879-NNNTB）
100 pin plastic QFP
ML62Q1573/1574/1575/1576/1577/1878/1879 - xxxGA
（Blank part: ML62Q1573/1574/1575/1576/1577/1878/1879-NNNGA）
xxx: ROM code number
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FEDL62Q1500-07
ML62Q1500/1800 Group how to read the part number
ML 62 Q 15 7 7 – xxx TB
Package Type
GA
TB
:QFP
:TQFP
ROM Code Number
NNN :Blank
xxx
:Custom Code Number
Program Memory Size
0
1
2
3
4
5
6
7
8
9
:32Kbyte
:48Kbyte
:64Kbyte
:96Kbyte
:128Kbyte
:160Kbyte
:192Kbyte
:256Kbyte
:384Kbyte
:512Kbyte
Pin Count
3
4
5
6
7
:48pin
:52pin
:64pin
:80pin
:100pin
Group Name
15
18
:1500 Group
:1800 Group
Program Memory Type
Q
:Flash Memory
CPU Type
62
:16bit CPU nX-U16/100
LAPIS Technology Logic Product
Figure 1 ML62Q1500/1800 Group Part Number
7/71
FEDL62Q1500-07
ML62Q1500/1800 Group Main Function List
Table 2 ML62Q1500/1800 Group Main Function List
Pin
Interrupt
Timer
Serial
Analog
Part number
ML62Q1530
ML62Q1531
ML62Q1532
ML62Q1533
ML62Q1534
ML62Q1540
ML62Q1541
48
42 41
ML62Q1542 52
ML62Q1543
ML62Q1544
ML62Q1550
ML62Q1551
ML62Q1552
ML62Q1553
46 45
3
31 10
6
6
2
12
1
ML62Q1554
ML62Q1555
64
58 57
ML62Q1556
ML62Q1557
ML62Q1858
ML62Q1859
ML62Q1563
ML62Q1564
ML62Q1565
ML62Q1566 80
ML62Q1567
ML62Q1868
ML62Q1869
ML62Q1573
ML62Q1574
ML62Q1575
ML62Q1576 100
ML62Q1577
ML62Q1878
ML62Q1879
1
2
1
1
2
2
4
72 71
4
43 12
8
8
6
16
2
92 91
*1 : One 16bit timer is configurable as two 8bit timers
*2 : Synchronous Communication unit includes UART and Synchronous Serial Port. UART mode and Synchronous
Serial Port can not be used at the same time in the same channel.
*3 : Shared with pins for crystal oscillation
8/71
FEDL62Q1500-07
BLOCK DIAGRAM
CPU（nX-U16/100）
ECSR1～3
DSR/CSR
PC
EPSW1～3
ELR1～3
LR
Multiplier/Divider
(Coprocessor)
GREG
0 ～15
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
（FLASH）
BUS
Controller
Instruction
Decoder
Instruction
Register
On-Chip
ICE
VDD
VSS
INT
SU0~5_SCLK*
SU0~5_SIN*
RAM
SU0~5_SOUT0*
Serial
Communication
VDDL
SU0~5_RXD0*
SU0~5_TXD0*
SU0~5_RXD1*
SU0~5_TXD1*
Unit *1
Power
Circuit
VREFO
*
Data FLASH
RESET_N
TEST0*2
SYSTEM
FLASH
INT
Controller
I2C Bus
Unit
I2CU0_SDA*
I2CU0_SCL*
INT
Clock
Generation
Circuit
OUTLSCLK*
OUTHSCLK*
Interrupt
INT
INT
I2C Bus
Master
I2CM0~1_SDA*
I2CM0~1_SCL*
Low-speed
RC
Oscillation
INT
WDT
VLS
TMH0~7OUT*
16-Bit
Timer
High-speed
PLL
Oscillation
INT
INT
INT
EXTRIG0～7
FTM0~7P*
FTM0~7N*
RC
Oscillation
(for WDT)
Functional
Timer
DMA
Controller
Low-speed
Crystal
Oscillation
XT0
XT1
CRC
Generator
INT
INT
INT
Low Speed
Time Base
Counter
TBCOUT0*
TBCOUT1*
VDD
VSS
VREF
SA-ADC
INT
INT
Simplified
RTC
AIN0 to AIN15*
BZ0P*
BZ0N*
Buzzer
CMP0~1P*
CMP0~1M*
Analog
Comparator
Safety
Function
INT
PX0~PX7
（X= 0~9,A,B)
PI00,PI01*3
GPIO
(External Interrupt)
D/A
Converter
DACOUT0~1*
Reset
Function
EXI0~11
* : Indicates the shared function of general ports.
*1 : Shared UART and Synchronous Serial Port.
*2 : Not available as the input port when connecting to the on-chip debug emulator.
*3 : Not available as the input port when connecting to the crystal resonator.
Figure 2 ML62Q1500/1800 Group Block Diagram
9/71
FEDL62Q1500-07
PIN CONFIGURATION
The port names in the pin-layout indicate 1st-function. Refer to Table-3 or Table-4 about other functions.
Pin Layout of 48pin TQFP Package
36
25
P30
P31
P50/EXI8
P13
P32
P12
P33
P11
P60
P10
P61
P07
TOP VIEW
TQFP48
P62
P06
P63
P05
P04/EXI2/EXTRG2
P64/EXI9
P65
P71
P72
P73
P66
P43
1
12
Figure 3 Pin Layout of 48pin TQFP Package
10/71
FEDL62Q1500-07
Pin Layout of 52pin TQFP Package
39
27
P51
P41
P30
P50/EXI8
P13
P31
P12
P32
P11
P33
P10
P60
TOP VIEW
TQFP52
P07
P61
P06
P62
P05
P63
P64/EXI9
P65
P04/EXI2/EXTRG2
P71
P72
P73
P66
P43
1
13
Figure 4 Pin Layout of 52pin TQFP52 Package
11/71
FEDL62Q1500-07
Pin Layout of 64pin TQFP/QFP Package
48
33
P40
P41
P53
P52
P51
P30
P31
P50/EXI8
P32
P13
P33
P12
P60
P11
TOP VIEW
TQFP64/QFP64
P61
P10
P62
P07
P63
P06
P64/EXI9
P65
P05
P04/EXI2/EXTRG2
P66
P70
P71
P72
P73
P67
P42
P43
1
16
Figure 5 Pin Layout of 64pin TQFP/QFP Package
12/71
FEDL62Q1500-07
Pin Layout of 80pin QFP Package
60
41
PB2
PB3
P96
P95
PB4
P94
PB5
P93
P40
P53
P41
P52
P30
P51
P31
P50/EXI8
P13
P32
P33
P12
TOP VIEW
QFP80
P60
P11
P61
P10
P62
P07
P63
P06
P64/EXI9
P65
P05
P04/EXI2/EXTRG2
P70
P66
P67
P71
P42
P72
P43
P73
1
20
Figure 6 Pin Layout of 80pin QFP Package
13/71
FEDL62Q1500-07
Pin Layout of 100pin TQFP Package
75
51
PB0
PB1
PA0
P97
PB2
P96
PB3
P95
PB4
P94
PB5
P93
P40
P92
P41
P91
P30
P90
P31
P53
P32
P52
P33
P51
TOP VIEW
TQFP100
P60
P50/EXI8
P13
P61
P62
P12
P63
P11
P64/EXI9
P65
P10
P07
P66
P06
P67
P05
P42
P04/EXI2/EXTRG2
P70
PB6
PB7
P71
P77
P72
P43
P73
1
25
Figure 7 Pin Layout of 100pin TQFP Package
14/71
FEDL62Q1500-07
Pin Layout of 100pin QFP Package
80
51
PB3
PB4
P96
P95
PB5
P94
P40
P93
P41
P92
P30
P91
P31
P90
P32
P53
P33
P52
P60
P51
TOP VIEW
QFP100
P61
P50/EXI8
P13
P62
P63
P12
P64/EXI9
P65
P11
P10
P66
P07
P67
P06
P42
P05
PB6
P04/EXI2/EXTRG2
P70
PB7
1
30
Figure 8 Pin Layout of 100pin QFP Package
15/71
FEDL62Q1500-07
PIN LIST
Table 3 Pin List (1/3)
rd func. 4th func.
Pin No.
Pin name Primary
2
nd func.
communica communica communica
3
5th func.
Timer
6th func.
Others
7th func.
Others
8th func.
ADC
(Primary
func.)
func.
Others
tions
tions
tions
3
-
3
-
3
-
3
3
5
VDD
VDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
42 52 54
-
4
-
4
-
4
-
4
4
6
VSS
-
41 51 53
NC
-
-
5
1
2
6
7
5
1
2
6
7
5
1
2
6
7
5
1
2
6
7
5
1
2
6
7
7
3
4
8
9
VDDL
XT0
PI00
PI01
-
XT1
RESET_N
P00
TEST0
8
9
8
9
8
8
8
10
P01
P02
P03
P04
DACOUT0
-
-
-
-
-
-
TBCOUT0 TBCOUT1
-
EXI0
EXTRG0
SU0_RXD0
SU0_SIN
11 14 19 21
FTM0P
FTM0N
OUTLSCLK
OUTHSCLK
-
CMP0M
CMP0P
-
-
AIN11
-
EXI1
SU0_TXD0
10 10 12 15 20 22
16 17 21 25 30 32
SU0_TXD1 I2CU0_SDA
EXTRG1 SU0_SOUT
EXI2
SU0_SCLK
EXTRG2
-
I2CU0_SCL TMH0OUT
17 18 22 26 31 33
18 19 23 27 32 34
19 20 24 28 33 35
20 21 25 29 34 36
21 22 26 30 35 37
P05
P06
P07
P10
P11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2CM0_SDA
SU0_RXD1 SU0_RXD0 I2CM0_SCL
SU0_TXD1
SU0_SCLK
-
-
-
-
SU0_RXD0
SU0_SIN
SU0_TXD0
SU0_SOUT
22 23 27 31 36 38
23 24 28 32 37 39
P12
P13
-
-
-
-
-
TMH4OUT
-
-
-
-
-
SU0_TXD1
TMH1OUT
-
TMH3OUT
25 27 35 45 57 59
26 28 36 46 58 60
27 29 37 47 59 61
P14
P15
P16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2CU0_SDA
SU1_SCLK
I2CU0_SCL TMH5OUT
EXI3
EXTRG3
28 30 38 48 60 62
29 31 39 49 61 63
30 32 40 50 62 64
31 33 41 51 63 65
P17
P20
P21
P22
SU0_RXD1 SU0_RXD0
-
-
-
FTM1P
FTM1N
FTM2P
FTM2N
TBCOUT0
TBCOUT1
OUTLSCLK
OUTHSCLK
BZ0P
AIN0
AIN1
AIN2
AIN3
-
SU0_TXD1
-
-
BZ0N
EXI4
EXTRG4
SU1_RXD0
SU1_SIN
-
-
SU1_TXD0
SU1_SOUT
-
SU1_TXD1 I2CM0_SDA
EXI5
32 34 42 52 64 66
P23
EXTRG5 SU1_SCLK
VREF
-
I2CM0_SCL TMH2OUT
-
-
VREFO
SU1_RXD0
SU1_SIN
SU1_TXD0
SU1_SOUT
33 35 43 53 65 67
34 36 44 54 66 68
35 37 45 55 67 69
36 38 46 56 68 70
P24
P25
P26
P27
-
-
-
-
-
-
-
AIN4
AIN5
AIN6
AIN7
-
SU1_TXD1
-
-
-
EXI6
EXTRG6
EXI7
EXTRG7
SU1_RXD1 SU1_RXD0 I2CU0_SDA
SU1_TXD1 I2CU0_SCL
FTM3P
FTM3N
TBCOUT0
TBCOUT1
BZ0P
BZ0N
-
16/71
FEDL62Q1500-07
Table 3 Pin List (2/3)
3rd func. 4th func.
communica communica communica
2
nd func.
Pin No.
Primary
func.
Others
*1
Pin name
(Primary
func)
5th func.
Timer
*1
6th func.
Others
7th func.
Others
8th func.
ADC
*1
tions
*1
tions
*1
tions
37 41 51 67 84 86
38 42 52 68 85 87
39 43 53 69 86 88
40 44 54 70 87 89
P30
P31
P32
P33
P40
P41
P42
P43
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TBCOUT0 TBCOUT1
-
SU1_RXD1 SU1_RXD0
-
-
-
-
-
-
-
-
-
-
-
-
SU1_TXD1
-
-
-
-
-
TMH3OUT
-
-
-
-
-
49 65 82 84
40 50 66 83 85
63 79 96 98
SU5_TXD1
-
-
-
-
-
-
-
-
-
SU3_TXD1
-
48 52 64 80 100 2
TBCOUT0 TBCOUT1
AIN10
-
-
9
12 17 19
P44
DACOUT1 SU4_RXD1 SU4_RXD0
-
-
-
-
-
-
-
-
-
-
10 13 18 20
13 16 21 23
P45
P46
P47
P50
P51
P52
P53
P54
P55
-
SU4_TXD1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11 14 17 22 24
-
-
24 25 29 33 38 40
EXI8
-
-
-
-
-
-
26 30 34 39 41
-
-
-
-
-
-
-
-
-
-
31 35 40 42
32 36 41 43
33 43 55 57
34 44 56 58
SU4_RXD1 SU4_RXD0
SU4_TXD1
-
-
SU2_RXD1 SU2_RXD0
TMH7OUT
-
SU2_TXD1
-
SU2_RXD0
SU2_SIN
SU2_TXD0
SU2_SOUT
-
-
39 47 57 69 71
48 58 70 72
P56
P57
-
-
-
-
-
-
-
-
-
-
-
AIN12
AIN13
-
SU2_TXD1
41 45 55 71 88 90
42 46 56 72 89 91
43 47 57 73 90 92
44 48 58 74 91 93
P60
P61
P62
P63
-
-
-
-
-
-
-
-
-
-
-
-
I2CM1_SCL
-
-
-
-
-
-
-
-
-
-
I2CM1_SDA
-
-
-
-
FTM4N
FTM4P
CMP1P
CMP1M
SU3_RXD0
SU3_SIN
SU3_TXD0
SU3_SOUT
45 49 59 75 92 94
P64
P65
EXI9
-
-
-
-
FTM5P
FTM5N
-
-
-
-
-
46 50 60 76 93 95
47 51 61 77 94 96
SU3_TXD1
-
AIN8
P66
P67
P70
P71
P72
P73
P74
P75
P76
P77
-
SU3_SCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AIN9
-
-
-
-
62 78 95 97
20 24 29 31
-
SU3_RXD1 SU3_RXD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TMH6OUT
15 16 19 23 28 30
14 15 18 22 27 29
13 14 17 21 26 28
12 13 16 20 25 27
11 12 15 19 24 26
-
-
-
-
-
-
-
-
-
-
-
-
EXI10
-
-
-
-
-
-
-
18 23 25
-
99
1
SU4_RXD0
SU4_SIN
SU4_TXD0
SU4_SOUT
-
-
-
-
-
-
9
9
11
P80
P81
-
-
-
-
-
-
-
-
-
-
-
-
-
10 10 12
11 11 13
SU4_TXD1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P82
P83
P84
P85
P86
P87
-
-
-
-
-
-
SU4_SCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 14
13 15
14 16
15 17
16 18
-
-
-
-
-
*1: The pins of name with DACOUT1, SU2, SU3, SU4, SU5, TMH6, TMH7, AIN12 or AIN13 are not assigned to products of
48/52/64 PIN-packages.
17/71
FEDL62Q1500-07
Table 3 Pin List (3/3)
rd func. 4th func.
Pin No.
Pin name Primary
2
nd func.
communica communica communica
3
5th func.
Timers
6th func.
Others
7th func.
Others
8th func.
ADC
(Primary
func)
func.
Others
tions
tions
tions
-
-
-
-
-
-
-
-
-
-
-
-
42 44
43 45
44 46
P90
P91
P92
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU4_RXD0
SU4_SIN
SU4_TXD0
SU4_SOUT
-
-
-
-
-
-
37 45 47
38 46 48
P93
P94
-
-
-
-
-
FTM6P
FTM6N
-
-
-
-
-
-
SU4_TXD1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
39 47 49
40 48 50
P95
P96
P97
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
-
SU4_SCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
49 51
50 52
53 55
54 56
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
59 71 73
60 72 74
EXI11
SU2_SCLK
FTM7P
AIN14
-
-
-
-
-
-
-
-
-
-
-
-
FTM7N
AIN15
-
-
-
-
-
73 75
74 76
75 77
76 78
77 79
-
-
-
-
-
-
-
-
-
-
SU5_RXD0
SU5_SIN
SU5_TXD0
SU5_SOUT
-
-
-
-
-
-
61 78 80
62 79 81
PB2
PB3
-
-
-
-
-
-
-
-
-
-
-
-
-
SU5_TXD1
-
-
-
-
-
-
-
-
-
-
-
-
-
63 80 82
64 81 83
PB4
PB5
PB6
PB7
-
-
-
-
SU5_SCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU5_RXD1 SU5_RXD0
-
-
97 99
98 100
-
-
-
-
18/71
FEDL62Q1500-07
PIN DESCRIPTION
Table 4 Pin Description (1/5)
Function
Power
Signal name
Pin name
VSS
I/O
Description
Negative power supply pin (-)
Logic
-
-
-
Positive power supply pin (+). Connect a capacitor CV
between this pin and VSS.
-
VDD
-
-
Power supply pin for internal logic (internal regulator’s
output). Connect a capacitor CL (1μF) between this pin and
VSS.
-
VDDL
-
-
Input for testing, is used as on-chip debug interface and ISP
function.
Test
TEST0
P00
I/O
-
P00 is initialized as pull-up input mode by the system reset.
Un used
NC
NC
-
-
Connect to VSS.
-
-
VREFO
P23
Reference voltage output
Reset input.
Applying “L” level shifts the MCU in system reset mode.
RESET_N
RESET_N
I
Applying “H” level shifts the CPU in program running mode. Negative
Used for on-chip debug interface and ISP function.
No pull-up resistor is installed.
Low speed crystal oscillation pins
Connect 32.768kHz crystal resonator and Connect
capacitors between the pin and VSS.
XT0
XT1
XT0
XT1
I
-
-
System
O
P02
P21
P03
P22
OUTLSCLK
OUTHSCLK
O
O
Low-speed clock output.
High-speed clock output.
-
-
General purpose input.
PI00,PI01
XT0,XT1
I
Not available as general inputs when using the crystal
resonator.
Positive
General purpose I/O port
- High-impedance
- Input with Pull-UP (initial value)
- Input without Pull-UP
- CMOS output
P00
P00
I/O
Positive
- N-channel open drain output
Not available to use as I/O pin when using for on-chip debug
interface or ISP function.
P01 to P07
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
P01 to P07
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
General
purpose port
General purpose I/O
- High-impedance (initial value)
- Input with Pull-UP
- Input without Pull-UP
- CMOS output
- N-channel open drain output
PA0 to PA7 PA0 to PA7
PB0 to PB7 PB0 to PB7
19/71
FEDL62Q1500-07
Table 4 Pin Description (2/5)
Description
Function
Signal name
SU0_TXD0
Pin name
P03
P13
P02
P07
P12
P17
P03
P10
P13
P20
P07
P17
P22
P25
P21
P24
P26
P32
P22
P25
P27
P33
P26
P32
P57
P54
P56
P55
P57
P54
P65
P64
P67
P42
P65
P67
P81
P94
P44
P52
P80
P93
P45
P53
P81
P94
P44
P52
I/O
O
Logic
Serial communication unit0 UART0 data output
Positive
Serial communication unit0 Full-duplex data input
Serial communication unit0 UART0 data input
SU0_RXD0
SU0_TXD1
I
Positive
Positive
Serial communication unit0 Full-duplex data output
Serial communication unit0 UART1 data output
O
SU0_RXD1
SU1_TXD0
I
Serial communication unit0 UART1 data input
Serial communication unit1 UART0 data output
Positive
Positive
O
Serial communication unit1 Full-duplex data input
Serial communication unit1 UART0 data input
SU1_RXD0
SU1_TXD1
I
Positive
Positive
Serial communication unit1 Full-duplex data output
Serial communication unit1 UART1 data output
O
SU1_RXD1
SU2_TXD0
SU2_RXD0
I
O
I
Serial communication unit1 UART1 data input
Serial communication unit2 UART0 data output
Positive
Positive
Positive
UART
Serial communication unit2 Full-duplex data input
Serial communication unit2 UART0 data input
Serial communication unit2 Full-duplex data output
Serial communication unit2 UART1 data output
SU2_TXD1
O
Positive
SU2_RXD1
SU3_TXD0
I
Serial communication unit2 UART1 data input
Serial communication unit3 UART0 data output
Positive
Positive
O
Serial communication unit3 Full-duplex data input
Serial communication unit3 UART0 data input
SU3_RXD0
I
Positive
Serial communication unit3 Full-duplex data output
Serial communication unit3 UART1 data output
SU3_TXD1
SU3_RXD1
SU4_TXD0
O
I
Positive
Positive
Positive
Serial communication unit3 UART1 data input
O
Serial communication unit4 UART0 data output
Serial communication unit4 Full-duplex data input
Serial communication unit4 UART0 data input
SU4_RXD0
SU4_TXD1
I
Positive
Positive
Serial communication unit4 Full-duplex data output
Serial communication unit4 UART1 data output.
O
SU4_RXD1
SU5_TXD0
I
Serial communication unit4 UART1 data input
Serial communication unit5 UART0 data output
Positive
Positive
PB3
O
20/71
FEDL62Q1500-07
Table 4 Pin Description (3/5)
Description
Function
UART
Signal name
SU5_RXD0
Pin name
PB2
I/O
I
Logic
Serial communication unit5 Full-duplex data input
Serial communication unit5 UART0 data input
Positive
PB5
P40
PB3
Serial communication unit5 Full-duplex data output
Serial communication unit5 UART1 data output.
SU5_TXD1
O
Positive
Positive
SU5_RXD1
SU0_SIN
PB5
P02
P12
P04
P11
P47
P03
P13
P21
P24
P16
P23
P22
P25
P56
PA3
P57
P64
P66
P65
P80
P93
P95
P82
P81
P94
PB2
PB4
PB3
P03
P15
P26
P46
P02
P04
P16
P27
P47
P06
I
I
Serial communication unit5 UART1 data input
Serial communication unit0 Synchronous serial data input
Positive
SU0_SCLK
I/O Serial communication unit0 Synchronous serial clock I/O
Positive
SU0_SOUT
SU1_SIN
O
I
Serial communication unit0 Synchronous serial data output
Serial communication unit1 Synchronous serial data input
Positive
Positive
SU1_SCLK
SU1_SOUT
I/O Serial communication unit1 Synchronous serial clock I/O
Positive
Positive
O
I
Serial communication unit1 Synchronous serial data output
Serial communication unit2 Synchronous serial data
SU2_SIN
SU2_SCLK
SU2_SOUT
SU3_SIN
Positive
Positive
Positive
Positive
Positive
Positive
Synchronous
Serial Port
I/O Serial communication unit2 Synchronous serial clock I/O
O
I
Serial communication unit2 Synchronous serial data output
Serial communication unit3 Synchronous serial data input
SU3_SCLK
SU3_SOUT
I/O Serial communication unit3 Synchronous serial clock I/O
O
Serial communication unit3 Synchronous serial data output
SU4_SIN
SU4_SCLK
SU4_SOUT
I
Serial communication unit4 Synchronous serial data input
Positive
Positive
Positive
I/O Serial communication unit4 Synchronous serial clock I/O
O
I
Serial communication unit4 Synchronous serial data output
Serial communication unit5 Synchronous serial data input
SU5_SIN
SU5_SCLK
SU5_SOUT
Positive
Positive
Positive
I/O Serial communication unit5 Synchronous serial clock I/O
O
Serial communication unit5 Synchronous serial data output
I2C Unit0 (Master and Salve) Data I/O
I/O N-channel open drain
I2CU0_SDA
Positive
Connect a pull-up resistor externally
I2C Unit0 (Master and Salve) Clock I/O
I/O N-channel open drain output
I2C Bus
I2CU0_SCL
I2CM0_SDA
Positive
Positive
Connect a pull-up resistor externally
I2C Master0 Data I/O pin
I/O N-channel open drain output
Connect a pull-up resistor externally
P22
21/71
FEDL62Q1500-07
Table 4 Pin Description (4/5)
I/O Description
Function
I2C Bus
Signal name
I2CM0_SCL
Pin name
P07
Logic
I2C Master0 Clock I/O
I/O N-channel open drain output
Connect a pull-up resistor externally
Positive
P23
I2C Master1 Data I/O
I2CM1_SDA
I2CM1_SCL
P61
I/O N-channel open drain output
Connect a pull-up resistor externally
Positive
Positive
I2C Master1 Clock I/O
P60
I/O N-channel open drain output
Connect a pull-up resistor externally
FTM0P
FTM0N
P02
P03
P17
P47
P20
P46
P21
P22
P01
P26
P27
P44
P63
P62
P64
P65
P93
P94
P86
PA3
P87
PA4
P02
P03
P04
P17
P21
P23
P26
P27
P04
P13
P23
P13
P33
P12
P16
P70
P54
P02
P03
O
O
Functional Timer0 P output
Functional Timer0 N output
Positive
Negative
FTM1P
FTM1N
O
O
Functional Timer1 P output
Functional Timer1 N output
Positive
Negative
FTM2P
FTM2N
O
O
Functional Timer2 P output
Functional Timer2 N output
Positive
Negative
FTM3P
FTM3N
O
O
Functional Timer3 P output
Functional Timer3 N output
Positive
Negative
FTM4P
FTM4N
FTM5P
FTM5N
FTM6P
FTM6N
O
O
O
O
O
O
Functional Timer4 P output
Functional Timer4 N output
Functional Timer5 P output
Functional Timer5 N output
Functional Timer6 P output
Functional Timer6 N output
Positive
Negative
Positive
Negative
Positive
Negative
Functional
Timer
(FTM)
FTM7P
FTM7N
O
O
Functional Timer7 P output
Functional Timer7 N output
Positive
Negative
EXTRG0
EXTRG1
EXTRG2
EXTRG3
EXTRG4
EXTRG5
EXTRG6
EXTRG7
TMH0OUT
TMH1OUT
TMH2OUT
I
I
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
16bit General Timer 0 output
-
-
I
-
I
-
I
-
I
-
I
-
I
-
O
O
O
Positive
Positive
Positive
16bit General Timer 1 output
16bit General Timer 2 output
TMH3OUT
O
16bit General Timer 3 output
Positive
16 bit Timer
TMH4OUT
TMH5OUT
TMH6OUT
TMH7OUT
EXTRG0
O
O
O
O
I
16bit General Timer 4 output
16bit General Timer 5 output
16bit General Timer 6 output
16bit General Timer 7 output
16bit Timer trigger input
Positive
Positive
Positive
Positive
-
EXTRG1
I
16bit Timer trigger input
-
22/71
FEDL62Q1500-07
Logic
Table 4 Pin Description (5/5)
Description
Function
Signal name
TBCOUT0
Pin name
P01
P17
P26
P31
P43
P01
P20
P27
P31
P43
P17
P26
P20
P27
P02
P03
P04
P17
P21
P23
P26
P27
P50
P64
P76
PA3
P23
P17
P20
P21
P22
P24
P25
P26
P27
P65
P66
P43
P03
P56
P57
PA3
PA4
P03
P02
P62
P63
P01
P44
I/O
The virtual frequency adjustment signal output or The low
speed time base counter output signal
O
Positive
Positive
Low-speed
Time Base
Counter
TBCOUT1
O
1Hz/2Hz clock output for the Simplified RTC
BZ0P
BZ0N
O
O
Buzzer output (positive phase)
Buzzer output (negative phase)
Positive
Buzzer
Negative
EXI0
EXI1
I
I
External Interrupt 0 Input
External Interrupt 1 Input
External Interrupt 2 Input
External Interrupt 3 Input
External Interrupt 4 Input
External Interrupt 5 Input
External Interrupt 6 Input
External Interrupt 7 Input
External Interrupt 8 Input
External Interrupt 9 Input
External Interrupt 10 Input
External Interrupt 11 Input
SA-ADC external reference voltage input
SA-ADC channel 0 input
SA-ADC channel 1 input
SA-ADC channel 2 input
SA-ADC channel 3 input
SA-ADC channel 4 input
SA-ADC channel 5 input
SA-ADC channel 6 input
SA-ADC channel 7 input
SA-ADC channel 8 input
SA-ADC channel 9 input
SA-ADC channel 10 input
SA-ADC channel 11 input
SA-ADC channel 12 input
SA-ADC channel 13 input
SA-ADC channel 14 input
SA-ADC channel 15 input
Comparator input 0 (noninverting input)
Comparator input 0 (inverting input)
Comparator input 1 (noninverting input)
Comparator input 1 (inverting input)
D/A converter 0 output
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EXI2
I
EXI3
I
EXI4
I
EXI5
I
External
Interrupt
EXI6
I
EXI7
I
EXI8
I
EXI9
I
EXI10
EXI11
VREF
I
I
-
I
AIN0
AIN1
I
AIN2
I
AIN3
I
AIN4
I
AIN5
I
Successive
approximation
type
A/D converter
(SA-ADC)
AIN6
I
AIN7
I
AIN8
I
AIN9
I
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
CMP0P
CMP0M
CMP1P
CMP1M
DACOUT0
DACOUT1
I
I
I
I
I
I
I
I
Analog
comparator
I
I
O
O
D/A converter
D/A converter 1 output
23/71
FEDL62Q1500-07
TERMINATION OF UNUSED PINS
Table 5 Termination of unused pins
Pin
pin termination
NC
RESET_N
Connect to VSS
Connect to VDD
Connect to VDD with initial state (pulled-up input mode)
.
P00/TEST0
XT0/PI00, XT1/PI01
P01 to P07
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
Open with initial state (Hi-impedance)
Note:
Terminate unused input pins according to the table 5 in order to avoid unexpected through-current
in the pins.
24/71
FEDL62Q1500-07
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
Unit
Parameter
Power supply voltage 1
Power supply voltage 2
Input voltage
Symbol
Condition
Rating
VDD
VDDL
VIN
Ta = +25°C
Ta = +25°C
Ta = +25°C
Ta = +25°C
-0.3 to +6.5
-0.3 to +2.0
-0.3 to VDD+0.3*1
V
V
V
V
VOUT
-0.3 to VDD+0.3*1
Output voltage
1pin
Total
1pin
-40*2
-180*2
+40
“H” level output current
“L” level output current
IOUTH
IOUTL
Ta = +25°C
mA
mA
Ta = +25°C
Ta = +25°C
Total
+180
1
Power dissipation
PD
W
Storage temperature
TSTG
―
-55 to +150
°C
*1 6.5V or lower
*2 The current flowing out the LSI through the pin is described in the negative number.
The applicable maximum current is the absolute value.
For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
[Note]
Stresses above the absolute maximum ratings listed in the above table may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these conditions is not implied.
Recommended Operating Conditions
(VSS = 0V)
Unit
Parameter
Symbol
Condition
Range
Operating temperature (Ambient)
Operating temperature (Chip-Junction)
Operating voltage
Ta
Tj
―
―
-40 to +105
-40 to +115
°C
°C
V
VDD
―
1.6 to 5.5
30k to 4M
30k to 25M
1.0 ±30%
VDD = 1.6 to 5.5V
VDD = 1.8 to 5.5V
―
Operating frequency (CPU)
VDDL pin external capacitance
fOP
CL
Hz
μF
25/71
FEDL62Q1500-07
Thermal characteristics
The maximum chip-junction temperature, Tjmax, may be calculated using the following equation.
푇
푗 푚ꢀꢁ
= 푇
+ 푃퐷 푚ꢀꢁ × 휃
ꢀ 푚ꢀꢁ 푗ꢀ
푇
ꢀ 푚ꢀꢁ
: maximum ambient temperature
푃퐷 푚ꢀꢁ : LSI maximum power dissipation
: Package junction to ambient thermal resistance
휃
푗ꢀ
Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to satisfy the
recommended conditions.
The following table shows the each package’s thermal resistance for thermal design reference estimated by simulation based
on the PCB (printed circuit board) conditions define as a below.
Value
Parameter
Symbol
Package type
Unit
L1
L2
TQFP48
TQFP52
TQFP64
QFP64
63.6
61.7
63.2
47.2
55.5
48.0
104.7
57.8
56.7
58.2
43.3
51.6
43.3
101.3
Thermal
resistance
θja
oC/W
QFP80
TQFP100
QFP100
PCB conditions:
PCB name
L1
L2
Unit
mm
layer
―
PCB size （L / W / T）
Number of layer
Wiring density
114.3 / 76.2 / 1.6
1
114.3 / 76.2 / 1.6
2
60% (top layer)
60%(top and bottom layer)
Wind condition
No wind (0m/s)
―
26/71
FEDL62Q1500-07
Current Consumption 1
Product： ML62Q1530, ML62Q1531, ML62Q1532, ML62Q1533, ML62Q1534, ML62Q1540,
ML62Q1541, ML62Q1542, ML62Q1543, ML62Q1544, ML62Q1550, ML62Q1551,
ML62Q1552, ML62Q1553, ML62Q1554
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Measuri
Parameter
Symbol
IDD0
Condition
Min.
Typ.*3
Max.
Unit
ng
circuit
Ta = -40 to
+85 oC
―
―
―
―
23
75
26
80
CPU is in STOP-D state.
Low-speed RC1K/RC32K and
PLL oscillation are stopped.
Supply current 0
µA
0.8
Ta = -40 to
+105 oC
Ta = -40 to
+85 oC
CPU is in STOP state.
Low-speed RC1K/RC32K and
PLL oscillation are stopped.
Supply current 1
IDD1
µA
µA
1.0
4.7
Ta = -40 to
+105 oC
Ta = -40 to
+85 oC
―
―
―
35
85
32
Low-speed RC32K Oscillating.
CPU is in HALT state*1. PLL
oscillation is stopped.
Supply current 2-1
IDD2-1
Ta = -40 to
+105 oC
Ta = -40 to
+85 oC
Low-speed Crystal Oscillating.
*4
1
Supply current 2-2
IDD2-2
µA
µA
3.0
CPU is in HALT state*1. PLL
oscillation is stopped.
Ta = -40 to
+105 oC
―
―
85
CPU: Running with low-speed
RC32K oscillation clock*1*2
PLL oscillation is stopped.
Ta = -40 to
+105 oC
Supply current 3
Supply current 4
Supply current 5
IDD3
IDD4
IDD5
105
17
3.3
4.7
CPU: Running with 16MHz PLL
oscillating clock*1*2
PLL 16MHz is oscillating.
VDD=1.8~5.5V
Ta = -40 to
+105 oC
―
―
4.5
6.0
mA
CPU: Running with 24MHz PLL
oscillating clock*1*2
Ta = -40 to
+105 oC
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
*
*
LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”
CPU running in wait mode
2
*3 On the condition of VDD=3.0V, Ta=+25oC
*4 When the noise filter is not used in the low power consumption mode
27/71
FEDL62Q1500-07
Current Consumption 2
Product： ML62Q1555, ML62Q1556, ML62Q1557, ML62Q1563, ML62Q1564, ML62Q1565, ML62Q1566,
ML62Q1567, ML62Q1573, ML62Q1574, ML62Q1575, ML62Q1576, ML62Q1577
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Measuri
Parameter
Symbol
IDD0
Condition
Min.
Typ.*3
Max.
Unit
ng
circuit
Ta = -40 to
+85 oC
―
―
―
―
55
110
60
CPU is in STOP-D state.
Low-speed RC1K/RC32K and
PLL oscillation are stopped.
Supply current 0
µA
1.0
Ta = -40 to
+105 oC
Ta = -40 to
+85 oC
CPU is in STOP state.
Low-speed RC1K/RC32K and
PLL oscillation are stopped.
Supply current 1
IDD1
µA
µA
1.3
5.5
Ta = -40 to
+105 oC
120
Ta = -40 to
+85 oC
Low-speed RC32K Oscillating.
CPU is in HALT state (LTBC and
WDT are operating*1). PLL
oscillation is stopped.
―
―
―
―
76
135
76
Supply current 2-1
IDD2-1
Ta = -40 to
+105 oC
Low-speed Crystal Oscillating.*4
CPU is in HALT state (LTBC and
WDT are operating*1). PLL
oscillation is stopped.
Ta = -40 to
+85 oC
1
Supply current 2-2
Supply current 3
µA
µA
IDD2-2
IDD3
4.5
20
Ta = -40 to
+105 oC
135
CPU: Running with low-speed
RC32K oscillation clock*1*2
PLL oscillation is stopped.
Ta = -40 to
+105 oC
―
150
CPU: Running with 16MHz PLL
oscillating clock*1*2
PLL 16MHz is oscillating.
VDD=1.8~5.5V
Ta = -40 to
+105 oC
Supply current 4
Supply current 5
IDD4
IDD5
―
―
6.2
8.5
5.0
6.8
mA
CPU: Running with 24MHz PLL
oscillating clock*1*2
Ta = -40 to
+105 oC
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
*
*
LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”
CPU running in wait mode
2
*3 On the condition of VDD=3.0V, Ta=+25oC
*4 When the noise filter is not used in the low power consumption mode
28/71
FEDL62Q1500-07
Current Consumption 3
Product： ML62Q1858, ML62Q1859, ML62Q1868, ML62Q1869, ML62Q1878, ML62Q1879
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Measuri
Parameter
Symbol
IDD0
Condition
Min.
Typ.*3
1.2
Max.
Unit
ng
circuit
Ta = -40 to
+85 oC
―
―
―
―
57
140
62
CPU is in STOP-D state.
Low-speed RC1K/RC32K and
PLL oscillation are stopped.
Supply current 0
µA
Ta = -40 to
+105 oC
Ta = -40 to
+85 oC
CPU is in STOP state.
Low-speed RC1K/RC32K and
PLL oscillation are stopped.
Supply current 1
IDD1
µA
µA
1.8
6.0
Ta = -40 to
+105 oC
150
Ta = -40 to
+85 oC
Low-speed RC32K Oscillating.
CPU is in HALT state (LTBC
and WDT are operating*1). PLL
oscillation is stopped.
―
―
―
78
165
78
Supply current 2-1
IDD2-1
Ta = -40 to
+105 oC
Ta = -40 to
+85 oC
Low-speed Crystal Oscillating.
*4
1
Supply current 2-2
CPU is in HALT state (LTBC
and WDT are operating*1). PLL
oscillation is stopped.
IDD2-2
µA
µA
4.5
20
Ta = -40 to
+105 oC
―
―
165
190
CPU: Running with low-speed
RC32K oscillation clock*1*2
PLL oscillation is stopped.
Ta = -40 to
+105 oC
Supply current 3
Supply current 4
Supply current 5
IDD3
IDD4
IDD5
CPU: Running with 16MHz PLL
oscillating clock*1*2
PLL 16MHz is oscillating.
VDD=1.8~5.5V
Ta = -40 to
+105 oC
―
―
5.0
7.0
4.0
5.7
mA
CPU: Running with 24MHz PLL
oscillating clock*1*2
Ta = -40 to
+105 oC
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
*
*
LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”
CPU running in wait mode
2
*3 On the condition of VDD=3.0V, Ta=+25oC
*4 When the noise filter is not used in the low power consumption mode
29/71
FEDL62Q1500-07
Low speed Crystal Oscillation
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Range
Typ.
Parameter
Symbol
fXTL
Condition
Unit
kHz
s
Min.
Max.
Crystal oscillation
frequency *1 *2
Crystal oscillation start
time
―
―
―
32.768
―
TXTL
―
―
2
*1: The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance
(CGL/CDL). As those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB
circuit for matching. Ask crystal resonator makers for matching and confirm the oscillation characteristics.
*2: The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring
capacitance or parasitic capacitance on the external circuits. Note for designing the external circuit.
- Make the wires on the external circuit as short as possible.
- Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between
the external capacitance and crystal resonator as short as possible.
- Ensure no signal line flowing big current runs near the oscillation circuit.
- Ensure no signal line runs under and near the oscillation circuit.
- Make ground of external capacitance the same as MCU ground VSS pin and connect them to the ground that
has low variation of current and voltage.
variation.
- The quality of oscillation characteristics might be lost depending on operating environment due to moisture
absorption of PCB and condensation of PCB surface, recommended to have measures such as covering the
oscillation circuit with resin.
Low speed Crystal Oscillation external circuit example
XT0
Crystal resonator
XT1
VSS
(32.768kHz）
CDL
CGL
External Clock Input
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Range
Parameter
Symbol
fEXCK
Condition
Unit
kHz
s
Min.
Typ.
Max.
Typ.
Typ.
Input Frequency
Input pulse width
―
―
32.768
-1.0%
1/fEXCK
x 0.4
+1.0%
1/fEXCK
x 0.6
tEXCKW
―
30/71
FEDL62Q1500-07
On-chip Oscillator
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measur
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ing
circuit
Ta= +25°C
Typ.
-1.0%
Typ.
-2.5%
Typ.
-3.0%
Typ.
-3.5%
Typ.
-1.0%
Typ.
-1.5%
Typ.
-2.5%
Typ.
-3.0%
Typ.
Typ.
+1.0%
Typ.
+2.5%
Typ.
+3.0%
Typ.
-3.5%
Typ.
+1.0%
Typ.
+1.5%
Typ.
+2.5%
Typ.
+3.0%
Typ.
32.768
32.768
32.768
32.768
32.768
32.768
16/24
VDD = 1.8 to 5.5V
Ta= -40 to +85°C
VDD = 1.8 to 5.5V
Ta= -40 to +105°C
VDD = 1.8 to 5.5V
Low-speed RC oscillator
frequency accuracy 1
fRCL1
Without software adjustment
kHz
VDD = 1.6 to 1.8V
Ta= -40 to +85°C
VDD = 1.8 to 5.5V
Ta= -40 to +105°C
VDD = 1.8 to 5.5V
Ta= -40 to +85°C
VDD = 1.8 to 5.5V
Ta= -40 to +105°C
VDD = 1.8 to 5.5V
Low-speed RC oscillator
frequency accuracy 2
With software adjustment
fRCL2
fPLL1
fPLL2
1
PLL oscillation frequency
accuracy 1
Without software adjustment
16/24
VDD = 1.6 to 1.8V
16/24
MHz
-3.5%
Typ.
-1.0%
Typ.
-1.5%
―
+3.5%
Typ.
+1.0%
Typ.
+1.5%
2
Ta= -40 to +85°C
VDD = 1.8 to 5.5V
Ta= -40 to +105°C
VDD = 1.8 to 5.5V
VDD = 1.6 to 5.5V
Ta= -40 to +105°C
VDD = 1.6 to 5.5V
16/24
PLL oscillation frequency
accuracy 2
With software adjustment
16/24
―
PLL oscillation start time
TPLL
ms
1kHz Low-speed RC oscillator
(for WDT) frequency accuracy
fRC1K
0.5
1
2.5
kHz
31/71
FEDL62Q1500-07
Input / Output pin 1
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measur
Parameter
Symbol
VOH1
Condition
Min.
Typ.
Max.
Unit
ing
circuit
Output voltage1
“H”/”L” level
(P00-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
IOH1=-10mA
VDD
-1.5
―
―
V
DD≥4.5V
IOH1=-1mA
DD≥1.6V
VDD
-0.5
―
―
―
―
V
IOL1=+10mA
DD≥4.5V
―
―
1.5
0.5
V
VOL1
IOL1=+1mA
VDD≥1.6V
V
2
Output voltage2
“L” level
IOL2=+15mA
DD≥4.5V
―
―
―
―
―
―
―
―
0.7
0.5
0.4
0.4
V
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
IOL2=+8mA
DD≥3.0V
V
When N-ch open
drain output
mode is selected
VOL2
IOL2=+3mA
DD≥2.0V
V
IOL2=+2mA
DD≥1.6V
V
32/71
FEDL62Q1500-07
Input / Output pin 2
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measuri
Parameter
Symbol
IOH1
Condition
Min.
Typ.
Max. Unit
ng
circuit
V
DD≥4.5V
-10*3*5
-1*3*5
―
―
―
―
“H” level output
current1 *6
1pin
VDD≥1.6V
Total of ‘P00-P07,
P10-P13, P44-P47,
P50-P53, P70-P76,
P80-P87，P90-P97, PA0’
VDD≥4.5V
-90*5
―
―
―
―
or ‘P14-P17, P20-P27,
P30-P33, P40-P43,
P54-P57 P60-P67,P77,
PA1-PA7，PB0-PB7’
“H” level output total
current *1*4
IOH3
VDD≥1.6V
-20*5
(duty≤50%)
VDD≥4.5V
VDD≥1.6V
VDD≥4.5V
VDD≥1.6V
VDD≥4.5V
VDD≥3.0V
VDD≥2.0V
VDD≥1.6V
-180*5
-40*5
―
―
―
―
―
―
―
―
―
―
―
10*3
1*3
15*3
mA
8*3
3*3
2*3
All pin total
(duty≤50%)
“L” level output
current1 *6
1pin (CMOS output
mode)
IOL1
IOL2
―
―
―
“L” level output
current2 *6
1pin (Nch open drain
output mode)
―
―
Total of P00-P07,
P10-P13, P44-P47,
P50-P53, P70-P76,
P80-P87, P90-P97, PA0’
or ‘P14~P17, P20-P27,
P30-P33, P40-P43,
P54-P57 P60-P67,P77,
PA1-PA7, PB0-PB7’
(Nch open drain output
mode,duty≤50%)
V
DD≥4.5V
―
―
―
―
―
―
―
―
90
40
15
10
3
VDD≥3.0V
VDD≥2.0V
VDD≥1.6V
“L” level output total
current *2*4
IOL3
All pin total
(Nch open drain output
mode,duty≤50%)
V
DD≥4.5V
―
―
―
―
180
20
VDD≥1.6V
Output leak
(P00-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
（P80-P87）
（P90-P97）
（PA0-PA7）
（PB0-PB7）
IOOH
IOOL
VOH=VDD (High impedance mode)
―
―
―
+1
μA
―
VOL=VSS (High impedance mode)
-1*5
33/71
FEDL62Q1500-07
*1 Sink-out current from VDD to the output pin, which can guarantee the device operation.
*2 Sink-in current from the output pin to VSS, which can guarantee the device operation.
*3 Do not beyond total current.
*4 The total current is on the condition of Duty≤50%(same applies to IOH1).
When the duty>50% the total current is calculated by following formula.
Total current = IOL3 x 50/n (When the duty is n%)
<For an example> When IOL3=100mA and n=80%,
Total current = IOL3 x 50/80 = 62.5mA
Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2.
Do not apply current larger than Absolute Maximum Ratings.
*5 The current flowing out the LSI through the pin is described in the negative number.
The applicable maximum current is the absolute value.
For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
*6 VOH1, VOL1, and VOL2 are satisfied with this spec.
34/71
FEDL62Q1500-07
Input / Output pin 3
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measur
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ing
circuit
IIH1
IIL1
VIH1=VDD
―
―
―
1
Input current1
(RESET_N)
VIL1=VSS
-1*1
―
μA
IIL2
VIL2=VSS (pull-up mode) *2
VIL2=VSS (pull-up mode) *2
VIH2=VDD (High impedance mode)
VIL2=VSS (High impedance mode)
-1500*1 -300*1 -20*1
V/IIL2
IIH2Z
IIL2Z
3.7
―
-1*1
10
―
―
80
1
kΩ
Input current2
(P00/TEST0)
―
μA
Input current3
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
IIL3
VIL1=VSS (pull-up mode) *2
-250*1
22
-30*1
100
―
-2*1
800
1
4
V/IIL3
IIH3Z
IIL3Z
VIL1=VSS (pull-up mode) *2
kΩ
VIH1=VDD (High impedance mode)
VIL1=VSS (High impedance mode)
―
μA
-1*1
―
―
IIH4
IIL4
VIH1=VDD
VIL1=VSS
―
-1*1
―
―
1
Input current4
(PI00-PI01)
―
Input voltage1
(RESET_N)
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
(PI00-PI01)
0.7
x VDD
VIH1
VIL1
―
―
―
―
VDD
V
5
0.3
x VDD
0
0.7
x VDD
VIH2
VIL2
―
―
―
―
VDD
Input voltage2
(P00/TEST0)
0.25
x VDD
0
Pin capacitance
(RESET_N)
(P00/TEST0)
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
(PI00-PI01)
f = 10kHz
Ta = +25°C
CPIN
―
―
10
pF
―
*1 The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the
absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
*2 Measurement conditions: Typ. : VDD = 3.0V, Max. : VDD = 1.6V, Min. : VDD = 5.5V
35/71
FEDL62Q1500-07
Synchronous Serial Port
Slave mode
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
SCK input cycle
SCK input pulse width
Symbol
tSCYC
tSW
Condition
Min.
Typ.
―
―
Max.
―
―
Unit
µs
µs
―
―
1 *2
0.5 *3
100+
VDD=2.4 to 5.5V
―
―
―
―
―
ns
ns
ns
ns
HSCLK*1×3
200+
SOUT output delay time
SIN input setup time
tSD
VDD=1.8 to 5.5V
―
HSCLK*1×3
HSCLK*1
x1
tSS
tSH
―
―
―
―
80+
SIN input hold time
HSCLK*1×3
*1 Cycle of high speed clock
*2 Need input cycles of HSCLK x8 or longer
*3 Need input cycles of HSCLK x4 or longer
tSCYC
tSW
tSW
0.7×VDD
SUn_SCLK*
0.3×VDD
tSD
tSD
0.7×VDD
0.3×VDD
SUn_SOUT*
tSS
tSH
0.7×VDD
0.3×VDD
SUn_SIN*
* 2nd to 8th function of port, n=0 to 5
36/71
FEDL62Q1500-07
Master mode
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
SCK output cycle
Symbol
tSCYC
Condition
Min.
―
Typ.
SCLK*1
SCLK*1
×0.5
―
Max.
―
Unit
ns
―
SCLK*1
×0.4
―
SCLK*1
×0.6
100
160
―
SCK output pulse width
tSW
tSD
tSS
tSH
―
ns
VDD=2.4 to 5.5V
VDD=1.8 to 5.5V
VDD=2.4 to 5.5V
VDD=1.8 to 5.5V
VDD=2.4 to 5.5V
VDD=1.8 to 5.5V
ns
ns
ns
ns
ns
ns
SOUT output delay time
SIN input setup time
SIN input hold time
―
―
―
―
―
120
180
80
―
―
―
100
―
*1 Clock cycle selected by bit12~8(SnCK4~0) of the serial port n mode register (SIOnMOD)
VDD≥2.4V: min250ns , VDD≥1.8V: min500ns
tSCYC
tSW
tSW
0.7×VDD
0.3×VDD
SUn_SCLK*
SUn_SOUT*
SUn_SIN*
tSD
tSD
0.7×VDD
0.3×VDD
tSS
tSH
0.7×VDD
0.3×VDD
* 2nd to 8th function of port, n=0 to 5
37/71
FEDL62Q1500-07
I2C Bus Interface
Standard Mode (100kbps)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
SCL clock frequency
fSCL
―
0
―
100
kHz
SCL hold time
(start/restart condition)
tHD:STA
―
4.0
―
―
µs
SCL ”L” level time
SCL ”H” level time
tLOW
tHIGH
―
―
4.7
4.0
―
―
―
―
µs
µs
SCL setup time
(restart condition)
tSU:STA
―
4.7
―
―
µs
SDA hold time
SDA setup time
tHD:DAT
tSU:DAT
―
―
0
―
―
―
―
µs
µs
0.25
SDA setup time
(stop condition)
tSU:STO
―
4.0
―
―
µs
Bus-free time
tBUF
―
4.7
―
―
µs
When using the I2C as the master, configure the I2C master n mode register(I2MnMOD) and I2C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
Re-start
Condition
Stop
Condition
I2CUn_SDA
I2CMn_SDA
0.7×VDD
0.3×VDD
0.7×VDD
0.3×VDD
I2CUn_SCL
I2CMn_SCL
tSU:STO
F
tHD:STA
tLOW
tSU:STA tHD:STA
tSU:DAT tHD:DAT
tHIGH
n：0 to 1
38/71
FEDL62Q1500-07
Fast Mode (400 kbps)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
SCL clock frequency
fSCL
―
0
―
400
kHz
SCL hold time
(start/restart condition)
tHD:STA
―
0.6
―
―
µs
SCL ”L” level time
SCL ”H” level time
tLOW
tHIGH
―
―
1.3
0.6
―
―
―
―
µs
µs
SCL setup time
(restart condition)
tSU:STA
―
0.6
―
―
µs
SDA hold time
SDA setup time
tHD:DAT
tSU:DAT
―
―
0
―
―
―
―
µs
µs
0.1
SDA setup time
(stop condition)
tSU:STO
tBUF
―
―
0.6
1.3
―
―
―
―
µs
µs
Bus-free time
When using the I2C as the master, configure the I2C master n mode register(I2MnMOD) and I2C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
Re-start
Condition
Stop
Condition
0.7×VDD
0.3×VDD
I2CUn_SDA
I2CMn_SDA
0.7×VDD
0.3×VDD
I2CUn_SCL
I2CMn_SCL
tSU:STO
F
tHD:STA
tLOW
tSU:STA tHD:STA
tSU:DAT tHD:DAT
tHIGH
n：0 to 1
39/71
FEDL62Q1500-07
1Mbps Mode
Parameter
(VDD=2.7 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
SCL clock frequency
fSCL
―
0
―
1000
kHz
SCL hold time
(start/restart condition)
tHD:STA
tLOW
―
―
―
―
―
―
―
―
0.26
0.5
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
µs
µs
µs
µs
µs
µs
µs
µs
SCL ”L” level time
SCL ”H” level time
tHIGH
0.26
0.26
0
SCL setup time
(restart condition)
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
SDA hold time
SDA setup time
0.1
SDA setup time
(stop condition)
0.26
Bus-free time
0.5
When using the I2C as the master, configure the I2C master n mode register(I2MnMOD) and I2C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
Re-start
Condition
Stop
Condition
0.7×VDD
0.3×VDD
I2CU0_SDA
I2CMn_SDA
0.7×VDD
0.3×VDD
I2CU0_SCL
I2CMn_SCL
tSU:STO
F
tHD:STA
tLOW
tSU:STA tHD:STA
tSU:DAT tHD:DAT
tHIGH
n：0 to 1
40/71
FEDL62Q1500-07
Reset
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measur
ing
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
circuit
Reset pulse width*2
P00 ”H” level setup time*1
P00 ”H” level hold time*1
PRST
tSP00
―
―
―
2
1
1
―
―
―
―
―
―
ms
ms
ms
1
tHP00*1
*1： except ISP mode. Refer to the User’s manual “25.4 In-System Programing Function” for the timing in ISP mode.
*2： VDD=1.6V or over at power on.
VIH1
VIL1
VIL1
RESET_N
*2
PRST
“H” level input
“H” level or “L” level
“H” level or “L” level
P00/TEST0
tSP00
tHP00
Note:
RESET_N input shorter pulse than the Reset pulse width (PRST) valid time should be avoided.
The shorter pulse input may cause unexpected behavior.
41/71
FEDL62Q1500-07
Slope of Power supply and Power On Reset
(VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measur
ing
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
circuit
Power on rising slope
Power on falling slope
SVR
SVF
―
―
―
―
―
―
60
2
V/ms
V/ms
Power on reset detection
voltage
VPORR
VPORF
At Power up (rising)
At Power down (falling)
1.47
1.33
1.57
1.49
1.80
1.58
V
V
1
Power on reset minimum
pulse width
PPOR
VINIT
―
200
1.8
―
―
―
―
μs
Power on voltage
At power on
V
CPU operation start time
(from the release of reset to
the CPU starts to run）
tCPUI
―
11
16
―
ms
―
At Power supply voltage level change
SVR
At Power supply restart
SVF
SVF
SVR
SVR
VDD
VINIT
VPORR
VPORF
0V
PPOR
tCPUI
At Power off
At power on
Note:
If a pulse shorter than the Power on reset minimum pulse width is asserted to VDD, it may cause the
MCU malfunction.
Apply prevent measurement such as bypass capacitors or external reset input, and so on.
Start the high-speed clock when the VDD is within the operating voltage.
42/71
FEDL62Q1500-07
VLS
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Condition
VLS0LV *1
Measuring
circuit
Parameter
Symbol
Min.
Typ.
Max.
Unit
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
IVLS
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
3.86
3.84
3.57
3.55
2.94
2.92
2.85
2.83
2.75
2.73
2.66
2.64
2.56
2.54
2.46
2.44
2.37
2.35
1.98
1.96
1.89
1.87
1.79
1.77
―
4.06
4.00
3.76
3.70
3.11
3.05
3.01
2.95
2.91
2.85
2.81
2.75
2.71
2.65
2.61
2.55
2.51
2.45
2.11
2.05
2.01
1.95
1.91
1.85
50
4.26
4.16
3.95
3.85
3.28
3.18
3.17
3.07
3.07
2.97
2.96
2.86
2.86
2.76
2.76
2.66
2.65
2.55
2.24
2.14
2.13
2.03
2.03
1.93
―
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
VLS threshold
voltage *2
V
1
VLS Current
―
nA
*1 Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV).
*2 The Data VSL0LV = 0CH~0FH is not available to use, if the data is specified it will the same spec as that 0BH is
specified.
Analog Comparator
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Measuring
Parameter
Symbol
VCMR
Condition
Min.
Typ.
Max.
Unit
circuit
Comparator same
phase input
voltage range
VDD
-1.5
―
0.1
―
V
Comparator0
input offset
Ta=+25oC、VDD=5.0V
VCMOF
―
5
―
mV
V
1
Comparator
Reference
Voltage
VCMREF
―
0.75
0.8
0.85
43/71
FEDL62Q1500-07
Successive Approximation Type A/D Converter
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Parameter
Resolution
Overall error
Symbol
nAD
Condition
Min.
―
Typ.
―
Max.
10
Unit
bit
―
4.5V≤ Reference voltage*1≤5.5V
2.7V≤ Reference voltage*1≤5.5V
2.2V≤ Reference voltage*1<2.7V
1.8V≤ Reference voltage*1<2.2V
Reference voltage = Internal
-3.5
-4
1.2
―
―
―
3.5
4
―
-6
6
Integral non-linearity
error
INLAD
-10
10
-15
―
15
reference voltage (VREFI
)
2.7V≤ Reference voltage*1≤5.5V
2.2V≤V Reference voltage*1<2.7V
1.8V≤ Reference voltage*1<2.2V
Reference voltage = Internal
-3
-5
-9
―
―
―
3
5
9
LSB
Differential non-linearity
error
DNLAD
-14
―
14
reference voltage(VREFI
)
Zero-scale error
Full-scale error
ZSE
FSE
VREF
VREFI
RI≤1kΩ
-6
-6
―
―
6
RI≤1kΩ
―
6
A/D reference voltage
Internal reference voltage
1.8
1.5
2.25
4.5
18
―
VDD
1.6
427
427
427
V
―
1.55
―
4.5V≤VDD≤5.5V
2.2V≤VDD≤5.5V
1.8V≤VDD≤5.5V
Conversion time
tCONV
―
μs
―
*1 : VDD or P23/VREF is selected for the reference voltage of Successive Approximation Type A/D Converter.
The current flows during the ADC sampling as it takes charging. Make the output impedance of the analog signal source 1kΩ
or smaller. Also, putting 0.1uF capacitor on the ADC input pin is recommended to reduce the noise.
VDD
VDDL
1.0μF
A
RI≤1kΩ
-
1.0μF
AINx
Analog input
+
VSS
0.1μF
44/71
FEDL62Q1500-07
D/A Converter
Parameter
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Symbol
nDA
Condition
―
Min.
―
Typ.
―
Max.
8
Unit
bit
Resolution
Conversion cycle
tc
―
10
―
―
μs
Integral non-linearity error
INLDA
RL=4MΩ
-2
―
2
LSB
Differential non-linearity
error
DNLDA
Ro
RL=4MΩ
-1
3
―
1
9
Output impedance
―
6
kΩ
Reference Voltage Output
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105oC, unless otherwise specified)
Parameter
Output voltage
Output impedance
Symbol
VREFO
RVREFO
Condition
Min.
―
―
Typ.
1.55
―
Max.
―
500
Unit
V
kΩ
―
―
Flash Memory
(VSS= 0V)
Unit
Parameter
Symbol
TOP
Condition
Data flash memory, At write/erase
Flash ROM, At write/erase
At write/erase
Range
-40 to +85
0 to +40
+1.8 to +5.5
10000
100
Operating temperature
Operating voltage
°C
V
VDD
CEPD
CEPP
Data Flash
Program Flash
Maximum rewrite count
times
Program Flash
Block erase
16K
all area
1K
―
―
―
B
B
Data Flash
Erase unit
Program Flash
Sector erase
Data Flash
128
Block erase /
Sector erase
Program Flash
Data Flash
Program Flash
Data Flash
―
Erase time (Max.)
Write unit
50
ms
B
4
1
80
40
15
―
―
―
YDR
Write time (Max.)
μs
Data retention period
years
45/71
FEDL62Q1500-07
Measuring circuit
Measuring circuit 1
CV : 1.0μF
CL : 1.0μF
CGL : 12pF
CDL : 12pF
VDD
VDDL
XT0 XT1
VSS
A
CV
CL
CGL
CDL
Measuring circuit 2
(*2)
VIH
V
(*1)
Current
load
VIL
VDD
VDDL
VSS
(*1) Input logic circuit to determine the specified measuring conditions
(*2) Measured connecting specified pins
Measuring circuit 3
VIH
(*2)
A
(*1)
VIL
VDD
VDDL
VSS
(*1) Input logic circuit to determine the specified measuring conditions
(*2) Measured connecting specified pins
46/71
FEDL62Q1500-07
Measuring circuit 4
(*2)
A
VDD
VSS
VDDL
(*2) Measured connecting specified pins
Measuring circuit 5
VIH
(*1)
VIL
VDD
VDDL
VSS
(*1) Input logic circuit to determine the specified measuring conditions
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FEDL62Q1500-07
Characteristics graphs
These Graphs on the following pages are references for designing an application.
48/71
FEDL62Q1500-07
IOH vs. VDD-VOH1 (VDD=5V Typ.)
IOH vs. VDD-VOH1 (VDD=5V Typ.)
-40[℃]
25[℃]
85[℃]
105[℃]
5
4
3
2
1
0
-60
-50
-40
-30
-20
-10
0
IOH[mA]
IOH vs. VDD-VOH1 (VDD=3V Typ.)
IOH vs. VDD-VOH1 (VDD=3V Typ.)
-40[℃]
25[℃]
85[℃]
105[℃]
3
2.5
2
1.5
1
0.5
0
-30
-25
-20
-15
-10
-5
0
IOH[mA]
49/71
FEDL62Q1500-07
IOL vs. VOL1 (VDD=5V Typ.)
IOL vs. VOL1 (VDD=5V Typ.)
-40[℃]
25[℃]
85[℃]
105[℃]
5
4
3
2
1
0
0
10
20
30
40
50
IOL[mA]
IOL vs. VOL1 (VDD=3V Typ.)
IOL vs. VOL1 (VDD=3V Typ.)
-40[℃]
25[℃]
85[℃]
105[℃]
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
IOL[mA]
50/71
FEDL62Q1500-07
IOL vs. VOL2 (VDD=5V Typ.)
IOL vs. VOL2 (VDD=5V Typ.)
-40[℃]
25[℃]
85[℃]
105[℃]
5
4
3
2
1
0
0
20
40
60
80
100
IOL[mA]
IOL vs. VOL2 (VDD=3V Typ.).
IOL vs. VOL2 (VDD=3V Typ.)
-40[℃]
25[℃]
85[℃]
105[℃]
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
IOL[mA]
51/71
FEDL62Q1500-07
VDD vs. IIL2 (Typ. VIL2=VSS)
VDD vs IIL2 (Typ. VIL2=VSS)
-40℃
25℃
85℃
105℃
0
-100
-200
-300
-400
-500
-600
-700
1
2
3
4
5
6
VDD[V]
Pull-up resistor
VDD vs. VDD/IIL2 (Typ. VIL2=VSS)
Pull-up resistor
VDD vs VDD/IIL2 (Typ. VIL2=VSS)
-40℃
25℃
85℃
105℃
14
12
10
8
6
4
2
0
1
2
3
4
5
6
VDD[V]
52/71
FEDL62Q1500-07
VDD vs. IIL3 (Typ. VIL3=VSS)
VDD vs IIL3 (Typ. VIL3=VSS)
-40℃
25℃
85℃
105℃
0
-50
-100
-150
-200
1
2
3
4
5
6
VDD[V]
Pull-up resistor
VDD vs. VDD/IIL3 (Typ. VIL3=VSS)
Pull-up resistor
DD vs VDD/IIL3 (Typ. VIL3=VSS)
V
-40℃
25℃
85℃
105℃
350
300
250
200
150
100
50
0
1
2
3
4
5
6
VDD[V]
53/71
FEDL62Q1500-07
Product: ML62Q1530, ML62Q1531, ML62Q1532, ML62Q1533, ML62Q1534, ML62Q1540, ML62Q1541, ML62Q1542,
ML62Q1543, ML62Q1544, ML62Q1550, ML62Q1551,ML62Q1552, ML62Q1553, ML62Q1554
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25οC CPU 16MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
operating frequency of CPU [MHz]
VDD=3V, temp=25οC CPU 16MHz no Wait mode (Typ.)
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz no Wait mode (Typ.)
Stop the clock supply to peripherals.
2.5
2
1.5
1
0.5
0
0
2
4
6
8
10
operating frequency of CPU [MHz]
54/71
FEDL62Q1500-07
Product: ML62Q1530, ML62Q1531, ML62Q1532, ML62Q1533, ML62Q1534, ML62Q1540, ML62Q1541, ML62Q1542,
ML62Q1543, ML62Q1544, ML62Q1550, ML62Q1551, ML62Q1552, ML62Q1553, ML62Q1554
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25οC CPU 24MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
6
5
4
3
2
1
0
0
5
10
15
20
25
30
operating frequency of CPU [MHz]
VDD=3V, temp=25οC CPU 24MHz no Wait mode (Typ.)
Current consumption vs.operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz no Wait mode (Typ.)
Stop the clock supply to peripherals.
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
7
operating frequency of CPU [MHz]
55/71
FEDL62Q1500-07
Product: ML62Q1555, ML62Q1556, ML62Q1557, ML62Q1563, ML62Q1564, ML62Q1565, ML62Q1566, ML62Q1567,
ML62Q1573, ML62Q1574, ML62Q1575, ML62Q1576, ML62Q1577
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25οC CPU 16MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
5
4
3
2
1
0
0
5
10
15
20
operating frequency of CPU [MHz]
VDD=3V, temp=25οC CPU 16MHz no Wait mode (Typ.)
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz no Wait mode (Typ.)
Stop the clock supply to peripherals.
3.5
3
2.5
2
1.5
1
0.5
0
0
2
4
6
8
10
operating frequency of CPU [MHz]
56/71
FEDL62Q1500-07
Product: ML62Q1555, ML62Q1556, ML62Q1557, ML62Q1563, ML62Q1564, ML62Q1565, ML62Q1566, ML62Q1567,
ML62Q1573, ML62Q1574, ML62Q1575, ML62Q1576, ML62Q1577
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25οC CPU 24MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
operating frequency of CPU [MHz]
VDD=3V, temp=25οC CPU 24MHz no Wait mode (Typ.)
Current consumption vs.operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz no Wait mode (Typ.)
Stop the clock supply to peripherals.
3
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
7
operating frequency of CPU [MHz]
57/71
FEDL62Q1500-07
Product: ML62Q1858, ML62Q1859, ML62Q1868, ML62Q1869, ML62Q1878, ML62Q1879
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25οC CPU 16MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
5
4
3
2
1
0
0
5
10
15
20
operating frequency of CPU [MHz]
VDD=3V, temp=25οC CPU 16MHz no Wait mode (Typ.)
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz no Wait mode (Typ.)
Stop the clock supply to peripherals.
3
2.5
2
1.5
1
0.5
0
0
2
4
6
8
10
operating frequency of CPU [MHz]
58/71
FEDL62Q1500-07
Product: ML62Q1858, ML62Q1859, ML62Q1868, ML62Q1869, ML62Q1878, ML62Q1879
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25οC CPU 24MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz Wait mode (Typ.)
Stop the clock supply to peripherals.
6
5
4
3
2
1
0
0
5
10
15
20
25
30
operating frequency of CPU [MHz]
VDD=3V, temp=25οC CPU 24MHz no Wait mode (Typ.)
Current consumption vs. operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz no Wait mode (Typ.)
Stop the clock supply to peripherals.
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
7
operating frequency of CPU [MHz]
59/71
FEDL62Q1500-07
Consumption current of ADC vs. operating voltage
PLL frequency=16MHz temp=25οC ch0 VREF=VDD
consumption current of ADC
(PLL frequency=16MHz temp=25oC ch0 VREF=VDD
)
1.2
1
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
60/71
FEDL62Q1500-07
TEMP vs. Low-speed RC oscillator frequency accuracy 1
without software adjustment (Typ.)
Low-speed RC oscillator frequency accuracy 1
without software adjustment (Typ.)
VDD=1.8V
VDD=3V
VDD=5.5V
4
3
2
1
0
-1
-2
-3
-4
-40
-20
0
20
40
60
80
100
Temp[oC]
TEMP vs. PLL oscillator frequency accuracy 1
without software adjustment (24MHz Typ.)
PLL oscillator frequency accuracy 1
without software adjustment (24MHz Typ.)
VDD=1.8V
VDD=3V
VDD=5.5V
4
3
2
1
0
-1
-2
-3
-4
-40
-20
0
20
40
60
80
100
Temp[oC]
61/71
FEDL62Q1500-07
PACKAGE DIMENSIONS
48pin TQFP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
62/71
FEDL62Q1500-07
52pin TQFP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
63/71
FEDL62Q1500-07
64pin TQFP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
64/71
FEDL62Q1500-07
64pin QFP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
65/71
FEDL62Q1500-07
80pin QFP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
66/71
FEDL62Q1500-07
100pin TQFP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
67/71
FEDL62Q1500-07
100pin QFP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
68/71
FEDL62Q1500-07
REVISION HISTORY
Page
Previous Current
Document
No.
Date
Description
Edition
Edition
FEDL62Q1500-01
FEDL62Q1500-02
Dec 17, 2018
Jan 9, 2019
-
-
1st Revision.
Changed the products under developing (Table 1 ML62Q1500
Group Product List)
1
26
1
1
26
1
Deleted “(TBD)” of Current Consumption 1
Changed the products under developing (Table 1 ML62Q1500
Group Product List)
28
32
28
32
Updated Current Consumption 3
Added comment “*6” to the IOHL.
FEDL62Q1500-03
FEDL62Q1500-04
May 15, 2019
52
52
Updated 16MHz Characteristics graphs
Updated 24MHz Characteristics graphs
Added 16MHz and 24MHz Characteristics graphs
Updated the descriptions of DMA and Functional Timer.
53,55
-
53,55
56,57
3,4
3,4
Changed IOUTH (total) and IOUTL (total) of Absolute Maximum
Ratings to 180mA from 150mA.
May 31, 2019
25
25
32
24
32
24
Corrected comment of the IOHLs.
Changed termination of unused pins
Added parameter “Operating temperature(Chip-Junction)”
in Recommended Operating Conditions
25
25
Removed the section “Operation Confirmed Crystal
Unit(32.768kHz)”.
This section is mentioned in Applications Note;
“Operation-confirmed oscillator for ML62Q1000 series”.
25
26
41
Added thermal characteristics section
FEDL62Q1500-05
Mar 19, 2020
40
Added comments and notes to the reset characteristics
Revised overall of “Power On Reset” section as “Slope of
Power supply and Power On Reset” section.
The major revisions are
40
42
Added definitions of Power on rising/falling slope, Power on
voltage, CPU operation start time, and added Note.
Corrected typo
*
*
4,8,9
4,8,9
Changed comment for UART.
Corrected pin name of Buzzer and description of SA-ADC in
Table 4.
23
23
FEDL62Q1500-06
FEDL62Q1500-07
Jul 15, 2020
41
41
Corrected comment in waveform of P00/TEST0.
Changed company name
1
-
1
70
*
Added Notes in general description section.
Added Notes for product usage
Corrected typo
May 22, 2022
*
69/71
FEDL62Q1500-07
Notes for product usage
Notes on this page are applicable to the all microcontroller products.
For individual notes on each LAPIS Technology microcontroller product, refer to [Note]
in the chapters of each user's manual.
The individual notes of each user’s manual take priority over those contents in this page if they are different.
1. HANDLING OF UNUSED INPUT PINS
Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong operation or
increasing the current consumption due to noise, etc. If the handlings for the unused pins are described in the chapters,
follow the instruction.
2. STATE AT POWER ON
At the power on, the data in the internal registers and output of the ports are undefined until the power supply voltage
reaches to the recommended operating condition and "L" level is input to the reset pin.
On LAPIS Technology microcontroller products that have the power on reset function, the data in the internal registers
and output of the ports are undefined until the power on reset is generated.
Be careful to design the application system does not work incorrectly due to the undefined data of internal registers and
output of the ports.
3. ACCESS TO UNUSED MEMORY
If reading from unused address area or writing to unused address area of the memory, the operations are not guaranteed.
4. CHARACTERISTICS DIFFERENCE BETWEEN THE PRODUCTS
Electrical characteristics, noise tolerance, noise radiation amount, and the other characteristics are different from each
microcontroller product.
When replacing from other product to LAPIS Technology microcontroller products, please evaluate enough the
apparatus/system which implemented LAPIS Technology microcontroller products.
5. USE ENVIRONMENT
When using this product in a high humidity environment and an environment where dew condensation, take
moisture-proof measures.
70/71
FEDL62Q1500-07
Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application notes, etc.), and
ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within the ranges specified. LAPIS
Technology disclaims any and all liability for any malfunctions, failure or accident arising out of or in connection with the use of LAPIS
Technology Products outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within such
usage conditions specified ranges, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent
personal injury, fire or the other damage from break down or malfunction of LAPIS Technology Products, please take safety at your own
risk measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing
backups and fail-safe procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard operation of
semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software,
and information in the design of your product or system. And the peripheral conditions must be taken into account when designing circuits
for mass production. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising
from the use of these circuits, software, and other related information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology or any third
party with respect to LAPIS Technology Products or the information contained in this document (including but not limited to, the Product
data, drawings, charts, programs, algorithms, and application examples、etc.). Therefore LAPIS Technology shall have no responsibility
whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,
gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications requiring a
high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative and must obtain written
agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic lights, fire/crime prevention,
safety equipment, medical systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all
liability for any losses and damages incurred by you or third parties arising by using the Product for purposes not intended by us. Do not use
our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and
submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS
Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility for any damages arising
from any inaccuracy or misprint of such information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. LAPIS
Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and
provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations
and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or LAPIS Technology's
Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2018 – 2022 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
71/71
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