ML7386 [ROHM]
ML7386/ML7386B是支持315MHz～960MHz频段的数据发送专用无线LSI。ML7386支持10mW模式，ML7386B支持10mW和1mW两个功率模式。;
| 型号： | ML7386 |
| 厂家： | 
ROHM |
| 描述： | ML7386/ML7386B是支持315MHz～960MHz频段的数据发送专用无线LSI。ML7386支持10mW模式，ML7386B支持10mW和1mW两个功率模式。 无线 |
| 文件： | 总53页 (文件大小：626K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL7386B-08
Issue Date: Mar. 06, 2020
ML7386/7386B
Sub GHz band wireless transmitter IC
■Overview
ML7386/ML7386B are a low power RF transmitter IC for narrowband system. It includes RF part, MOD part and
HOST interface part in single-chip. It supports various frequency band from 200 MHz to 972 MHz. It is possible to
use as wireless alarm and security systems, low power telemetory and industrial remote control systems.
ML7386 supports only 10mW mode. ML7386B supports both 10mW and 1mW mode.
■Features
• Support 200 MHz to 972 MHz operation. (*1)
• Support narrow band systems with channel spacing of 12.5 or 25 kHz
• High accurate modulation implemented by direct modulation scheme using fractional-N PLL
• Multiple modulation scheme : 2-FSK/MSK
• Data speed : 2400/4800/7200 bps (NRZ coding)
Extended data rate function can set 1.2kbps to 100kbps (NRZ coding) (*1)
• Supports NRZ code and Manchester code
In case of using Manchester code, DCLK frequency becomes half to NRZ coding case.
• Programmable frequency deviation: ±0.6kHz to ±100kHz (*1)
• Configurable data polarity
• On chip oscillation cell: 16MHz to 36MHz (*1)
• Support direct input from TCXO: 16MHz to 36MHz (*1)
• Frequency trimming function (Fractional-N PLL architecture enables fine tuning of synthsizer frequency)
• Synchronous serial peripheral interface (SPI)
• Built in voltage regulated Power Amp (PA) and power control function
ML7386 suppoers 10mW mode only
ML7386B supports 10mW and 1mW mode.
• Test Pattern generation (PN9, CW, 0/1, all-1, all-0 pattern)
• Power supply voltage : 2.0 V to 3.6V (10mW mode)
1.8 V to 3.6V (1mW mode )
• Operating temperature -40 to +85 ˚C
• Power consumption (tentative)
Deep Sleep Mode 0.03 uA (Typ.) (Register non-retain)
Sleep Mode
Idle Mode
Stop Mode
TX (10mW)
TX (1mW)
0.3 uA (Typ) (Register retain)
0.25 mA (Typ) (Oscillator cell OFF)
1.0 mA (Typ.) (Transmitter OFF)
23.8 mA (Typ.) (TCXO mode)
6.4 mA (Typ.) (TCXO mode)
• Package
28 pin WQFN 4.0mm x 4.0mm x 0.8mm
Pb free, RoHS compliant
*1: These specifications show the setting range base on the ML7386 and ML7386B function.
Performance is guaranteed under the condition specified in “Performance guarantee condition”
If using ML7386 and ML7386B under the condition not specified in “Performance guarantee condition”,
evaluation and confirmation should be required under user specific condition.
1/52
FEDL7386B-08
ML7386/ML7386B
■Description Convention
1) Numbers description
‘0xnn’ indicates hexadecimal and ‘0bnn’ indicates binary
Example: 0x11=17 (decimal), 0b11=3 (decimal)
2) Register description
[<register name>: <register address>] register
Example: [RF_MODE: 0x00] register
Register name: RF_MODE
Register address: 0x00
3) Bit name description
<bit name> ([<register name>: <register address> (<bit location>)])
Example: txtest_en([TXD_SEL: 0x02(3)])
Bit name: test_en
Register name: TXD_SEL
Register address: 0x02
Bit location: bit3
2/52
FEDL7386B-08
ML7386/ML7386B
■Block Diagram
C1 C1
1.8V to 3.6V
VDD_PA
Registers
VDD_I
REG_CORE
VDD_RF
VDD_VCO
VDD_CP
REG_OUT
SSN
SCK
SDI
VBG
4
RF_BB(1.5V)
Regulator
SDO
C5
LP_CTLN
REG_PA
PA Regulator
R2
LPF
C4
C9
C10
L4
L3
L1
C1
Fractional―N
C3
PA
MOD
PLL
TXD
10dBm
ANT
TXC
LD
L2
C2
ATEST
VDD_VCO
C8
CLK_GEN
Oscillation/
Input Switch
Reset
RSTN
VB EXT
GND_PA
VCO_IND_N
VCO_IND_P
XO
XI
TCXO
R1
L5
26 MHz
C6
C7
Fig.1 Block diagram
3/52
FEDL7386B-08
ML7386/ML7386B
■PIN Assignment
28 pin WQFN
22
23
24
25
26
27
28
14
１3
１2
11
10
9
14
１3
１2
11
10
9
22
23
24
25
26
27
28
ANT
TXC
TXD
SSN
SCK
SDI
TXC
TXD
SSN
SCK
SDI
ANT
GND_PA
GND_PA
VDD_RF
VDD_RF
VCO_IND_N
VCO_IND_P
VCO_IND_N
VCO_IND_P
TOP VIEW
BOTTOM VIEW
GND
GND
VB_EXT
VB_EXT
SDO
LD
SDO
LD
8
8
VDD_VCO
VDD_VCO
Fig.2 PIN ASSIGNMENT
NOTE: Pattern shown in the centre of the chip is located at bottom side of the chip (GND PAD)
4/52
FEDL7386B-08
ML7386/ML7386B
■PIN Definitions
Symbols
IRF
ORF
IA
IOSc
OOSc
I
: RF input
: RF output
: Analog input
: Oscillator input
: Oscillator output
: Digital input
: Digital output
: Schmitt Trigger input
O
Is
●RF / Analog pins
Pin
Active
Level
Pin name
No
I/O
at reset
Detail function
PLL loop filter pin
1
LPF
IRF
ORF
ORF
-
-
-
-
O
O
-
3
ATEST
Analog test output
22
25
26
ANT
RF signal output to antenna
VCO_IND_N
VCO_IND_P
-
-
Pin for external inductor of VCO
Pin for external inductor of VCO
-
-
External capacitor pin for local oscillator
stability
38
VB_EXT
-
-
-
5/52
FEDL7386B-08
ML7386/ML7386B
●SPI interface pins
Pin
Active
Level
Pin name
No
I/O
O
at reset
Detail function
9
SDO
SDI
-
-
L
I
SPI data output
10
I
SPI data input
SPI clock input
11
12
SCK
SSN
Is
Is
P
L
I
I
SDI is captured at rising edge
SDO is output at falling edge
SPI enable input
●TX data interface pins
Pin
Active
Level
Pin name
No
I/O
I
at reset
Detail function
13
14
TXD
TXC
-
I
TX data input
TX clock output
TXD is captured at rising edge
O
P
L
●Regulator pinst
Pin
No
Active
Level
Pin name
I/O
at reset
Detail function
Monitor pin for power supply to digital core
(typ.1.5V) Connection for external capacitor
with 10uF
4
REG_CORE
-
-
-
Back bias pin. Connection for external
capacitor with 0.1 μF.
Regulator output (typ.1.5V) Connection for
external capacitor with 6.8 μF
Regulator output for PA. (1.5V to 2.0V)
Connection for external capacitor with 1 uF.
18
19
21
VBG
-
-
-
-
-
-
-
-
-
REG_OUT
REG_PA
6/52
FEDL7386B-08
ML7386/ML7386B
●Miscellaneous
Pin
No
Active
Level
Pin name
I/O
at reset
Detail function
External clock (TCXO) input pin.
*Fixed to GND level when crystal oscillator is
used.
26MHoecillator pin2
*Fixed to GND level when external clock
generator is used
26MHz oscillator pin1
*Fixed to GND level when external clock
generator is used
PLL Lock detect pin
L: PLL unlock status
H: PLL lock status
Hardware reset
L: Rest, stop
H: Normal operation
Sleep mode control pin
L: Deep sleep mode
5
TCXO
XO
IA
-
I
6
7
Oosc
Iosc
O
-
O
I
XIN
-
8
LD *1
RSTN
LP_CTLN
H
L
L
L
I
15
16
Is
I
I
H: Exit from deep sleep mode
*1 Activated when write 0x18 to the [RF_MODE: 0x00] register.
●Power Supply
Pin
No
Active
Level
Pin name
VDD_CP
VDD_IO
I/O
at reset
Detail function
Power supply pin for PLL charge pump block.
(Connection for REG_OUT pin. Typ.1.5V)
Power supply for digital IOs
(Input voltage from 1.8 V to 3.3 V)
Power supply pin for PA block.
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17
20
23
24
28
VDD_PA
GND_PA
VDD_RF
VDD_VCO
(Input voltage from 1.8V to 3.3V)
GND pin for PA block.
Power supply pin for RF blocks.
(Connection for REG_OUT pin. Typ.1.5V)
Power supply pin for VCO block.
(Connection for REG_OUT pin. Typ.1.5V)
7/52
FEDL7386B-08
ML7386/ML7386B
●Unused pins
Followings are recommendation for unused pins
Pin Name Recommendation
XO
Fixed to GND (When TCXO is used)
Fixed to GND (When TCXO is used)
Fixed to GND (When Crystal OSC is used)
Left OPEN
XI
TCXO
ATEST
(Note)
If input pins are high-impedence state and leave open, excess current could be drawn. Care must be taken that
unused input pins and unused I/O pins should not be left open.
8/52
FEDL7386B-08
ML7386/ML7386B
■Electrical Characteristics
●Absolute Maximum Ratings
Item
Symbol
VDDIO
Condition
Rating
Unit
V
Power Supply (I/O) (*1)
Power Supply (RF) (*2)
-0.3 to +4.6
-0.3 to +2.0
VDDRF
V
Digital Input Voltage
VDIN
-0.3 to VDDIO+0.3
V
RF Input Voltage
VRFIN
VAIN
VAIN2
VDO
-0.3 to VDDRF+0.3
-0.3 to VDDIO+0.3
-0.3 to VDDRF+0.3
-0.3 to VDDIO+0.3
V
V
V
V
Analog Input Voltage
Analog Input Voltage2 (*3)
Digital Output Voltage
Ta=-40 to 85°C
GND=0V
RF Output Voltage
VRFO
-0.3 to VDDRF+0.3
V
Analog Output Voltage
Analog Output Voltage2 (*4)
Digital Input Current
RF Input Current
VAO
VAO2
IDI
-0.3 to VDDIO+0.3
-0.3 to VDDRF+0.3
-10 to +10
-2 to +2
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
IRF
Analog Input Current
Analog Input Current2 (*3)
Digital Output Current
RF Output Current
IAI
-2 to +2
IAI2
IDO
IRFO
IAO
IAO2
Pd
-2 to +2
-10 to +10
-2 to +2
Analog Output Current
Analog Output Current2 (*4)
Power Dicipatin
-2 to +2
-2 to +2
Ta=+25°C
-
500
Storage Temperature
Tstg
-55 to +125
(*1) VDD_IO, VDD_PA pins
(*2) VDD_RF, VDD_VCO, VDD_CP pins
(*3) XI pins
(*4) XO pin
9/52
FEDL7386B-08
ML7386/ML7386B
●Recommended Operating Conditions
Item
Symbol
Conditions
Min
Typ
Max
Unit
Power Supply (I/O)
VDDIO
VDD_IO, VDD_PA pins
1.80
2.70
3.60
V
VDD_RF, VDD_VCO,
VDD_CP pins
Power Supply (RF)
VDDRF
1.45
1.50
1.55
V
RF characteristic temperature
Operating Temperature
Ta
Ta
-
-25
-40
−
+25
+25
−
+85
+85
20
°C
°C
ns
-
Rising time Digital Input
Falling time Digital Input
Output loads Digital Ouput
TIR1
TIF1
CDL
Digital input pins (*1)
Digital Input pins (*1)
All Digital Output pins
−
−
20
ns
−
−
50
pF
Master Clock1
Master Clock2
FMCK1
FMCK2
XIN, XOUT pins (*2)
TCXO pin (*2)
-4ppm
-4ppm
26
26
+4ppm
+4ppm
MHz
MHz
-400ppm
-200ppm
-200ppm
7200
4800
2400
+400ppm
+200ppm
+200ppm
TX clock Output
FCLKOUT
TXC pin
Vpp
SPI clock frequency
SPI clock duty ratio
FSCLK
DSCLK
SCLK pin
SCLK pin
0.1
45
2
8
MHz
%
50
55
ANT pin
12.5kHz channel spacing
RF frequency
FRF1
426.2500
−
426.8375
Mhz
(*1) Those pines with symbol I or Is at I/Ocolumn in the Pin Definition section
(*2) Minimum and maximum limit are defined in standards. Please refer standards, i.e ARIB STD-T67, RCR
STD-30 and so on.
10/52
FEDL7386B-08
ML7386/ML7386B
●Power Consumption
(Condition: VDDIO=1.8V to 3.6V, Ta=-40˚C to + 85˚C, Fmck=26MHz)
Item
Symbol
Conditions
Min
Typ (*2)
Max
Unit
Deep Sleep state
(Registers are not retained)
IDDS1
−
0.03
15.0
µA
Sleep state
(Registres are retained)
IDDS2
IDD1
IDD2
IDD3
IDD4
−
−
−
−
−
0.3
0.25
0.65
23.8
6.4
30.0
1.5
µA
mA
mA
mA
mA
Idle state (*3)
(OSC circuit OFF, RF OFF)
Power Consumption (*1)
Stop state
(OSC circuit ON, RF OFF)
3.0
TX state (10mW) (*4), (*5)
TX state (1mW) (*4), (*5)
52.0
20.0
(*1) Power consumption is sum of current consumption of all power supply pins
(*2) “Typ” value is centre value under condition of VDDIO=2.7V, 25 °C .
(*3) If using SPI access with 8 MHz speed, specified current is added to the each value.
(*4) SPI access speed is 2 MHz and data transmission speed at 4800 bps
(*5) In case of using TCXO. In case of using crystal, adding 0.3mA under the typical condtiion.
11/52
FEDL7386B-08
ML7386/ML7386B
●DC Characteristics
(Condition: VDDIO=1.8V to 3.6V, VDDR1=1.45V to 1.55V, Ta=-40˚C to + 85˚C, Fmck=26MHz)
Item
Symbol
Conditions
Min
Typ (*2)
Max
Unit
VDDIO
* 0.77
VIH1
(*1), (*2)
XI pin
−
VDDIO
V
Voltage Input High
VDDRF
* 0.9
VIH2
VIL1
VIL2
VI
−
−
VDDRF
V
V
VDDIO
* 0.18
(*1), (*2)
XI pin
0
0
Voltage Input Low
Input Voltage
VDDRF
* 0.10
−
V
TCXO pin
(*2)
0.8
−
−
VDDRF
Vp-p
V
Threshold Voltage High
level
VDDIO
* 0.77
VT+
1.2
Threshold Voltage Low
level
VDDIO
* 0.18
VT-
(*2)
0.8
−
V
IIH1
IIL1
VIH = VDDIO (*1), (*2)
VIL = 0 V (*1), (*2)
-2
-2
−
−
2
2
μA
μA
Input Leakage Current
VDDIO
* 0.78
Voltage Ouput level H
Voltage Ouput level L
VOH
VOL
IOH=-4 mA (*3)
IOL= 4 mA (*3)
Sleep state
−
−
VDDIO
0.3
−
V
V
0
1.3
1.5
1.5
6
V
−
−
−
−
−
−
REG_CORE
Regulator output
voltage
Other states
V
−
REG_OUT Exclude sleep state
V
−
CIN
COUT
CRFI
Input pins (*1),(*2)
Output pins (*3)
pF
pF
pF
−
9
−
RF input pins (*4)
9
−
Input Capacitance
CRFO
CAI
RF output pins (*5
9
9
pF
pF
−
−
−
−
Analog input pins (*6)
(*1) Pins with symbol I at the I/O column in the Pin Definitions section
(*2) Pins with symbol Is at the I/O column in the Pin Definitions section
(*3) Pins with symbol O ar the I/O column in the Pin Definitions section. XO pin is excluded
(*4) Pins with symbol IRF at the I/O column in the Pin Definitions section
(*5) Pins with symbol ORF at the I/O column in the Pin Definitions section
(*6) Pins with symbol IA at the I/O column in the Pin Definitions section
12/52
FEDL7386B-08
ML7386/ML7386B
●RF Characteristics
[Performance guarantee condition]
Data Rate
:
:
:
:
:
:
:
2400 bps / 4800 bps / 7200 bps
2-FSK/MSK
12.5 kHz / 25.0 kHz
426.0250 MHz to 426.8375MHz
1.8V to 3.6V (unless specifing alternate condition)
-25°C to 85 °C (unless specifing alternate condition)
26 MHz (unless specifing alternate condition)
Modulation scheme
Channel spacing
Frequency
Power supply
Temperatute
Master clock
[Start up time]
Item
Condition
LP_CTLN = H
Min
Typ
Max
Unit
Regulator start up time
-
600
1500
µs
Crystal oscillator start up time
(*1)
26 MHz
-
715
1115
µs
PLL amd PA start up time
(TCXO mode :IDLE mode)
TX start up time (*2)
-
-
1460
50
1600
100
µs
µs
(OSC mode :STOP mode)
PLL lock up time (*3)
frequency change in TX state
[Transmitter performance]
Item
TX Power (10 mW mode)
(*4)
Condition
Min
Typ
Max
Unit
[PA_ADJ:0x10]=0xnn
5
−
12
mW
TX Power (1 mW mode)
(*4), (*7)
[PA_ADJ: 0x10]=0xnn
0.5
−
1.2
-40
mW
dBc
[PA_BIAS:0x16]=0xnn
Adjacent Channel Power Ratio
[ACPR] (*5)
±12.5kHz offset ± 4.25 kHz bandwidth
4800 bps, Fdev=2.1 kHz
-48
Occupied bandwidth [OBW]
99%, 4800 bps, Fdev=2.1 kHz
4.0
−
−
8.5
kHz
kHz
Frequency deviation range (*6)
Modultation index
±0.6
±4.2
MSK
0.49
0.50
-32
0.51
-26
-
4800 bps, Fdev=1.2 kHz
10mW output
−
dBm
Spurious emission radiated CW
PN9, 10mW output
−
-32
-26
dBm
Adjacent spurious emission
±112.5kHz offset ± 50 kHz bandwidth
4800 bps, Fdev=2.1 kHz
13/52
FEDL7386B-08
ML7386/ML7386B
(*1) The time to output rectangular clock from oscillation circuit into the stable counter from setting STOP mode
(0x10) to [RF_MODE:0x00] register. After counting 0x1FFF, the oscillation block output to internal circuits
and enable to start TX operation.
Crystal oscillator
Clcok stable time
start up time
Output of oscillation
circuit
Gated output of
oscillation circuit
400 µs
Stable Counter
315 µs
Expired at 0x1FFF (26MHz)
Clock Stable Flag
Internal Clock
(*2) The time to converge in ±10 kHz of PLL frequency from setting ACT mode (0x18) into [RF_MODE:0x00]
register. LD pin will rise before PLL is converged.
(*3) When in operating F0 with TX state, the transition time to converge in ±10 kHz in PLL frequency (F1).
(*4) Fine adjustment of PA_ADJ value is required because of variation of external components or PCB. Output
power may be varied depending on temperature or power supply variation. It is recommended to adjust
[PA_ADJ:0x10] register in order to meet required power.(*5) ACPR performance is result after adjusting
channel frequency within +/-0.25ppm accuracy.
(*6) Frequency deviation range and RF channel frequency are showing possible range, it is not guranteed the all
performance described in this data sheet.
(*7) 1mW mode is applied to ML7386B only.
14/52
FEDL7386B-08
ML7386/ML7386B
■Timing Characteristics
●SPI interface
(Condition: VDDIO=1.8V to 3.6V, Ta=-40˚C to + 85˚C)
Item
Symbol
FSCLK
Condition
Min
0.1
125
20
Typ
2
Max
8
Unit
SCLK clock frequency
SSN input setup time
SSN input hold time
SCK high pulse width
SCK low pulse width
SDI input setup time
SDI input hold time
SSN assert interval
MHz
TSSNSU
TSSNH
−
−
ns
ns
−
−
ns
ns
ns
ns
ns
TWSCKH
TWSCKL
TSDISU
TSDIH
56
−
−
Load capacitance
CL=20pF
56
−
−
5
−
−
15
−
−
TSSNAI
125
−
−
SCK high
pulse width
SCK
1 clock
ns
SDO output delay
TSDOH
−
NOTE: All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%.
SSN
TSSNH
FSCLK
TSSNSU
TWSCKL
SCK
TWSCKH
TSDISU
TSDIH
SDI
MSB IN
BITS6-1
LSB IN
TSDOH
TSDOH
TSDOH
BITS6-1
LSB OUT
MSBOUT
SDO
SSN
TSSNAI
SCK has to be “L” when it is not active.
15/52
FEDL7386B-08
ML7386/ML7386B
SPI Data format
SCK
SSN
SDI
Write data field (8 bit)
Address field
(6 bit)
LD
“1
W
SCK
SSN
SDI
Dummy write (8 bit)
Address field
(6 bit)
LD
“1
R
“0”
SDO
Read data field (8 bit)
16/52
FEDL7386B-08
ML7386/ML7386B
●TX Data interface
(Condition: VDDIO=1.8V to 3.6V, Ta=-40˚C to + 85˚C)
Item
Symbol
Condition
Min
Typ
Max
Unit
TXD Input setup time
TDISU
5
µs
−
−
Load capacitance
CL=50pF
TXD Input hold time
TXC clock frequency
TDIH
5
µs
−
−
-400 ppm
-200 ppm
-200 ppm
7200
4800
2400
+400 ppm
+200 ppm
+200 ppm
FDCLK
kHz
NOTE: All timing parameter is defined at voltage level of VDDIO x 20% and VDDIO x 80%.
FDCLK
DCLK
TDISU
TDIH
TXD
VALID
VALID
VALID
[Delay timing of demodulated RF signal]
T baud [μs]
TXC
TXD
A
Don’t Care
B
B
Fdev transition
time
A
RF signal
A
B
[]T_PLL_TR:0x07]
10us(max)
10us(max)
Setting value *(4/26MHz) *10us
T baud + 10[μs]
[Note]
After data input is end at TX data interface, valid RF signal is still transmitting due to demodulation delay.
When transit from ACT mode by [RF_MODE: 0x00] register, this delay timing should be considered.
17/52
FEDL7386B-08
ML7386/ML7386B
●Power ON
(Condition: VDDIO=1.8V to 3.6V, Ta=-40˚C to + 85˚C)
Item
Symbol
Condition
All power supply pins
(After power on)
Min
Typ
Max
Unit
RESETN delay time
(Power on)
TRDL
1.6
ms
−
−
RESETN assert time
(pulse width)
TRPLS
TLDL
TLRH
200
100
1.5
ns
µs
ms
−
−
−
−
−
−
All power supply pins
(After power on)
LP_CNLN delay time
(Power on)
LP_CTLN rising time
VDD=”H”
NOTE: All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%.
VDD
GND
VDD
TRDL
TRPLS
RSTN
TLDL
TLRH
LP_CTLN
SPI Access
prohibited
SPI Access
prohibited
SPI Access
possible
SPI Access
possible
18/52
FEDL7386B-08
ML7386/ML7386B
●Low Power Control interface
(Condition: VDDIO=1.8V to 3.6V, Ta=-40˚C to + 85˚C)
Item
Symbol
Condition
Min
Typ
Max
Unit
LP_CTLN falling time
TLRL
TLPLS
TLRH
VDD=”H”
VDD=”H”
VDD=”H”
0
µs
−
−
LP_CTLN pulse width
LP_CTLN rising time
1200
1.5
µs
−
−
−
−
ms
NOTE: All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%.
VDD
GND
VDD
TLRH
TLRL
RSTN
TLPLS
LP_CTLN
Deep sleepstate
19/52
FEDL7386B-08
ML7386/ML7386B
●State Transition
ML7386/ML7386B has 5 operating modes. Except for Deep Sleep state, state transition is available by
[RF_MODE: 0x00] register.
•
•
•
•
•
Deep Sleep state:
Sleep state:
Idle state:
Stop state:
ACT state:
Shut down the LSI and current consumption is minimum.
Retain register values and minimized current consumption.
Register access is available and oscillation circuit is off state.
Register access is available and oscillation circuit is on state.
RF circuit is on state.
Block condition in each state is shown as below table.
Oscillation
Circuit
OFF
RF
Circuit
OFF
OFF
OFF
OFF
Current
(Typ.)
0.03μA
0.3μA
0.25mA
State
Registers
SPI Access
Deep Sleep
Sleep
Not Retain
Retain
Retain
Not available
Not available (*1)
Available
OFF
OFF
ON
Idle
Stop
Retain
Available
0.65mA
23.8mA(10mW)
6.4mA (1mW)
Act
Retain
Available
ON
ON
*1: In the Sleep state, only the Idle state transition command is acceptable.
[State Diagram]
vco_ovr_cal_en = 0b1
([VCO_CAL_EN:0x12(0)])
ACT
VCO_OVER_CAL
Auto-transition,
after completion
rf_mode[7:0] = except for 0x18
[RF_MODE:0x00]
rf_mode[7:0] = 0x18
[RF_MODE:0x00]
vco_seq_cal_en = 0b1
([VCO_CAL_EN:0x12(1)])
RSTN=0
Stop
VCO_CAL
Auto-transition,
after completion
rf_mode[7:0] = 0x10 or 18
[RF_MODE:0x00]
or
vco_seq_cal_en=0b1
([VCO_CAL_EN:0x12(1)]
rf_mode[7:0] = except for 0x10 or 18
[RF_MODE:0x00]
RSTN=1
Idle
Power OFF
Reset
RSTN=0
rf_mode[7:0] = 0x40
[RF_MODE:0x00]
Any SPI access
LP_CTLN=1
LP_CTLN=0
Register control
Signal control
Sleep
Deep Sleep
State not register
retain
20/52
FEDL7386B-08
ML7386/ML7386B
Required wait time at each state transition is shown as below table.
Current
state
Sleep
Sleep
Sleep
Idle
State
to be moved
Idle
rf_mode[7:0]
[RF_MODE:0x00]
Required Wait Time [ms]
No.
Possibility
(*2)
1.5
2.3
-
0.1
0.8
2.715
0.1
0.1
1.6
0.12
0.1
0.1
1
2
3
4
5
6
7
8
9
O
O
X (*1)
O
O
O
O
O
O
O
0x00
0x10
-
Stop
ACT
Sleep
Stop
ACT
Sleep
Idle
ACT
Sleep
Idle
Stop
0x40
0x10
0x18
0x40
0x00
0x18
0x40
0x00
0x10
Idle
Idle
Stop
Stop
Stop
ACT
ACT
ACT
10
11
12
O
O
*1: The state transition from Sleep state to ACT state is proghibited. Once Idle transiion is necessary.
In this case, total transition time 1.5ms + 2.715ms = 4.215ms
*2: During the waiting time, [RF_MODE:0x00, [CLK_SEL:0x0E]and [VCO_CAL_EN:0x12] register accesses
are prohibited.
[Off to Idle]
The following shows the operation timing from power off state to Idle state.
VDD
0.1ms
LP_CTLN
Regulator start up time
1.5ms
RSTN
State
Off
Transition time
Deep Sleep
Idle
SPI Access
prohibited
SPI Access
possible
21/52
FEDL7386B-08
ML7386/ML7386B
[Sleep to Idle]
The following shows the operation timing from sleep state to Idle state.
Sleep release
SPI access to any rgister
SSN
Transition time
1.5ms
Idle
State
Sleep
RF regulator start up time
SPI Access possible
SPI Access
prohibited
The following register access is prohibited.
[RF_MODE:0x00],
[CLK_SEL:0x0E],
Some register access is
restricted.
[VCO_CAL_EN:0x12]
[Idle to ACT]
The following shows the operation timing from Idle state to ACT state.
Set [RF_MODE:0x00] = 0x18
SSN
0 μs when using TCXO
RF start up time
1115μs
1600μs
Transition time
ACT
State
Sleep
Stop
TXC start flag
(Internal signal)
TXC
Half boaud rate clock
104μs @ 4800bps
22/52
FEDL7386B-08
ML7386/ML7386B
[ACT to Sleep]
The following shows the operation timing from ACT state to Sleep state.
Set [RF_MODE:0x00] = 0x40
SSN
120μs
State
ACT
RF off time
Sleep
●VCO calibration
VCO calibration is the function to correct the VCO oscillation frequency due to the variation of chip components.
Please refer “ML7386/ML7386B application manual”.
23/52
FEDL7386B-08
ML7386/ML7386B
■Registers
●Register setting flow
The following shows the register setting flow which uses test pattern transmission as a reference.
For details of setting value to each register,
please refer to the “ML7386Family_Register_Tool20150106en.xls”.
Register
Address
0x0E
0x01
0x02
0x03
0x04
0x05
0x06
Setting
value
0x00
0x00
0x08
0x10
0xC4
0x4E
0x06
No
Remark
1
2
3
4
5
6
7
Select clock source (“Xtal”=0x00, “TCXO”=0x01)
Baud rate setting (2400bps)
Select test pattern (“PN9”=0x08, “CW”=0C, “1010”=0x09)
Channel frequency setting (426.250MHz)
Execute VCO calibration
Refer “ML7386/ML7386B Application manual”
8
9
10
11
12
13
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x1A
0x31
0x44
0x50
0x54
0xFF
Frequency deviation setting (2.1kHz)
Frequency deviation transition time setting (2400bps)
Transmission power adjustment
14
15
16
17
18
0x10
0x16
0x17 *1
0x2A *1
0x00
0x02
0x55
0x00
0x00
0x18
Select PA (“1mW”=00, ”10mW”=0x01)
PA bias setting (“1mW”=02, ”10mW”=0x07)
Set ACT state
Data transmitted after 2.715ms
19 0x00 0x00
Stop transmission and move to Idle state.
*1: These registers are supported for ML7386B.
24/52
FEDL7386B-08
ML7386/ML7386B
●Register map
The space shown as gray highlighted part are not implemented in LSI or reserved bits. The space shown as lined
mesh part are required to fill fixed value. The address not exisit in the memory map is not accesible.
: Implemented as functionable register (Read and Write)
: Impelemted as reserved bits
: Impelemted as required to fill fixed value
Bit assignment
Address
Symbol
RF_MODE
BR
TXD_SEL
PLL_N
PLL_FL
PLL_FM
PLL_FH
PLL_FIT
F_DEV0
F_DEV1
F_DEV2
F_DEV3
F_DEV4
Function
RF state setting
Baud Rate setting
Data configuration
Default
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x00
0x00
0x00
0x10
0xC4
0x4E
0x06
0x00
0x1A
0x32
0x44
0x52
0x54
PLL N parameter setting
PLL Frequency setting (low byte)
PLL Frequency setting (middlebyte)
PLL Frequency setting (high4 bits)
PLL frequency adjustment
Frequency deviation #0 setting
Frequency deviation #1 setting
Frequency deviation #2 setting
Frequency deviation #3 setting
Frequency deviation #4 setting
Frequency deviation transition time
setting
0x0D
T_PLL_TR
0x86
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x1A
0x2A
CLK_SEL
SRST
PA_ADJ
clock configuration
Software reset setting
PA gain adjustment
VCO calibration value R/W control
VCO calibration execution
PLL charge pump current control
0x00
0x00
0x77
0x20
0x00
0x0F
0x28
0x15
0x16
0x01
0x00
0x07
w
w
w
w
w
w
w
w
VCO_CAL
VCO_CAL_EN
PLL_CPI
BR_FLEX_SET_L Extended baud rate setting (low byte)
BT_FLEX_SET_H Extended baud rate setting (high byte)
PA_BIAS
PA_SEL
F_DEV_RESO
PA_REG
PA bias control
PA selection
Frequency deviation resolution setting
PA requlator output setting
[Note] All register access is available when RSTN=”H”.
The method to access each register described in “SPI Data format” section.
25/52
FEDL7386B-08
ML7386/ML7386B
0x00[RF_MODE]
Function: RF state setting
Address: 0x00
Defalut value: 0x00
Default
R/W
Bit
7-0
Symbol
Description
Value
RF state setting
x40: Sleep state (Regurator OFF, OSC OFF)
x18: ACT state (TX ON)
rf_mode[7:0]
0000_0000
R/W
x10: Stop state (Requlator ON, OSC ON)
x00: Idle state (Regulator ON, OSC OFF)
[Notes]
1. When write any other data shown in the list, ML7386 will move to Idle state
2. .If executing VCO active calibration([VCO_CAL_EN:0x12]=0x01), 2.8ms wait is required after ACT state
command execution.
3. During state trnsition time, SPI access is prohibited. Please refer to the “State Transition”.
0x01[BR]
Function: Baud rate setting
Address: 0x01
Default Value 0x00
Default
Value
0000_0
Bit
7-3
Symbol
Description
R/W
R/W
Reserved
Reserved
Baud rate setting
0b000: 2400 bps
0b001: 4800 bps
0b010: Reserved
0b011: 7200 bps
0b100: Reserved
0b101: Reserved
2-0
baud_rate [2:0]
000
R/W
0b11*: Valid [BR_FLEX_L/H: 0x14/15] register setting
[Note]
1. When using 26MHz as a master clock, this register setting is vaild. If using any other master clock frequency,
baud_rate[2:0] should be set as 0b11* and data rate is set by [BR_FLEX_SET_/HL:0x14/15] registers.
26/52
FEDL7386B-08
ML7386/ML7386B
0x02[TXD_SEL]
Function: Data configuration
Address: 0x02
Default Value 0x00
Default
R/W
Bit
7
Symbol
txdinv
Description
Value
Data polality
0: Positive (When TXD=”1”, plus frequency deviation)
1: Negative (When TXD=”1”, minus frequency deviation)
Coding control
0
R
6
5-4
3
manchester_en
Reserved
0: NRZ coding
1: Manchester coding
reserved
Output data selection
0
00
0
R/W
R/W
R/W
txtest_en
0: TXD input
1: Test pattern
Test pattern selection
0b000: PN9 (generated in LSI)
0b010: Contiuous “0101”
0b010: All “0”
2-0
txtest_sel[2:0]
000
R/W
0b011: All “1”
0b1xx: Carrier Wave (xx are don’t care)
[Coding]
Manchester coding
A line code in which the encoding of each data bit has at least one transition and
occupies the same time. Then 2 clock cycles are required to transmit a data.
1
1
0
TXD(NRZ)
Manchester coding
(Ex.)
0
1
0
1
0
0
TXD (NRZ)
TXC
Manchester coding (Air)
Note: If baud-rate is set to 2400 bps, ML7386 outputs TXC clock with 1200
clock/sec.
27/52
FEDL7386B-08
ML7386/ML7386B
0x03[PLL_N]
Function: PLL “N” parameter setting
Address: 0x03
Default Value 0x10
426.2500MHz (Oscillation frequency: 26MHz)
Default
R/W
Bit
Symbol
Reserved
pll_set [24:20]
Description
Value
7-5
5-1
Reserved
000
R/W
R/W
N parameter (5 bit) set
1_0000
[Detail description]
1. See section “Programming Channel frequency”
0x04[PLL_FL]
Function: PLL frequency setting (low byte)
Address: 0x04
Default Value 0xC4
426.250MHz (Oscillation frequency: 26MHz)
Default
Value
Bit
Symbol
Description
R/W
7-0
pll_set[7:0]
Frequency parameter for the the Channel (bit7 to bit0) 1100_0100
R/W
[Detail description]
1. See section “Programming Channel frequency”
0x05[PLL_FM]
Function: PLL frequency setting (middle byte)
Address: 0x05
Default Value 0x4e
426.250MHz (Oscillationl frequency: 26MHz)
Default
Value
Bit
Symbol
Description
R/W
7-0
pll_set[15:8]
Frequency parameter for the Channel (bit15 to bit8)
0100_1110
R/W
[Detail description]
1. See section “Programming Channel frequency”
28/52
FEDL7386B-08
ML7386/ML7386B
0x06[PLL_FH]
Function: PLL Frequency setting (high byte)
Address: 0x06
Default Value :0x06
426.250MHz (Oscillation frequency: 26MHz)
Default
R/W
Bit
Symbol
Reserved
pll_set[19:16]
Description
Value
7-4
3-0
Reserved
Frequency parameter for the Channel (bit19 to bit16)
0000
0110
R/W
R/W
[Detail description]
1. See section “Programming Channel frequency”
0x07[PLL_FIT]
Function: PLL frequency adjustment
Address: 0x07
Default Value 0x00
Default
Value
Bit
7
Symbol
pll_fit[7]
pll_fit[6:0]
Description
R/W
R/W
R/W
Polarity of PLL frequency adjustment offset
0: set as +
0
1: set as -
Offset value (0 to 127)
[Set value] * 25Hz
6-0
000_0000
0x08[F_DEV0]
Function: Frequency deviation #0 setting
Address: 0x08
Default Value 0x1A
Default
Value
Bit
Symbol
Description
Frequency deviation #0
R/W
7-0
f_dev0[7:0]
0001_1010
R/W
[Detail description]
1. See section “Programming FSK modulation”
29/52
FEDL7386B-08
ML7386/ML7386B
0x09[F_DEV1]
Function: Frequency deviation #1 setting
Address: 0x09
Default Value 0x32
Default
R/W
Bit
Symbol
Description
Description
Description
Value
7-0
f_dev1[7:0]
Frequency deviation #1
0011_0010
R/W
[Detail description]
1. See section “Programming FSK modulation”
0x0A[F_DEV2]
Function: Frequency deviation #2 setting
Address: 0x0A
Default Value 0x44
Default
Value
Bit
Symbol
R/W
7-0
f_dev2[7:0]
Frequency deviation #2
0100_0100
R/W
[Detail description]
1. See section “Programming FSK modulation”
0x0B[F_DEV3]
Function: Frequency deviation #3 setting
Address: 0x0B
Default Value 0x52
Default
Value
Bit
Symbol
R/W
7-0
f_dev3[7:0]
Frequency deviation #3
0101_0010
R/W
[Detail description]
1. See section “Programming FSK modulation”
30/52
FEDL7386B-08
ML7386/ML7386B
0x0C[F_DEV4]
Function: Frequency deviation #4 setting
Address: 0x0C
Default Value 0x54
Default
R/W
Bit
Symbol
Description
Frequency deviation #4
Value
7-0
f_dev4[7:0]
0101_0100
R/W
[Detail description]
1. See section “Programming FSK modulation”
0x0D[T_PLL_TR]
Function: Frequency deviation transition time setting
Address: 0x0D
Default Value 0x86
Default
Value
Bit
Symbol
Description
R/W
Frequency deviation trasition time
[Set value] * 0.154 us]
7-0
tim_plltr[7:0]
1000_0110
R/W
Default(0x86) = 20.6 us
[Detail description]
1. See section “Programming Frequency deviation”
2. It is necessary to adjust parametr depending on the data rete which is defined by [BR] register (x01).
See table below.
Data rate
[bps]
2400
4800
7200
[BR:0x01] register
baud_rate[2:0]
0b000
tim_plltr[7:0]
0xFF
0x87
0x5A
0b001
0b011
31/52
FEDL7386B-08
ML7386/ML7386B
0x0E[CLK_SEL]
Function: Clock configuration
Address: 0x0E
Default Value 0x00
Default
R/W
Bit
Symbol
Reserved
Description
Value
7-1
1
Reserved
0000_00
0
R/W
R/W
Fixed value
Fixed with 0b0
Input clock type select
0: OSC
0
srcck_sel
0
R/W
1: TCXO
0x0F[SRST]
Function: Softwate reset control
Address: 0x0F
Default Value 0x00
Default
Value
Bit
Symbol
Description
R/W
W
software reset
0x46 : Reset RF (digital block)
0xA7: Reset whole block
(register initializartion) *1
7-0
srstn[7:0]
0000_0000
[Note]
*1 : It seems that [VCO CAL:0x11] register is not initialized by “0xA7” software resert. Since the registaer
reload the value which located in RF(digital block) after reset.
0x10[PA_ADJ]
Function:Output power adjustment
Address: 0x10
Default Value 0x77
Default
Value
Bit
7-4
Symbol
pa_adj[3:0]
Description
R/W
R/W
Adjustment value for PA output. (10mW mode)
0b1111: Max output
0111
0b000 : Minimum output
Adjustment value for PA output. (1mW mode)
0b1111: Max output
3-0
pa_adj0[3:0]
0111
R/W
0b000 : Minimum output
[Detail description]
1. For more details, please refer to the “10mW TX power adjustment” or “1mW TX power adjustment”
32/52
FEDL7386B-08
ML7386/ML7386B
0x11[VCO_CAL]
Function: VCO caliburation value read or write control
Address: 0x11
Default Value 0x20
Default
R/W
Bit
Symbol
Description
Value
Overwrite enable
0: Read mode
1: Overwrite mode
7
6
b_vcoovr_cal
Reserved
0
0
R/W
R/W
Reserved
VCO calibration data
If bit7=0, Current VCO calibration result
If bit7=1, Overwrite value
5-0
b_vco_cal[5:0]
10_0000
R/W
0b00_0000: Minimum value
0b11_1111: Maximum value
0x12[VCO_CAL_EN]
Function: VCO caliburation enable control
Address: 0x12
Default Value 0x00
Default
Value
Bit
7-2
Symbol
Reserved
Description
R/W
R/W
Reserved
0000_00
When set to “1”, VCO Idle calibration will be started.
After completion of calibration, this bit will be cleared to
0b0.
When set to “1”, VCO active calibration will be started.
After completion of calibration, this bit will be cleared to
0b0.
1
0
vco_seq_cal_en
vco_ove_cal_en
0
R/W
R/W
0
[Detail description]
1. For mode details, please refer to the “VCO calibration”.
33/52
FEDL7386B-08
ML7386/ML7386B
0x13[PLL_CPI]
Function: PLL charge pump current control
Address: 0x13
Default Value 0x0F
Default
R/W
Bit
Symbol
Reserved
Description
Value
7-4
3
Reserved
0000
1
R/W
R/W
Fixed value
Fixed with 0b1.
Charge pump cuurent selection
(Adjusting PLL loop band width)
0b000: 10μA
0
cp_cal[2:0]
111
R/W
0b111: 150μA
(Change 20μA per 1 LSB)
0x14[BR_FLEX_SET_L]
Function: Extended baud-rate setting (low byte)
Address: 0x14
Default Value 0x28
Default
Value
Bit
7-0
Symbol
Description
R/W
R/W
Extended baud-rate setting (low byte)
Note: Combined together with [BR_FLEX_SET_H:0x15]
register.
br_flex_set[7:0]
0010_1000
Set value = (Master clock / wanted baud-rate /2) -1
[Notes]
1. If [BR:0x01] is set to 0x06 or 0x07, extended baud-rate setting becomes valid.
2. .If using extended baud-rate operation, evaluation and confirmation should be required under user specific
condition.
0x15[BR_FLEX_SET_H]
Function: Extended baud-rate setting (high byte)
Address: 0x15
Default Value 0x15
Default
Value
Bit
7-0
Symbol
Description
R/W
R/W
Extended baud-rate setting (high byte)
For details please refer to [BR_FLEX_SET_L] register
br_flex_set[15:8]
0001_0101
[Extended baud-rate setting]
When want to use 32.768kbps with 26MHz master clock.
(26.000,000 / 32768 / 2) = 1 = 395.7 = 0x018b
Then;
[BR_FLEX_SET_L:0x14] = 0x8b
[BR_FLEX_SET_H:0x15] = 0x01
34/52
FEDL7386B-08
ML7386/ML7386B
0x16[PA_BIAS]
Function: Bias adjustment for PA
Address: 0x16
Default Value 0x55
Default
R/W
Bit
7
Symbol
Fixed value
Description
Value
Fixed with 0b0
0
R/W
R/W
Local buffer set for 10mW mode
0b1: Max bias (Max output power)
0b0: Minimum bias
6
local_bias
1
PA bias set for 10mW mode
0b11: Max bias (Max output power)
0b00: Minimum bias
5-4
3
pa_bias [1:0]
Fixed value
local_bias0
01
0
R/W
R/W
R/W
Fixed with 0b0
Local buffer set for 1mW mode
0b1: Max bias (Max output power)
0b0: Minimum bias
2
1
PA bias set for 1mW mode
0b11: Max bias (Max output power)
0b00: Minimum bias
1-0
pa_bias0[1:0]
01
R/W
[Detail description]
1. This register control the bias level for PA and used for coarse sdjustment of output power.
0x17[PA_SEL]
Function: PA selection
Address: 0x17
Default Value 0x01
Default
Value
Bit
7-2
Symbol
Reserved
Description
R/W
R/W
Reserved
0000_00
PA state
1
0
pa_off
pa_sel
0: Normal operation
1: OFF state
PA selection
0: 1mW mode
1: 10mW mode
0
R/W
R/W
1
35/52
FEDL7386B-08
ML7386/ML7386B
0x1A[F_DEV_RESO]
Function: Frequency deviation resolution setting
Address: 0x1A
Default Value 0x00
Default
R/W
Bit
7-4
Symbol
Reserved
Description
Value
Reserved
0000
R/W
Frequency deviation resolution (setting range: 0 to 4)
y=seting value (0 to 4)
Resolution = 2^y * (Fref/2^20) [Hz]
Fref: Master clock frequency
3-0
dev_reso[3:0]
0000
R/W
[Note] If using this register, evaluation and confirmation should be required under user specific condition.
The following shos the relation between resolution and setting value ( Fref=26MHz)
dev_reso[3:0]
0b0000
Resolution [Hz]
Max frequency deviation [kHz]
25
50
99
198
396
6.3
12.7
25.3
50.6
101.2
0b0001
0b0010
0b0011
0b0100
0x2A[PA_REG]
Function: PA regulator output setting
Address: 0x2A
Default Value 0x07
Default
Value
Bit
7-3
Symbol
Reserved
Description
R/W
R/W
Reserved
0000_0
PA regulator output setting
0b010: 1mW mode
0b111: 10mW mode
Other setting: reserved
2-0
pa_reg[2:0]
111
R/W
[Note] Appropriate value should be set according to the RF design.
36/52
FEDL7386B-08
ML7386/ML7386B
■RF Adjustment
●Tx Power Adjustment
The ML7386B has two Popwer Amplifiers(PA) for 10mW mode and 1mW mode. Appropriate PA should be
selected in the design. This section shows the power sdjusting methodology for each power mode.
In each power mode, optimum matching circuit should be reqired. In the 10mW mode design, if select 1mW
mode PA, RF performances are not guranteed. Sama as in 1mW mode design.
37/52
FEDL7386B-08
ML7386/ML7386B
●10mW Tx Power Adjustment
It is possible to adjust the Tx power by [PA_ADJ:0x10] and [PA_BIAS:0x16] registers. The following flow
shows the example to adjusting Tx power to 10mW.
Adjusting power range should be set to more than +/- 5% to the desired level.
(In the following flow, the upper limit set to 11mW and the lower limit set to 9mW, ie +/- 10%.)
pa_sel:
located at bit 0 of [PA_SEL:0x2A] reister
located at bit 7-4 of [PA_ADJ:0x10] register
located at the bit 6 of [PA_BIAS:0x16] register
located at bit 5-4 of [PA_BIAS:0x16] register
located at bit 2-0 of [PA_REG:0x2A] register
pa_adj :
local_bias:
pa_bias:
pa_reg:
local_bias=1
pa_bias=3
All number inforation is described in decimal.
[10mW search flow ]
local_bias=0
pa_bias=3
Tx Power
local_bias=0
pa_bias=2
Find setting as output
power becomes in the
adjusting power range.
local_bias=0
pa_bias=1
11mW
9mW
local_bias=0
pa_bias=0
If still not reach lower limit
level with pa_adj=15, then
increment pa_bias_10
Increment pa_adj
Search start point
pa_bias=0
pa adj=0
0
15
pa_adj
[Note] If set local_bias=1, higher power is achivable than local_bias=0. Overrup power zone will exist.
38/52
FEDL7386B-08
ML7386/ML7386B
[10mW power adjustment flow]
All number inforation is described in decimal.
START
pa_sel=1
pa_reg=7
*10mW PA setting
local_bias=0
pa_bias=0
pa_adj=0
local_bias=1
pa_bias=0
pa_adj=0
pa_bias= pa_bias+1
pa_adj=0
pa_adj= pa_adj+1
No
Adjustment
Tx Power < Upper limit?
(Ex. 1.1mW)
Failure
Yes
No
Tx Power > Lower limiy?
(Ex. 0.9mW )
No
pa_adj=15?
Yes
Yes
No
No
pa_bias=3?
Yes
local_bias=1?
Adjustment
Completed
Adjustment
Failure
39/52
FEDL7386B-08
ML7386/ML7386B
●1mW Tx Power Adjustment
It is possible to adjust the Tx power by [PA_ADJ:0x10] and [PA_BIAS:0x16] registers. The following flow
shows the example to adjusting Tx power to 10mW.
Adjusting power range should be set to more than +/- 5% to the desired level.
(In the following flow, the upper limit set to 1.1mW and the lower limit set to 0.9mW, ie +/- 10%.)
pa_sel:
located at bit 0 of [PA_SEL:0x2A] reister
located at bit 3-0 of [PA_ADJ:0x10] register
located at the bit 2 of [PA_BIAS:0x16] register
located at bit 1-0 of [PA_BIAS:0x16] register
located at bit 2-0 of [PA_REG:0x2A] register
pa_adj0 :
local_bias0:
pa_bias0:
pa_reg:
All number inforation is described in decimal.
local_bias0=1
pa_bias0=3
[1mW search flow ]
Tx Power
local_bias0=0
pa_bias0=3
Find setting as output
power becomes in the
adjusting power range.
local_bias0=0
pa_bias0=2
1.1mW
0.9mW
local_bias0=0
pa_bias0=1
Decreasing pa_adj0
local_bias0=0
pa_bias0=0
If still not reach upper limit
level with pa_adj0=15,
then increment pa_bias0
Search start point
pa_bias0=0
pa_adj0=15
0
15
pa_adj0
[Note] If set local_bias0=1, higher power is achivable than local_bias0=0. Overrup power zone will exist.
40/52
FEDL7386B-08
ML7386/ML7386B
[1mW power adjustment flow]
All number inforation is described in decimal.
START
pa_sel=0
pa_reg=2
*1mW PA setting
local_bias0=0
pa_bias0=0
pa_adj0=15
local_bias0=1
pa_bias0=0
pa_bias0= pa_bias0+1
No
No
Tx Power > Lower limit?
(Ex. 0.9mW)
pa_bias0=3?
Yes
Yes
No
local_bias0=1?
Yes
Adjustment
Failure
No
No
Tx Power < Upper limit?
(Ex. 1.1mW )
pa_adj0= pa_adj0-1
Yes
Adjustment
Completed
41/52
FEDL7386B-08
ML7386/ML7386B
●Programming Channel Frequency
It is possible to configure channel frequency by registers of [PLL_N:0x03], [PLL_FL:0x04],
[PLL_FM:0x05] and [PLL_FH:0x06] registers.
The relation between setting frequency and each parameter are shown in the following formula.
f= fREF * (N+F/220)
f
: PLL oscillation frequency
: Desired frequency
: freqency error (freal – f)
: PLL reference frequency (master clock: 26MHz)
: N parameter (Integer part)
: F parameter (Fractional part
freal
ferr
fREF
N
F
Each frequency register will have following values.
N = int[ f / fREF
]
F = int[ (f / fREF - N) * 220 ] ••• Internal block uses 20 bits width
Therefore frequency error will be ferr = f real - {fREF×{(N+F/220 )}
Ex) If f=426.2500MHz, each parameter will be as follows when fREF = 26MHz
N = int[ 426.2500M / 26M ] = 16
F = int[ {426.2500M /26M - 16 * 220 ] = 413380 (0x64EC4)
Here
[PLL_N:0x03] = 0x10
[PLL_FL:0x04] = 0xC4
[PLL_FM:0x05] = 0x4E
[PLL_NA:0x06] = 0x06
In this case freuqency error will be ferr=426. 2500M - {26M * (16+ 413380 /220 )} = + 22.9Hz
Setting resolution depends on master clock. If 26MHz, the resolution is 25Hz.
42/52
FEDL7386B-08
ML7386/ML7386B
Following shows the setting table for 426MHz channels of Japan band as reference.
[RCR STD-30]
CH
No.
Frequency
[MHz]
PLL_NA
(0x03)
PLL_FL
(0x04)
PLL_FM
(0x05)
PLL_FH
(0x06)
Ferr
(Hz)
1
426.2500
426.2625
426.2750
426.2875
426.3000
426.3125
426.3250
426.3375
426.3500
426.3625
426.3750
426.3875
426.4000
426.4125
426.4250
426.4375
426.4500
426.4625
426.4750
426.4875
426.5000
426.5125
426.5250
426.5375
426.5500
426.5625
426.5750
426.5875
426.6000
426.6125
426.6250
426.6375
426.6500
426.6625
426.6750
426.6875
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
C4
BD
B5
AD
A5
9D
95
8D
85
7E
76
6E
66
5E
56
4E
46
3F
37
2F
27
1F
17
0F
07
00
F8
F0
E8
E0
D8
D0
C8
C0
B9
B1
4E
50
52
54
56
58
5A
5C
5E
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
7A
7C
7E
80
81
83
85
87
89
8B
8D
8F
91
93
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
06
22.9
1.1
2
3
4.2
4
7.2
5
10.3
13.4
16.4
19.5
22.5
0.8
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3.8
6.9
9.9
13.0
16.0
19.1
22.1
0.4
3.4
6.5
9.5
12.6
15.6
18.7
21.7
0.0
3.1
6.1
9.2
12.2
15.3
18.3
21.4
24.4
2.7
5.7
43/52
FEDL7386B-08
ML7386/ML7386B
[RCR STD-30] (continue)
CH
No.
Frequency
[MHz]
PLL_NA
(0x03)
PLL_FL
(0x04)
PLL_FM
(0x05)
PLL_FH
(0x06)
Ferr
(Hz)
37
38
39
40
41
42
43
44
45
46
47
48
426.7000
426.7125
426.7250
426.7375
426.7500
426.7625
426.7750
426.7875
426.8000
426.8125
426.8250
426.8375
10
10
10
10
10
10
10
10
10
10
10
10
A9
A1
99
91
89
81
7A
72
6A
62
5A
52
95
97
99
9B
9D
9F
A1
A3
A5
A7
A9
AB
06
06
06
06
06
06
06
06
06
06
06
06
8.8
11.8
14.9
17.9
21.0
24.0
2.3
5.3
8.4
11.4
14.5
17.5
44/52
FEDL7386B-08
ML7386/ML7386B
[ARIB STD-T67]
CH
No.
Frequency
[MHz]
PLL_NA
(0x03)
PLL_FL
(0x04)
PLL_FM
(0x05)
PLL_FH
(0x06)
Ferr
(Hz)
1
2
426.0250
426.0375
426.0500
426.0625
426.0750
426.0875
426.1000
426.1125
426.1250
426.1375
10
10
10
10
10
10
10
10
10
10
52
4A
42
3B
33
2B
23
1B
13
0B
2B
2D
2F
31
33
35
37
39
3B
3D
06
06
06
06
06
06
06
06
06
06
17.55
20.60
23.65
1.91
3
4
5
4.96
6
8.01
7
11.06
14.11
17.17
22.22
8
9
10
The following table shows the relation between master clock and frequency setting range
Master clock
[MHz]
PLL frequency setting raneg
Frequency
Resolution
[Hz]
17
Minimum
[MHz]
200
211
222
233
244
255
266
278
289
300
311
322
333
344
355
366
377
389
400
Maximum
[MHz]
486
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
513
540
567
594
621
648
675
702
729
756
783
810
837
864
891
918
18
19
20
21
22
23
24
25
26
27
28
29
30
31
31
32
945
972
33
34
.
45/52
FEDL7386B-08
ML7386/ML7386B
●Programming FSK modulation
ML7386/ML7386B outputs filtered FSK modulation, the shaping figure is defined by fiollowing registers
[F_DEV0:0x08] to [F_DEV4:0x0C] and [T_PLL_TR: 0x0D] registers.
Keeping better performance of OBWand suprious emission , each fdev parameter should be set as below table
depnds on the wanted frequency deviation. Tansision time parameter should be set depends on the data rate.
If using except for 26MHz master clock, the setting parameters can be calcurated by the
“ML7386Family_Register_Tool20150106en.xls”.
And evaluation and confirmation should be required under user specific condition.
[Frequency deviation setting list]
[Master Clock = 26MHz]
Fdev
(KHz)
F_DEV0
(0x08)
F_DEV1
(0x09)
F_DEV2
(0x0A)
F_DEV3
(0x0B)
F_DEV4
(0x0C)
0.6
0.7
07
08
0A
0B
0C
0D
0F
10
11
12
14
15
16
17
19
1A
1B
1C
1E
1F
20
21
23
24
25
0E
10
13
15
17
1A
1C
1E
21
23
26
28
2A
2D
2F
31
34
36
39
3B
3D
40
42
45
47
13
16
1A
1D
20
23
27
2A
2D
31
34
37
3A
3E
41
44
47
4B
4E
51
54
58
5B
5E
62
16
1A
1E
22
26
2A
2D
31
35
39
3D
41
44
48
4C
50
54
58
5B
5F
63
67
6B
6F
72
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1 (default)
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
46/52
FEDL7386B-08
ML7386/ML7386B
[Master Clock = 26MHz] (continue)
Fdev
(KHz)
F_DEV0
(0x08)
F_DEV1
(0x09)
F_DEV2
(0x0A)
F_DEV3
(0x0B)
F_DEV4
(0x0C)
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
26
28
29
2A
2B
2D
2E
2F
30
32
33
34
49
4C
4E
50
53
55
58
5A
5C
5F
61
63
65
68
6B
6F
72
75
78
7C
7F
82
85
89
76
7A
7E
82
86
89
8D
91
95
99
9D
A0
7D
81
85
89
8D
91
95
99
9D
A1
A5
A9
[Frequency deviation transition time setting list]
[Master Clock = 26MHz]
Data rate
[bps]
2400
[T_PLL_TR: 0x0D]
Tim_plltr[7:0]
0xFF
4800
0x87
7200
0x5A
47/52
FEDL7386B-08
ML7386/ML7386B
●Fractional Spurious
Fractional N spurious appears depends on the carrier frequency by following equations.
1. fractional[Carrier frequency / master clock] * master clock
2. (1- fractional[Carrier frequency /master clock] ) * master clock
If a fractional spurious appears within +/- 200 kHz to the channel frequency, the fractional spurious emission
could not be decreased. It is strongly recommended that the channel frequency should not be used.
So it means the range +/- 200 kHz to (26MHz * n) is not usable. (n=1,2,3.)
ML7386/ML7386B supports the operation frequency range from 200MHz to 972MHz. For this range
following frequency is unable operation frequency by the fractional spurious.
[Master Clock = 26MHz]
Spurious
frequency
[MHz]
208
Spurious
lower limit
[MHz]
207.8
233.8
259.8
285.8
311.8
337.8
363.8
389.8
415.8
441.8
467.8
493.8
519.8
545.8
571.8
597.8
623.8
649.8
675.8
701.8
727.8
753.8
779.8
805.8
831.8
857.8
881.8
907.8
933.8
959.8
Spurious
upper limit
[MHz]
208.2
234.2
260.2
286.2
312.2
338.2
364.2
390.2
416.2
442.2
468.2
494.2
520.2
546.2
572.2
598.2
624.2
650.2
676.2
702.2
728.2
754.2
780.2
806.2
832.2
858.2
882.2
908.2
934.2
960.2
n
n-8
n=9
234
260
286
312
338
364
390
416
442
468
494
520
546
572
598
624
650
676
702
728
754
780
806
832
858
882
908
934
n=10
n=11
n=12
n=13
n=14
n=15
n=16
n=17
n=18
n=19
n=20
n=21
n=22
n=23
n=24
n-25
n=26
n=27
n=28
n-29
n=30
n=31
n=32
n=33
n=34
n=35
n=36
n=37
960
48/52
FEDL7386B-08
ML7386/ML7386B
■Package diagram
Remarks for surface mount type package
Surface mount type package is very sensitive affected by heating from reflow process, humidity during storaging
Therefore, in case of reflow mouting process, please contact sales representative about product name, package
name, number of pin, package code and required reflow process condition (reflow method, temperature, number of
reflow process), storage condition.
49/52
FEDL7386B-08
ML7386/ML7386B
■Reference Footprint Pattern (Recommendation)
For reference
Unit: mm
When laying out PC boards, it is important to design the foot pattern so as
to give consideration to ease of mounting, bonding, positioning of parts,
reliability, wiring, and elimination of slder bridges.
The optimum design for the foot pattern varies with the materials of the
substrate, the sort and thichness of used soldering paste, and the way of
soldering. Therefore when laying out the foot pattern on the PC boards, refer
to this figure which mean the mounting area that the package leads are
allowable for soldering PC boards.
50/52
FEDL7386B-08
ML7386/ML7386B
■Revision History
Page
Previous
Edition
Document
No.
Date
Description
Initial release (ML7386)
Current
Edition
FEDL7386-01
FEDL7386B-01
FEDL7386B-02
FEDL7386B-03
FEDL7386B-04
FEDL7386B-05
FEDL7386B-06
FEDL7386B-07
Dec. 27, 2011
Dec. 3, 2012
Jan. 7, 2013
–
–
–
–
–
Initial release (ML7386B including ML7386)
Added Timing characteristics
15
1
Feb. 18, 2013
Jun. 11, 2013
Sep. 27, 2013
Mar. 13, 2014
Apr. 16, 2014
–
Modified TX Frequency range
–
34
24
13
27
23
24
Added PLL_CPI register setting
Added register setting flow
–
13
27
23
24
Modified TX Frequency range
Modified a polarity of txdinv
Modified the sentence of VCO Calibration
Modified the Register setting flow
Modified the register explanation.
0x17[PA_SEL]
FEDL7386B-08
Mar. 06, 2020
35
35
Updated the register setting tool.
ML7386Family_Register_Tool20150106en.xls
24,46
24,46
51/52
FEDL7386B-08
ML7386/ML7386B
■Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality,
semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent
personal injury or fire arising from failure, please take safety measures such as complying with the derating
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe
procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our
Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided
only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken
into account when designing circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and
examples of application circuits for the Products. No license, expressly or implied, is granted hereby under
any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the
information contained in this document; therefore LAPIS Semiconductor shall have no responsibility
whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such
technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication,
consumer systems, gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
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相关型号：
ML7396D
ML7396系列是适用于900MHz频段智能仪表的Sub-GHz宽频无线LSI。ML7396D适用于支持ARIB STD-T108（特定小功率无线基站 920MHz频段智能仪表用、遥控用及数据传输用无线基站）的无线基站，可使用IEEE802.15.4d和IEEE802.15.4g的数据包收发功能。ML7396D与之前的ML7396B具有相同的功能，都均有更出色的接收灵敏度。
ROHM
ML7404
ML7404是支持315MHz～960MHz频段的低功耗Sub-GHz无线LSI。产品内置符合IEEE802.15.4k标准的展频通信功能，可实现低功耗远距离无线通信。另外，作为窄带通信功能，安装了带宽可调的信道选择滤波器，因此可支持信道间隔为12.5kHz和50kHz以上的系统。产品符合欧洲智能仪表通信标准（Wireless M-Bus）中的F模式（434MHz）和S/T/C模式（868MHz）、日本国内的小功率安防系统无线基站和特定小功率无线基站（400MHz频段/920MHz频段）标准。ML7404与ML7344/ML7345/ML7406系列在封装、引脚排列和主要寄存器方面规格相同，因此在日本国内外的窄频和宽频Sub-GHz应用中可实现电路板和软件通用。
ROHM
ML7406
ML7406是支持750MHz～960MHz频段的低功耗Sub-GHz宽频无线LSI。ML7406主要用于ISM（Industrial, Scientific and Medical）频段和SRD（Short Range Device）用频段的无线基站。其中还特别内置了欧洲智能仪表通信标准（EN13757-4:2011：Wireless M-BUS）数据包格式的收发功能。
ROHM
ML7416N
ML7416N是集成了微控制器和900MHz频段无线单元的低功耗Sub-GHz宽频无线LSI。ML7416N的无线单元相当于ML7396D，微控制器单元配备了ARM Cortex-M0+内核、512KB Flash ROM和64KB RAM。
ROHM
ML7436N
ML7436N是一款集成了微控制器和389MHz～1,100MHz频段以及2.4GHz频段无线单元的低功耗Sub-GHz无线LSI。ML7436N的微控制器单元配备了ARM Cortex-M3内核、1MB Flash ROM和256KB RAM。产品具有大容量内存，还可搭载多跳和网状网络等先进通信协议，非常适用于新一代智能仪表和物联网设备。
ROHM
ML7456N (新产品)
ML7456N是一款集成了微控制器和315MHz～920MHz频段无线单元的Sub-GHz低功耗无线LSI。ML7456N的无线单元相当于ML7414，微控制器单元配备了蓝碧石自有的16bit CPU内核、64KB Flash ROM和8KB RAM。
ROHM
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