ML9445A_技术文档

FEDL9445A-01

Issue Date: Apr. 2, 2019

ML9445A

180-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

GENERAL DESCRIPTION

The ML9445A is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot

matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU).

Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the

ML9445A makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few

chips.

Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is

possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip,

it is possible to construct a graphic display system with a maximum of 65 × 180 dots.

The ML9445A has 65 common signal outputs and 180 segment signal outputs and one chip can drive a display of

up to 65 × 180 dots.

FEATURES

• Direct display of the RAM data using the bit map method

Display RAM data “1” ... Dot is displayed

Display RAM data “0” ... Dot is not displayed (during forward display)

• Display RAM capacity

65 × 180 × 2 = 23,400 bits

• LCD Drive circuits

65 common outputs, 180 segment outputs

• MPU interface: Can select an 8-bit parallel or serial interface or I²C (Write Only)

• Built-in voltage multiplier circuit for the LCD drive power supply

• Built-in LCD drive voltage adjustment circuit

• Built-in LCD drive bias generator circuit

• Can select frame reversal drive or line reversal drive by command

• Built-in oscillator circuit (Internal RC oscillator/external clock input)

• A variety of commands

Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page

address, set display start address, etc.

• Power supply voltage

Logic power supply: V_DD-V_SS= 2.7 V to 5.5 V

Voltage multiplier reference voltage: V_IN-V_SS= 2.7 V to 5.5 V

(2- to 5-time multiplier available)

LCD Drive voltage: V_BI-V_SS= 6.0 to 18.5 V

• Package: ML9445ADVWA Gold bump chip (Bump hardness: Low, DV)

• This device is not resistant to radiation and light.

1/84

FEDL9445A-01

ML9445A

BLOCK DIAGRAM

V_DD

V1

V2

SEGMENT

Drivers

COMMON

Drivers

V3

V4

V5

V_SS

Common Output stae

Selection circuit

VS1–

SVD2

VS2–

VC2+

VC3+

VC4+

VC5+

VC6+

VS3-

VC7+

V_H

Display data latch circuit

Display data RAM

FR

SYNC

CL

65 180

2

×

V_OUT1

V_OUT2

DOF

S

M/

V_IN

VR

V_RS

IRS

Column address circuit

CLS

VCH

TEST1

TEST2

TEST3

Command decoder

MPUInterface

Status

Bus holder

2/84

FEDL9445A-01

ML9445A

ABSOLUTE MAXIMUM RATINGS

V_SS= 0 V

Parameter

Power supply voltage

Bias voltage

Symbol

V_DD

Condition

Ta= 25°C

Ta = 25°C

Rated value

–0.3 to +6.5

–0.3 to +20

Unit Applicable pins

V

V_DD

V_BI

V1 to V5

Voltage multiplier output

voltage

V_OUT

Ta= 25°C

–0.3 to +20

V

V_OUT1,V_OUT2

2-time multiplication

3-time multiplication

4-time multiplication

5-time multiplication

–0.3 to +5.5

–0.3 to +5.0

–0.3 to +4.0

Voltage multiplier reference

voltage

V_IN

V

V_IN

Input voltage

V_I

I_S

Ta = 25°C

—

–0.3 to V_DD+0.3

－2.0 to +2.0

125

V

All inputs

All outputs

—

Output short-circuit current

Chip temperature

mA

°C

T_C

Storage temperature range

T_STG

—

–55 to +150

—

Note: Do not use the ML9445A by short-circuiting one output pin to another output pin as well as to other pin

(input pin, input/output pin, or power supply pin).

RECOMMENDED OPERATING CONDITIONS

V_SS= 0 V

Uni

t

Parameter

Symbol

Condition

MIN

TYP

MAX

Applicable pins

Power supply voltage

Bias voltage

V_DD

V_BI

—

2.7

6.0

—

5.5

V

V_DD

18

18.5

V1 to V5

2-time multiplication

3-time multiplication

4-time multiplication

5-time multiplication

3.0

2.7

5.5

Voltage multiplier reference

voltage

V_IN

—

V

V_IN

4.625

3.7

Voltage multiplier output

voltage

V_OUT

T_a

External input

—

6.0

18

—

18.5

105

V

V_OUT1,V_OUT2

—

Operating temperature range

–40

°C

Note 1: The electrical characteristics are influenced by COG trace resistance. This LSI always has to

be evaluated before using.

V_OUT1V_OUT2

、

V1 (V_BI)

V_IN

V2～V5

V_DD

V_CC

GND

System(MPU)

V_SS

ML9445A

3/84

FEDL9445A-01

ML9445A

Note 2: The voltages V_DD, V_IN, V1 to V5, V_OUT1and V_OUT2are values taking V_SS= 0 V as the reference.

Note 3: The highest bias potential is V1 and the lowest is V_SS.

Note 4: Always maintain the relationship V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V_SSamong these voltages.

Note 5: When using an external power supply, follow the procedure for power application.

When applying external power to the V_OUT1pin only, apply V_OUT1after V_DD.

When applying external power to the V_OUT2pin only, apply V_OUT2after V_DD.

When applying external power to the V1 pin only, apply V1 after V_DD.

When applying external power to the V1 pin to V5 pin, apply V1 to V5 after V_DD.

Note that the above (Note 4) must be satisfied including transient state at power application.

Note 6: When using an external power supply, follow the procedure for power removal described

below.

When external power is in use for the V_OUT1pin only, remove V_OUT1after V_DD.

When external power is in use for the V_OUT2pin only, remove V_OUT2after V_DD.

When external power is in use for the V1 pin only, remove V1 after V_DD.

When external power is in use for the V1 pin to V5 pin, remove V1 to V5 after V_DD.

Note that the above (Note 4) must be satisfied including transient state at power removal.

4/84

FEDL9445A-01

ML9445A

ELECTRICAL CHARACTERISTICS

DC Characteristics

[V_SS=0V, V_DD=2.7 to 5.5V, Ta =–40 to +105°C]

Applicable

Parameter

Symbol

Condition

Min

Typ

Max

Unit

pins

“H” Input voltage

“L” Input voltage

“H” Output voltage

“L” Output voltage1

“L” Output voltage2

Input current 1

V_IH

V_IL

0.8 × V_DD

—

V_DD

0.2 × V_DD

—

V

*1

0

0.8 × V_DD

—

V_OH

V_OL1

V_OL2

I_IL1

I_OH= –0.5 mA

I_OL= 0.5 mA

V

*2

0.2 × V_DD

+1.0

—

SDAACK

–1.0

–3.0

*3

*4

V_I= V_DDor V_I= 0 V

µA

Input current 2

I_IL2

+3.0

Ta=25°C,

F=10kHz

Input capacitance

C_I

—

8

12

—

pF

*1

V1 output voltage

Ta = 25°C

V1TC

-0.06

%/°C

V1

temperature gradient

V1 = 12 V *5

Reference voltage

V1 output voltage

V_REG

V1

Ta = 25°C

*6

2.925

10.59

3.00

3.075

11.13

V

V_RS

V1

10.86

2-time

multiplication *7

9

—

3-time

multiplication *8

13.5

Voltage multiplier

output voltage

V_OUT

V

V_OUT1

4-time

multiplication *9

5-time

multiplication *10

13.5

0.6

—

V_OUT- V1 voltage

Vot1

R_ON

*11

V

V_OUT2,V1

I_O= ±50 µA,

V1=10V, 1/9bias

SEG0 to 179,

COMS0,

COMS1,

1.0

1.5

LCD driver ON

resistance

kΩ

I_O= ±50 µA,

V1=6V, 1/4bias

—

2.0

3.0

COM0 to 63

Ta = 25°C

799

666

832

—

865

998

kHz

Internal

oscillation

f_OSC

*12

Oscillator

frequency

External

input

f_EXT

—

100

250

kHz

CL*12

*1:

A0, DB0 to DB5, DB6 (SCL), DB7 (SI), RD(E), WR(R/W), CS1, CS2, CLS, CL, M/S, C86, P/S, RES,

IRS, FR, DOF, SYNC Pins

*2:

*3:

*4:

DB0 to DB7, FR, DOF, SYNC, CL Pins

A0, RD(E), WR(R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS Pins

Applicable to the pins DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, DOF, SYNC in the high

impedance state.

*5:

*6:

Temperature gradient select : (DB2, DB1, DB0)=(0, 1, 0)

Ta = 25°C, D7=0,α =57, (1+Rb/Ra) = 4, Voltage multiplier output voltage (V_OUT) = 13.5 V (External

input), LCD drive output = no-load, See Power Supply Circuit. (Page 39)

5/84

FEDL9445A-01

ML9445A

*7:

*8:

*9:

V_IN= 5.0 V, voltage multiplier capacitor C1 = 2.6 to 4.0 µF, voltage multiplier output load current

I = 500 µA. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit

and V/F circuit, by power control set command.

V_IN= 5.00 V, voltage multiplier capacitor C1 = 2.6 to 4.0 µF, voltage multiplier output load current

I = 500 µA. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit

and V/F circuit, by power control set command.

V_IN= 3.75 V, voltage multiplier capacitor C1 = 2.6 to 4.0 µF, voltage multiplier output load current

I = 500 µA. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit

and V/F circuit, by power control set command.

*10: V_IN= 3.0 V, voltage multiplier capacitor C1 = 2.6 to 4.0 µF, voltage multiplier output load current

I = 500 µA. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit

and V/F circuit, by power control set command.

*11: V1 load current I = 400 µA. 8 V is externally input to V_OUT2.

The voltage adjustment circuit and V/F circuit operate by power control set command.

LCD output = no load

*12: See Table 1 for the relationship between the oscillator frequency and the frame frequency.

Table 1. Relationship among the oscillator frequency (f_OSC), external input frequency(f_EXT

display clock frequency (f_LCDCK), and LCD frame frequency (f_FR)

)

Ratio of dividing frequency: 1/n , Number of Display Line : L

Display clock frequency

(f_LCDCK

LCD frame frequency

(f_FR

_OSC/(16*n*L)

Parameter

)

1/65 to 1/50 duty

Fosc/16/n

F_OSC* (2/3)/16/n

F_OSC*(1/2)/16/n

F_OSC* (1/4)/16/n

f_EXT/16

F

When the internal

oscillator is used

1/49 to 1/34 duty

1/33 to 1/18 duty

1/17 or less

F_OSC*(3/4) /(16*n*L)

F_OSC*(1/2) /(16*n*L)

F_OSC*(1/4) /(16*n*L)

f_EXT/(16*L)

ML9445A

When the internal oscillator is not used

6/84

FEDL9445A-01

ML9445A

• Operating current consumption value

(1) During display operation, internal power supply OFF (The current flowing through V_DDwith V1 to V5

externally applied when an external power supply is used, not including the current for the LCD drive)

[V_SS=0V, Ta=25°C]

Rated value

Display mode

All-white

Symbol

I_DD

Condition

Unit

Min

—

Typ

175

155

175

155

Max

300

250

300

250

V_DD= 5 V, V1- V_SS= 11 V, no load

V_DD= 2.7 V, V1- V_SS= 8 V, no load

V_DD= 5 V, V1- V_SS= 11 V, no load

V_DD= 2.7 V, V1- V_SS= 8 V, no load

µA

—

Checker pattern

I_DD

µA

—

(2) During display operation, internal power supply ON (Total of currents flowing through V_DDand V_IN)

[V_SS=0V, Ta=25°C]

Rated value

Typ

Display

mode

Symbol

Condition

Unit

Min

—

Max

700

Frame reversal,

_DD,V_IN= 5 V, 3-time voltage multiplication

V

450

300

V1 - V_SS= 11 V, no load

Frame reversal,

V_DD,V_IN= 2.7 V, 4-time voltage multiplication

V1 - V_SS= 8 V, no load

All-white

I_DDIN

—

600

800

µA

16-line reversal,

V_DD,V_IN= 5 V, 3-time voltage multiplication

V1 - V_SS= 11 V, no load

600

Frame reversal,

V

_DD,V_IN= 5 V, 3-time voltage multiplication

1450

1700

1500

1700

2000

1700

V1 - V_SS= 11 V, no load

Frame reversal,

Checker

pattern

V_DD,V_IN= 2.7 V, 4-time voltage multiplication

V1 - V_SS= 8 V, no load

I_DDIN

µA

16-line reversal,

V_DD,V_IN= 5 V, 3-time voltage multiplication

V1 - V_SS= 11 V, no load

• Power save mode current consumption

[V_SS=0V, Ta=25°C]

Rated value

Typ

Parameter

Symbol

I_DDS1

Condition

Unit

Min

—

Max

20

Sleep mode

V_DD= 3.7 V

4

µA

7/84

FEDL9445A-01

ML9445A

Temperature Sensor Characteristics

[V_SS=0V, V_DD=2.7 to 5.5V, Ta=–40 to +105°C]

Rated value

Unit

Parameter

Symbol

V_SVD2

V_GRA

Condition

Min

Typ

Max

-40℃

25℃

105℃

1.482

1.177

0.801

1.506

1.2

0.824

1.529

1.224

0.848

V

Output voltage

Output voltage temperature

gradient

—

-4.7

—

mV/℃

Output voltage setup

time

t_SEN

I_SEN

—

100

—

ms

25℃

10

30

µA

Operating current

8/84

FEDL9445A-01

ML9445A

Switching Characteristics

• System bus Write characteristics 1 (80-series MPU)

V_IH

V_IL

V_IH

V_IL

A0

t_AW8

t_AH8

CS1

(CS2 = “H”)

t_CYC8

t_CCLW

V_IH

WR

V_IL

t_CCHW

t_DS8

t_DH8

DB0 to DB7

(Write)

V_IH

V_IL

V_IH

V_IL

• System bus Read characteristics 1 (80-series MPU)

V_IH

V_IL

V_IH

V_IL

A0

t_AH8

t_AW8

CS1

(CS2 = “H”)

t_CYC8

V_IH

t_CCLR

V_IH

RD

V_IL

t_CCHR

t_OH8

t_ACC8

V_OH

V_OL

V_OH

V_OL

DB0 to DB7

(Read)

9/84

FEDL9445A-01

ML9445A

[V_DD=2.7 to 5.5V, Ta=–40 to +105°C]

Rated value

Parameter

Address hold time

Symbol

Condition

Unit

Min

5

Max

—

t_AH8

t_AW8

Address setup time

System cycle time

5

—

t_CYC8

t_CCLW

t_CCLR

t_CCHW

t_CCHR

t_DS8

300

60

240

60

40

15

—

Control L pulse width (WR)

Control L pulse width (RD)

Control H pulse width (WR)

Control H pulse width (RD)

Data setup time

—

ns

—

Data hold time

t_DH8

—

RDAccess time

t_ACC8

t_OH8

240

100

CL = 100 pF

Output disable time

10

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are

(tr + tf) ≤ (t_CYC8– t_CCLW– t_CCHW) or (tr + tf) ≤ (t_CYC8– t_CCLR– t_CCHR).

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

Note 3: The values of t_CCLWand t_CCLRare specified during the overlapping period of CS1at “L”

(CS2 = “H”) and the “L” levels of WRand RD, respectively.

10/84

FEDL9445A-01

ML9445A

• System bus Write characteristics 2 (68-series MPU)

V_IH

V_IL

V_IH

V_IL

A0

t_AH6

t_AW6

R/W

V_IL

CS1

(CS2 = “H”)

t_CYC6

t_EWHW

E

V_IH

V_IL

t_EWLW

t_DS6

t_DH6

DB0 to DB7

(Write)

V_IH

V_IL

V_IH

V_IL

• System bus Read characteristics 2 (68-series MPU)

V_IH

V_IL

V_IH

V_IL

A0

V_IH

t_AW6

t_AH6

V_IH

R/W

CS1

(CS2 = “H”)

t_CYC6

t_EWHR

E

V_IH

V_IL

t_EWLR

t_OH6

t_ACC6

V_OH

V_OL

V_OH

V_OL

DB0 to DB7

(Read)

11/84

FEDL9445A-01

ML9445A

[V_DD=2.7 to 5.5V, Ta=–40 to +105°C]

Rated value

Parameter

Address hold time

Symbol

Condition

Unit

Min

5

Max

—

t_AH6

t_AW6

t_CYC6

t_DS6

Address setup time

System cycle time

Data setup time

Data hold time

5

—

300

40

15

—

t_DH6

—

Access time

t_ACC6

t_OH6

240

100

—

ns

CL = 100 pF

Output disable time

10

240

60

Read

Write

Read

Write

t_EWHR

t_EWHW

t_EWLR

t_EWLW

Enable H pulse width

Enable L pulse width

—

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are

(tr + tf) ≤ (t_CYC6– t_EWLW– t_EWHW) or (tr + tf) ≤ (t_CYC6– t_EWLR– t_EWHR).

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

Note 3: The values of t_EWLWand t_EWLRare specified during the overlapping period of CS1at “L”

(CS2 = “H”) and the “H” level of E.

12/84

FEDL9445A-01

ML9445A

• Serial interface

t_CSS

t_CSH

CS1

V_IL

(CS2 = “1”)

t_SAH

V_IH

V_IL

t_SCYC

V_IH

t_SAS

V_IH

V_IL

A0

t_SLW

V_IH

SCL

V_IL

t_f

t_SHW

t_r

t_SDH

t_SDS

V_IH

V_IL

V_IH

V_IL

SI

[V_DD=2.7 to 4.5 V, Ta=–40 to +105°C]

Rated value

Parameter

Symbol

Condition

Unit

Min

250

100

150

100

150

Max

—

Serial clock period

SCL “H” Pulse width

SCL “L” Pulse width

Address setup time

Address hold time

Data setup time

Data hold time

t_SCYC

t_SHW

t_SLW

t_SAS

t_SAH

t_SDS

t_SDH

t_CSS

t_CSH

ns

CS setup time

CS hold time

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

13/84

FEDL9445A-01

ML9445A

• I²C interface timing

t_{ꢇꢁꢂꢅꢈꢉ}

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

SDA

SCL

SDA

t_BUF

t_LOW

t_HIGH

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_ILV_IL

t_{ꢀꢁꢂꢃꢄꢅ}

t_{ꢀꢁꢂꢁꢅꢄ}

VIH

t_{ꢃꢆꢂꢁꢅꢄ}

V_IL

t_{ꢃꢆꢂꢃꢄꢅ}

t_{ꢃꢆꢂꢃꢄꢊ}

(V_DD= 2.7 to 5.5 V, Ta = -40 to +105°C)

Item

SCL clock frequency

Symbol

f_SCL

Condition

—

Min.

—

Max.

3.4

Unit

MHz

Hold time (repeat) "STATRT"

condition

t_HD,STA

—

160

—

SCL "L" pulse width

t_LOW

t_HIGH

—

160

60

—

SCL "H" pulse width

Setup time for repeat "START"

condition

t_SU,STA

—

160

—

ns

Data hold time

t_HD,DAT

t_SU,DAT

t_SU,STO

—

0

70

—

Data setup time

10

Setup time for "STOP" condition

Bus free time between "STOP"

condition and "START" condition

Data valid acknowledge time

Data bus load capacitance

Noise pulse width tolerance

160

t_BUF

—

160

—

t_VD,ACK

Cb

—

240

100

10

pF

ns

t_wf

Note 1: The input signal rise and fall times are specified as 0.1µs or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

14/84

FEDL9445A-01

ML9445A

• Display control output timing

V_OH

t_DFR

CL(OUT)

V_IH

V_IL

FR

[V_DD=2.7 to 5.5V, Ta=–40 to +105°C]

Rated value

Unit

Parameter

Symbol

t_DFR

Condition

Min

—

Typ

20

Max

80

FR Delay time

CL = 50 pF

ns

Note 1: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

Note 2: Valid only when the device operates in master mode.

• Reset input timing

t_f

t_r

t_RW

V_IH

V_IL

RES

V_IL

t_R

Internal state

Being reset

Reset complete

[V_DD=2.7 to 5.5 V, Ta=–40 to +105°C]

Rated value

Unit

Parameter

Symbol

Condition

—

Min

—

1

Typ

—

Max

1

Reset time

Reset “L” pulse width

Noise pulse width tolerance

t_R

µs

ns

t_RW1

t_RW2

—

50

Note 1: The input signal rise and fall times (t_r, t_f) are specified as 15 ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V_DDas the reference.

15/84

FEDL9445A-01

ML9445A

PIN DESCRIPTION

Number

of pins

Function Pin name

I/O

Description

These are 8-bit bi-directional data bus pins that can be connected to

8-bit standard MPU data bus pins.

When a serial interface is selected (P/S= “L”,C86= “H”):

DB7: Serial data input pin (SI)

DB0 to

DB7

DB6: Serial clock input pin (SCL)

2*8

When the serial interface and the I2C interface are selected,

DB0 to DB5 pins will be in the high impedance state.

Fix the DB0 to DB5 pins at “H” or “L” level.

DB0 to DB7 will be in the high impedance state when the chip select is

in the inactive state.

Normally, the lowest bit of the MPU address bus is connected and used

for distinguishing between data and commands.

A0

2

I

A0 = “H”: Indicates that DB0 to DB7 is display data.

A1 = “L”: Indicates that DB0 to DB7 is control data.

Initial setting is made by making RES = “L”. The reset operation is

made during the active level of the RESsignal.

RES

When the parallel interface and the serial interface are selected:

These are the chip select signals. The Chip Select of the LSI

becomes active when CS1 is “L” and also CS2 is “H” and allows

the input/output of data or commands.

When the I2C interface is selected:

These are the slave address input signals. They set the lower 2

bits of the slave address.

CS1(SA0)

2*2

I

MPU

Interface

CS2(SA1)

The active level of this signal is “L” when connected to an 80-series

MPU. This pin is connected to the RDsignal of the 80-series MPU, and

the data bus of the ML9445A goes into the output state when this

signal is “L”.

RD

2

I

The active level of this signal is “H” when connected to a 68-series

MPU. This pin will be the Enable and clock input pin when connected

to a 68-series MPU.

When a serial interface and I²C interface are selected (P/S= “L”), fix

this pin at “H” or “L” level.

(E)

The active level of this signal is “L” when connected to an 80-series

MPU. This pin is connected to the WR signal of the 80-series MPU.

The data on the data bus is latched into the ML9445A at the rising edge

of the WRsignal.

WR

When connected to a 68-series MPU, this pin becomes the input pin for

the Read/Write control signal.

2

I

(R/W)

R/W= “H”: Read, R/W= “L”: Write

When a serial interface and I²C interface are selected (P/S= “L”), fix

this pin at “H” or “L” level.

16/84

FEDL9445A-01

ML9445A

Number

of pins

Function Pin name

I/O

Description

This is the pin for selecting the MPU interface type.

When parallel interface is selected (P/S= “H”):

C86 = “H”: 68-Series MPU interface.

C86

2

I

C86 = “L”: 80-Series MPU interface.

When serial interface and I²C interface are selected (P/S= “L”):

C86 = “H”: Serial interface.

C86 = “L”: I²C interface.

P/S= “H”: Parallel interface.

P/S= “L”: Serial interface or I²C interface.

The pins of the LSI have the following functions depending on the state of

P/Sinput.

MPU

Interface

Data/comman

P/S

Data

Read/Write

Serial clock

P/S

2

I

d

“H”

“L”

A0

DB0 to DB7

RD, WR

—

SI/SDA (DB7)

—

SCL(DB6)

During serial data input, it is not possible to read the display data in the

RAM

The I²C bus acknowledge output signal. Normally, use it as it is

connected with the SDA pin. Connect an external pull-up resistor

whenever necessary, as it is an open drain pin. The pull-up connection

destination supply voltage shall be the V_DDsupply voltage or less.

SDAACK

2

I

This is the pin for selecting whether to enable or disable the internal

oscillator circuit for the display clock.

Oscillator

CLS

CLS = “H”: The internal oscillator circuit is enabled.

circuit

CLS = “L”: The internal oscillator circuit is disabled (External input).

When CLS = “L”, the display clock is input at the pin CL.

This is the pin for selecting whether master operation or slave operation is

made towards the ML9445A. During slave operation, the synchronization

with the LCD display system is achieved by inputting the timing signals

necessary for LCD display.

M/S= “H”: Master operation

M/S= “L”: Slave operation

The functions of the different circuits and pins will be as follows

depending on the states of M/Sand CLS signals.

Display

timing

generator

M/S

2

I

circuit

Oscillator

circuit

Power

supply circuit

Enabled

M/

S

CLS

CL

FR

SYNC

DOF

“H”

“L”

“H”

“L”

Enabled

Disabled

Output

Input

Output

Input

Output

Input

Output

Input

“H”

“L”

Enabled

Disabled

Input

17/84

FEDL9445A-01

ML9445A

Number

of pins

Function Pin name

I/O

Description

This is the clock input/output pin.

The function of this pin will be as follows depending on the states of M/S

and CLS signals.

M/S

CLS

“H”

“L”

CL

Output

Input

“H”

CL

2

“H”

“L”

When the ML9445A is used in the master/slave mode, the corresponding

CL pin has to be connected.

Display

timing

generator

This is the input/output pin for LCD display frame reversal signal.

M/S= “H”: Output

circuit

FR

2

I/O

M/S= “L”: Input

When the ML9445A is used in the master/slave mode, the

corresponding FR pin has to be connected.

This is the blanking control pin for the LCD display.

M/S= “H”: Output

DOF

2

I/O

M/S= “L”: Input

When the ML9445A is used in the master/slave mode, the

corresponding DOFpin has to be connected.

This is the input/output pin for LCD synchronize signal.

When the ML9445A is used in the master/slave mode, the

corresponding SYNC pin has to be connected.

SYNC

This is the pin for selecting the resistor for adjusting the voltage V1.

IRS = “H”: The internal resistor is used.

IRS = “L”: The internal resistor is not used. The voltage V1 is adjusted

using the external potential divider resistors connected to the pins VR.

This pin is effective only in the master operation. This pin is tied to the

“H” or the “L” level during slave operation.

IRS

2

I

Power

supply

V_DD

circuit

V_SS

10

12

—

These pins are tied to the MPU power supply pin V_CC.

These are the 0 V pins connected to the system ground (GND).

These pins are internal logic power supply pin.

Connect capacitors between V_SSpin.

VCH

V_IN

3

—

These are the reference power supply pins of the voltage multiplier circuit

for driving the LCD.

18/84

FEDL9445A-01

ML9445A

Number

of pins

Function Pin name

I/O

—

Description

These are the output pins for the LCD power supply voltage adjustment

circuit. Leave these pins open.

These are the output pins during 1^stvoltage multiplication.

V_RS

V_OUT1

V_H

2

4

3

I/O

Connect a capacitor between these pins and V_SS

These are the power input/output pins during 2^ndvoltage multiplication.

Connect a capacitor between these pins and V_SS

These are the output pins during 2^ndvoltage multiplication.

Connect a capacitor between these pins and V_SS

.

V_OUT2

.

These are the multiple level power supply pins for the LCD power

supply. The voltages specified for the LCD cells are applied to these

pins after resistor network voltage division or after impedance

transformation using operational amplifiers. The voltages are specified

taking V_SSas the reference, and the following relationship should be

maintained among them.

V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V_SS

V1

V2

V3

V4

V5

Master operation: When the power supply is ON, the following voltages

are applied to V2 to V5 from the built-in power supply circuit. The

selection of voltages is determined by the LCD bias set command.

4*5

I/O

Bias

V2

1/4

1/5

1/6

1/7

1/8

1/9

Power

supply

circuit

3/4×V1 4/5×V1 5/6×V1 6/7×V1 7/8×V1 8/9×V1

2/4×V1 3/5×V1 4/6×V1 5/7×V1 6/8×V1 7/9×V1

2/4×V1 2/5×V1 2/6×V1 2/7×V1 2/8×V1 2/9×V1

1/4×V1 1/5×V1 1/6×V1 1/7×V1 1/8×V1 1/9×V1

V3

V4

V5

Voltage adjustment pins. Voltages between V1 and V_SSare applied

using a resistance voltage divider. These pins are effective only when

the internal resistors for voltage V1 adjustment are not used (IRS = “L”).

Do not use these pins when the internal resistors for voltage V1

adjustment are used (IRS = “H”).

VR

2

I

These are the pins for connecting the negative side of the capacitors

for 1^stvoltage multiplication.

VS1–

VS2–

VC2+

VC3+

7

5

O

Connect capacitors between these pins and VC3+, VC5+.

These are the pins for connecting the negative side of the capacitors

for 1^stvoltage multiplication.

Connect capacitors between these pins and VC4+, VC6+.

These are the input pins for 1^stvoltage multiplication.

This pin inputs voltage which is open or same with V_INdepending on

voltage multiplication scaling factor.

These are the input pins for 1^stvoltage multiplication.

Apply the voltage equal to V_INto the pins or leave them open, depending

on voltage multiplication values.

I

I/O

19/84

FEDL9445A-01

ML9445A

Number

of pins

Function Pin name

VC4+

I/O

Description

These are the pins for connecting the positive side of the capacitors for

1^stvoltage multiplication. Connect capacitors between VS2– and these

pins. For 3-time voltage multiplication, the pins are configured as

inputs for voltage multiplication.

5

These are the pins for connecting the positive side of the capacitors for

1^stvoltage multiplication. Connect capacitors between VS1– and these

pins. For 2-time voltage multiplication, the pins are configured as inputs

for voltage multiplication.

VC5+

I/O

Power

supply

These are the pins for connecting the positive side of the capacitors for

1^stvoltage multiplication.

VC6+

VS3-

VC7+

5

4

O

circuit

Connect capacitors between VS2– and these pins.

These are the pins for connecting the positive side of the capacitors for

2^ndvoltage multiplication.

Connect capacitors between VC7+ and these pins.

These are the pins for connecting the positive side of the capacitors for

2^ndvoltage multiplication.

Connect capacitors between VS3- and these pins.

These are the LCD segment drive outputs.

One of the levels among V1, V3, V4, and V_SSis selected depending on

the combination of the display RAM content and the FR signal

Output voltage

RAM Data

FR

Forward display Reverse display

H

L

V1

V_SS

V3

V4

SEG0 to

SEG179

180

O

H

L

H

L

V1

L

V4

V_SS

Power save

—

V_SS

LCD

Drive

output

The output voltage is V_SSwhen the Display OFF command is

executed.

These are the LCD common drive outputs.

One of the levels among V1, V2, V5, and V_SSis selected depending on

the combination of the scan data and the FR signal.

Scan data

FR

H

Output voltage

H

V_SS

V1

COM0 to

COM63

H

L

64

O

L

H

V2

L

V5

Power save

—

V_SS

The output voltage is V_SSwhen the Display OFF command is

executed.

20/84

FEDL9445A-01

ML9445A

Number

of pins

Function Pin name

I/O

O

Description

These are the common output pins only for indicators. Both pins

output the same signal. Leave these pins open when they are not

used. The same signal is output in both master and slave operation

modes.

LCD

COMS0

Drive

2

COMS1

output

Temp

SVD2

sensor

2

2*2

２

O

I

This is analog voltage output pin for temperature sensor.

TEST1

These are the pins for testing the IC chip. It has a Internal pull-down

resistor. Use it as it is connected to GND.

TEST3

Test pin

This pins for testing the IC chip. Leave these pins open during normal

use.

TEST2

I

This is a floating pin.

Avoid this pin from shorting with pins other than DUMMY in the wiring

on the Chip On Glass.

—

DUMMY

31

—

21/84

FEDL9445A-01

ML9445A

FUNCTIONAL DESCRIPTION

MPU Interface

• Selection of interface type

The ML9445A carries out data transfer using either the 8-bit bi-directional data bus (DB0 to DB7) or the serial data

input line (SI/SDA). Either the 8-bit parallel data input or serial data input can be selected interfaceｓ as shown in

Table 2 by setting the P/Spin and C86 pin to the “H” or the “L” level.

Table 2 Selection of interface type (parallel/serial/I²C)

P/S

C86

CS1

CS2

A0

RD

WR

DB7

DB6

DB0 to DB5

H:68

L:80

CS1

CS2

A0

E

R/W

DB7

DB6

DB0 to DB5

H: Parallel input

RD

WR

L: Serial input

I²C

H: Serial

L:I²C

CS1

CS2

SA1

A0

—

SI

SCL

—

SA0

SDA

A hyphen (—) indicates that the pin can be tied to the “H” or the “L” level.

• Parallel interface

When the parallel interface is selected, (P/S= “H”), it is possible to connect this LSI directly to the MPU bus of

either an 80-series MPU or a 68-series MPU as shown in Table 3. depending on whether the pin C86 is set to “H”

or “L”.

Table 3 Selection of MPU during parallel interface (80–/68–series)

C86

CS1

CS2

A0

RD

WR

DB0 to DB7

H: 68-Series MPU bus

L: 80-Series MPU bus

CS1

CS2

A0

E

R/W

DB0 to DB7

RD

WR

The data bus signals are identified as shown in Table 4 below depending on the combination of the signals A0, RD

(E), and WR(R/W) of Table 3.

Table 4 Identification of data bus signals during parallel interface

Common

A0

68-Series

80-Series

R/W

RD

WR

Display data read

Display data write

Status read

1

0

1

0

1

0

1

0

1

0

1

0

Control data write (command)

22/84

FEDL9445A-01

ML9445A

Serial Interface

When the serial interface is selected (P/S= “L”, C86 =“H”), the serial data input (SI) and the serial clock input

(SCL) can be accepted if the chip is in the active state (CS1= “L” and CS2 = “H”). The serial interface consists of

an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence

DB7, DB6, ... , DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge

of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or

command is judged based on the A0 input, and the data is treated as display data when A0 is “H” and as command

when A0 is “L”. The A0 input is read in and identified at the rising edge of the (8 × n) th serial clock pulse after the

chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift

register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface.

It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL

signal. We recommend verification of operation in an actual unit.)

CS1

CS2

DB7

1

DB5

3

DB7

9

DB3

DB6 DB5 DB4 DB2

DB6

2

DB4 DB3 DB2 DB1 DB0

SI

SCL

A0

4

5

6

7

8

10 11 12 13 14

Fig. 1 Signal chart during serial interface

• I²C Interface

Slave address

Control byte

R/W

COMMAND

LSB

P

S

0

1

0

SA1 SA0

0

A

MSB

DATA/Command

CO RS

Salve address: 0 1 1 0 0

CO: Consecutive control byte setting bit

0: Last control byte, 1: Consecutive control byte

RS: Command/data setting bit

0: Command data, 1: Display data

When the I²C interface is selected (P/S= “L”, C86 =“L”), the I²C data input (SDA) and the I²C clock input (SCL)

can be data input. For the I²C interface, each IC is assigned with a 7-bit slave address. The first one byte in the

transfer consists of this 7-bit slave address and the R/W bit that indicates the data transfer direction. Always input

"0" to the eighth R/W bit because the ML9445A is a write-only LSI.

The eight bits next to the slave address is a control byte. The first one bit is CO: consecutive command setting bit

and the next one bit is RS: command/data setting bit (the remaining six bits are the Don't care bits).

When CO = "0": Means the last control byte.

When CO = "1": Means the control bytes are successively input.

When RS = "0": Means the data to be input next is the command data.

When RS = "1": Means the data to be input next is the display data.

The display data can be successively input.

23/84

FEDL9445A-01

ML9445A

Example of Data Setting

• When inputting two commands

When inputting two commands

SA0

COMMAND

V_IH

S

0

1

0

1

0

A

1

0

A

COMMAND

DATA/Com

0

P

•

When inputting the command and display data

SA1

COMMAND

Display data

S

0

1

0

A

1

0

A

Display data

P

• Chip select

The ML9445A has the two chip select pins CS1and CS2, and the MPU interface or the serial interface is enabled

only when CS1= “L” and CS2 = “H”. When the chip select signals are in the inactive state, the DB0 to DB7 lines

will be in the high impedance state and the inputs A0, RD, and WRwill not be effective. When the serial interface

has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state.

When the I2C interface is selected, CS1 and CS2 become the slave address setting pins SA0 and SA1.

• Accessing the display data RAM and the internal registers

Accessing the ML9445A from the MPU side requires merely that the cycle time (t_CYC) be satisfied, and high speed

data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the

ML9445A carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data

bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus

holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU

reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in

the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a

restriction on the read sequence of the display data RAM, which is that the read instruction immediately after

setting the address does not read out the data of that address, but that data is output as the data of the address

specified during the second data read sequence, and hence care should be taken about this during reading.

Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (The

status read cannot use dummy read cycles.) This relationship is shown in Figs 2(a) and 2(b).

24/84

FEDL9445A-01

ML9445A

• Data write

WR

Dn

Dn + 1

Dn + 2

Dn + 3

DATA

Latch

Dn

Dn + 1

Dn + 2

BUS Holder

Write Signal

g n

i m i t

e t n I

Fig. 2(a) Write sequence of display data RAM

• Data read

WR

RD

P

M

N

unknown

Dn

Dn + 1

DATA

Address

Preset

Read Signal

Column

Address

Increment N + 1

Dn

Preset N

unknown

N + 2

Dn + 1

Dn + 2

BUS Holder

Data Read

Dn

Address Set

N

Data Read

Dn + 1

Data Read

(Dummy)

Fig. 2(b) Read sequence of display data RAM

Dn = Data

N = Address data

25/84

FEDL9445A-01

ML9445A

Display Data RAM

• Display data RAM

This is the RAM storing the dot data for display and has an organization of 65 (8 pages × 8 bits +1) × 180 × 2 bits.

It is possible to access any required bit by specifying the page address and the column address. Since the display

data DB7 to DB0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in

Fig. 3, there are fewer restrictions during display data transfer when the ML9445A is used in a multiple chip

configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the

display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the

signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when

the display data RAM is accessed asynchronously during the LCD display operation.

DB0

DB1

DB2

DB3

DB4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

…

0

COM0

COM1

COM2

COM3

COM4

…

Display data RAM

LCD Display

Fig. 3 Relationship between display data RAM and LCD display

• Page address circuit / Column address circuit

The page address of the display data RAM is specified using the page address set command as shown in Fig. 4. For

Address incremental direction, either the column direction or page direction can be selected by the Display Data

Input Direction Select command. Whichever direction is chosen, increment is carried out by positive one(+1) after

write or read operation.

When the column direction is selected for address increment, the column address is increased by +1 for every write

or read operation. After the column address has accessed up to B3H, the page address is incremented by +1 and the

column address shifts to 00H.

When the page direction is selected for address increment, the page address is increased with the column address

locked in position. When the page address has accessed up to Page17, the column address is incremented by +1,

and the page address goes to Page 0.

Whichever direction is selected for address increment, the page address goes back to Page 0 and column address to

00H after access up to the column address B3H of page address Page17.

Also, as is shown in Table 5, it is possible to reverse the correspondence relationship between the display data

RAM column address and the segment output using the ADC command (the segment driver direction select

command). This reduces the IC placement restrictions at the time of assembling LCD modules.

Table 5 Correspondence relationship between the display data RAM column address

and the segment output

SEGMENT Output

ADC

SEG0

00(H)

B3(H)

SEG179

B3(H)

DB0 = “0”

DB0 = “1”

→

←

Column Address

→

←

00(H)

26/84

FEDL9445A-01

ML9445A

• Line address circuit

The line address circuit is used for specifying the line address corresponding to the common output when

displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display is

specified using the display start line address set command (COM0 output in the forward display state of the

common output, and COM63 output in the reverse display state). The display area starts from the specified display

start line address to cover the area corresponding to the lines specified by the Duty Set command in the direction

where the line address increments.

It is possible to carry out screen scrolling by dynamically changing the line address using the display start line

address set command.

• Display data latch circuit

The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being

output to the LCD drive circuits. Since the commands for selecting forward/reverse display and turning the display

ON/OFF control the data in this latch, the data in the display data RAM will not be changed.

Oscillator Circuit

This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S= “H”

and also CLS = “H”. The oscillations will be stopped when CLS = “L”, and the display clock has to be input to the

CL pin.

27/84

FEDL9445A-01

ML9445A

Line

COM

When the common output

state is normal display

Page Address

DB4 DB3 DB2 DB1 DB0

Data

Address

Output

DB0

00(H)

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

01(H)

02(H)

03(H)

04(H)

05(H)

06(H)

07(H)

08(H)

09(H)

0A(H)

0B(H)

0C(H)

0D(H)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Page0

Page1

0E(H) (Start)

COM14

…

31(H)

32(H)

33(H)

34(H)

35(H)

36(H)

37(H)

38(H)

39(H)

3A(H)

3B(H)

3C(H)

3D(H)

3E(H)

3F(H)

40(H)

41(H)

42(H)

43(H)

44(H)

45(H)

46(H)

47(H)

48(H)

49(H)

4A(H)

4B(H)

4C(H)

4D(H)

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

Page6

Page7

Page8

Page9

4E(H)

…

71(H)

72(H)

73(H)

74(H)

75(H)

76(H)

77(H)

78(H)

79(H)

7A(H)

7B(H)

7C(H)

7D(H)

7E(H)

7F(H)

80(H)

81(H)

Page14

Page15

1

0

1

Page16

Page17

COMS

The 80(H) is

displayed

irrespective of the

display start line

address.

Fig. 4 Display data RAM address map

28/84

FEDL9445A-01

ML9445A

Display Timing Generator Circuit

This circuit generates the timing signals for the line address circuit and the display data latch circuit from the

display clock. The display data is latched in the display data latch circuit and is output to the segment drive output

pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit

and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit

and is output to the segment drive output pins in synchronization with the display clock. The read out of the

display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU.

As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed

asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR), field

start signal (SYNC) are generated by this circuit from the display clock. The drive waveforms of the frame

reversal drive method shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. The drive

waveforms of the line reversal drive method shown in Fig. 5(b) are also generated by the command.

64 65

1

2

3

4

60

62 63

1

2

3

4

5

6

61

64 65

6

LCDCK

(display clock)

FR

V1

V2

COM0

V5

V_SS

V1

V2

COM1

V5

V_SS

RAM

DATA

V1

V3

V4

V_SS

SEGn

Fig. 5(a) Waveforms in the frame reversal drive method

29/84

FEDL9445A-01

ML9445A

65

64

1

2

3

4

5

6

60 61 62 63 64 65

1

2

3

4

5

6

LCDCK

(display clock)

FR

V1

V2

COM0

V5

V_SS

V1

V2

COM1

V5

V_SS

RAM

DATA

V1

V3

V4

V_SS

SEGn

Fig. 5(b) Waveforms in the line reversal drive method

When the ML9445A is used in a multiple chip configuration, it is necessary to supply the slave side display timing

signals (FR, CL, and DOF) from the master side.

The statuses of the signals FR, CL, and DOFare shown in Table 6.

Table 6 Display timing signals in master mode and slave mode

Operating mode

FR

CL

DOF

Output

Input

SYNC

Output

Input

Internal oscillator circuit enabled (CLS = H)

Internal oscillator circuit disabled (CLS = L)

Internal oscillator circuit disabled (CLS = H)

Internal oscillator circuit disabled (CLS = L)

Output

Input

Output

Input

Master mode

(M/S= “H”)

Slave mode

(M/S= “L”)

Input

30/84

FEDL9445A-01

ML9445A

Common Output State Selection Circuit (see Table 7)

Since the common output scanning directions can be set using the common output state selection command in the

ML9445A, it is possible to reduce the IC placement restrictions at the time of assembling LCD modules.

Table 7 Common output state settings

State

Common Scanning direction

COM0 → COM63

Forward Display

Reverse Display

COM63 → COM0

LCD Drive Circuit

This LSI incorporates 246 sets of multiplexers for the ML9445A that generate 4-level outputs for driving the LCD.

These output the LCD drive voltage in accordance with the combination of the display data, common scanning

signals, and the FR signal. Fig. 6 shows examples of the segment and common output waveforms in the frame

reversal drive method.

31/84

FEDL9445A-01

ML9445A

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

V_DD

V_SS

FR

V1

V2

V3

V4

V5

COM0

V_SS

COM8

COM9

V1

V2

V3

COM10

COM11

COM12

COM13

COM14

COM15

COM1

COM2

V4

V5

V_SS

V1

V2

V3

V4

V5

V_SS

V1

V2

V3

SEG0

SEG1

SEG2

V4

V5

V_SS

V1

V2

V3

V4

V5

V_SS

V1

V2

V3

V4

V5

V_SS

V1

V2

V3

V4

V5

0V

-V5

-V4

COM0-SEG0

-V3

-V2

-V1

V1

V2

V3

V4

V5

0V

-V5

-V4

COM0-SEG1

-V3

-V2

-V1

Fig. 6 Output waveforms in the frame reversal drive method

(FR waveform/common waveform/segment waveform/voltage difference

between common and segment)

32/84

FEDL9445A-01

ML9445A

Power Supply Circuit

The ML9445A includes a power supply circuit for generating the voltage required for driving liquid crystals,

consisting of four blocks; the 1^stvoltage multiplier circuit, 2^ndvoltage multiplier circuit, V1 voltage adjustment

circuit, and voltage follower circuit. The circuit is effective only when the master operates. In the power supply

circuit, it is possible to control the ON/OFF of each of the circuits of the 1^stvoltage multiplier circuit, 2^ndvoltage

multipliers circuit, V1 voltage adjustment circuit, and voltage follower circuit separately, by using the power

control set command. As a result, it is possible to use some parts of functions of both the external power supply and

the internal power supply. Table 8-1 describes the functions controlled by the 4-bit data of the power control set

command and Table 8-2 outlines the functions of power supply blocks.

Figure 6-2 shows the voltage relationship among the power supply circuit blocks.

Table 8-1 Details of functions controlled by the bits of the power control set command

Control bit

DB3

Function controlled by the bit

2^ndVoltage multiplier circuit control bit

1^stVoltage multiplier circuit control bit

DB2

DB1

Voltage adjustment circuit (V1 voltage adjustment circuit) control bit

Voltage follower circuit (V/F circuit) control bit

DB0

V_OUT2

V₁

x2

V₂

V₃

V₄

V₅

V_OUT1

x2～x5

VH

V_IN

V_SS

2^ndVoltage

V1 Voltage

multiplier circuit

1^stVoltage

multiplier circuit

V/F circuit

adjustment

circuit

Fig. 6-2 The Voltage relationship among the power supply circuit blocks.

33/84

FEDL9445A-01

ML9445A

Table 8-2 Overview of Power Supply Block Functions

Input

Output

Parameter

Function

Voltage

Generates a multiplied voltage VOUT1 by multiplying the voltage between

VIN and GND using the charge pump. Connecting a capacitor for voltage

multiplication allows you to multiply the voltage by 2 to 5 times.

1^stVoltage

V_IN

V_OUT1

multiplier circuit

Consists of a voltage adjustment circuit and a 2-time voltage multiplier

circuit. The voltage adjustment circuit generates VRS as the base voltage

of the 2-time voltage multiplier circuit, and then the 2-time voltage multiplier

circuit generates VOUT2 by multiplying VRS by 2 times.

2^ndVoltage

VH,

V_OUT1

multiplier circuit

V_OUT2

V1 voltage

This circuit adjusts the V1 voltage and generates the LCD drive voltage V1. V_OUT2

Resistive division is performed between V1 and VSS with a specified bias

V1

adjustment circuit

V2, V3,

V4, V5

Voltage follower circuit ratio, and the LCD drive voltages V2, V3, V4, and V5 are generated by the

voltage follower.

V1

For the combination of power supply circuit operations, the six possible states shown in Table 9 can be set by the

register value of the power control set command.

Table 9 Sample combination for reference

Circuit

External

voltage

input

2^nd

Voltage

1^st

No.

State used

DB3 DB2 DB1 DB0

V1

Voltage

V/F

ON

Adjustment

multiplier multiplier

Only the internal power

supply is used

1

2

1

0

1

ON

V_IN

Only the internal power

supply is used (2^ndVoltage

multiplier is not used)

OFF

Only the internal power

supply is used (1^stVoltage

multiplier is not used)

3

1

0

1

ON

OFF

ON

V_OUT1

V1 adjustment and V/F

circuits are used

4

5

6

0

1

0

1

0

OFF

ON

OFF

ON

V_OUT2

V1

Only V/F circuits are used

Only the external power

supply is used

OFF

V1 to V5

If combinations other than the above are used, normal operation is not guaranteed.

34/84

FEDL9445A-01

ML9445A

1, The 1^stvoltage multiplier circuit, 2^ndvoltage multipliers circuit, V1 voltage adjustment circuit, and V/F

circuit are used(all internal power supplies)

Use this combination when not using the power supply from the external. All voltages required for driving LCD

are generated from the VIN voltage. All internal power supplies are used. See Figure 13-1.

2, Only the 1^stvoltage multiplier circuit, V1 voltage adjustment circuit, and V/F circuit are used (2^nd

voltage multiplier circuit is not used)

Use this combination when not using the power supply from the external. All voltages required for

driving LCD are generated from the VIN voltage.

The number of capacitors for voltage multiplication can be reduced by stopping the 2^ndvoltage multiplier circuit.

Short V_OUT1, V_H, and V_OUT2to use this combination. See Figure 13-2.

3, Only the 2^ndvoltage multiplier circuit, V1 voltage adjustment circuit, and V/F circuit are used (1^st

voltage multiplier circuit is not used)

Use this combination when the V_OUT1voltage can be supplied from the external. Although the capacitor for the 1^st

voltage multiplication is not connected, set the command to use the 1^stvoltage multiplier circuit (DB2 = “0”).

See Figure 13-3.

4, Only the V1 voltage adjustment circuit and V/F circuit are used

Use this combination when the V_OUT2voltage can be supplied from the external. The V2, V3, V4, and V5 voltages

are generated, which are the LCD drive voltages generated by the internal V1 voltage adjustment circuit and V/F

circuit. Connect capacitors for retaining voltages to the V1 to V5 pins. The V1 voltage can be adjusted by the V1

voltage adjustment command and the electronic potentiometer command. See Figure 13-4.

5, Only the V/F circuit is used

Use this combination when the V1 voltage can be supplied from the external.

Connect capacitors for retaining voltages to the V2, V3, V4, and V5 pins which output the LCD drive voltages

generated by the V/F circuit. See Figure 13-5.

6, Only the external power supply is used (all internal power supplies are OFF)

Use this combination when the V1, V2, V3, V4, and V5 voltages can be supplied from the external.

See Figure 13-6.

35/84

FEDL9445A-01

ML9445A

• 1^stVoltage multiplier circuits

The 1^stvoltage multiplier circuit can multiply the VIN to VSS voltage by 2, 3, 4, or 5 times.

Fig. 7-1 to 7-4 show the circuit connections and the voltage relationships.

Fig. 7-1 2-time voltage multiplier circuit and voltage relationships in 2-time multiplication

V_IN

V_SS

+

C1

V_OUT= 2 × V_IN

V_OUT1

VC6+

VC4+

VC2+

VS2–

VC5+

VC3+

= 10V

+

OPEN

*1 V_IN= 5V

V_S= 0 V

OPEN

Voltage relationship in

2-time multiplication

VS1–

2-time voltage

multiplier circuit

Connect capacitors between VC6+ and VS2- and between V_OUT1and V_SS, open the VC4+, VC2+, VC3+, and VS1-

pins, and short the V_INand VC5+ pins to use this connection. Should be used in the range of VIN = 3 to 5.5 V.

Fig. 7-2 3-time voltage multiplier circuit and voltage relationships in 3-time multiplication

V_IN

V_SS

+

V_OUT= 3 × V_IN

C1

V_OUT1

VC6+

VC4+

VC2+

VS2–

VC5+

VC3+

= 15V

+

OPEN

C1

*1 V_IN= 5V

V_S= 0 V

+

OPEN

Voltage relationship in

3-time multiplication

VS1–

3-time voltage

multiplier circuit

Connect capacitors between VC6+ and VS2-, between VC5+ and VS1-, and between V_OUT1and V_SS, open the

VC2+, and VC3+ pins, and short the V_INand VC4+ pins to use this connection.

Should be used in the range of VIN = 2.7 to 5.5 V.

36/84

FEDL9445A-01

ML9445A

Fig. 7-3 4-time voltage multiplier circuit and voltage relationships in 4-time multiplication

V_IN

V_SS

+

V_OUT= 4 × V_IN

C1

V_OUT1

VC6+

VC4+

VC2+

VS2–

VC5+

VC3+

= 18V

C1

+

OPEN

*1 V_IN= 4.5V

V_S= 0 V

C1

+

Voltage relationship in

4-time multiplication

VS1–

4-time voltage

multiplier circuit

Connect capacitors between VC6+ and VS2-, between VC4+ and VS2-, between VC5+ and VS1-, and between

_OUT1and V_SS, open the VC2+ pin, and short the V_INand VC3+ pins.

V

Should be used in the range of VIN = 2.7 to 4.625 V.

Fig. 7-4 5-time voltage multiplier circuit and voltage relationships in 5-time multiplication

V_IN

V_SS

+

V_OUT= 5 × V_IN

C1

V_OUT1

VC6+

VC4+

VC2+

VS2–

VC5+

VC3+

= 18.5V

+

C1

*1 V_IN= 3.7V

V_S= 0 V

C1

+

Voltage relationship in

5-time multiplication

VS1–

5-time voltage

multiplier circuit

Connect capacitors between VC6+ and VS2-, between VC4+ and VS2-, between VC5+ and VS1-, between VC3+

and VS1-, and between V_OUT1and V_SS, and short the V_INand VC2+ pins to use this connection.

Should be used in the range of VIN = 2.7 to 3.7 V.

*1: The voltage range of V_INshould be set from 6V to 18.5V so that the voltage at the pin V_OUTdoes not

exceed the voltage multiplier output voltage operating range.

37/84

FEDL9445A-01

ML9445A

• 2^ndVoltage multiplier circuits

It consists of a voltage adjustment circuit and 2-time voltage multiplier circuit. The voltage adjustment circuit

operates in V_OUT1voltage systems, generates V_Hwhich is the base voltage of the 2^ndvoltage multiplier circuit, and

generates V_OUT2with 2-time voltage multiplication of V_H.

The connection example for 2^ndvoltage multiplier circuits is shown in Fig. 9.

V_SS

+

V_OUT2

+

V_H

+

VC7+

VS3-

Fig. 9 Connection examples for 2^ndvoltage multiplier circuits

Connect capacitors between V_OUT2and V_SS, between V_Hand V_SS, and between VC7+ and VS3-.

When you stop the 2^ndvoltage multiplier circuit and operate the V1 voltage adjustment circuit with the 1^stboost

output, short the V_OUT2pin to use V_Hand V_OUT2

.

38/84

FEDL9445A-01

ML9445A

•

Voltage adjustment circuit

The voltage multiplier output V_OUTproduces the LCD drive voltage V1 via the voltage adjustment circuit. Since

the ML9445A incorporates a high accuracy constant voltage generator, a 128-level electronic potentiometer

function, and also resistors for voltage V1 adjustment, it is possible to build a high accuracy voltage adjustment

circuit with very few components.

(a) When the internal resistors for voltage V1 adjustment are used

It is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands

and without needing any external resistors, if the internal voltage V1 adjustment resistors and the electronic

potentiometer function are used. The voltage V1 can be obtained by the following equation A-1 or A-2 in the

range of V1<VOUT.

Electronic potentiometer setting, DB7=0

V1 = (1 + (Rb/Ra)) • VEV = (1 + (Rb/Ra)) • (1 – (α/600)) • VREG (Eqn. A-1)

Electronic potentiometer setting, DB7=1

V1 = (1 + (Rb/Ra)) • VEV = (1 + (Rb/Ra)) • (1 – (α/300)) • VREG (Eqn. A-2)

With the setting of the most significant bit for the electronic potentiometer setting, the values of ∆V for each step

can be changed. DB7=1 has 2-time ∆V than DB7=0.

VEV (Constant voltage supply +

electronic potentiometer)

+

V1

–

VRS

(VREG)

VR

Internal Rb

Internal Ra

Fig. 10 V1 voltage adjustment circuit (equivalent circuit)

VREG is a constant voltage generated inside the IC and VRS pin output voltage.

Here, α is the electronic potentiometer function which allows one level among 128 levels to be selected by merely

setting the data in the 7-bit electronic potentiometer register. The values of α set by the electronic potentiometer

register are shown in Table 10.

Table 10 Relationship between electronic potentiometer register and α

α

DB6

DB5

DB4

DB3

DB2

DB1

DB0

127

126

125

0

1

0

1

0

1

0

1

0

1

For the V1 voltage setting using the electronic potentiometer function, the nominal value of the V1 output voltage

accuracy is ±2.5%.

39/84

FEDL9445A-01

ML9445A

This value is shown under the following conditions: Ta=25℃, 4-time the voltage V1 adjustment internal resistor

ratio, external resistor Vout=18.5V, no V1 load, and display OFF. Rb/Ra is the voltage V1 adjustment internal

resistor ratio and can be adjusted to one of 8 levels by the voltage V1 adjustment internal resistor ratio set

command. The reference values of the ratio (1 + Rb/Ra) according to the 3-bit data set in the voltage V1

adjustment internal resistor ratio setting register are listed in Table 11.

Table 11 Voltage V1 adjustment internal resistor ratio setting register values and the ratio

(1+Rb/Ra) (Nominal)

Register

(1 + Rb/Ra)

DB2

0

DB1

0

DB0

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0

1

0

1

0

1

0

1

0

1

0

1

Note: Use V1 gain in the range from 2.5 to 6 times. Because this LSI has temperature gradient, V1

voltage rises at lower temperatures. When using V1 gain of 6 times, adjust the built-in electronic

potentiometer so that V1 voltage does not exceed 18.5 V.

When V1 is set using the built-in resistance ratio, the accuracies are shown in Table 12.

Table 12 Relation between V1 Output Voltage Accuracy and V1 Gain Using Built-in Resistor

V1 gain

Parameter

Unit

2.5 times

3 times

±2.5

9

3.5 times

4 times

±2.5

12

4.5 times

5 times

±2.5

15

5.5 times

6 times

±2.5

18

V1 output voltage accuracy

V1 maximum output voltage

±2.5

%

V

7.5

10.5

13.5

16.5

Note: The V1 maximum output voltages in Table 12 are nominal values when Tj = 25°C, and electronic

potentiometer α = 0. The V1 output voltage accuracy in Table 12 are values when V1 load current

I = 0 µA, 18.5 V is externally input to V_OUT, and display is turned OFF.

(b) When external resistors are used (voltage V1 adjustment internal resistors are not used)

It is also possible to set the LCD drive power supply voltage V1 without using the internal resistors for voltage V1

adjustment but connecting external resistors (Ra' and Rb') between V_SS& VR and between VR & V1. Even in this

case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using

commands if the electronic potentiometer function is used.

The voltage V1 can be obtained by the following equation B-1 or B-2 in the range of V1<V_OUTby setting the

external resistors Ra' and Rb' appropriately.

When the Electronic potentiometer setting DB7=0

V1 = (1 + (Rb'/Ra')) • VEV = (1 + (Rb'/Ra')) • (1 – (α/600)) • VREG (Eqn. B-1)

When the Electronic potentiometer setting DB7=1

V1 = (1 + (Rb'/Ra')) • VEV = (1 + (Rb'/Ra')) • (1 – (α/300)) • VREG (Eqn. B-2)

40/84

FEDL9445A-01

ML9445A

External Rb'

VR

External Ra'

–

V_SS

V1

+

VEV (Constant voltage supply +

electronic potentiometer)

Fig. 11 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 = 7 V at Tj = 25°C

When the electronic potentiometer register value is set to the middle value of (DB7, DB6, DB5, DB4, DB3, DB2,

DB1, DB0) = (0, 1, 0, 0, 0, 0, 0, 0), the value of α will be 63 and that of VREG will be 3.0 V, and hence the

equation B-1 becomes as follows:

V1 = (1 + (Rb'/Ra')) • (1 – (α/600)) • VREG

7 = (1 + (Rb'/Ra')) • (1 – (63/600)) • 3.0 (Eqn. B-3)

Further, if the current flowing through Ra' and Rb' is set as 5 µA, the value of Ra' + Rb' will be - Ra' + Rb' = 1.4

MΩ (Eqn. B-4)

and hence,

Rb'/Ra' = 1.61, Ra' = 537 kΩ, Rb' = 863 kΩ.

In this case, the variability range of voltage V1 using the electronic potentiometer function will be as given in

Table 13.

Table 13 Example 1 of V1 variable-voltage range using electronic potentiometer function

V1

Min

Typ

Max

Unit

[V]

Variable-voltage range

6.17 (α = 127)

7.0 (α = 31)

7.82 (α = 0)

(c) When external resistors are used (voltage V1 adjustment internal resistors are not used) and a variable resistor

is also used

It is possible to set the LCD drive power supply voltage V1 using fine adjustment of Ra' and Rb' by adding a

variable resistor to the case of using external resistors in the above case. Even in this case, it is possible to control

the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic

potentiometer function is used.

The voltage V1 can be obtained by the following equation C-1 and C-2 in the range of V1<V_OUTby setting the

external resistors R₁, R₂(variable resistor), and R₃appropriately and making fine adjustment of R₂(∆R₂).

When the Electronic potentiometer setting DB7=0

V1 = (1 + (R₃+ R₂– ∆R₂)/(R₁+ ∆R₂)) • VEV

= (1 + (R₃+ R₂– ∆R₂)/(R₁+ ∆R₂)) • (1 – (α/600)) • VREG (Eqn. C-1)

When the Electronic potentiometer setting DB7=1

V1 = (1 + (R₃+ R₂– ∆R₂)/(R₁+ ∆R₂)) • VEV

= (1 + (R₃+ R₂– ∆R₂)/(R₁+ ∆R₂)) • (1 – (α/300)) • VREG (Eqn. C-2)

41/84

FEDL9445A-01

ML9445A

External R₃

External R₂

Rb'

Ra'

VR

–

+

∆ R₂

V1

External R₁

VEV (Constant voltage supply +

electronic potentiometer)

V_SS

Fig. 12 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 in the range 5 V to 9 V using R₂at Tj = 25°C .

When the electronic potentiometer register value is set to (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0),

the value of α will be 63 and that of VREG will be 3.0 V, and hence in order to make V1 = 9 V when ∆R₂= 0Ω, the

equation C-1 becomes as follows:

9 = (1 + (R₃+ R₂)/R₁) • (1 – (63/600)) • (3.0) (Eqn. C-2)

In order to make V1 = 5 V when ∆R₂= R₂,

5 = (1 + R₃/(R₁+R₂)) • (1 – (63/600)) • (3.0) (Eqn. C-3)

Further, if the current flowing between V_SSand V1 is set as 5 µA, the value of R₁+ R₂+ R₃becomes-

R₁+ R₂+ R₃= 1.8 MΩ (Eqn. C-4)

and hence,

R₁= 537 kΩ, R₂= 430 kΩ, R₃= 833 kΩ.

In this case, the variability range of voltage V1 using the electronic potentiometer function and the increment size

will be as given in Table 14.

Table 14 Example 2 of V1 variable-voltage range using electronic potentiometer function and

variable resistor

V1

Min

Typ

Max

Unit

[V]

Variable-voltage range

4.40(α = 127)

7.0 (α = 63)

10.06 (α = 0)

In Figures 11 and 12, the voltage VEV is obtained by the following equation by setting the electronic

potentiometer between 0 and 127.

VEV = (1 - (α/600)) • VREG

α = 0 : VEV = (1 – (0/600)) • 3.0 V = 3.0 V

α = 63 : VEV = (1 – (63/600)) • 3.0 V = 2.680 V

α = 127 : VEV = (1 – (127/600)) • 3.0 V = 2.365 V

The increment size of the electronic potentiometer at VEV when VREG = 3.0 is :

3.0 – 2.365

∆ =

= 5 mV (Nominal)

127

42/84

FEDL9445A-01

ML9445A

When the electronic potentiometer register value is set to DB7= 1

VEV=(1-(α/300))•VREG

α=0

α=63

α=127

： VEV = （1 – （0/300））・3.0V = 3.0V

： VEV = （1 – （63/300））・3.0V = 2.360V

： VEV = （1 – （127/300））・3.0V = 1.730V

When VREG = 3.0 V

The increment size is :

3.0 V – 1.730 V

∆ =

= 10 mV (Nominal)

127

* When using the voltage V1 adjustment internal resistors or the electronic potentiometer function, it is necessary

to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using

the power control setting command. Also, when the voltage multiplier circuit is OFF, it is necessary to supply

a voltage externally to the V_OUTpin.

* The pin VR is effective only when the voltage V1 adjustment internal resistors are not used (pin IRS = “L”).

Leave this pin open when the voltage V1 adjustment internal resistors are being used (pin IRS = “H”).

* Since the input impedance of the pin VR is high, it is necessary to take noise countermeasures such as using

short wiring length or a shielded wire .

* The supply current increases in proportion to the panel capacitance. When power consumption increases, the

V

_OUTlevel may fall. The voltage (V_OUT– V1) should be more than 3 V.

• LCD Drive voltage generator circuits

The voltage V1 is converted by resistive divider to produce V2, V3, V4, and V5 voltages. V2, V3, V4, and V5

voltages are impedance – converted by the voltage follower, and is supplied to the LCD voltage generator circuits.

A bias ratio is chosen by the bias set command.

Table 15 Relationship between LCD bias set command and V2,V3,V4,V5

LCD Bias Set Command Register Value (DB2, DB1, DB0)

Voltage

(0, 0, 0)

1/4 bias

(0, 0, 1)

1/5 bias

(0, 1, 0)

1/6 bias

(0, 1, 1)

1/7 bias

(1, 0, 0)

1/8 bias

(1, 0, 1)

1/9 bias

V2

V3

V4

V5

3/4•V1

2/4•V1

1/4•V1

4/5•V1

3/5•V1

2/5•V1

1/5•V1

5/6•V1

4/6•V1

2/6•V1

1/6•V1

6/7•V1

5/7•V1

2/7•V1

1/7•V1

7/8•V1

6/8•V1

2/8•V1

1/8•V1

8/9•V1

7/9•V1

2/9•V1

1/9•V1

43/84

FEDL9445A-01

ML9445A

• Application circuits

Fig. 13-1 to 13-6 show reference examples of power supply circuits.

(Two V1 pins are described in the following examples for explanation, but they are the same.)

Fig. 13-1 When all internal power supplies are used

VIN = VDD, 5-time voltage multiplication.

The internal V1 voltage adjustment resistor is used.

The internal V1 voltage adjustment resistor is not used.

V_DD

S

IRS

M/

IRS

M/

C1

+

C1

+

VC7+

VS3-

VC7+

VS3-

V_IN

C1

+

C1

+

VC6+

VC4+

VC2+

VS2-

VC5+

VC3+

VS1-

VC6+

VC4+

VC2+

VS2-

VC5+

VC3+

VS1-

C1

+

C1

+

R1 R2 R3

V1

OPEN

VR

V_SS

VR

V_SS

C3

C2

C3

C2

+

V_OUT2

V_H

V_OUT1

V1

V2

V3

V_OUT2

V_H

V_OUT1

V1

V2

V3

V4

V5

V4

V5

Fig. 13-2 When using the 1^stvoltage multiplier circuit, voltage adjustment circuit, and V/F circuit

(2^ndvoltage multiplier circuit is stopped)

VIN = VDD, 5-time voltage multiplication.

The internal V1 voltage adjustment resistor is not used.

V_DD

S

IRS

M/

OPEN

VC7+

VS3-

V_IN

C1

+

VC6+

VC4+

VC2+

VS2-

VC5+

VC3+

VS1-

C1

+

R1 R2 R3

V1

VR

V_SS

V_OUT2

V_H

V_OUT1

V1

V2

V3

C3

C2

+

V4

V5

44/84

FEDL9445A-01

ML9445A

Fig. 13-3 When using the 2^ndvoltage multiplier circuit, voltage adjustment circuit, and V/F circuit

(1^stvoltage multiplier circuit is stopped)

The voltage multiplier circuits are not used.

The internal V1 voltage adjustment resistor is used.

V_DD

S

IRS

M/

C1

+

VC7+

VS3-

V_IN

OPEN

VC6+

VC4+

VC2+

VS2-

VC5+

VC3+

VS1-

OPEN

VR

V_SS

C3

+

V_OUT2

V_H

V_OUT1

V1

V2

V3

V4

C3

C2

+

V5

Fig. 13-4 When using only the voltage adjustment circuit and V/F circuit

(The 1^stand 2^ndvoltage multiplier circuits are stopped)

The voltage multiplier circuits are not used.

The internal V1 voltage adjustment resistor is used.

V_DD

S

IRS

M/

OPEN

VC7+

VS3-

V_IN

OPEN

VC6+

VC4+

VC2+

VS2-

VC5+

VC3+

VS1-

OPEN

VR

V_SS

External

V_OUT2

V_H

V_OUT1

OPEN

Power

Supply

C1

C2

+

V1

V2

V3

V4

V5

45/84

FEDL9445A-01

ML9445A

Fig. 13-5 When using only V/F circuit

(The 1^stand 2^ndvoltage multiplier circuits and the voltage adjustment circuit are stopped)

The voltage multiplier circuits are not used.

The internal V1 voltage adjustment resistor is used.

V_DD

S

IRS

M/

OPEN

VC7+

VS3-

V_IN

OPEN

VC6+

VC4+

VC2+

VS2-

VC5+

VC3+

VS1-

OPEN

VR

V_SS

OPEN

V_OUT2

V_H

V_OUT1

V1

V2

V3

External

C2

+

Power

Supply

V4

V5

Fig. 13-6 When not using the internal power supply (all supplied from the external)

The voltage multiplier circuits are not used.

The internal V1 voltage adjustment resistor is used.

V_DD

S

IRS

M/

OPEN

VC7+

VS3-

V_IN

OPEN

VC6+

VC4+

VC2+

VS2-

VC5+

VC3+

VS1-

OPEN

VR

V_SS

OPEN

V_OUT2

V_H

V_OUT1

V1

External

V2

Power

Supply

V3

V4

V5

46/84

FEDL9445A-01

ML9445A

• Capacitor Setting Reference Values

The optimal values for the capacitors C1 and C2 shown in the reference examples of power supply circuits vary

depending on the size of the liquid crystal panel.

Determine the capacitance by displaying a pattern with a heavy load and selecting a value that stabilizes the LCD

drive voltage. Table 16 shows the setting reference values for capacitors.

Table 16 Capacitor Setting Reference Values

Symbol

C1

C2

Descriptions

Capacity for supply voltage regulation

Liguid crystal drive voltage retaining(smoothing) capacitor

Capacity for set-up circuits

Reference setting value [

1.0 4.7

0.47

1.0

μF]

～

4.7

C3

～

If the LCD panel is so large that the satisfactory display quality cannot be obtained by changing the capacitor

values, stop the internal power supply circuit, and supply the LCD drive voltage from the external.

• Notes on COG Mounting

When mounting the COG, there are resistance components caused by ITO wiring between the IC or external

connecting parts (capacitor, resistor) and the power supply. These resistance components may degrade the liquid

crystal display quality or may malfunction the IC. When designing a liquid crystal module, take the following three

points into account and evaluate them under the practical prerequisites.

1, Trace resistance of voltage multiplying system pins

This IC's voltage multiplier circuits are switched with a transistor with very low ON resistance. In mounting the

COG, ITO's trace resistance gets into the switching transistor in series and controls the voltage multiplication

ability. Pay attention to the proper wiring to each capacitor, including making the ITO wiring as thick as possible.

2, Trace resistance of power supply pins

When current flow occurs momentarily as in case of the display switching, the supply voltage may drop

momentarily in synchronization with the occurrence of current flow. If the ITO's wiring resistance to the power

supply pin is high at this time, the supply voltage fluctuates greatly inside the IC and may malfunction the IC.

Try to reduce the wiring impedance of the power supply line as much as possible to supply stabilized power to the

IC.

3, Creation of module sample with changed sheet resistance

Evaluate the sample with the ITO trace resistance value changed, and select a sheet resistance material which has

as much operating margin as possible.

4, Recommended ITO resistance value

VDD,VSS,VIN ：≦ 50Ω

VS1-,VS2-,VC4+,VC5+,VC6+,VS3-,VC7+ ： ≦ 50Ω

VOUT1,VOUT2：≦ 50Ω

VCH,VH,V1,V2,V3,V4,V5 ： ≦ 100Ω

DB0～DB7,A0,CS1,RD,WR：≦ 1kΩ

RES,SVD2 ： ≦ 10kΩ

47/84

FEDL9445A-01

ML9445A

• Examples of Settings for the Power Supply Circuit

Setting example: Setting VDD=VIN=5V, all internal power supplies are used, V1 voltage=13.475V】

1^stvoltage multiplier circuit is used (3-time voltage multiplier) (see Figure 7-2)

2^ndvoltage multiplier circuit is used (see Figure 9)

Power control register: (DB4, DB3, DB2, DB1, DB0) = (1, 1, 1, 1)

Voltage V1 adjustment internal resistance ratio: (1+Rb/Ra) =5.5

Voltage V1 adjustment internal resistance ratio register: (DB2, DB1, DB0) = (1, 1, 0)

The electronic potentiometer set: α=55

Electronic potentiometer register: (DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0) = (1, 1, 0, 0, 1, 0, 0, 0)

Vout1output voltage 5voltag

Vout2output voltage 18V

V1output =（1 + （Rb/Ra））・（1 ・（（αα・（a））・VREG

=5.5 × (1-55/300) × 3

=13.475V

Adjustment of 9.515V to 16.5V can be performed by setting change of electronic potentiometer register.

48/84

FEDL9445A-01

ML9445A

Application circuits

TEST1

VSS_O

SDAACK

SYNC

FR

OPEN

CL

DOF

CS1

CS2

RES

A0

RES

A0

VSS_O

WR

RD

WR

RD

VDD_O

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

VCH

SVD2

OPEN

TEST2

VDD_O

M/S

CLS

C86

P/S

IRS

TEST3

VSS

VDD

VIN

OPEN

VC3+

VC5+

VS1-

VC2+

VC4+

VS2-

VC6+

VOUT1

VH

VS3-

VC7+

VOUT2

VR

OPEN

VRS

V1

V2

V3

V4

V5

Master Operation: M/S="H"

Parallel Data Input: P/S="H"

80-Series MPU Interface: C86="L"

Internal Oscillation circuit: CLS="H"

V1 Adjusting - Internal Resistor is used : IRS="H"

1^stvoltage multiplier circuit is used (see Figure 7-2)

2^ndvoltage multiplier circuit is used

C0=0.1uF, C1=1.0uF, C2=1.0uF, C3=4.7uF

49/84

FEDL9445A-01

ML9445A

• Cascade Connection Example

It is possible to expand the display area by using the ML9445A in a multiple chip configuration.

LCDPanel

360×65 Dots

COM

SEG

ML9445A

Master

M/S

SEG

ML9445A

Slave

M/S

COM

FR

SYNC

CL

DOF

V_DD

V_SS

*

When the internal oscillator circuit is used.

It is recommended to supply the LCD drive power supply from the external.

It is possible to use the master-side internal power supply to supply the power to the slave. However,

in this case, the required voltage may not be obtained due to the ITO trace resistance or the LCD

panel load. Make a thorough evaluation before using this configuration.

• Initial setting

Note: If electric charge remains in smoothing capacitor connected between the LCD driver voltage output pins (V1

to V5) and the V_SSpin, a malfunction might occur: the display screen gets dark for an instant when powered

on.

To avoid a malfunction at power-on, it is recommended to follow the flowchart in the “EXAMPLES OF

SETTINGS FOR THE INSTRUCTIONS” section in page 63.

50/84

FEDL9445A-01

ML9445A

LIST OF OPERATION

DBn

No Operation

A0 RD WR

Comment

7 6 5 4 3 2 1 0

1 0 1 0 1 1 1 0

1 0 1 0 1 1 1 1

Display OFF

0

1

0

LCD Display:

OFF when DB0 = 0 ON when DB0 = 1

1

Display ON

Forward or reverse LCD display mode

Forward when DB0 = 0

Reverse when DB0 = 1

Forward

Reverse

1 0 1 0 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 0 0 1 0 0

1 0 1 0 0 1 0 1

1 1 0 0 0 1 0 0

1 1 0 0 0 1 0 1

0

1

0

2

3

4

Display

LCD

OFF(Normal display)

ON

LCD

All-on display

Normal display when DB0 = 0

All-on display when DB0 = 1

Selects the common output scanning direction.

Forward when DB０ = 0

Reverse when DB0 = 1

Common output state

select

Display start line set

(2-byte command)

1 0 0 0 1 0 1 0

* * address

0

1

0

The display starting line address in the display

RAM is set.

5

6

Page address set

(2-byte command)

1 0 1 1 0 0 0 0

* * * address

0

1

0

The page address in the display RAM is set.

Column address set

(upper bits)

0 0 0 1 address

(upper bits)

The upper 4 bits of the column address in the

display RAM is set.

7

Column address set

(lower bits)

0 0 0 0 address

(lower bits)

The lower 4 bits of the column address in the

display RAM is set.

8

9

Display data write

Display data read

Write data

Read data

1

0

1

Writes data to the display data RAM.

Reads data from the display data RAM.

Display RAM data input direction.

Column direction when DB0=1

Page direction when DB0=1

1 0 0 0 0 1 0 0

1 0 0 0 0 1 0 1

0

1

0

Display data input direction

select

10

Correspondence to the segment output for the

display data RAM address.

Forward when DB0 = 0

Forward

1 0 1 0 0 0 0 0

1 0 1 0 0 0 0 1

0

1

0

11 ADC select

Reverse

Reverse when DB0 = 1

n-line inversion drive

register set

(2-byte command)

0 0 1 1 0 0 0 0

* * * ^{Invert line count}

12

0

1

0

Line invert drive. Set the line count.

Resets the line invert drive.

n-line OFF when DB0 = 0

n-line ON when DB1 = 1

n-line

13 inversion

OFF

ON

1 1 1 0 0 1 0 0

1 1 1 0 0 1 0 1

0

1

0

drive

0 1 1 0 1 1 0 1

* * Number of Duty

* * Start line

0

1

0

Display Duty set

(3-byte command)

14

Display duty set.

Incrementing column address

During a write: +1

During a read: 0

15 Read-modify-write

16 end

1 1 1 0 0 0 0 0

0

1

0

1 1 1 0 1 1 1 0

1 0 1 0 1 0 1 0

0

1

0

Releases the read-modify-write state.

Built-in oscillator circuit operation.

OFF when DB0 = 0

ON when DB1 = 1

OFF

ON

17 Built-in OSC

1 0 1 0 1 0 1 1

0 1 1 1 Frequency

0

1

0

Built-in oscillator frequency

select

18

19

Built-in oscillator frequency select.

Power control set

(2-byte command)

0 0 1 0 1 0 0 0

* * * * State

0

1

0

Select built-in power supply operation state.

51/84

FEDL9445A-01

ML9445A

0 0 1 0 0

Resistance

ratio setting

Voltage V1 adjustment

internal resistance ratio set

20

0

1

0

Selects the internal resistor ratio.

DBn

No Operation

A0 RD WR

Comment

7 6 5 4 3 2 1 0

0 1 0 1 0 0 0 0

* * * * * bias

1 0 0 0 0 0 0 1

Electronic volume

LCD bias set

21

0

1

0

Sets the LCD drive voltage bias ratio.

(2-byte command)

Electronic volume set

(2-byte command)

Sets data in the electronic potentiometer

register to adjust the V1 output voltage.

22

Discharges power supply circuit connection

capacitor.

OFF when DB0 = 0

OFF

1 1 1 0 1 0 1 0

1 1 1 0 1 0 1 1

0

1

0

23 Discharge

ON

ON when DB1 = 1

Power save

OFF when DB0 = 0

ON when DB1 = 1

OFF

ON

1 0 1 0 1 0 0 0

1 0 1 0 1 0 0 1

0

1

0

24 Power save

Temperature gradient

select

Setting of temperature gradient of LCD

voltage.

25

0 1 0 0 1 gradient

* * * * * gradient

0

1

0

1

26 Status read

Issues the temperature gradient select bit.

27 Reset

1 1 1 0 0 0 1 0

0 1 1 0 1 0 0 0

0 1 1 0 1 0 0 1

1 1 0 0 0 0 0 0

0

1

0

Reset command

Temperature

sensor

OFF

ON

Temperature sensor

OFF when DB0 = 0 ON when DB0 = 1

28

DB=0 : COM0

DB=1 : COM0

→COM1→ →COM63

Common output direction

select

29

30

→COM32→COM33→→COM31→COM63

1 1 0 0 0 0 0 1

0 1 0 1 0 1 0 1

Multiplier clock frequency

select (2-byte command)

Multiplier clock frequency select

Non-operation command

* * * * * * Frequency

31 NOP

1 1 1 0 0 0 1 1

*: Invalid data (input: Don’t care, output: Unknown)

52/84

FEDL9445A-01

ML9445A

DESCRIPTIONS OF OPERATION

Display ON/OFF (Write)

This is the command for controlling the turning on or off the LCD panel. The LCD display is turned on when a “1”

is written in bit DB0 and is turned off when a “0” is written in this bit.

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

1

DB2

1

DB1

1

DB0

1

Display ON

Display OFF

0

1

0

1

0

1

0

Forward/Reverse Display Mode (Write)

It is possible to toggle the display on and off condition without changing the contents of the display data RAM. In

this case, the contents of the display data RAM will be retained.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RAM Data

Display on when “H”

Display on when “L”

Forward

Reverse

0

1

0

1

0

1

0

1

LCD Display All-on ON/OFF (Write)

Using this command, it is possible to forcibly turn ON all displays irrespective of the contents of the display data

RAM. In this case, the contents of the display data RAM will be retained. Also, all displays can be in white in

combination with a display inversion command.

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

0

DB2

1

DB1

0

DB0

0

All-on display OFF

(Normal display)

All-on display ON

0

1

0

1

0

1

0

1

The power save mode will be entered into when the Display all-on ON command is executed in the display OFF

condition.

Common Output State Select (Write)

This command is used for selecting the scanning direction of the common output pins.

Scanning direction

COM0 COM63

COM63 COM0

A0

0

DB7

1

DB6

1

DB5

0

DB4

0

DB3

0

DB2

1

DB1

0

DB0

0

Forward

Reverse

→

0

1

0

1

0

1

*: Invalid data

53/84

FEDL9445A-01

ML9445A

Display Start Line Set (2-byte command)

This command specifies the display starting line address in the display data RAM.

Normally, the topmost line in the display is specified using the display start line set command.

It is possible to scroll the display screen by dynamically changing the address using the display start line set

command. This command is a 2-byte command to be used together with the Display Start Line Set Mode Set

Command and Display Start Line Set Register Set Command. So, be sure to set the both commands continuously.

• Display Start Line Set Mode Set (Write)

When this command is input, the Display Start Line Set Command becomes valid. Once the display start line set

mode is selected, any command other than the Display Start Line Set Command cannot be used. This status is

released when any data is stored in the register by the Display Start Line Set Command.

A0

0

DB7

1

DB6

0

DB5

0

DB4

0

DB3

1

DB2

0

DB1

1

DB0

0

• Display Start Line Set Register Set (Write)

Setting of data to low order 7 bits of the display start line register by this command allows specification of the

display start line address of the display data RAM. In addition, the most significant bit is for data setting of COM

output pins only for indicators (COMS), and the data of 80H for 0 and 81H for 1 is for indicators.

After the display start line register is set by inputting this command, the display start line mode is released.

Line

COMS

Data

A0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

address

00H

01H

02H

03H

0

1

0

1

0

1

80H

7EH

7FH

00H

01H

02H

03H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

81H

7EH

7FH

0

1

0

1

Sequence of setting the Display Start Line

Set Display Start Line Mode

Set Display Start Line Register

The display start line set mode is released

54/84

FEDL9445A-01

ML9445A

Page Address Set (2-byte command)

This command specifies the page address which corresponds to the lower address when accessing the display data

RAM from the MPU side.

It is possible to access any required bit in the display data RAM by specifying the page address and the column

address. This command is a 2-byte command to be used together with the Page Address Mode Set Command and

Page Address Resister Set Command. So, be sure to set the both commands continuously.

• Page Address Mode Set (Write)

When this command is input, the Page Address Mode Set Command becomes valid. Once the Page Address Mode

is selected, any command other than the Page Address Resister Set Command cannot be used. This status is

released when any data is stored in the register by the Page Address Resister Set Command.

A0

0

DB7

1

DB6

0

DB5

1

DB4

1

DB3

0

DB2

0

DB1

0

DB0

0

• Page Address Register Set (Write)

When a 5-bit data is set in the page address register by this command, the line address takes the following value.

After the page address register is set by inputting this command, the display page address set mode is released.

Page address

Page 0

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

*

0

1

0

1

0

Page 1

0

Page 3

0

Page 16

Page 17

0

*

1

0

1

*: Invalid data

Note: Do not specify values that do not exist as an address.

Sequence of setting the Page Address Register

Set Page Address Mode

Set Page Address Register

The display start line set mode is released

55/84

FEDL9445A-01

ML9445A

Column Address Set (Write)

This command specifies the column address of the display data RAM. The column address is specified by

successively writing the upper 4 bits and the lower 4 bits.

A0

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

a7

DB2

a6

DB1

a5

DB0

a4

Upper bits

Lower bits

0

a3

a2

a1

a0

Column address

a7

0

a6

a5

a4

0

a3

0

a2

a1

a0

0

00H

01H

02H

0

1

0

1

0

B2H

B3H

1

0

1

0

1

0

1

Note: Do not specify values that do not exist as an address.

Display Data Write (Write)

This command writes an 8-bit data at the specified address of the display data RAM. After writing, column address

or page address is automatically incremented +1 by the Display Data Input Direction Select command. This

enables the MPU to write the display data continuously.

A0

1

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write data

Display Data Read (Read)

This command read the 8-bit data from the specified address of the display data RAM. Since the column address is

automatically incremented (by +1) after reading the data, the MPU can read successive display data from the

display data RAM. Further, one dummy read operation is necessary immediately after setting the column data or

page data. The display data cannot be read out when the serial interface is being used.

A0

1

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Read data

Display Data Input Direction Select (Write)

This command sets the direction where the display RAM address number is automatically incremented.

A0

0

DB7

1

DB6

0

DB5

0

DB4

0

DB3

0

DB2

1

DB1

0

DB0

Column

Page

0

1

0

1

0

1

0

56/84

FEDL9445A-01

ML9445A

ADC Select (Segment driver direction select) (Write)

Using this command it is possible to reverse the relationship of correspondence between the column address of the

display data RAM and the segment driver output. It is possible to reverse the sequence of the segment driver

output pin by the command.

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

0

DB2

0

DB1

0

DB0

0

Forward

Reverse

0

1

0

1

0

1

n-line Inversion Drive Register Set (2-byte command)

This command sets the number of inversion lines of the liquid crystal AC drive to the register and starts line

inversion drive. This command is a 2-byte command to be used together with the n-line inversion drive register

mode set command and the n-line inversion drive register set command. So, be sure to set the both commands

continuously.

• n-line Inversion Drive Register Mode Set (Write)

When this command is input, the n-line inversion drive register set command becomes valid.

Once the n-line inversion drive register mode is selected, any command other than the n-line inversion drive

register set command cannot be used. This status is released when any data is stored in the register by the n-line

inversion drive register set command.

A0

0

DB7

0

DB6

0

DB5

1

DB4

1

DB3

0

DB2

0

DB1

0

DB0

0

• n-line Inversion Drive Register Set (Write)

Setting of 5-bit data in the n-line inversion drive register by this command allows specification of the number of

inversion lines. The n-line inversion drive register mode is released after the n-line inversion drive register is set by

inputting this command.

Number of line reversal

A0

*

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

2

3

*

0

1

0

1

0

*

31

32

1

0

1

*: Invalid data

57/84

FEDL9445A-01

ML9445A

Sequence of setting the Display Start Line

n-Line Inversion Drive Mode

n-Line Inversion Drive Register

n-Line Inversion Drive set mode is released

n-line Inversion Drive ON/OFF (Write)

This command provides ON/OFF control of n-line inverting drive.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

0

DB2

1

DB1

DB0

0

OFF

ON

0

1

0

1

Display Duty Set (3-byte command)

This command allows change display duty.

Setting of the start line and duty of common output allows display of arbitrary location and the number of lines.

COM output only for indicators (COMS) is output always after end line output. In addition, if the built-in oscillator

circuit is used, execute master clock division depending on the setting. 1/65 to 1/50 duty: No division, 1/49 to 1/34

duty: 2/3 division, 1/33 to 1/18: 1/2 division, 1/18 duty or less: 1/4 division

This command is a 3-byte command to be used in combination with the display duty mode set command, display

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢂꢆꢅꢄꢉꢆꢂꢄꢊꢋꢌꢌꢍꢎꢀꢏꢄꢉꢂꢍꢅꢂꢄꢐꢈꢎꢆꢄꢅꢆꢇꢈꢉꢂꢆꢅꢄꢉꢆꢂꢄꢊꢋꢌꢌꢍꢎꢀꢑꢄꢍꢎꢀꢄꢂꢒꢆꢅꢆꢓꢋꢅꢆꢄꢔꢆꢄꢉꢁꢅꢆꢄꢂꢋꢄꢁꢉꢆꢄꢂꢒꢆꢄꢂꢒꢅꢆꢆꢄꢊꢋꢌꢌꢍꢎꢀꢉꢄ

continuously.

• Display Duty Mode Set (Write)

When this command is input, the display duty register set command and start line register set command become

valid. Once the display duty mode is selected, any command other than the display duty register set command/start

line register set command cannot be used. This status is released when any data is stored in the register by the

display duty register set command and start line register set command.

A0

0

DB7

0

DB6

1

DB5

1

DB4

0

DB3

1

DB2

1

DB1

0

DB0

1

58/84

FEDL9445A-01

ML9445A

• Display Duty Register Set (Write)

When a 6-bit data is set in the display duty register by this command, the display duty address takes the following

value.

Display Duty

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1/3

1/4

1/5

*

0

1

*

0

1

0

1/64

1/65

0

*

1

0

1

*: Invalid data

• Start Line Register Set (Write)

When a 6-bit data is set in the start line register by this command, the start line address takes the following value.

When the status of common output is reversed, the commons in parentheses first will start. After the start line

register is set by inputting this command, the display duty set mode is released.

Start Line

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

COM0 (COM63)

COM1 (COM62)

COM2 (COM61)

COM3 (COM60)

*

0

1

0

1

0

1

0

COM62 (COM1)

COM63 (COM0)

0

*

1

0

1

*: Invalid data

Sequence of setting the Display Duty Set Register

Set Display Duty Mode

Set Display Duty Register

Set Start Line Register

The display start line set mode is released

59/84

FEDL9445A-01

ML9445A

Read Modify Write (Write)

This command is used in combination with the end command. When this command is issued once, the page

address and column address are not changed when the display data read command is issued, but is incremented (by

+1) only when the display data write command is issued. (The incremental direction can be set by the display data

input direction select command.) This condition is maintained until the end command is issued. When the end

command is issued, the column address is restored to the address that was effective at the time the read modify

write command was issued last. Using this function, it is possible to reduce the overhead on the MPU when

repeatedly changing the data in special display area such as a blinking cursor.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

0

DB2

0

DB1

0

DB0

0

End (Write)

This command releases the read-modify-write mode and restores the page address and column address to the value

at the beginning of the mode.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

1

DB2

1

DB1

1

DB0

0

Restored

....

N

N + 1 N + 2

N + m

N

N + 3

Column address

or

Page address

Read-modify-write mode set

End

Built-in Oscillator Circuit ON/OFF (Write)

This command starts the built-in oscillator circuit operation. It is enabled only in the master operation mode (M/S

=HIGH) when built-in oscillator circuit is valid (CLS=HIGH).

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

1

DB2

0

DB1

1

DB0

0

OFF

ON

0

1

0

1

0

1

0

1

60/84

FEDL9445A-01

ML9445A

Operation Clock Frequency Select (Write)

This command sets the dividing rate of the internal operation clock for the built-in oscillator frequency fosc. It is

enabled only when the built-in oscillator circuit in ON. It is divided together with the display Duty set division.

When the built-in oscillator circuit is OFF, the external clock f_EXTto be input to CL pin directly becomes the

internal operation clock.

Ratio of dividing

A0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

frequency

1/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1/4.5

1/5

1/5.5

1/6

1/7

1/8

1/10

1/12

1/14

1/16

1/18

1/20

1/24

1/28

1/32

Frame frequencies for typical numbers of display lines are listed below.

Frame Frequency [Hz]

DB3

DB2

DB1

DB0

65 Line

200

178

160

145

133

114

100

80

50 Line

260

231

208

189

173

149

130

104

87

49 Line

34 Line

255

227

204

185

170

146

127

102

85

33 Line

197

18 Line

361

321

289

263

241

206

181

144

120

103

90

17 Line

191

170

153

139

127

109

96

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

177

157

141

129

118

101

88

175

158

143

131

113

98

71

79

76

67

59

66

64

57

74

51

73

56

55

50

65

44

64

49

48

44

58

39

57

44

80

42

40

52

35

51

39

72

38

33

43

29

42

33

60

32

29

37

25

36

28

52

27

25

33

22

32

25

45

24

The table above shows the values at 25°C

61/84

FEDL9445A-01

ML9445A

The calculation formula for frame frequencies is shown below. It depends on the number of Duty sets.

Duty

1/65 to 1/50 duty

1/49 to 1/34 duty

1/33 to 1/18 duty

1/17 or less

LCD frame frequency (f_FR

)

F_OSC/(16*n*L)

F_OSC*(2/3) /(16*n*L)

F_OSC*(1/2) /(16*n*L)

F_OSC*(1/4) /(16*n*L)

Ratio of dividing frequency: n , Number of Display Line : L

Power Control Set (2-byte command)

This command set the functions of the power supply circuits. This command is a 2-byte command to be used

together with the Power Control Mode Set Command and Power Control Register Set Command.

• Power Control Mode Set (Write)

When this command is issued, the power control register set command becomes effective. Once the power control

mode is set, it is not possible to issue any command other than the power control register set command. This

condition is released after data has been set in the register using the power control register set command.

A0

0

DB7

0

DB6

0

DB5

1

DB4

0

DB3

1

DB2

0

DB1

0

DB0

0

• Power Control Register Set (Write)

When a power supply circuit is set in the power control register by this command, the line address takes the

following value. After the display start line is set by inputting this command, the power control set mode is

released.

A0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

2^ndvoltage multiplier circuit: OFF

2^ndvoltage multiplier circuit: ON

0

1

1^stvoltage multiplier circuit: OFF

0

1

1^stvoltage multiplier circuit: ON

0

*

Voltage adjustment circuit: OFF

Voltage adjustment circuit: ON

0

1

Voltage follower circuits: OFF

Voltage follower circuits: ON

0

1

*: Invalid data

Sequence of setting the Power Control Register

Set Power Control Mode

Set Power Control Register

The power control mode is released

62/84

FEDL9445A-01

ML9445A

Voltage V1 Adjustment Internal Resistor Ratio Set

This command sets the ratios of the internal resistors for adjusting the voltage V1.

Resistor ratio

A0

0

DB7

0

DB6

0

DB5

1

DB4

0

DB3

0

DB2

0

DB1

0

DB0

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Note: Because this LSI has temperature gradient, V1 rises at lower temperatures. When using V1 gain

of 6 times, adjust the built-in electronic potentiometer so that V1 does not exceed 18.5 V.

LCD Bias Set (2-byte command)

This command is used for selecting the bias ratio of the voltage necessary for driving the LCD device or panel.

This command is a 2-byte command to be used together with the LCD Bias Set Command and LCD Bias Register

Set Command.

• LCD Bias Mode Set (Write)

When this command is issued, the LCD bias register set command becomes effective. Once the LCD bias mode is

set, it is not possible to issue any command other than the LCD bias register set command. This condition is

released after data has been set in the register using the power LCD bias register set command.

A0

0

DB7

0

DB6

1

DB5

0

DB4

1

DB3

0

DB2

0

DB1

0

DB0

0

63/84

FEDL9445A-01

ML9445A

• LCD Bias Register Set (Write)

The bias ratio is set with setting of data to the LCD bias register with this command. After this command is input

and the LCD bias register is set, the LCD bias mode is released.

LCD bias

1/4 bias

1/5 bias

1/6 bias

1/7 bias

1/8 bias

1/9 bias

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

0

DB1

0

DB0

0

*

0

1

0

1

0

1

0

1

0

1

0

1

*: Invalid data

(1,1,0) and (1,1,1) settings are forbidden.

Sequence of setting the LCD Bias Register

Set LCD Bias Mode

Set LCD Bias Register

The LCD bias mode is released

64/84

FEDL9445A-01

ML9445A

Electronic Potentiometer (2-byte command)

This command is used for controlling the LCD drive voltage V1 output by the voltage adjustment circuit of the

internal LCD power supply and for adjusting the intensity of the LCD display. This is a two-byte command

consisting of the Electronic potentiometer mode set command and the Electronic potentiometer register set

command, both of which should always be issued successively as a pair.

• Electronic potentiometer mode set (Write)

When this command is issued, the electronic potentiometer register set command becomes effective.

Once the electronic potentiometer mode is set, it is not possible to issue any command other than the Electronic

potentiometer register set command. This condition is released after data has been set in the register using the

Electronic potentiometer register set command.

A0

0

DB7

1

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

1

• Electronic potentiometer register set (Write)

By setting a 7-bit data in the electronic potentiometer register using this command, it is possible to set the LCD

drive voltage V1 to one of the 128 voltage levels.

The electronic potentiometer mode is released after some data has been set in the electronic potentiometer register

using this command.

⊿

V

α

A0

0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

127

126

125

124

0

1

0

1

0

1

0

small

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

127

126

125

124

large

1

0

1

0

1

Sequence of setting the electronic potentiometer register:

Electronic potentiometer mode set

potentiometer

The electronic potentiometer mode is released

65/84

FEDL9445A-01

ML9445A

Discharge ON/OFF (Write)

This command discharges the capacitors connected to the power supply circuit.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

1

DB2

0

DB1

DB0

0

OFF

ON

1

0

1

0

1

0

1

This command short circuits each liquid crystal potential (V1 to V5) and Vss. When voltage is supplied to each

liquid crystal drive potential externally, be sure to turn off the external power before executing this command.

Power Save ON/OFF (Write)

This command establishes the power save mode, thereby ensuring a substantial reduction of current consumption.

A0

0

DB7

1

DB6

0

DB5

1

DB4

0

DB3

1

DB2

0

DB1

0

DB0

0

OFF

ON

0

1

0

1

0

1

0

1

In the power save status, the display data and operation status before power save activation are held, and the

display data RAM can be accessed from MPU.

The power save OFF command is to release the power save status, and it returns to the status before the power save

activation. If built-in power supply is used, it is turned on after the power save OFF command execution, and after

a fixed time period for stabilization of the output voltage, the display operation is started.

The internal conditions in the power save mode are as follows:

(1) Stop of internal oscillator circuit.

(2) Stop of LCD power supply circuit.

(3) Stop of liquid crystal drive circuit (VSS level output is issued as the segment and common driver output).

(4) Operation of VCH generation circuit and temperature sensor circuit.

Temperature Gradient Set

This command sets the temperature gradient characteristics of the liquid crystal drive voltage output from the

built-in power supply circuit from eight states to one state. The temperature gradient of the liquid crystal drive

voltage can be set according to the liquid crystal temperature gradient to be used.

Temperature gradient [%/°C]

A0

0

DB7

0

DB6

1

DB5

0

DB4

0

DB3

1

DB2

0

DB1

0

DB0

0

0.00

-0.03

-0.06

-0.08

-0.10

-0.13

-0.15

-0.18

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

66/84

FEDL9445A-01

ML9445A

Status Read (Read)

This command reads out the temperature gradient select bit set on the register.

A0

DB7

*

DB6

*

DB5

*

DB4

*

DB3

*

DB2

T1

DB1

T2

DB0

T3

0

*: Invalid data

Reset (Write)

This command initializes the display start line number, column address, page address, common output state,

voltage V1 adjustment internal resistor ratio and the electronic potentiometer function, and also releases the

read-modify-write mode or the test mode. This command does not affect the contents of the display data RAM.

The reset operation is made after issuing the reset command.

The initialization after switching on the power is carried out by the reset signal input to the RESpin.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

0

DB2

0

DB1

1

DB0

0

Temperature Sensor ON/OFF (Write)

ON/OFF of a temperature sensor is specified with this command.

A0

0

DB7

0

DB6

1

DB5

1

DB4

DB3

DB2

0

DB1

DB0

OFF

ON

0

1

0

1

0

1

0

The temperature sensor circuit is controlled independently from Power Save Command.

Common Output Direction Select (Write)

This command sets the direction of the common output pin.

Direction

Normal Type

Comb Type

A0

0

DB7

1

DB6

1

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

0

1

0

1

Normal Type: COM0→COM1→ …. →COM63

Comb Type: COM0→COM32→COM1→COM33→ …. →COM31→COM63

67/84

FEDL9445A-01

ML9445A

Multiplier Clock Frequency Select (2-byte command)

This command selects the multiplier clock frequency of the 1^stand 2^ndvoltage multiplier circuits. This command is

a 2-byte command to be used together with the multiplier clock frequency select mode set command and the

multiplier clock frequency select register set command. So, be sure to set the both commands continuously.

• Multiplier Clock Frequency Select mode set (Write)

When this command is input, the multiplier clock frequency select register set command becomes valid. Once the

multiplier clock frequency select mode is selected, any command other than the multiplier clock frequency select

register set command cannot be used. This status is released when any data is stored in the register by the multiplier

clock frequency select register set command.

A0

0

DB7

0

DB6

1

DB5

0

DB4

1

DB3

0

DB2

1

DB1

0

DB0

1

• Multiplier Clock Frequency register set (Write)

Setting of data in the multiplier clock frequency select register by this command allows specification of the

multiplier clock frequency. The multiplier clock frequency select mode is released when the multiplier clock

frequency select register is set by inputting this command.

Frequency

A0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Internal Clock

fOSC/64

External Clock

fEXT/8

0

1

0

1

*

fOSC/32

fEXT/4

fOSC/16

fEXT/2

Sequence of setting the multiplier clock frequency register:

Multiplier Clock Frequency mode set

Multiplier Clock Frequency

The Multiplier Clock Frequency mode is released

NOP (Write)

This is a No Operation command.

A0

0

DB7

1

DB6

1

DB5

1

DB4

0

DB3

0

DB2

0

DB1

1

DB0

1

68/84

FEDL9445A-01

ML9445A

Initialized Condition Using the RES pin

This LSI goes into the initialized condition when the RESinput goes to the “L” level. The initialized condition

consists of the following conditions.

(1) Display OFF

(2) Forward display mode

(3) All-on display off

(4) Common output state: Forward

(5) Display start line: Set to 1^stline, Indicator address: Set to 80H

(6) Page address: Set to 0 page

(7) Column address: Set to 0 address

(8) Display data input direction: Column direction

(9) ADC select: Incremented (ADC command DB0 = “L”)

(10) n-line inversion drive: OFF

(11) n-line reversal number register: (DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0)

(12) Display duty set: 1/65Duty, Start Line COM0

(13) Read-modify-write: OFF

(14) Built-in oscillation circuit: OFF

(15) Oscillation frequency register: (DB4, DB3, DB2, DB1, DB0) = (0, 0, 0, 0)

(16) Power control register: (DB4, DB3, DB2, DB1, DB0) = (0, 0, 0, 0)

(17) Voltage V1 adjustment internal resistor ratio register: (DB2, DB1, DB0) = (1, 0, 0)

(18) LCD Power supply bias ratio: 1/9 bias

(19) The electronic potentiometer register set mode is released.

Electronic potentiometer register: (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0)

(20) Discharge: OFF

(21) Power save: OFF

(22) Temperature gradient resistor: (DB2, DB1, DB0) = (0, 0, 0) (0.00%/°C)

(23) Register data in the serial interface: Clear

(24) Temperature sensor: OFF

(25) Common Output Direction: Normal

(26) Multiplier Clock Frequency: (DB1, DB0)=(0,0)

On the other hand, when the reset command is used, only the conditions (6) to (7), (13) above are set. As is shown

in the “MPU Interface (example for reference)”, the RESpin is connected to the Reset pin of the MPU and the

initialization of this LSI is made simultaneously with the resetting of the MPU. This LSI always has to be reset

using the RESpin at the time the power is switched ON. Also, excessive current can flow through this LSI when

the control signal from the MPU is in the high impedance state. It is necessary to take measures to ensure that the

input pins of this LSI do not go into the high impedance state after the power has been switched ON.

69/84

FEDL9445A-01

ML9445A

EXAMPLES OF SETTINGS FOR THE INSTRUCTIONS

Initial setup

V_DD-V_SSPower supply ON when the pin RES= “L”

Power supply stabilization

Release reset state (RESPin = “H”)

Initial settings state (default)

*1

Function setting using command input (user settings)

*2

*3

*4

*5

*6

*7

Display Forward/Reverse

LCD Display All-on ON/OFF

Common Output State Select

Display Start Line Set

ADC Select

Display Duty Set

*(a)

Function setting using command input (user settings)

n-line Inversion Drive Register Set

n-line Inversion Drive ON/OFF

*8

*9

Function setting using command input (user settings)

Built-in Oscillator Frequency Select

Built-in Oscillator Circuit ON/OFF

*10

*11

Function setting using command input (user settings)

LCD Bias Set

*12

*13

*14

*15

*16

When the external LCD power supply

circuit is used

External LCD power supply entry

Voltage V1 Adjustment Internal Resistor Ratio Set

Electronic Potentiometer

Temperature Gradient Set

Power Control Set

Wait for stabilization of the external

LCD power supply

*(b)

Wait for more than 300 ms

Initial setting state complete

*(a): Carry out power control set within 5ms after releasing the reset state.

The 5ms duration changes depending on the panel characteristics and the value of the smoothing

capacitor. We recommend verification of operation using an actual unit.

*(b): When trace resistance in COG mounting does not exist, wait for over 300 ms.

Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier

capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI.

Notes: Sections to be referred to

*1:

*2:

*3:

*4:

*5:

*6:

*7:

*8:

Functional description “Reset circuit”

Description of operation “Forward/Reverse Display Mode”

Description of operation “LCD Display All-on ON/OFF”

Description of operation “Common Output Status Select”

Description of operation “Display Start Line Set”

Description of operation “ADC Select”

Description of operation “Display Duty Set”

Description of operation “n-line Inversion Drive Register Set”

70/84

FEDL9445A-01

ML9445A

*9:

Description of operation “n-line Inversion Drive ON/OFF”

*10: Description of operation “Built-in Oscillator Frequency Select”

*11: Description of operation “Built-in Oscillator Circuit ON/OFF”

*12: Description of operation “LCD Bias Set”

*13: Functional description “Power supply circuit”,

Operation description “Voltage V1 adjustment internal resistor ratio set”

*14: Functional description “Power supply circuit”,

Operation description “Electronic Potentiometer”

*15: Operation description “Temperature Gradient Set”

*16: Functional description “Power supply circuit”,

Operation description “Power Control set”

71/84

FEDL9445A-01

ML9445A

Data Display

End of initial settings

Function stabilization using command input (user settings)

Display data input direction select

*17

Function stabilization using command input (user settings)

Page address set

*18

Function stabilization using command input (user settings)

Column address set

*19

Function stabilization using command input (user settings)

Display data write

*20

Function stabilization using command input (user settings)

Display ON/OFF

*21

End of data display

Notes: Sections to be referred to

*17: Description of operation “Display Data Input direction Select”

*18: Description of operation “Page Address Set”

*19: Description of operation “Column Address Set”

*20: Description of operation “Display Data Write”

*21: Description of operation “Display ON/OFF”

72/84

FEDL9445A-01

ML9445A

Power Supply OFF (*22)

Any state

Function stabilization using command input (user settings)

Power Save ON

*23

When an external LCD power supply circuit is used

External LCD power supply OFF

Function stabilization using command input (user settings)

Discharge ON

*24

V_DD-V_SSPower supply OFF

Notes: Sections to be referred to

*22: The power supply of this LSI is switched OFF after switching OFF the internal power supply.

Function description “Power supply circuit”

If the power supply of this LSI is switched OFF when the internal power supply is still ON, since

the state of supplying power to the built-in LCD drive circuits continues for a short duration, it

may affect the display quality of the LCD panel. Always follow the power supply switching OFF

sequence.

*23: Description of operation “Power Save”

*24:

Description of operation “Discharge”

73/84

FEDL9445A-01

ML9445A

Refresh

Although the ML9445A holds operation state by commands, excessive external noise might change the internal

state.

On a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from

occurring. It is recommended to use the refresh sequence periodically to control sudden noise.

- Display Forward/Reverse

- Set “LCD ALL-on display“ OFF

- Common output state select

- Display start line set

- ADC select

- Display Duty set

Set to the state in which all commands have been set.

- n-line inversion drive register set

- n-line inversion drive ON/OFF

- LCD bias set

- Voltage V1 adjustment internal resistance

ratio set

- Electronic potentiometer

- Temperature gradient select

- Power control set

- Release the read-modify-write sate (END)

(*25)

- Set “NOP” operation

Test mode release command

(E3(H))

- Display data input direction select

- Page address set

- Column address set

- Display data write

Refresh RAM

- Display ON

*25: Regardless of presence of setting of “Read-modify-write” command, please carry out “END”

command.

74/84

FEDL9445A-01

ML9445A

MPU INTERFACE

The ML9445A series ICs can be connected directly to the 80-series and 68-series MPUs.

Further, by using the serial interface, it is possible to operate the LSI with a minimum number of signal lines.

In addition, it is possible to expand the display area by using the ML9445A series LSIs in a multiple chip

configuration. In this case, it is possible to select the individual LSI to be accessed using the chip select signals.

•

80-Series MPU

V_CC

V_DD

A0

A1 to A7

IORQ

A0

CS1

C86

Decoder

CS2

DB0 to DB7

RD

DB0 to DB7

RD

WR

RES

S

P/

V_SS

GND

RESET

V_SS

•

68-Series MPU

V_CC

V_DD

A0

CS1

A0

A1 to A15

VMA

C86

Decoder

CS2

DB0 to DB7

E

W

DB0 to DB7

E

W

R/

RES

S

P/

V_SS

GND

RESET

V_SS

•

Serial interface

V_CC

V_DD

A0

CS1

Port 3

Port 4

C86

Port 5

CS2

Can be tied to

either level.

Port1

SI

Port2

RES

SCL

RES

V_SS

S

P/

GND

RESET

V_SS

75/84

FEDL9445A-01

ML9445A

PAD CONFIGURATION（ML9445A）

Pad layout

Chip size ：12.7 x 1.26 mm

Chip thickness : 400µm ±20µm

197

432

B

Y

196

181

433

X

(0,0)

448

A

1

Bump and alignment mark dimensions (pattern face)

180

PAD No.1～180

: 35 µm×72 µm

: 84 µm×30µm

: 30 µm×84 µm

: 84 µm×30 µm

PAD No.181～196

PAD No.197～432

PAD No.433～448

Alignment marks A and B : See below

[Mark A]

[Mark B]

Coordinate position

30μm

47μm

55μm

30μm

47μm

55μm

Aluminum (top metal) Passivation

Alignment marks

Mark A

X-coordinate ( m)

Y-coordinate ( m)

µ

6215

-488

-6228

508

Mark B

76/84

FEDL9445A-01

ML9445A

Pad center coordinates

Pad

X-coordinate Y-coordinate

m) m)

Pad

number

41

X-coordinate Y-coordinate

Pad name

number

Pad name

(

µ

(

µ

(

µ

m)

(µm)

1

DUMMY

TEST1

V_SS

-6059

-5979

-5919

-5839

-5759

-5699

-5619

-5559

-5479

-5419

-5339

-5279

-5199

-5139

-5059

-4999

-4919

-4859

-4779

-4719

-4639

-4579

-4499

-4419

-4359

-4279

-4219

-4139

-4059

-3999

-3919

-3859

-3779

-3719

-3639

-3579

-3499

-3439

-3359

-3299

-488

DB6

-3193

-3133

-3001

-2941

-2838

-2778

-2718

-2615

-2555

-2475

-2415

-2335

-2255

-2195

-2115

-2055

-1975

-1915

-1835

-1775

-1695

-1635

-1555

-1495

-1391

-1331

-1271

-1211

-1151

-1091

-1031

-971

-488

2

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

3

DB7

4

DB7

5

SDAACK

SYNC

FR

VCH

SVD2

TEST2

V_DD

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

FR

CL

DOF

CS1

CS2

RES

A0

M/

S

CLS

C86

P/

S

IRS

TEST3

V_SS

A0

V_SS

WR

RD

V_SS

RD

V_SS

V_DD

V_SS

DB0

DB1

DB2

DB3

DB4

DB5

V_SS

-911

V_SS

-851

V_DD

-771

-711

-651

-591

-531

-471

77/84

FEDL9445A-01

ML9445A

Pad

number

81

X-coordinate Y-coordinate

Pad name

Pad number Pad name

(

µ

m)

(

µ

m)

(

µ

m)

(µm)

V_DD

-411

-351

-271

-211

-151

-91

-488

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

VC6+

V_OUT1

DUMMY

V_H

2469

2529

2589

2649

2709

2789

2849

2909

2969

3049

3109

3189

3249

3309

3369

3449

3509

3569

3629

3709

3769

3829

3889

3969

4029

4089

4169

4229

4309

4369

4449

4509

4589

4669

4729

4789

4849

4929

4989

5049

5109

5189

5249

5309

5369

-488

82

83

V_IN

84

V_IN

85

V_IN

86

V_IN

87

V_IN

-31

88

V_IN

29

89

V_IN

89

90

V_IN

149

91

DUMMY

VC3+

VC5+

VS1-

VC2+

VC4+

VS2-

229

92

309

93

369

V_H

94

429

V_H

95

489

V_H

96

549

VS3-

VC7+

V_OUT2

DUMMY

VR

97

629

98

689

99

749

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

809

869

949

1009

1069

1129

1189

1249

1309

1389

1449

1509

1569

1629

1709

1769

1829

1889

1949

2029

2089

2149

2209

2269

2329

2389

VR

V_RS

DUMMY

V1

V2

V3

78/84

FEDL9445A-01

ML9445A

Pad

number

171

X-coordinate Y-coordinate

m) m)

Pad

number

216

X-coordinate Y-coordinate

Pad name

(

µ

(

µ

(

µ

m)

(µm)

V4

5449

5509

5569

5629

5709

5769

5829

5889

5969

6049

6215

6025

5975

5925

5875

5825

5775

5725

5675

5625

5575

5525

5475

5425

5375

5325

5275

5225

5175

5125

-488

-390

-340

-290

-240

-190

-140

-90

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

COMS0

SEG0

5075

5025

4975

4925

4875

4825

4775

4725

4675

4475

4425

4375

4325

4275

4225

4175

4125

4075

4025

3975

3925

3875

3825

3775

3725

3675

3625

3575

3525

3475

3425

3375

3325

3275

3225

3175

3125

3075

3025

2975

2925

2875

2825

2775

2725

495

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

V4

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

V4

V5

DUMMY

COM31

COM30

COM29

COM28

COM27

COM26

COM25

COM24

COM23

COM22

COM21

DUMMY

COM20

COM19

COM18

COM17

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

COM8

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

-40

SEG8

10

SEG9

60

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

110

160

210

260

310

360

495

79/84

FEDL9445A-01

ML9445A

Pad

number

261

X-coordinate Y-coordinate

m) m)

Pad

number

306

X-coordinate Y-coordinate

Pad name

(

µ

(

µ

(

µ

m)

(µm)

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

2675

2625

2575

2525

2475

2425

2375

2325

2275

2225

2175

2125

2075

2025

1975

1925

1875

1825

1775

1725

1675

1625

1575

1525

1475

1425

1375

1325

1275

1225

1175

1125

1075

1025

975

495

SEG81

SEG82

425

375

495

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

SEG83

325

SEG84

275

SEG85

225

SEG86

175

SEG87

125

SEG88

75

SEG89

25

SEG90

-25

SEG91

-75

SEG92

-125

-175

-225

-275

-325

-375

-425

-475

-525

-575

-625

-675

-725

-775

-825

-875

-925

-975

-1025

-1075

-1125

-1175

-1225

-1275

-1325

-1375

-1425

-1475

-1525

-1575

-1625

-1675

-1725

-1775

SEG93

SEG94

SEG95

SEG96

SEG97

SEG98

SEG99

SEG100

SEG101

SEG102

SEG103

SEG104

SEG105

SEG106

SEG107

SEG108

SEG109

SEG110

SEG111

SEG112

SEG113

SEG114

SEG115

SEG116

SEG117

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

925

875

825

775

725

675

625

575

525

475

80/84

FEDL9445A-01

ML9445A

Pad

number

351

X-coordinate Y-coordinate

m) m)

Pad

number

396

X-coordinate Y-coordinate

Pad name

(

µ

(

µ

(

µ

m)

(µm)

SEG126

SEG127

SEG128

SEG129

SEG130

SEG131

SEG132

SEG133

SEG134

SEG135

SEG136

SEG137

SEG138

SEG139

SEG140

SEG141

SEG142

SEG143

SEG144

SEG145

SEG146

SEG147

SEG148

SEG149

SEG150

SEG151

SEG152

SEG153

SEG154

SEG155

SEG156

SEG157

SEG158

SEG159

SEG160

SEG161

SEG162

SEG163

SEG164

SEG165

SEG166

SEG167

SEG168

SEG169

SEG170

-1825

-1875

-1925

-1975

-2025

-2075

-2125

-2175

-2225

-2275

-2325

-2375

-2425

-2475

-2525

-2575

-2625

-2675

-2725

-2775

-2825

-2875

-2925

-2975

-3025

-3075

-3125

-3175

-3225

-3275

-3325

-3375

-3425

-3475

-3525

-3575

-3625

-3675

-3725

-3775

-3825

-3875

-3925

-3975

-4025

495

SEG171

SEG172

SEG173

SEG174

SEG175

SEG176

SEG177

SEG178

SEG179

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

DUMMY

COM54

COM55

COM56

COM57

COM58

-4075

-4125

-4175

-4225

-4275

-4325

-4375

-4425

-4475

-4675

-4725

-4775

-4825

-4875

-4925

-4975

-5025

-5075

-5125

-5175

-5225

-5275

-5325

-5375

-5425

-5475

-5525

-5575

-5625

-5675

-5725

-5775

-5825

-5875

-5925

-5975

-6025

-6215

495

360

310

260

210

160

110

60

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

10

81/84

FEDL9445A-01

ML9445A

Pad

number

441

X-coordinate Y-coordinate

m) m)

Pad

number

X-coordinate Y-coordinate

Pad name

(

µ

(

µ

(

µ

m)

(µm)

COM59

COM60

COM61

COM62

COM63

COMS1

DUMMY

-6215

-40

-90

442

443

444

445

446

447

448

-140

-190

-240

-290

-340

-390

82/84

FEDL9445A-01

ML9445A

REVISION HISTORY

Page

Document No.

Date

Description

Previous Current

Edition

FEDL9445A-01

Apr. 2, 2019

–

Final edition 1

83/84

FEDL9445A-01

ML9445A

Notes

1) The information contained herein is subject to change without notice.

2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality,

semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent

personal injury or fire arising from failure, please take safety measures such as complying with the derating

characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe

procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our

Products beyond the rating specified by LAPIS Semiconductor.

3) Examples of application circuits, circuit constants and any other information contained herein are provided

only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken

into account when designing circuits for mass production.

4) The technical information specified herein is intended only to show the typical functions of the Products and

examples of application circuits for the Products. No license, expressly or implied, is granted hereby under

any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the

information contaiꢎꢆꢀꢄ ꢈꢎꢄ ꢂꢒꢈꢉꢄ ꢀꢋꢊꢁꢌꢆꢎꢂꢑꢄ ꢂꢒꢆꢅꢆꢓꢋꢅꢆꢄ ꢕꢖꢗꢘꢙꢄ ꢙꢆꢌꢈꢊꢋꢎꢀꢁꢊꢂꢋꢅꢄ ꢉꢒꢍꢐꢐꢄ ꢒꢍꢚꢆꢄ ꢎꢋꢄ ꢅꢆꢉꢛꢋꢎꢉꢈꢔꢈꢐꢈꢂꢃꢄ

whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such

technical information.

5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication,

consumer systems, gaming/entertainment sets) as well as the applications indicated in this document.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please

contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships,

trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical

systems, servers, solar cells, and power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment,

nuclear power control systems, and submarine repeaters.

9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance

with the recommended usage conditions and specifications contained herein.

10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this

document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS

Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such

information.

11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the

RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office.

LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with

any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries, you must abide

by the procedures and provisions stipulated in all applicable export laws and regulations, including without

limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS

Semiconductor.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

http://www.lapis-semi.com/en/

84/84


型号：	ML9445A
厂家：	ROHM
描述：	ML9445A是进行位图显示的点阵图形液晶显示用LSI。在8位微处理器（以下简称“MPU”）的控制下，驱动点阵图形液晶显示面板。由于位图方式的液晶驱动所需的所有功能都已内置在1枚芯片中，因此使用ML9445A可以用更少的芯片数量来实现位图方式的点阵图形液晶显示系统。采用位图方式，显示用RAM的1位数据与显示面板1个点的亮灯和非亮灯相对应，因此可支持汉字显示等需要更高灵活性的显示。1枚芯片最大可构建65 ×180点的图形显示系统。ML9445A内置65路公共信号输出和180路段信号输出功能，可用1枚芯片实现65 × 180点的显示。驱动微处理器
文件：	总85页 (文件大小：871K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML9445A [ROHM]

相关型号：

ML9470-11

ML9470-12

ML9471

ML9473

ML9477

ML9478C

ML9479E

ML9480

ML9484

ML961B8S

ML9620

ML9701A