NC7WZ07L6X [ROHM]
TinyLogic UHS Dual Buffer (Open-Drain Outputs); TinyLogic UHS双缓冲（漏极开路输出）
| 型号： | NC7WZ07L6X |
| 厂家： | 
ROHM |
| 描述： | TinyLogic UHS Dual Buffer (Open-Drain Outputs) |
| 文件： | 总9页 (文件大小：988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2013
NC7WZ07
TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
Features
Description
The NC7WZ07 is a dual buffer with open-drain outputs
from Fairchild’s Ultra-High Speed (UHS) series of
TinyLogic®. The device is fabricated with advanced
CMOS technology to achieve ultra-high speed with high
output drive, while maintaining low static power
dissipation over a broad VCC operating range. The
device is specified to operate over a very broad VCC
operating range. The device is specified to operate over
the 1.65 V to 5.5 V VCC range. The inputs and outputs
are high impedance when VCC is 0 V. Inputs tolerate
voltages up to 7 V independent of VCC operating voltage.
.
.
.
.
.
Ultra-High Speed: tPZL 2.3 ns (Typical)
High IOL Output Drive: ±24 mA at 3 V VCC
Broad VCC Operating Range: 1.65 V to 5.50 V
Power Down High Impedance Inputs/Outputs
Over-Voltage Tolerance Inputs Facilitate 5 V to 3 V
Translation
.
.
Proprietary Noise/EMI Reduction Circuitry
Ultra-Small MicroPak™ Packages
Ordering Information
Part Number
NC7WZ07P6X
NC7WZ07L6X
NC7WZ07FHX
Top Mark
Package
Packing Method
Z07
D3
6-Lead SC70, EIAJ SC88 1.25 mm Wide
3000 Units on Tape & Reel
5000 Units on Tape & Reel
6-Lead MicroPak™, 1.00 mm Wide
D3
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch 5000 Units on Tape & Reel
Connection Diagrams
IEEE/IEC
Figure 1. Logic Symbol
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
Pin Configurations
Figure 2. SC70 (Top View)
Figure 3. MicroPak™ (Top Through View)
Figure 4. Pin 1 Orientation
Notes:
1. AAA represents product code top mark (see Ordering Information).
2. Orientation of top mark determines pin one location.
3. Reading the top mark left to right, pin one is the lower left pin.
Pin Definitions
Pin # SC70
Pin # MicroPak™
Name
A1
Description
Input
1
2
3
4
5
6
1
2
3
4
5
6
GND
A2
Ground
Input
Y2
Output
VCC
Y1
Supply Voltage
Output
Function Table
Y= A
Inputs
A
Output
Y
LOW Logic Level
HIGH Logic Level
LOW Logic Level
High Impedance Output State, Open Drain
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.5
-0.5
-0.5
Max.
7.0
Unit
V
Supply Voltage
VIN
DC Input Voltage
7.0
V
VOUT
IIK
DC Output Voltage
7.0
V
DC Input Diode Current
DC Output Diode Current
DC Output Current
VIN < -0.5 V
VOUT < -0.5 V
-50
mA
mA
mA
mA
°C
°C
°C
IOK
-50
IOUT
±50
ICC or IGND
TSTG
TJ
DC VCC or Ground Current
Storage Temperature Range
Junction Temperature Under Bias
±100
+150
+150
+260
150
-65
TL
Junction Lead Temperature (Soldering, 10 Seconds)
SC70-6
PD
Power Dissipation at +85°C
MicroPak™-6
MicroPak2™-6
130
mW
V
120
Human Body Model, JEDEC:JESD22-A114
Charge Device Model, JEDEC:JESD22-C101
4000
2000
ESD
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Supply Voltage Operating
Supply Voltage Data Retention
Input Voltage
Conditions
Min.
1.65
1.5
0
Max.
5.50
5.5
Unit
VCC
V
VIN
5.5
V
V
VOUT
Output Voltage
0
5.5
VCC at 1.8 V, ±0.15 V,
2.5 V ± 0.2 V
0
20
tr, tf
Input Rise and Fall Times
ns/V
VCC at 3.3 V ±0.3 V
VCC at 5.0 V ±0.5 V
0
0
10
5
TA
Operating Temperature
Thermal Resistance
-40
+85
425
500
560
°C
SC70-6
MicroPak™-6
MicroPak2™-6
°C/W
JA
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
3
DC Electrical Characteristics
TA=+25°C
TA=-40 to +85°C
Symbol
Parameter
VCC
Conditions
Units
Min.
Typ. Max.
Min.
Max.
1.65 to 1.95
2.30 to 5.50
1.65 to 1.95
2.30 to 5.50
0.75VCC
0.70VCC
0.75VCC
0.70VCC
HIGH Level Input
Voltage
VIH
VIL
V
V
0.25VCC
0.30VCC
0.25VCC
0.30VCC
LOW Level Input
Voltage
HIGH Level
Output Leakage
Current
VIN=VIH,
VOUT=VCC or GND
ILKG
1.65 to 5.50
±5
±10
µA
1.65
1.80
2.30
3.00
4.50
1.65
2.30
3.00
3.00
4.50
0.00
0.00
0.00
0.00
0.00
0.80
0.10
0.16
0.24
0.25
0.10
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
0.00
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
VIN=VIL, IOL=100 µA
LOW Level Output
Voltage
VOL
V
IOL=4 mA
IOL=8 mA
IOL=16 mA
IOL=24 mA
IOL=32 mA
Input Leakage
Current
IIN
IOFF
ICC
0 to 5.5
0
±0.1
1
±1.0
10
µA
µA
µA
0 VIN 5.5 V
Power Off
Leakage Current
VIN or VOUT=5.5 V
Quiescent Supply
Current
1.65 to 5.50 VIN=5.5 V, GND
1
10
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
4
AC Electrical Characteristics
TA=-40 to
+85°C
TA=+25°C
Symbol
Parameter
VCC
Conditions
Units Figure
Min.
Typ. Max. Min.
Max.
1.65
1.80
1.8
1.8
1.2
0.8
0.5
1.8
1.8
1.2
0.8
0.5
6.6
5.5
3.7
2.9
2.3
5.5
4.3
2.8
2.1
1.4
2.5
4.0
3
11.5
9.5
5.8
4.4
3.5
11.5
9.5
5.8
4.4
3.5
1.8
1.8
1.2
0.8
0.5
1.8
1.8
1.2
0.8
0.5
12.6
10.5
6.4
CL=50 pF,
RU=500
RD=500
VI=2 x VCC
2.50 ± 0.20
3.30 ± 0.30
5.00 ± 0.50
1.65
4.8
ns
3.9
Figure 5
Figure 6
tPZL, tPLZ Propagation Delay
12.6
10.5
6.4
CL=50 pF,
RU=500
RD=500
VI=2 x VCC
1.80
2.50 ± 0.20
3.30 ± 0.30
5.00 ± 0.50
0
4.8
3.9
CIN
Input Capacitance
Output Capacitance
pF
COUT
0
3.30
Power Dissipation
Capacitance(5)
CPD
pF
Figure 7
5.00
4
Note:
5. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating
current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic
operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).
Notes:
6. CL includes load and stray capacitance.
7. Input PRR = 1.0MHz, tW = 500ns.
Figure 5. AC Test Circuit
Figure 6. AC Waveforms
Note:
8. Input=AC Waveform; tr=tf=1.8ns.
9. PRR=Variable; Duty Cycle=50%.
Figure 7. ICCD Test Circuit
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
5
Physical Dimensions
SYMM
C
L
±0.20
A
2.00
0.65
0.50 MIN
6
4
B
PIN ONE
±0.10
1.25
1.90
1
3
0.30
0.15
(0.25)
0.40 MIN
0.10
A B
1.30
0.65
1.30
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.00
0.80
1.10
0.80
0.10 C
0.10
0.00
C
2.10±0.30
SEATING
PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE
PLANE
A) THIS PACKAGE CONFORMS TO EIAJ
SC-88, 1996.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH.
(R0.10)
0.25
0.10
D) DRAWING FILENAME: MKT-MAA06AREV6
0.20
30°
0°
0.46
0.26
DETAIL A
SCALE: 60X
Figure 8. 6-Lead, SC70, EIAJ SC88, 1.25 mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
3000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
P6X
Trailer (Hub End)
75 (Typical)
Empty
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
6
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 9. 6-Lead, MicroPak™, 1.0 mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
L6X
Trailer (Hub End)
75 (Typical)
Empty
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
7
Physical Dimensions
0.89
0.35
0.05 C
2X
1.00
B
A
5X 0.40
1X 0.45
PIN 1
0.66
MIN 250uM
1.00
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.35
0.05 C
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
0.57
1X
(0.08) 4X
DETAIL A
0.09
0.19
6X
1
2
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
0.35
5X
0.25
0.60
6
5
4
0.10
.05 C
C B A
0.40
0.30
0.35
(0.08)
4X
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
0.075X45°
CHAMFER
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
DETAIL A
PIN 1 LEAD SCALE: 2X
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 10. 6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
FHX
Trailer (Hub End)
75 (Typical)
Empty
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
8
© 2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ07 • Rev. 1.0.7
9
相关型号：
NC7WZ07P6_NL
Buffer, LVC/LCX/Z Series, 2-Func, 1-Input, CMOS, PDSO6, 1.25 MM, LEAD FREE, EIAJ, SC-88, SC-70, 6 PIN
FAIRCHILD
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