K1C6416B2E-FI70T [SAMSUNG]
DRAM;
| 型号： | K1C6416B2E-FI70T |
| 厂家： | 
SAMSUNG |
| 描述： | DRAM 动态存储器 |
| 文件： | 总50页 (文件大小：1160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
K1C6416B2E
UtRAM2
64Mb (4M x 16 bit) UtRAM2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
Document Title
8Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory 2
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial
Oct. 15, 2008
Preliminary
- Design Target
Nov. 14, 2008
Preliminary
0.1
ISBD 30 -> 50uA
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
Table of Contents
64Mb (4M x 16 bit) UtRAM2
1. GENERAL DESCRIPTION........................................................................................................................................... 5
2. FEATURES & FUNCTION BLOCK DIAGRAM............................................................................................................. 5
3. PRODUCT FAMILY............................................................................................................................................... 5
4. BALL DESCRIPTIONS.......................................................................................................................................... 6
5. POWER UP SEQUENCE............................................................................................................................................. 7
6. ABSOLUTE MAXIMUM RATINGS ......................................................................................................................... 8
7. RECOMMENDED DC OPERATING CONDITIONS................................................................................................ 8
8. CAPACITANCE..................................................................................................................................................... 8
9. DC AND OPERATING CHARACTERISTICS ......................................................................................................... 9
10. CRE (CONTROL REGISTER ENABLE)..................................................................................................................... 10
10.1. Bus Configuration Register...................................................................................................................................... 10
10.2. Refresh Configuration Register ............................................................................................................................... 11
10.3. Burst Length (BCR[2:0]) Default = Continuous Burst .............................................................................................. 11
10.4. Burst Wrap (BCR[3]) Default = No Wrap ................................................................................................................. 11
10.5. Drive Strength (BCR[5:4]) Default = 1/2 Drive Strength .......................................................................................... 12
10.6. WAIT Configuration (BCR[8]) Default = 1 CLK Prior ............................................................................................... 12
10.7. WAIT Polarity (BCR[10]) Default = Active HIGH...................................................................................................... 12
10.8. Operating Mode (BCR[15]) Default = Asynchronous Operation.............................................................................. 12
10.9. Latency Counter (BCR[13:11]) Default = 3 Clock Latency ...................................................................................... 12
10.10. Initial Access Latency (BRC[14]) Default = Variable ............................................................................................. 12
10.11. Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh.............................................................................. 14
10.12. Deep Power-Down (RCR[4]) Default = DPD Disabled .......................................................................................... 14
10.13. Device Identification Register ................................................................................................................................ 14
10.14. Software Access.................................................................................................................................................... 17
11. BUS OPERATING MODES........................................................................................................................................ 18
11.1. Asynchronous Mode (default mode)........................................................................................................................ 18
11.1.1 Asynchronous (Page) read operation.................................................................................................................... 18
11.1.2 Asynchronous write operation............................................................................................................................... 18
11.2. Functional Description (Asynch. mode) ............................................................................................................. 18
12. Burst Mode Operation................................................................................................................................................. 19
12.1. synchronous Mode .................................................................................................................................................. 19
12.1.1 Synchronous Burst Read Operation...................................................................................................................... 19
12.1.2 Synchronous Burst Write Operation...................................................................................................................... 19
12.2. Functional Description (Synch. mode) ............................................................................................................... 20
12.3. Mixed-Mode Operation ............................................................................................................................................ 21
12.4. Burst Suspend ......................................................................................................................................................... 21
12.5. Boundary Crossing .................................................................................................................................................. 21
12.6. WAIT Operation....................................................................................................................................................... 21
12.7. LB / UB Operation.................................................................................................................................................... 21
13. LOW-POWER OPERATION....................................................................................................................................... 22
13.1. Temperature Compensated Self Refresh................................................................................................................ 22
13.2. Partial Array Refresh ............................................................................................................................................... 22
13.3. Deep Power-Down Operation.................................................................................................................................. 22
13.4. AC Input/Output Reference Waveform & AC Output Load Circuit........................................................................... 22
14. TIMING REQUIREMENTS ......................................................................................................................................... 23
14.1. Asynchronous READ Cycle Timing Requirements ............................................................................................. 23
14.2. Asynchronous WRITE Cycle Timing Requirements............................................................................................ 23
14.3. Brst READ Cycle Timing Requirements............................................................................................................. 24
14.4. Burst WRITE Cycle Timing Requirements............................................................................................................... 24
15. TIMING DIAGRAMS................................................................................................................................................... 25
15.1. Asynchronous READ............................................................................................................................................... 25
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Table of Contents
15.2. Asynchronous READ Using ADV ............................................................................................................................ 26
15.3. PAGE MODE READ................................................................................................................................................ 27
15.4. Single-Access Burst READ Operation—Variable Latency ...................................................................................... 28
15.5. 4-Word Burst READ Operation—Variable Latency ................................................................................................. 29
15.6. Single-Access Burst READ Operation—Fixed Latency........................................................................................... 30
15.7. 4-Word Burst READ Operation—Fixed Latency...................................................................................................... 31
15.8. 4-Word Burst READ Operation— Row Boundary Crossing .................................................................................... 32
15.9. READ Burst Suspend .............................................................................................................................................. 33
15.10. CS-Controlled Asynchronous WRITE.................................................................................................................... 34
15.11. LB/UB-Controlled Asynchronous WRITE .............................................................................................................. 35
15.12. WE-Controlled Asynchronous WRITE................................................................................................................... 36
15.13. Asynchronous WRITE Using ADV......................................................................................................................... 37
15.14. Burst WRITE Operation—Variable Latency Mode................................................................................................. 38
15.15. Burst WRITE Operation—Fixed Latency Mode..................................................................................................... 39
15.16. 4-Word Burst WRITE Operation— Row Boundary Crossing................................................................................. 40
15.17. Burst WRITE Followed by Burst READ ................................................................................................................. 41
15.18. Burst READ Interrupted by Burst READ or WRITE............................................................................................... 42
15.19. Burst WRITE Interrupted by Burst WRITE or READ—Variable Latency Mode..................................................... 43
15.20. Burst WRITE Interrupted by Burst WRITE or READ—Fixed Latency Mode ......................................................... 44
15.21. Asynchronous WRITE Followed by Burst READ................................................................................................... 45
15.22. Asynchronous WRITE (ADV LOW) Followed By Burst READ .............................................................................. 46
15.23. Burst READ Followed by Asynchronous WRITE (WE-Controlled)........................................................................ 47
15.24. Burst READ Followed by Asynchronous WRITE Using ADV ................................................................................ 48
15.25. Asynchronous WRITE Followed by Asynchronous READ—ADV LOW ................................................................ 49
15.26. Asynchronous WRITE Followed by Asynchronous READ .................................................................................... 50
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UtRAM2
1. GENERAL DESCRIPTION
SAMSUNG’s UtRAM products are designed to meet the request from the customers who want to cope with the fast growing mobile applica-
tions that need high-speed random access memory. UtRAM is the solution for the mobile market with its low cost, high density and high per-
formance feature. K1C6416B2E is fabricated by SAMSUNG′s advanced CMOS technology using one transistor memory cell. The device
supports the traditional SRAM like asynchronous operation (asynchronous page read and asynchronous write), the NOR flash like synchro-
nous operation (synchronous burst read and asynchronous write) and the fully synchronous operation (synchronous burst read and synchro-
nous burst write). These operation modes are defined through the Confifuration Register Setting. It supports the special features for the
standby power saving. Those are the PAR(Partial Array Refresh) mode, DPD(Deep Power Down) mode and internal TCSR(Temperature
Compensated Self Refresh). It also supports variable and fixed latency, driver strength settings, Burst sequence (wrap or No-wrap) options
and a device ID register (DIDR).
2. FEATURES & FUNCTION BLOCK DIAGRAM
• Process technology: CMOS
• Organization: 4M x 16 bit
Clk gen.
Pre-charge circuit
• Power supply voltage: 1.7V~1.95V
• Three state outputs
• Supports Configuration Register Set
- CRE pin set up
- Software set up
V
V
V
CC
CCQ
SS
Memory
Array
VSSQ
• Supports power saving modes
- PAR (Partial Array Refresh)
- DPD (Deep Power Down)
- Internal TCSR (Temperature Compensated Self Refresh)
• Supports driver strength optimization
• Support 2 operation modes
- Asynchronous mode (4-Page)
- Synchronous mode
Row
select
Row
Addresses
I/O Circuit
Data
cont
DQ0~DQ7
Column Select
• Random access time:70ns
• Page access time:20ns
Data
cont
DQ8~DQ15
• Synchronous burst operation
- Max. clock frequency : 104MHz
- Fixed and Variable read latency
- 4 / 8 / 16 / 32 and Continuous burst
- Wrap / No-wrap
Data
cont
Column Address
- Latency : 3(Variable) @ 104MHz
3(Variable) @ 80MHz
2(Variable) @ 66MHz
- Burst stop
- Burst read suspend
CLK
CS
ADV
OE
Control Logic
WE
UB
LB
CRE
- Burst write data masking
WAIT
3. PRODUCT FAMILY
Current Consumption
CLK Freq.
(Max.)
Product Family
Operating Mode
Operating Temp.
Vcc / Vccq
Standby
Operating
(ISB1, Max.)
(ICC2P, Max.)
Asynch. Mode
Synch. Mode
K1C6416B2E-I
Industrial(-40~85°C)
1.7~1.95V
104MHz
180uA
40mA
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Preliminary
K1C6416B2E
UtRAM2
4. BALL DESCRIPTIONS
Symbol
Type
Description
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched
during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the
BCR or the RCR.
A[21:0]
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When
configured for synchronous operation, the address is latched on the first rising CLK edge when ADV is active.
CLK is static LOW during asynchronous access READ and WRITE operations and during PAGE READ
ACCESS operations.
CLK
(note1)
Input
Address valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on
the rising edge of ADV during asynchronous READ and WRITE operations. ADV can be held LOW during
asynchronous READ and WRITE operations.
ADV
(note1)
Input
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations
access the RCR, BCR, or DIDR.
CRE
Chip Select: Activates the device when LOW. When CS is HIGH, the device is disabled and goes into standby
or deep power-down mode.
CS
OE
WE
Input
Input
Input
Output enable: Enables the output buffers when LOW. When OE is HIGH, the output buffers are disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE is LOW, the cycle is a WRITE to either a
configuration register or to the memory array.
LB
UB
Input
Input
Lower byte enable. DQ[7:0]
Upper byte enable. DQ[15:8]
DQ[15:0]
Input/Output Data inputs/outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CS.
WAIT
(note1)
Output
WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted and
should be ignored during asynchronous and page mode operations. WAIT is High-Z when CS is HIGH.
RFU
VCC
-
Reserved for future use.
Supply
Supply
Supply
Supply
Device power supply: (1.70V–1.95V) Power supply for device core operation.
I/O power supply: (1.70V–1.95V) Power supply for input/output buffers.
VSS must be connected to ground.
VCCQ
VSS
VSSQ
VSSQ must be connected to ground.
NOTE :
1) When using asynchronous mode exclusively, the CLK and ADV inputs can be tied to VSS. WAIT will be asserted but should be ignored during asynchronous
mode operations.
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Preliminary
K1C6416B2E
UtRAM2
5. POWER UP SEQUENCE
After VCC and VCCQ reach minimum operating voltage(1.7V), drive CS High. Then the device gets into the Power Up mode. Wait for minimum
150µs to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the appropriate
device operation, be sure to keep the following power up sequence. Asynch. mode is default mode and is set up after power up.
VCC(Min)
VCC
VCCQ(Min)
VCCQ
150us
Min. 0ns
CS
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Preliminary
K1C6416B2E
UtRAM2
6. ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN, VOUT
VCC, VCCQ
PD
Ratings
-0.2 to VCCQ+0.3V
-0.2 to 2.5V
1.0
Unit
V
Voltage on any pin relative to Vss
Power supply voltage relative to Vss
Power Dissipation
V
W
Storage temperature
TSTG
-65 to 150
-40 to 85
°C
°C
Operating Temperature
TA
NOTE :
1) Stresses greater than "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under
recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
7. RECOMMENDED DC OPERATING CONDITIONS
Item
Symbol
VCC
Min
1.7
Typ
1.8
1.8
0
Max
1.95
Unit
V
Power supply voltage(Core)
Power supply voltage(I/O)
Ground
VCCQ
VSS, VSSQ
VIH
1.7
1.95
V
0
0
V
VCCQ+0.22)
0.4
Input high voltage
Input low voltage
VCCQ-0.4
-0.23)
-
V
VIL
-
V
NOTE :
1) TA = -40 to 85°C, otherwise specified.
2) Overshoot: VCCQ +1.0V in case of pulse width ≤20ns. Overshoot is sampled, not 100% tested.
3) Undershoot: -1.0V in case of pulse width ≤20ns. Undershoot is sampled, not 100% tested.
8. CAPACITANCE
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
Input capacitance
Input/Output capacitance
-
-
CIO
VIO=0V
8
pF
NOTE :
1) Freq.=1MHz, TA=25°C
2) Capacitance is sampled, not 100% tested.
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UtRAM2
9. DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
VIN=Vss to VCCQ
Min
-1
Typ
Max
1
Unit
µA
Input Leakage Current
Output Leakage Current
ILI
-
-
ILO
CS=VIH, CRE=VIL, OE=VIH or WE=VIL, VIO=VSS to VCCQ
-1
1
µA
Cycle time=min tRC/min tWC, IIO=0mA4), 100% duty, CS=VIL,
CRE=VIL, VIN=VIL or VIH
6)
ICC2
-
-
-
-
-
-
-
-
-
-
40
mA
mA
Average Operating
Current (Async)
Cycle time=min tRC+3 min tPC, IIO=0mA4), 100% duty, CS=VIL,
CRE=VIL, VIN=VIL or VIH
ICC2P
40
104Mhz:TBD
VIN = VCCQ or 0V
CS=VIL, IIO=0mA4)
ICC3I
80Mhz:TBD mA
66Mhz:TBD
104Mhz:TBD
80Mhz:TBD mA
66Mhz:TBD
Average Operating
Current (Burst)
ICC3R
104Mhz:TBD
ICC3W
80Mhz:TBD mA
66Mhz:TBD
Output Low Voltage
Output High Voltage
VOL
VOH
IOL=0.2mA
IOH=-0.2mA
-
-
-
-
-
-
-
-
-
-
-
0.2
-
V
V
0.8xVCCQ
< 40°C
< 85°C
-
-
-
-
-
-
-
-
120
180
115
110
105
165
155
145
µA
µA
CS=VCCQ, CRE=0V, Other inputs=0V or VCCQ
1)
Standby Current(CMOS)
ISB1
(Toggle is not allowed)5)
1/2 Block
< 40°C 1/4 Block
1/8 Block
µA
CS=VCCQ, CRE=0V, Other inputs=0V or VCCQ
2)
Partial Refresh Current
ISBP
(Toggle is not allowed)5)
1/2 Block
< 85°C 1/4 Block
1/8 Block
µA
µA
CRE=0V, CS=VCCQ, Other inputs=0V or VCCQ (Toggle is not
Deep Power Down Current
ISBD
-
-
50
allowed)5)
NOTE :
1) ISB1 is measured after 60ms after CS high. CLK should be fixed at high or at Low.
2) Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1).
3) Internal TCSR (Temperature Compensated Self Refresh) is used to optimize refresh cycle below 40°C.
4) IIO=0mA; This parameter is specified with the outputs disabled to avoid external loading effects.
5) VIN=0V; all inputs should not be toggle.
6) This parameter is for page disable mode, Clock should not be inserted between ADV low and WE low during Write operation.
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K1C6416B2E
UtRAM2
10. CRE (CONTROL REGISTER ENABLE)
The configuration register values are written via Address pins. In an asynchronous WRITE, the values are latched into the configuration regis-
ter on the rising edge of ADV, CS, or WE, whichever occurs first; LB and UB are “Don’t Care.” For reads, address inputs other than A[19:18]
are “Don’t Care,” and register bits 15:0 are output as data (ADV HIGH) on A[15:0]. Immediately after performing a configuration register READ
or WRITE operation, reading the memory array is highly recommended.
10.1 Bus Configuration Register
The BCR defines how the device interacts with the system memory bus. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through
the register access software sequence with A = 0001h on the third cycle.
A19~A18
A15
A14
A13~A11
A10
A8
A5~A4
A3
A2~A0
RS
OM
IL
LC
WP
WC
DS
BW
BL
Initial Latency
IL
Latency Count
Register Select
Operating Mode
A19
A18
0
RS
A15
0
OM
A14
0
A13
0
A12
A11
0
LC
0
1
0
RCR
BCR
DIDR
Synch.
Variable (default)
Fixed
0
0
1
1
0
0
1
1
0
0
1
Asynch (default)
1
0
1
1
1
0
0
2
0
1
3 (default)
1
0
4
5
6
7
1
1
1
0
1
1
Driver Strength
Burst Wrap
Burst Length
Wait Polarity
WP
Wait Config.
A10
A8
WC
A5
A4
DS
A3
BW
A2
A1
A0
BL
0
Active Low
0
at data
0
0
Full Drive
0
Wrap
0
0
1
4 word
Active High
(default)
1 CLK prior
(default)
1/2 Drive
(default)
No Wrap
(default)
1
1
0
1
1
0
1
0
8 word
1
1
0
1
1/4 Drive
Reserved
0
1
1
0
1
0
16 word
32 word
Continuous
(default)
1
1
1
NOTE:
1) A6, A7, A9, A16, A17, A20 ~ A22 are reserved and should be ’1’
2) The registers are set automatically to default value.
3) Refresh command will be denied during continuous operation. CS low should not be longer than tBC(max. 2.5us)
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K1C6416B2E
UtRAM2
10.2 Refresh Configuration Register
The refresh configuration register (RCR) defines how the device performs its self refresh. Altering the refresh parameters can reduce current
consumption during standby mode. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software
sequence with A = 0000h on the third cycle.
A19~A18
A7
A4
A2~A0
RS
PAGE
DPD
PAR
Register Select
A18
Page
Deep Power Down
Partial Refresh
A19
RS
A7
PAGE
A4
DPD
A2
A1
A0
PAR
0
1
0
0
0
1
RCR
BCR
DIDR
0
1
Disable(default)
Enable
0
1
Enable
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full Array (default)
Bottom 1/2 Array
Bottom 1/4 Array
Bottom 1/8 Array
None of Array
Disable (default)
Top 1/2 Array
Top 1/4 Array
Top 1/8 Array
NOTE:
1) A3, A5, A6, A8~A15, A16, A17, A20 ~ A22 are reserved and should be ’1’
2) The registers are set automatically to default value.
10.3 Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length of
4, 8, 16, 32 words or continuous.
10.4 Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4-, 8-, 16-, or 32-word READ or WRITE burst wraps within the burst length, or steps through sequential
addresses.
Table 1. Sequence and Burst Length
4 word
Starting
Address
8 word
16 word
32 word
Burst Length
Continuous
Burst
Burst Wrap
Burst
Burst Length
Burst Length
Length
BCR[3] Wrap Decimal Linear
Linear
Linear
Linear
Linear
0-1-2-3
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
0 - 1 - 2 ~ 29-30-31
1 - 2 - 3 ~ 30-31 - 0
2 - 3 - 4 ~ 31 - 0 - 1
0 - 1 - 2 - 3 - 4 - 5 ~
1 - 2 - 3 - 4 - 5 - 6 ~
2 - 3 - 4 - 5 - 6 - 7 ~
0
1-2-3-0
1
2-3-0-1
2
3-0-1-2
3-4-5-6-7-0-1-2
~
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
~
3 - 4 - 5 ~ 0 - 1 - 2
~
3 - 4 - 5 - 6 - 7 - 8 ~
~
3
~
WRAP
Yes
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7 - 8 - 9 ~ 4 - 5 - 6
~
7 - 8 - 9 - 10-11-12 ~
~
7
~
~
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17 ~ 12- 13- 14
~
15-16-17-18-19-20 ~
~
15
~
31- 0 - 1 ~ 28-29-30
0 - 1 - 2 ~ 29-30-31
1 - 2 - 3 ~ 30-31-32
2 - 3 - 4 ~ 31-32-33
31-32-33-34-35-36 ~
0 - 1 - 2 - 3 - 4 - 5 ~
1 - 2 - 3 - 4 - 5 - 6 ~
2 - 3 - 4 - 5 - 6 - 7 ~
31
0
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0- 1- 2- 3- 4- 5- 6 -7
1- 2- 3- 4- 5- 6- 7- 8
2- 3- 4- 5- 6- 7- 8- 9
0- 1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15
1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16
2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17
1
2
3- 4- 5- 6- 7- 8- 9-10
~
3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17-18
~
3 - 4 - 5 ~ 32-33-34
~
3 - 4 - 5 - 6 - 7 - 8 ~
~
3
~
No
WRAP
No
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22
7 - 8 - 9 ~ 36-37-38
~
7 - 8 - 9 - 10-11-12 ~
7
~
~
~
15-16-17-18-19-20-21-22-23-24-25-26-27-28-29-30
15-16-17 ~ 44-45-46
15-16-17-18-19-20 ~
~
15
~
~
31-32-33 ~ 60-61-62
31-32-33-34-35-36 ~
31
Revision 0.1
Nov 2008
- 11 -
Preliminary
K1C6416B2E
UtRAM2
10.5 Drive Strength (BCR[5:4]) Default = 1/2 Drive Strength
The optimization of output driver strength is possible to adjust for the different data loadings. The device can minimize the noise generated on
the data bus during read operation. The device supports full, 1/2 and 1/4 driver strength. The device’s default mode is 1/2 driver strength. Out-
puts are configured at 1/2 drive strength during testing.
Table 2. Drive Strength
Driver Strength
Impedance(typ.)
Full
1 / 2
1 / 4
25~30Ω
50Ω
100Ω
CL = 15pF to 30pF
104 MHz at light load
Recommendation
CL = 30pF to 50pF
CL = 15pF or lower
NOTE :
1) Impedance values are typical values, not 100% tested.
10.6 WAIT Configuration (BCR[8]) Default = 1 CLK Prior
The WAIT signal is output signal indicating the status of the data on the bus whether or not it is valid. WAIT configuration is to decide the tim-
ing when WAIT asserts or desserts. WAIT asserts (or desserts) one clock prior to the data when A8 is set to 1. (WAIT asserts (or desserts) at
data clock when A8 is set to 0). WAIT polarity is to decide the WAIT signal level at which data is valid or invalid. Data is valid if WAIT signal is
high when A10 is set to 0. (Data is valid if WAIT signal is low when A10 is set to 1). All the timing diagrams in this SPEC are illustrated based
on following setup; A[10]:0 and A[8]:1.
Below timing shows WAIT signal’s movement when word boundary crossing happens in No-wrap mode
10.7 WAIT Polarity (BCR[10]) Default = Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal
requires a pull-up or pull-down resistor to maintain the de-asserted state.
Figure 1: WAIT Configuration During Burst Operation
No-Wrap. Row Boundary Crossing. LATENCY : 2. WP : Low Enable
CLOCK
Row Boundary Crossing period
(Only exists in No-wrap mode or Continuous mode)
D510 D511
D512 D513 D514 D515
D509
I / O
1CLK
1CLK
1CLK
WAIT
BCR[8]:1
de-assertion
de-assertion
assertion
WAIT
BCR[8]:0
de-assertion
de-assertion
assertion
NOTE: Non-default BCR setting: WAIT active LOW.
10.8 Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
10.9 Latency Counter (BCR[13:11]) Default = 3 Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value
transferred. For allowable latency codes.
10.10 Initial Access Latency (BRC[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to detect
delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that allows for worst-
case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to mon-
itor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter.
Revision 0.1
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Nov 2008
Preliminary
K1C6416B2E
UtRAM2
Table 3. Variable Latency Configuration Codes
Latency
Max Input CLK Frequency (MHz)
BCR[13:11]
Latency Configuration
Normal
Refresh Collision
104
66(15ns)
104(9.62ns)
-
80
52(19,2ns)
80(12.5ns)
-
66
40(25ns)
66(15ns)
-
010
011
2(3 clocks)
3(4 clocks)-default
Reserved
2
3
-
4
6
-
Others
Table 4. Fixed Latency Configuration Codes
Max Input CLK Frequency (MHz)
BCR[13:11]
Latency Configuration
Latency Count (N)
104
33 (30ns)
80
66
010
011
2 (3 clocks)
3 (4 clocks)
4 (5 clocks)
5 (6 clocks)
6 (7 clocks)
Reserved
2
3
4
5
6
-
20 (50ns)
40 (25ns)
52 (19.2ns)
66 (15ns)
80 (12.5ns)
-
20 (50ns)
33 (30ns)
40 (25ns)
52 (19.2ns)
66 (15ns)
-
52 (19.2ns)
66 (15ns)
80 (12.5ns)
104 (9.62ns)
-
100
101
110
Others
NOTE:
1) Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
Figure 2: Latency Counter (Variable Initial Latency, No Refresh Collision)
VIH
CLK
VIL
VIH
ADV
VIL
VIH
VIL
VALID
A[21:0]
ADDRESS
Code 2
VIH
VIL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
Code 3 (Default)
Code 4
VIH
VIL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DQ[15:0]
VIH
VIL
Valid
Output
Valid
Output
Valid
Output
Undefined
Don’t Care
Figure 3: Latency Counter (Fixed Latency)
N-1
Cycles
Cycle N
VIH
VIL
CLK
A[21:0]
ADV
tAA
VIH
VIL
Valid
Address
tAADV
tCO
VIH
VIL
VIH
VIL
CS
tACLK
VOH
VOL
DQ[15:0]
(READ)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
tSP
tHD
VOH
VOL
DQ[15:0]
(WRITE)
Valid
Input
Valid
Input
Valid
Input
Valid
Input
Valid
Input
Burst Identified
(ADV = LOW)
Undefined
Don’t Care
Revision 0.1
Nov 2008
- 13 -
Preliminary
K1C6416B2E
UtRAM2
10.11 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by
refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array,
one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map.
Table 5. Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Full die
Address Space
000000h-3FFFFFh
000000h-1FFFFFh
000000h-0FFFFFh
000000h-07FFFFh
0
Size
Density
64Mb
32Mb
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
0 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
One-half die
One-quarter of die
One-eighth of die
None of die
0Mb
One-half of die
One-quarter of die
One-eighth of die
200000h-3FFFFFh
300000h-3FFFFFh
380000h-3FFFFFh
32Mb
16Mb
8Mb
10.12 Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage pro-
vided by this memory. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the device will
require 150µs to perform an initialization procedure before normal operations can resume. Deep power-down is enabled by setting RCR[4] =
0 and taking CS HIGH. DPD can be enabled using CRE or the software sequence to access the RCR. Taking CS LOW for at least 10µs dis-
ables DPD and sets RCR[4] = 1. it is not necessary to write to the RCR to disable DPD. BCR and RCR values (other than BCR[4]) are pre-
served during DPD.
Figure 4: DPD Entry and Exit Timing Parameters & Initialization and DPD Timing Parameters
tDPD
tDPDX
tPU
Symbol
tDPD
Min
10
Max
Unit
µs
CS
Write
RCR[4] = 0
tDPDX
tPU
10
µs
DPD Enabled
DPD EXIT
Device Initialization
150
µs
10.13 Device Identification Register
The DIDR provides information on the device manufacturer, generation and the specific device configuration. This register is read-only. The
DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with A= 0002h on the third cycle.
Table 6. Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
Device version
Bit
DIDR[10:8])
DIDR[7:5]
DIDR[4:0]
Field name
Row Length
Device density
UtRAM generation
Vendor ID
Bit
Bit
Setting
Bit
Bit
Setting
Length
Version
Density
Generation
Setting
Setting
Setting
Options
512 words
1b
6th
101b
64Mb
010b
UtRAM2
010b
01100
Revision 0.1
Nov 2008
- 14 -
Preliminary
K1C6416B2E
UtRAM2
Figure 5: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
tCPH
Initiate control register access
CS
tCW
A[21:0]
OPCODE
Address
Address
(Except A[19:18])
tAVS
Select
A[19:18]
CRE
Register
tAVH
tAVS
tVP
ADV
OE
tWP
Write address value to control register
WE
LB/UB
DQ[15:0]
Data Valid
Don’t Care
NOTE:
1) A[19:18] = 00b to load RCR, and 10b to load BCR.
Figure 6: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation
0
1
2
3
4
5
6
7
CLK
CS
tCPH
tCSP
Latch control register value
OPCODE
A[21:0]
Address
Address
(Except A[19:18])
tSP
Latch control register address
Select
A[19:18]
CRE
Register
tHD
tSP
tSP
tSP
tHD
ADV
OE
tHD
WE
WAIT
tCSW
DQ[15:0]
Don’t Care
NOTE:
1) Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2) A[19:18] = 00b to load RCR, and 10b to load BCR.
3) CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions
require a corresponding number of additional CS LOW cycles.
Revision 0.1
Nov 2008
- 15 -
Preliminary
K1C6416B2E
UtRAM2
Figure 7: Register READ, Asynchronous Mode Followed by READ ARRAY Operation
A[22:0]
ADDRESS
(except A[19:18])
tAVS
tAVH
tAA
1
Select Register
A[19:18]
ADDRESS
CRE
ADV
tAVS
tAA
tVP
tAAVD
tCPH
tHZ
CS
OE
Initiate Register Access
tCO
tOE
tOLZ
tLZ
tOHZ
tBHZ
WE
tBA
LB/UB
tLZ
DQ[15:0]
CR Valid
Data Valid
Don’t Care
Undefined
NOTE :
1) A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
Figure 8: Register READ, Synchronous Mode Followed by READ ARRAY Operation
CLK
Latch Control Register Value
A[22:0]
ADDRESS
ADDRESS
(except A[19:18])
tSP
Latch Control Register Address
2
A[19:18]
tHD
tSP
CRE
ADV
tHD
tHD
tSP
tCBPH3
tABA
CS
OE
tCSP
tHZ
tOHZ
tBOE
tHD
tSP
LB/UB
tACLK
tKOH
tOLZ
tCW
WAIT
High-Z
High-Z
Data
Valid
DQ[15:0]
CR Valid
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2) A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3) CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions require a
corresponding number of additional CS LOW cycles.
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
10.14 Software Access
Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configu-
ration registers can be modified and all registers can be read using the software sequence. The configuration registers are loaded using a
four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations. The read sequence
is virtually identical except that an asynchronous READ is performed during the fourth operation. The address used during all READ and
WRITE operations is the highest address of the device being accessed (3FFFFF); the contents of this address are not changed by using this
sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be
accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h,
the sequence will access the DIDR. During the fourth operation, DQ[15:0] transfer data in to or out of bits 15–0 of the registers. The use of the
software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However,
the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to
VSS. The port line often used for CRE control purposes is no longer required.
Figure 9: Load Configuration Register
ADDRESS
Max
ADDRESS
Max
ADDRESS
Max
ADDRESS
Max
Address
CS
OE
WE
LB/UB
DATA
XXXXh
XXXXh
CR Value In
RCR: 0000h
BCR: 0001h
Don’t Care
Figure 10: Read Configuration Register
ADDRESS
Max
ADDRESS
Max
ADDRESS
Max
ADDRESS
Max
Address
CS
OE
WE
LB/UB
DATA
XXXXh
XXXXh
CR Value Out
RCR: 0000h
BCR: 0001h
DIDR: 0002h
Don’t Care
Revision 0.1
Nov 2008
- 17 -
Preliminary
K1C6416B2E
UtRAM2
11. BUS OPERATING MODES
The bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by the value
loaded into the BCR.
11.1 Asynchronous Mode (default mode)
11.1.1 Asynchronous (Page) read operation
Asynchronous read operation starts when CS, OE and UB or LB are asserted. ADV can be taken HIGH to capture the address. First data will
be driven out of the DQ bus after random access time(tAA) and second, third and fourth data can be driven out after page access time(tPA)
when using the page addresses (A0, A1). WE should be de-asserted during read operation. The CLK input must be held static LOW during
read operation. WAIT will be driven while the device is enabled and its state should be ignored.
11.1.2 Asynchronous write operation
Asynchronous write operation starts when CS, WE and UB or LB are asserted. The data to be written is latched on the rising edge of CS, WE,
or LB/UB (whichever occurs first). OE is don’t care during write operation and WE will override OE. WE LOW time must be limited to tCSM.
The CLK input must be held static LOW during write operation. WAIT signal is Hi-Z.
Figure 11: READ Operation (ADV = LOW, WE = HIGH).
Figure 12: WRITE Operation(ADV = LOW, OE = HIGH)
< tCSM
CS
CS
Address
WE
Address Valid
< tCSM
Address
Add0
Add1 Add2 Add3
tAA
tAPA tAPA tAPA
OE
LB/UB
LB/UB
tWC = WRITE Cycle Time
Data
High-Z
Data Valid
DATA
D0
D1
D2
D3
Don’t Care
Undefined
Don’t Care
11.2 Functional Description (Asynch. mode)
Asynchfonous Mode
UB /
LB
Power
CLK
ADV
CS
OE
WE
CRE
WAIT DQ[15:0] Notes
BCR[15] = 1
Read
Active
Active
Standby
Idle
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
L
L
L
L
L
Low-Z Data out
4
4
Write
Low-Z
High-Z
Low-Z
Data in
High-Z
X
Standby
No operation
X
X
H
L
X
X
X
X
5,6
4,6
Configuration register
write
Active
Active
L
L
L
L
L
X
L
L
X
L
L
H
X
H
H
X
X
L
Low-Z
Low-Z
High-Z
High-Z
Configuration register
read
Config.
Reg.out
Deep Power-
down
DPD
H
X
X
High-Z
7
NOTE:
1) CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD modes. CLK must be static
(HIGH or LOW) during burst suspend.
2) The WAIT polarity is configured through the bus configuration register (BCR[10]).
3) When LB and UB are in select mode (LOW), DQ[15:0] are affected. When only LB is in select mode, DQ[7:0] are affected. When only UB is in the select mode,
DQ[15:8] are affected.
4) The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.
7. DPD is initiated when CS transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CS transitions from HIGH to LOW.
Revision 0.1
- 18 -
Nov 2008
Preliminary
K1C6416B2E
UtRAM2
12. Burst Mode Operation
12.1 synchronous Mode
12.1.1 Synchronous Burst Read Operation
Burst Read command is implemented when ADV is detected low at clock rising edge. WE should be de-asserted. Burst operation re-starts
whenever ADV is detected low at clock rising edge even in the middle of operation.
12.1.2 Synchronous Burst Write Operation
Burst Write command is implemented when ADV & WE are detected low at clock rising edge. Burst Write operation re-starts whenever ADV
is detected low at clock rising edge even in the middle of Burst Write operation.
Figure 13: Burst Mode READ (4-word burst)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CS
A[22:0]
ADV
Latency Code 3 (4 clocks)
OE
WE
LB/UB
WAIT
DQ[15:0]
READ Burst Identified
(WE = HIGH)
READ Burst Identified
(WE = HIGH)
Don’t Care
Undefined
NOTE :
1) Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency;
2) Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay.
3) Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access.
Figure 14: Burst Mode WRITE (4-word burst)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CS
A[22:0]
ADV
Latency Code 3 (4 clocks)
WE
LB/UB
WAIT
DQ[15:0]
WRITE Burst Identified
(WE = LOW)
READ Burst Identified
(WE = HIGH)
Don’t Care
NOTE:
1) Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency;
2) Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen, or
thirty-two words. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency).
Variable latency allows minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh
cycles. Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency
time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also
provides improved performance at lower clock frequencies.
Figure 15: Refresh Collision During Variable-Latency READ Operation
VIH
CLK
VIL
VIH
CS
VIL
VIH
Valid
Address
A[22:0]
VIL
VIH
VIL
ADV
OE
VIH
VIL
VIH
VIL
WE
VIH
LB/UB
WAIT
VIL
VOH
High-Z
VOL
VOH
VOL
D3
D0
D1
D2
DQ[15:0]
Additional WAIT states inserted to allow refresh completion.
Undefined
Don’t Care
NOTE:
1) Non-default BCR settings for refresh collision during variable-latency READ operation:
2) Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
12.2 Functional Description (Synch. mode)
Burst Mode
UB /
LB
Power
CLK
ADV
CS
OE
WE
CRE
WAIT DQ[15:0]
Notes
BCR[15] = 0
Async read
Async write
Standby
Active
Active
Standby
Idle
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
L
L
L
L
L
Low-Z Data out
4,8
4
Low-Z
High-Z
Low-Z
Data in
High-Z
X
X
X
H
L
X
X
X
X
5,6
4,6
No operation
Initial burst read
Initial burst write
Active
Active
L
L
L
L
X
H
H
L
L
L
L
Low-Z
Low-Z
X
X
4,9
4,9
X
Data in or
Data out
Burst continue
Burst suspend
Active
Active
Active
H
X
L
L
L
L
X
H
X
X
X
L
X
X
H
L
X
X
Low-Z
Low-Z
Low-Z
4,9
4,9
X
L
High-Z
Configuration register
write
Configuration register
read
High-Z
9,10
Config.
reg.out
Active
L
L
L
H
X
H
X
L
Low-Z
High-Z
9,10
7
Deep power-
down
DPD
X
H
X
X
High-Z
NOTE:
1) CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD modes. CLK must be static
(HIGH or LOW) during burst suspend.
2) The WAIT polarity is configured through the bus configuration register (BCR[10]).
3) When LB and UB are in select mode (LOW), DQ[15:0] are affected. When only LB is in select mode, DQ[7:0] are affected. When only UB is in the select mode,
DQ[15:8] are affected.
4) The device will consume active power in this mode whenever addresses are changed.
5) When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6) VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.
7) DPD is initiated when CS transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CS transitions from HIGH to LOW.
8) When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by all vendors. (Some vendors also support
asynchronous READ.)
9) Burst mode operation is initialized through the bus configuration register (BCR[15]).
10) Initial cycle. Following cycles are the same as BURST CONTINUE. CS must stay LOW for the equivalent of a single-word burst (as indicated by WAIT).
Revision 0.1
- 20 -
Nov 2008
Preliminary
K1C6416B2E
UtRAM2
12.3 Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous
operation. The asynchronous WRITE operations require that the clock (CLK) remain LOW during the entire sequence. The ADV signal can be
used to latch the target address, CS can remain LOW when transitioning between mixed-mode operations with fixed latency enabled; how-
ever, the CS LOW time must not exceed tCSM. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory
controllers.
12.4 Burst Suspend
To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts
are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE
should be taken HIGH to disable the outputs. otherwise, OE can remain LOW. Note that the WAIT output will continue to be active, and as a
result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE is taken LOW, then
CLK is restarted after valid data is available on the bus. The CS LOW time is limited by refresh considerations. CS must not stay LOW longer
than tCSM. If a burst suspension will cause CS to remain LOW for longer than tCSM, CS should be taken HIGH and the burst restarted with a
new CS LOW/ADV LOW cycle.
12.5 Boundary Crossing
Continuous bursts or No wrap burst have the ability to start at a specified address and burst to the end of the address. It goes back to the first
address and continues the burst operation. WAIT will be asserted at the boundary of the row and be desserted after crossing boundary of the
row.
12.6 WAIT Operation
The WAIT output is typically connected to a shared systemlevel WAIT signal. The shared WAIT signal is used by the processor to coordinate
transactions with multiple memories on the synchronous bus. Once a READ or WRITE operation has been initiated, WAIT goes active to indi-
cate that additional time is required before data can be transferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into this device. When WAIT
transitions to an inactive state, the data burst will progress on successive clock edges. CS must remain asserted during WAIT cycles (WAIT
asserted and WAIT configuration BCR[8] = 1). Bringing CS HIGH during WAIT cycles may cause data corruption. (Note that for BCR[8] = 0,
the actual WAIT cycles end one cycle after WAIT de-asserts. When using variable initial access latency (BCR[14] = 0), the WAIT output per-
forms an arbitration role for READ operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for addi-
tional clock cycles until the refresh has completed. When the refresh operation has completed, the READ operation will continue normally.
WAIT will be asserted but should be ignored during asynchronous READ and WRITE operations. By using fixed initial latency (BCR[14] = 1),
this device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is
available at the start of the burst.
Figure 16: Wired or WAIT Configuration
UtRAM2
WAIT
External
Pull-Up
Pull-Down
Resistor
READY
WAIT
RDY
Processor
Other
Other
Device
Device
12.7 LB / UB Operation
The LB enable and UB enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be transferred
to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the
rising edge of CS, WE, LB, or UB, whichever occurs first. LB and UB must be LOW during READ cycles. When both the LB and UB are dis-
abled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be
deselected, it remains in an active mode as long as CS remains LOW.
Revision 0.1
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Nov 2008
Preliminary
K1C6416B2E
UtRAM2
13. LOW-POWER OPERATION
13.1 Temperature Compensated Self Refresh
Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This UtRAM2 device includes an on-
chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually adjusts the
refresh rate to match that temperature.
13.2 Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby
current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-
quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address
map. READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will
become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR.
13.3 Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided
by the UtRAM2 device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the UtRAM2
device will require 150µs to perform an initialization procedure before normal operations can resume. During this 150µs period, the current
consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD can be enabled
by writing to the RCR using CRE or the software access sequence; DPD starts when CS goes HIGH. DPD is disabled the next time CS goes
LOW and stays LOW for at least 10µs.
13.4 AC Input/Output Reference Waveform & AC Output Load Circuit
Test Points
VccQ
1
50Ω
2
2
Output
Test Points
Input
VccQ/2
VccQ/2
VccQ/2
DUT
30pF
VssQ
NOTE :
1) AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2) Input timing begins at VCCQ/2 and Output timing ends at VCCQ/2.
3) All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b)
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
14. TIMING REQUIREMENTS
14.1 Asynchronous READ Cycle Timing Requirements
Parameter
Address access time
Symbol
tAA
Min
Max
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
ADV access time
tAADV
tAPA
tAVS
tAVH
tBA
70
Page access time
20
Address setup to ADV HIGH
Addredd hold from ADV going HIGH
LB/UB access time
5
2
70
8
LB/UB disable to DQ High-Z output
LB/UB enable to Low-Z output
Maximum CS pulse width
CS LOW to WAIT valid
tBHZ
tBLZ
tCSM
tCSW
tCO
1
2
4
10
1
2.5
7.5
70
Chip select access time
CS LOW to ADV HIGH
tCVS
tHZ
7
Chip disable to DQ and WAIT High-Z output
Chip enable to Low-Z output
Output enable to valid output
Output hold from address change
Output disable to DQ High-Z output
Output ebable to Low-Z output
Page READ cycle time
8
20
8
1
2
tLZ
10
5
tOE
tOH
tOHZ
tOLZ
tPC
1
2
5
20
70
5
READ cycle time
tRC
ADV pulse width LOW
tVP
14.2 Asynchronous WRITE Cycle Timing Requirements
Parameter
Address and ADV LOW setup time
Address setup to ADV going HIGH
Addredd hold from ADV going HIGH
Address valid to end of WRITE
LB/UB select to end of WRITE
CS LOW to WAIT valid
Symbol
tAS
Min
0
Max
7.5
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tAVS
tAVH
tAW
5
2
70
70
1
tBW
tCSW
tCPH
tCVS
tCW
tDH
CS HIGH between subsequent async operations
CS LOW to ADV HIGH
5
1,4
2
7
Chip enable to end of WRITE
Data HOLD from WRITE time
Data WRITE setup time
70
0
3
tDW
tHZ
20
Chip disable to WAIT High-Z output
Chip enable to Low-Z output
End WRITE to Low-Z output
ADV pulse width
tLZ
10
5
1
2
tOW
tVP
5
ADV setup to end of WRITE
WRITE cycle time
tVS
70
70
tWC
tWHZ
tWP
tWPH
tWR
1
2
WRITE to DQ High-Z output
WRITE pulse width
8
55
10
0
WRITE pulse width HIGH
WRITE recovery time
NOTE:
1) The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
2) The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
3) WE LOW time must be limited to tCSM (2.5µs).
4) A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by the condition either clocked CS high or CS HIGH for longer than 15ns. CS must not remain
LOW longer than tCSM.
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
14.3 Brst READ Cycle Timing Requirements
104MHz
80MHz
66MHz
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
Address access time (fixed latency)
ADV access time (fixed latency)
Addredd hold from ADV going HIGH
Burst to READ access time (variable latency)
CLK to output delay
tAA
tAADV
tAVH
70
70
70
70
70
70
ns
ns
ns
ns
ns
ns
2
2
2
tABA
35.9
7
46.5
9
56.5
11
tACLK
tBOE
Burst OE LOW to output delay
20
20
20
CS HIGH between subsequent burst or mixed mode
operations
tCBPH
5
6
8
ns
3
3
Maximum CS pulse width
CS or ADV LOW to WAIT valid
CLK period
tCSM
tCSW
tCLK
tCO
2.5
7.5
2.5
7.5
2.5
7.5
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
9.62
12.5
15
Chip select access time (fixed latency)
CS setup time to active CLK edge
Hold time from active CLK edge
Chip desable to DQ and WAIT High-Z output
CLK rise or fall time
70
70
70
tCSP
tHD
3
2
4
2
5
2
tHZ
8
1.6
7
8
1.8
9
8
1
tKHKL
tKHTL
tKOH
tKP
2.0
11
CLK to WAIT valid
2
2
3
2
2
4
2
2
5
Output HOLD from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
ADV HIGH to CLK Rising
tOHZ
tOLZ
tSP
8
8
8
1
2
5
3
2
5
4
2
5
5
2
tAHCR
14.4 Burst WRITE Cycle Timing Requirements
104MHz
80MHz
66MHz
Parameter
Symbol
Unit
Notes
Min
0
Max
Min
0
Max
Min
0
Max
Address and ADV LOW setup time
Addredd hold from ADV going HIGH
tAS
ns
ns
tAVH
2
2
2
CS HIGH between subseuent burst or mixed mode
operations
tCBPH
5
6
8
ns
3
3
Maximum CS pulse width
CS LOW to WAIT valid
tCSM
tCSW
tCLK
tCSP
tHD
2.5
7.5
2.5
7.5
2.5
7.5
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
9.62
3
1
12.5
4
1
15
5
Clock period
CS setup to CLK active edge
Hold time from active CLK edge
Chip disable to WAIT High-Z output
Last clock to ADV LOW (fixed latency)
CLK rise or fall time
2
2
2
tHZ
8
8
8
1
tKADV
tKHKL
tKHTL
tKP
15
15
15
1.6
7
1.8
9
2.0
11
Clock to WAIT valid
2
3
3
2
2
4
4
2
2
5
5
2
CLK HIGH or LOW time
Setup time to activate CLK edge
ADV HIGH to CLK Rising
tSP
tAHCR
NOTE:
1) The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
2) The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
3) A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by the condition either clocked CS is high or CS HIGH for longer than
15ns. CS must not remain LOW longer than tCSM.
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
15. TIMING DIAGRAMS
15.1 Asynchronous READ
(CRE=VIL, WE=VIH)
tRC
Address
ADV
Valid Address
tAVS
tAVH
tAA
tCO
tOH
tHZ
CS
tBA
UB/, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
High-Z
Valid output
DQ[15:0]
tLZ
tHZ
tCSW
High-Z
High-Z
WAIT
Undefined
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
3) At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
4) tOE(max) is met only when OE becomes enabled after tAA(max).
5) If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to
sustain standby state for min. tRC at least once in every 2.5us.
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
15.2 Asynchronous READ Using ADV
(CRE=VIL, WE=VIH)
Valid Address
Address
tAA
tAVH
tAVS
ADV
tAADV
tVP
tCVS
CS
tCO
tHZ
tBA
UB/ LB
tBHZ
tOE
OE
tOLZ
tBLZ
tLZ
tOHZ
DQ[15:0]
High-Z
High-Z
Valid output
tHZ
tCSW
High-Z
WAIT
Undefined
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
3) At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
4) tOE(max) is met only when OE becomes enabled after tAA(max).
5) If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to
sustain standby state for min. tRC at least once in every 2.5us.
Revision 0.1
Nov 2008
- 26 -
Preliminary
K1C6416B2E
UtRAM2
15.3 PAGE MODE READ
(CRE=VIL, WE=VIH)
tRC
Address
A[1:0]
Valid Address
Valid
Address
Valid
Address
Valid
Address
Valid Address
tAA
tPC
ADV
CS
tCSM
tCO
tBA
tHZ
UB/ LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tAPA
tOH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
WAIT
High-Z
High-Z
tLZ
tHZ
tCSW
High-Z
Undefined
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
3) At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
4) tOE(max) is met only when OE becomes enabled after tAA(max).
5) If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to
sustain standby state for min. tRC at least once in every 2.5us.
Revision 0.1
Nov 2008
- 27 -
Preliminary
K1C6416B2E
UtRAM2
15.4 Single-Access Burst READ Operation—Variable Latency
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
tHD
VIH
VIL
A[22:0]
Valid Address
tSP
tHD
VIH
VIL
ADV
CS
tAVH
tHZ
tHD
tAHCR
tCSP
VIH
VIL
tOHZ
tBOE
VIH
VIL
OE
tOLZ
tSP
tHD
VIH
VIL
WE
tSP
tHD
VIH
VIL
LB/UB
WAIT
tKHTL
tCSW
VOH
VOL
High-Z
High-Z
tACLK
tKOH
VOH
VOL
High-Z
Valid Output
DQ[15:0]
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 28 -
Preliminary
K1C6416B2E
UtRAM2
15.5 4-Word Burst READ Operation—Variable Latency
(CRE=VIL)
tKP tKP
tCLK
tKHKL
VIH
VIL
CLK
tHD
tSP
VIH
VIL
A[22:0]
Valid Address
tSP tHD
VIH
VIL
ADV
tAVH
tHD
tHD
tSP
tAHCR
VIH
VIL
LB/UB
tCSP
tABA
tCSM
tCBPH
VIH
VIL
CS
OE
tHZ
tBOE
VIH
VIL
tOHZ
tKHTL
tSP
tHD
VIH
VIL
WE
tCSW
VOH
VOL
High-Z
WAIT
tKOH
tACLK
VIH
VIL
Valid
Output
Valid
Valid
Valid
DQ[15:0]
IN/OUT
High-Z
Output Output Output
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 29 -
Preliminary
K1C6416B2E
UtRAM2
15.6 Single-Access Burst READ Operation—Fixed Latency
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
tHD
VIH
VIL
A[22:0]
Valid Address
tHD
tSP
VIH
VIL
ADV
CS
tAVH
tHD
tHZ
tCSP
tAHCR
VIH
VIL
tOHZ
tBOE
VIH
VIL
OE
tOLZ
tSP
tHD
VIH
VIL
WE
tHD
tSP
VIH
VIL
LB/UB
WAIT
tKHTL
tCSW
High-Z
VOH
VOL
tACLK
tKOH
VOH
VOL
DQ[15:0]
High-Z
Valid Output
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
NOTE :
1)Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 30 -
Preliminary
K1C6416B2E
UtRAM2
15.7 4-Word Burst READ Operation—Fixed Latency
(CRE=VIL)
tKP tKP
tCLK
tKHKL
VIH
CLK
VIL
tHD
tSP
VIH
A[22:0]
ADV
Valid Address
VIL
tAA
tSP tHD
tAVH
VIH
VIL
tAHCR
tAADV
tHD
tHD
tSP
VIH
VIL
LB/UB
CS
tCBPH
tCSP
tCSM
VIH
VIL
tCO
tHZ
tBOE
VIH
VIL
OE
tOHZ
tOLZ
tKHTL
tSP
tHD
VIH
VIL
WE
tCSW
VOH
VOL
High-Z
WAIT
tKOH
tACLK
VIH
VIL
DQ[15:0]
IN/OUT
Valid
Output
Valid
Valid
Valid
High-Z
Output Output Output
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
15.8 4-Word Burst READ Operation— Row Boundary Crossing
(CRE=VIL)
tCLK
tKHKL
VIH
CLK
VIL
tHD
tSP
VIH
A[22:0]
ADV
Valid Address
VIL
tAA
tSP tHD
tAVH
VIH
VIL
tAHCR
tAADV
tHD
tSP
VIH
VIL
LB/UB
CS
tHD
tCBPH
tCSP
tCSM
VIH
VIL
tHZ
tCO
tBOE
VIH
VIL
OE
tOHZ
tOLZ
tKHTL
tSP
tHD
VIH
VIL
WE
tCSW
VOH
VOL
High-Z
WAIT
tKOH
tACLK
VIH
VIL
High-Z
DQ[15:0]
IN/OUT
Valid
Output
Valid
Output
Valid
Valid
Output Output
READ Burst Identified
(WE = HIGH)
End of Row
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
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Preliminary
K1C6416B2E
UtRAM2
15.9 READ Burst Suspend
(CRE=VIL)
tCLK
NOTE 2
VIH
CLK
VIL
tHD
tSP
VIH
VIL
Valid
Valid
Address
A[21:0]
ADV
CS
Address
tSP tHD
tAVH
VIH
VIL
tAHCR
tCSM
tCBPH
tHZ
tCSP
VIH
VIL
NOTE 3
tOHZ
tOHZ
VIH
VIL
OE
WE
tSP tHD
VIH
VIL
tSP
VIH
VIL
LB/UB
tBOE
tOLZ
tCSW
tCSW
VOH
VOL
High-Z
WAIT
tKOH
tBOE
tOLZ
VOH
VOL
High-Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]OUT
tACLK
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions during burst suspend.
3) OE can stay LOW during burst suspend. If OE is LOW, DQ[15:0] will continue to output valid data.
4) Don’t care must be in VIL or VIH.
Revision 0.1
- 33 -
Nov 2008
Preliminary
K1C6416B2E
UtRAM2
15.10 CS-Controlled Asynchronous WRITE
(CRE=VIL)
tWC
VIH
A[22:0]
Valid Address
VIL
tWR
tAW
tAS
VIH
ADV
VIL
tCPH
tCW
tBW
VIH
CS
VIL
VIH
UB/LB
VIL
VIH
OE
VIL
tWPH
tWP
VIH
WE
VIL
tDH
tDW
VIH
DQ[15:0]
High-Z
Valid Input
IN
VIL
tWHZ
tLZ
VOH
VOL
DQ[15:0]
OUT
tHZ
tCSW
VIH
VIL
High-Z
High-Z
WAIT
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte
operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high
or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.
3) tCW is measured from the CS going low to the end of write.
4) tAS is measured from the address valid to the beginning of write.
5) tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
Revision 0.1
Nov 2008
- 34 -
Preliminary
K1C6416B2E
UtRAM2
15.11 LB/UB-Controlled Asynchronous WRITE
(CRE=VIL)
tWC
VIH
A[22:0]
Valid Address
VIL
tAW
tAS
tWR
VIH
VIL
ADV
CS
tCW
tBW
VIH
VIL
VIH
VIL
UB/LB
OE
VIH
VIL
tWPH
High-Z
tCSW
tWP
VIH
VIL
WE
tDH
tDW
VIH
VIL
DQ[15:0]
IN
Valid Input
tWHZ
tLZ
VOH
VOL
DQ[15:0]
OUT
tHZ
VIH
VIL
High-Z
High-Z
WAIT
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte
operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high
or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.
3) tCW is measured from the CS going low to the end of write.
4) tAS is measured from the address valid to the beginning of write.
5) tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
Revision 0.1
Nov 2008
- 35 -
Preliminary
K1C6416B2E
UtRAM2
15.12 WE-Controlled Asynchronous WRITE
(CRE=VIL)
tWC
VIH
A[22:0]
Valid Address
VIL
tAW
tWR
VIH
ADV
VIL
tCW
tBW
VIH
CS
VIL
VIH
UB/LB
VIL
VIH
OE
VIL
tAS
tWPH
tWP
VIH
WE
VIL
tDH
tDW
VIH
DQ[15:0]
High-Z
Valid Input
IN
VIL
tWHZ
tLZ
tOW
VOH
VOL
DQ[15:0]
OUT
tHZ
tCSW
High-Z
VIH
VIL
High-Z
WAIT
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte
operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high
or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.
3) tCW is measured from the CS going low to the end of write.
4) tAS is measured from the address valid to the beginning of write.
5) tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
Revision 0.1
Nov 2008
- 36 -
Preliminary
K1C6416B2E
UtRAM2
15.13 Asynchronous WRITE Using ADV
(CRE=VIL)
VIH
A[22:0]
Valid Address
VIL
tAVS
tAVH
tVS
tVP
VIH
VIL
tAS
tAS
ADV
CS
tAW
tCW
VIH
VIL
tBW
VIH
VIL
UB/LB
OE
VIH
VIL
tWP
tWPH
VIH
VIL
WE
tDH
tDW
VIH
VIL
DQ[15:0]
IN
High-Z
Valid Input
tWHZ
tLZ
tOW
VOH
VOL
DQ[15:0]
OUT
tHZ
tCSW
High-Z
VIH
VIL
High-Z
WAIT
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte
operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high
or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.
3) tCW is measured from the CS going low to the end of write.
4) tAS is measured from the address valid to the beginning of write.
5) tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
Revision 0.1
Nov 2008
- 37 -
Preliminary
K1C6416B2E
UtRAM2
15.14 Burst WRITE Operation—Variable Latency Mode
(CRE=VIL)
tKHKL
tKP
tCLK
tKP
VIH
VIL
CLK
tHD
tSP
VIH
VIL
A[22:0]
Valid Address
tAS3
tAVH
tKADV
tSP tHD
VIH
VIL
ADV
tAHCR
tSP tHD
tAS3
VIH
VIL
LB/UB
tCSM
tCBPH
tCSP
tHD
VIH
VIL
CS
OE
VIH
VIL
tSP tHD
VIH
VIL
WE
tKHTL
tHZ
tCSW
High-Z
VOH
VOL
High-Z
WAIT
NOTE 2
tSP
tHD
VIH
VIL
D2
DQ[15:0]
D1
D3
D4
WRITE Burst Identified
(WE = LOW)
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay; burst length four; burst wrap enabled.
2) WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3) tAS required if tCSP > 20ns.
4) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 38 -
Preliminary
K1C6416B2E
UtRAM2
15.15 Burst WRITE Operation—Fixed Latency Mode
(CRE=VIL)
tKHKL
tKP
tCLK
tKP
VIH
VIL
CLK
tSP
tHD
VIH
VIL
A[22:0]
Valid Address
tAS3
tAVH
tKADV
tSP tHD
VIH
VIL
ADV
tAHCR
tSP tHD
tAS3
VIH
VIL
LB/UB
tCSM
tCBPH
tCSP
tHD
VIH
VIL
CS
OE
VIH
VIL
tSP tHD
VIH
VIL
WE
tKHTL
tHZ
tCSW
High-Z
VOH
VOL
High-Z
WAIT
NOTE 2
tSP
tHD
VIH
VIL
D2
DQ[15:0]
D1
D3
D4
WRITE Burst Identified
(WE = LOW)
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay; burst length four; burst wrap enabled.
2) WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3) tAS required if tCSP > 20ns.
4) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 39 -
Preliminary
K1C6416B2E
UtRAM2
15.16 4-Word Burst WRITE Operation— Row Boundary Crossing
(CRE=VIL)
tKP
tCLK
tKP
tKHKL
VIH
VIL
CLK
tHD
tSP
VIH
VIL
A[22:0]
Valid Address
tSP tHD
tAVH
VIH
VIL
ADV
LB/UB
CS
tAHCR
tHD
tSP
VIH
VIL
tHD
tCBPH
tCSP
A
VIH
VIL
tHZ
VIH
VIL
OE
tSP
tHD
VIH
VIL
WE
tKHTL
tCSW
VOH
VOL
High-Z
WAIT
tSP
tHD
VIH
VIL
DQ[15:0]
IN/OUT
High-Z
D1
D2
D3
D4
End of Row
WRITE Burst Identified
(OE = HIGH)
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
3) D2 can be written when CS goes high at Point A.
Revision 0.1
Nov 2008
- 40 -
Preliminary
K1C6416B2E
UtRAM2
15.17 Burst WRITE Followed by Burst READ
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
tHD
tSP
tHD
VIH
VIL
Valid
Valid
A[22:0]
Address
Address
tSP
tKADV3
tHD
tSP
tSP
tHD
tAVH
VIH
ADV
tSP
tHD
tAHCR
tAHCR
VIL
VIH
LB/UB
VIL
tCSP
tCBPH
tHD
VIH
VIL
CS
OE
NOTE2
tCSP
tOHZ
VIH
VIL
tSP
tHD
VIH
VIL
tSP
tHD
WE
tBOE
tCSW
tCSW
VOH
VOL
High-Z
WAIT
tKOH
tSP
tHD
tACLK
VOH
VIH
VIL
Valid
Valid
Valid
Valid
High-Z
D0
D1
D2
D3
High-Z
DQ[0:15]
Output Output Output Output
VOL
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
2) A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CS HIGH, or
b) CS HIGH for longer than 15ns. CS can stay LOW between burst READ and burst WRITE operations, but CS must not remain LOW longer than tCSM.
See burst interrupt diagrams for cases where CS stays LOW between bursts.
3) Only fixed latency requires tKADV.
4) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 41 -
Preliminary
K1C6416B2E
UtRAM2
15.18 Burst READ Interrupted by Burst READ or WRITE
(CRE=VIL)
READ Burst interrupted with new READ or WRITE. See Note 2.
tCLK
VIH
VIL
CLK
tHD
tHD
tSP
tSP
VIH
VIL
Valid
Valid
A[22:0]
Address
Address
tSP tHD
tSP tHD
tAVH
VIH
VIL
ADV
CS
tAHCR
tAHCR
tCSM (Note 3)
tCSP
tHD
VIH
VIL
tSP tHD
tSP tHD
VIH
VIL
WE
tKHTL
tBOE
VOH
VOL
tBOE
High-Z
WAIT
tOHZ
tCSW
VIH
VIL
OE
2nd Cycle READ
tSP
VIH
VIL
LB/UB
2nd Cycle READ
tKOH
tKOH
tACLK
High-Z
VOH
VOL
DQ[15:0]OUT
2nd Cycle WRITE
Valid
Output
Valid
Valid
Valid
Valid
High-Z
Output Output Output Output
tACLK
VIH
VIL
OE
2nd Cycle WRITE
VIH
VIL
LB/UB
2nd Cycle WRITE
tSP
tHD
VIH
VIL
DQ[15:0]IN
2nd Cycle WRITE
High-Z
D0
D1
D2
D3
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.
2) Burst interrupt shown on first allowable clock (i.e., after the first data received by the controller).
3) CS can stay LOW between burst operations, but CS must not remain LOW longer than tCSM.
4) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 42 -
Preliminary
K1C6416B2E
UtRAM2
15.19 Burst WRITE Interrupted by Burst WRITE or READ—Variable Latency Mode
(CRE=VIL)
WRITE Burst interrupted with new WRITE or READ. See Note 2.
tCLK
VIH
CLK
VIL
tHD
tHD
tSP
tSP
VIH
VIL
Valid
Address
Valid
Address
A[22:0]
tSP tHD
tSP tHD
VIH
VIL
ADV
CS
tAHCR
tAHCR
tCSM (Note 3)
tCSP
tHD
VIH
VIL
tSP tHD
tSP tHD
VIH
VIL
WE
tKHTL
VOH
VOL
High-Z
High-Z
WAIT
tCSW
VIH
VIL
OE
2nd Cycle WRITE
tSP tHD
VIH
VIL
LB/UB
2nd Cycle WRITE
tSP tHD
tSP tHD
VIH
VIL
DQ[15:0]IN
2nd Cycle WRITE
High-Z
D0
D0
D1
D2
D3
tOHZ
tBOE
VIH
OE
2nd Cycle READ
VIL
tSP
VIH
VIL
LB/UB
2nd Cycle READ
tKOH
VOH
VOH
VOL
Valid
Output
Valid
Valid
Valid
High-Z
DQp15:0]OUT
2nd Cycle READ
Output Output Output
VOL
tACLK
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable latency; latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.
2) Burst interrupt shown on first allowable clock (i.e., after first data word written).
3) CS can stay LOW between burst operations, but CS must not remain LOW longer than tCSM.
4) Don’t care must be in VIL or VIH.
Revision 0.1
- 43 -
Nov 2008
Preliminary
K1C6416B2E
UtRAM2
15.20 Burst WRITE Interrupted by Burst WRITE or READ—Fixed Latency Mode
(CRE=VIL)
WRITE Burst interrupted with new WRITE or READ. See Note 2.
tCLK
VIH
CLK
VIL
tSP
tSP
VIH
VIL
Valid
Address
Valid
Address
A[22:0]
tSP tHD
tSP tHD
tKADV
VIH
VIL
ADV
CS
tAHCR
tAHCR
tCSM (Note 3)
tCSP
tHD
VIH
VIL
tSP tHD
tSP tHD
VIH
VIL
WE
tKHTL
VOH
VOL
High-Z
High-Z
WAIT
tCSW
VIH
VIL
OE
2nd Cycle WRITE
tSP tHD
VIH
VIL
LB/UB
2nd Cycle WRITE
tSP tHD
tSP tHD
VIH
VIL
DQ[15:0]IN
2nd Cycle WRITE
High-Z
D0
D0
D1
D2
D3
tOHZ
tBOE
VIH
OE
2nd Cycle READ
VIL
tSP
VIH
VIL
tHD
LB/UB
2nd Cycle READ
tKOH
VOH
VOH
VOL
Valid
Output
Valid
Valid
Valid
High-Z
DQ[15:0]OUT
2nd Cycle READ
Output Output Output
VOL
tACLK
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: Fixed latency; latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2) Burst interrupt shown on first allowable clock (i.e., after first data word written).
3) CS can stay LOW between burst operations, but CS must not remain LOW longer than tCSM.
4) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 44 -
Preliminary
K1C6416B2E
UtRAM2
15.21 Asynchronous WRITE Followed by Burst READ
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
Valid Address
tSP tHD
tHD
tWC
tWC
VIH
VIL
A[22:0]
ADV
Valid Address
tAVS
Valid Address
tAW
tWR
VIH
VIL
tAHCR
tVS
tHD
tVP
tSP
tBW
VIH
VIL
LB/UB
tCVS
tCW
tCBPH
Note 2
tCSP
VIH
VIL
CS
OE
tAS
tOHZ
VIH
VIL
tWC
tWPH
tHD
tSP
tAS
tWP
VIH
VIL
WE
tCSW
tCSW
tBOE
VOH
VOL
High-Z
WAIT
tKOH
tACLK
VOH
VOL
VIH
VIL
DQ[15:0]
IN/OUT
Valid
Output
Valid
Valid
Valid
High-Z
High-Z
Data
Data
Output Output Output
tDH
tDW
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
2) When transitioning between asynchronous and variable-latency burst operations, CS must go HIGH. CS can stay LOW when transitioning to fixed-latency
burst READs. A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CS
HIGH, or b) CS HIGH for longer than 15ns.
3) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 45 -
Preliminary
K1C6416B2E
UtRAM2
15.22 Asynchronous WRITE (ADV LOW) Followed By Burst READ
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
Valid Address
tHD
tHD
tWC
tWC
VIH
VIL
A[22:0]
Valid Address
Valid Address
tAW
tWR
tSP
VIH
VIL
ADV
LB/UB
CS
tAHCR
tSP
tBW
VIH
VIL
tCBPH
Note 2
tCW
tCSP
VIH
VIL
tOHZ
VIH
VIL
OE
tWC
tWPH
tHD
tSP
tWP
VIH
VIL
WE
tCSW
tCSW
tBOE
VOH
VOL
High-Z
WAIT
tKOH
tACLK
VOH
VOL
VIH
VIL
DQ[15:0]
IN/OUT
Valid
Output
Valid
Valid
Valid
High-Z
High-Z
Data
Data
Output Output Output
tDH
tDW
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for asynchronous WRITE, with ADV LOW, followed by burst READ: Fixed or variable latency; latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2) When transitioning between asynchronous and variable-latency burst operations, CS must go HIGH. CS can stay LOW when transitioning to fixed-latency
burst READs. A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CS
HIGH, or b) CS HIGH for longer than 15ns.
3) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 46 -
Preliminary
K1C6416B2E
UtRAM2
15.23 Burst READ Followed by Asynchronous WRITE (WE-Controlled)
(CRE=VIL)
tCLK
VIH
CLK
VIL
tWC
tSP
tHD
VIH
VIL
A[22:0]
Valid Address
Valid Address
tAW
tSP
tHD
tWR
VIH
VIL
ADV
CS
tAHCR
tHD
tCBPH
Note 2
tHZ
tCW
tCSP
VIH
VIL
tOHZ
tBOE
VIH
VIL
OE
tAS
tWPH
tWP
tBW
tOLZ
tSP
tHD
VIH
VIL
WE
tSP
VIH
VIL
LB/UB
WAIT
tKHTL
tHZ
tCSW
tCSW
High-Z
VOH
VOL
High-Z
tDH
tACLK
tKOH
tDW
VIH
VOH
VOL
High-Z
Valid Output
Valid Input
DQ[15:0]
VIL
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for burst READ followed by asynchronous WE-controlled WRITE: Fixed or variable latency; latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2) When transitioning between asynchronous and variable-latency burst operations, CS must go HIGH. CS can stay LOW when transitioning from fixed-latency
burst READs; asynchronous operation begins at the falling edge of ADV. A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied
by either of the following two conditions: a) clocked CS HIGH, or b) CS HIGH for longer than 15ns.
3) Don’t care must be in VIL or VIH.
Revision 0.1
- 47 -
Nov 2008
Preliminary
K1C6416B2E
UtRAM2
15.24 Burst READ Followed by Asynchronous WRITE Using ADV
(CRE=VIL)
tCLK
VIH
CLK
VIL
tSP
tHD
VIH
VIL
Valid Address
Valid Address
A[22:0]
ADV
tAVS
tVS
tSP
tHD
tVP
VIH
VIL
tAHCR
tAW
tHD
tCBPH
tHZ
tAS
tCW
tCSP
VIH
VIL
CS
OE
WE
Note 2
tOHZ
tBOE
VIH
VIL
tAS
tOLZ
tWPH
tWP
tSP
tHD
VIH
VIL
tBW
tSP
VIH
VIL
LB/UB
WAIT
tKHTL
tHZ
tCSW
tCSW
High-Z
VIH
VIL
High-Z
tDH
tKOH
tDW
tACLK
VIH
VIH
VIL
DQ[15:0]
IN/OUT
High-Z
Valid Output
Valid Input
VIL
READ Burst Identified
(WE = HIGH)
Undefined
Don’t Care
NOTE :
1) Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV: Fixed or variable latency; latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2) When transitioning between asynchronous and variable-latency burst operations, CS must go HIGH. CS can stay LOW when transitioning from fixed-latency
burst READs; asynchronous operation begins at the falling edge of ADV. A refresh opportunity must be provided every tCSM. A refresh opportunity is satisfied
by either of the following two conditions: a) clocked CS HIGH, or b) CS HIGH for longer than 15ns.
3) Don’t care must be in VIL or VIH.
Revision 0.1
- 48 -
Nov 2008
Preliminary
K1C6416B2E
UtRAM2
15.25 Asynchronous WRITE Followed by Asynchronous READ—ADV LOW
(CRE=VIL)
VIH
Valid Address
Valid Address
Valid Address
A[22:0]
VIL
tAW
tWR
tAA
VIH
VIL
ADV
tBHZ
tBW
tBLZ
VIH
VIL
LB/UB
tHZ
tCW
tCPH
VIH
VIL
CS
OE
tOHZ
Note 1
tLZ
tOE
VIH
VIL
tWC
tWPH
tAS
tWP
VIH
VIL
WE
tHZ
tHZ
tCSW
tWHZ
VIH
VIL
WAIT
tOLZ
VOH
VOL
VIH
VIL
DQ[15:0]
IN/OUT
High-Z
High-Z
Data
Data
Valid Output
tDW
tDH
Undefined
Don’t Care
NOTE :
1) When configured for synchronous mode (BCR[15] = 0), CS must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval.
Otherwise, tCPH is only required after CS-controlled WRITEs.
2) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 49 -
Preliminary
K1C6416B2E
UtRAM2
15.26 Asynchronous WRITE Followed by Asynchronous READ
(CRE=VIL)
VIH
Valid Address
Valid Address
Valid Address
tAA
A[22:0]
VIL
tAVS
tVP
tAW
tVS
tWR
VIH
VIL
ADV
tBHZ
tCVS
tCW
tBLZ
tBW
VIH
VIL
LB/UB
tCPH
tHZ
VIH
VIL
CS
OE
Note 1
tLZ
tAS
tOHZ
VIH
VIL
tWC
tAS
tWP
tWPH
tOLZ
VIH
VIL
WE
tCSW
tWHZ
VIH
VIL
WAIT
tOE
VOH
VOL
VIH
VIL
DQ[15:0]
IN/OUT
High-Z
High-Z
Data
Data
Valid Output
tDH
tDW
Undefined
Don’t Care
NOTE :
1) When configured for synchronous mode (BCR[15] = 0), CS must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval.
Otherwise,tCPH is only required after CS-controlled WRITEs.
2) Don’t care must be in VIL or VIH.
Revision 0.1
Nov 2008
- 50 -
相关型号：
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SAMSUNG
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