K1S32161CD-FI70T [SAMSUNG]

Memory IC, 2MX16, CMOS, PBGA48;


型号：	K1S32161CD-FI70T
厂家：	SAMSUNG
描述：	Memory IC, 2MX16, CMOS, PBGA48
文件：	总10页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K1S32161CD

UtRAM

Document Title

2Mx16 bit Page Mode Uni-Transistor Random Access Memory

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial Draft

October 04, 2004

Preliminary

1.0

Finalize

April 06, 2005

Final

- Added Lead Free Product

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

April 2005

- 1 -

K1S32161CD

UtRAM

2M x 16 bit Page Mode Uni-Transistor CMOS RAM

FEATURES

GENERAL DESCRIPTION

• Process Technology: CMOS

• Organization: 2M x16 bit

The K1S32161CD is fabricated by SAMSUNG′s advanced

CMOS technology using one transistor memory cell. The device

support 4 page mode operation, Industrial temperature range

and 48 ball Chip Scale Package for user flexibility of system

design. The device also supports Internal Temperature Compen-

sated Self Refresh for low standby current.

• Power Supply Voltage: 2.7~3.1V

• Three State Outputs

• Compatible with Low Power SRAM

• Support 4 page read mode

• Package Type: 48-FBGA-6.00x8.00

PRODUCT FAMILY

Power Dissipation

Speed

(tRC)

Product Family

Operating Temp.

Vcc Range

PKG Type

Standby

Operating

(ISB1, Max.)

(ICC2, Max.)

K1S32161CD-I

Industrial(-40~85°C)

2.7~3.1V

70ns

100µA

35mA

48-FBGA-6.00x8.00

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

Clk gen.

Precharge circuit.

CS2

I/O1

I/O3

Vcc

Vss

I/O7

I/O8

A20

Vcc

Vss

I/O9

I/O10

Vss

CS1

I/O2

I/O4

I/O5

I/O6

Row

select

Row

Addresses

Memory array

I/O11

I/O12

I/O13

I/O14

A19

A17

DNU

A14

A12

I/O Circuit

Column select

Data

cont

I/O1~I/O8

Vcc

A16

A15

A13

A10

Data

cont

I/O9~I/O16

I/O15

I/O16

A18

Data

cont

Column Addresses

A11

CS1

CS2

48-FBGA: Top View(Ball Down)

Control Logic

Name

Function

Name

Vcc

Vss

Function

Power

Ground

CS1,CS2 Chip Select Inputs

Output Enable Input

Write Enable Input

Address Inputs

Upper Byte(I/O9~16)

Lower Byte(I/O1~8)

Do Not Use

A0~A20

I/O1~I/O16 Data Inputs/Outputs

DNU

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

April 2005

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K1S32161CD

UtRAM

POWER UP SEQUENCE

1. Apply power.

2. Maintain stable power(Vcc min.=2.7V) for a minimum 200µs with CS1=high.or CS2=low.

TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)

Min. 200µs

VCC(Min)

VCC

CS1

CS2

Power Up Mode

NormalOperation

POWER UP(1)

1. After V^CCreaches VCC(Min.), wait 200µs with CS1 high. Then the device gets into the normal operation.

TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)

Min. 200µs

VCC(Min)

VCC

CS1

CS2

Power Up Mode

Normal Operation

POWER UP(2)

1. After V^CCreaches VCC(Min.), wait 200µs with CS2 low. Then the device gets into the normal operation.

Revision 1.0

April 2005

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K1S32161CD

UtRAM

FUNCTIONAL DESCRIPTION

CS1

X¹⁾

CS2

X¹⁾

I/O1~8

High-Z

Dout

I/O9~16

High-Z

Dout

Mode

Power

Standby

Active

X¹⁾

Deselected

X¹⁾

Deselected

X¹⁾

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

X¹⁾

High-Z

Dout

Active

Dout

X¹⁾

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

High-Z

Din

1. X means don′t care. (Must be low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Symbol

VIN, VOUT

VCC

Ratings

-0.2 to VCC+0.3V

-0.2 to 3.6V

1.0

Unit

Storage temperature

TSTG

-65 to 150

-40 to 85

°C

Operating Temperature

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-

ability.

Revision 1.0

April 2005

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K1S32161CD

UtRAM

PRODUCT LIST

Industrial Temperature Product(-40~85°C)

Part Name

Function

K1S32161CD-FI70

K1S32161CD-BI70

48-FBGA, 70ns, 2.9V

48-FBGA, 70ns, 2.9V, LF

1. LF : Lead Free Product

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

2.7

Typ

Max

3.1

Unit

Supply voltage

Ground

2.9

Vss

Vcc+0.3²⁾

0.6

Input high voltage

Input low voltage

VIH

2.2

-0.2³⁾

VIL

1. TA=-40 to 85°C, otherwise specified.

2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.

3. Undershoot: -1.0V in case of pulse width ≤20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

Min

Max

Unit

VIN=0V

VIO=0V

Input/Output capacitance

CIO

1. Capacitance is sampled, not 100% tested.

DC AND OPERATING CHARACTERISTICS

Typ¹⁾

Symbol

Item

Test Conditions

Min

Max

Unit

Input leakage current

ILI

VIN=Vss to Vcc

-1

µA

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH,

VIO=Vss to Vcc

Output leakage current

ILO

µA

Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V,

LB≤0.2V or/and UB≤0.2V, CS2≥Vcc-0.2V, VIN≤0.2V or

VIN≥VCC-0.2V

ICC1

ICC2

Average operating current

Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH,

LB=VIL or/and UB=VIL,VIN=VIL or VIH

Output low voltage

Output high voltage

VOL

VOH

IOL=2.1mA

IOH=-1.0mA

0.4

2.4

Other inputs = 0~Vcc

1) CS1≥Vcc-0.2V, CS2≤Vcc-0.2V (CS1 controlled) or

2) 0V≤CS2≤0.2V(CS2 controlled)

Standby Current(CMOS)

ISB1

100

µA

1. Typical values are tested at VCC=2.9V, TA=25°C and not guaranteed.

2. ISB1 is measured after 60ms from the time when standby mode is set up.

Revision 1.0

April 2005

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K1S32161CD

UtRAM

AC OPERATING CONDITIONS

Dout

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.4 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V

Output load: CL=50pF

1. Including scope and jig capacitance

AC CHARACTERISTICS(Vcc=2.7~3.1V, TA=-40 to 85°C)

Speed Bin

70ns¹⁾

Parameter List

Symbol

Units

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

Output Enable to Valid Output

UB, LB Access Time

tCO

tOE

tBA

Chip Select to Low-Z Output

tLZ

UB, LB Enable to Low-Z Output

Read

tBLZ

tOLZ

tHZ

Output Enable to Low-Z Output

Chip Disable to High-Z Output

UB, LB Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Page Cycle

tBHZ

tOHZ

tOH

tPC

Page Access Time

tPA

Write Cycle Time

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

UB, LB Valid to End of Write

tAW

tBW

tWP

tWR

tWHZ

tDW

tDH

tOW

55¹⁾

Write

Write Pulse Width

Write Recovery Time

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

1. tWC(min)=90ns or tWP(min)=70ns for continuous write operation over 50 times.

Revision 1.0

April 2005

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K1S32161CD

UtRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH)

tRC

Address

tOH

tAA

tCO

CS1

CS2

tHZ

tBA

UB, LB

tBHZ

tOE

tOLZ

tBLZ

tLZ

tOHZ

High-Z

Data out

Data Valid

TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)

Valid

Address

A20~A2

Valid

Address

Valid

Address

A1~A0

Address Address

tAA

tPC

CS1

CS2

tCO

tPA

Data

tOHZ

tOE

High Z

Data

Valid

Data

Valid

Data

Valid

DQ15~DQ0

Valid

(READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

3. tOE(max) is met only when OE becomes enabled after tAA(max).

4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or

needs to sustain standby state for min. tRC at least once in every 4us.

Revision 1.0

April 2005

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K1S32161CD

UtRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

tCW

Address

CS1

tWR

CS2

tAW

tBW

UB, LB

tWP

tAS

tDW

tDH

High-Z

Data in

Data Valid

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

tWC

Address

tWR

tAS

tCW

CS1

tAW

CS2

tBW

UB, LB

tWP

tDW

tDH

Data Valid

Data in

High-Z

Data out

Revision 1.0

April 2005

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K1S32161CD

UtRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

tWR

tAS

tCW

CS1

CS2

tAW

tBW

UB, LB

tWP(1)

tDW

tDH

Data Valid

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)

tWC

Address

CS1

tWR

tCW

tAW

CS2

tBW

UB, LB

tAS

tWP

tDH

tDW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting

UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-

sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS1 going low to the end of write.

3. t^ASis measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.

Revision 1.0

April 2005

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K1S32161CD

UtRAM

Unit: millimeters

PACKAGE DIMENSION

48 BALL FINE PITCH BGA(0.75mm ball pitch)

Top View

Bottom View

#A1

Detail A

Side View

Min

Typ

0.75

6.00

3.75

8.00

5.25

0.45

Max

Notes.

5.90

6.10

1. Bump counts: 48(8 row x 6 column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are ±0.050 unless

specified beside figures.

4. Typ : Typical

7.90

8.10

0.40

0.50

1.00

5. Y is coplanarity

0.25

0.10

Revision 1.0

April 2005

- 10 -

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