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K1S3216B9E-FI70T [SAMSUNG]

DRAM;
K1S3216B9E-FI70T
型号： K1S3216B9E-FI70T
厂家： SAMSUNG    SAMSUNG
描述：

DRAM

动态存储器
文件： 总17页 (文件大小：417K)
中文：  中文翻译
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Preliminary  
K1S3216B9E  
UtRAM  
32Mb (2M x 16 bit) Multiplexed UtRAM  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND  
IS SUBJECT TO CHANGE WITHOUT NOTICE.  
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS  
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN  
SAMSUNG PRODUCTS OR TECHNOLOGY.  
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUAR-  
ANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar  
applications where Product failure could result in loss of life or personal or physical harm, or any military or defense  
application, or any governmental procurement to which special terms or provisions may apply.  
* Samsung Electronics reserves the right to change products or specification without notice.  
Revision 0.0  
- 1 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
Document Title  
2M x 16 bit Multiplexed Asynchronous Uni-Transistor Random Access Memory  
Revision History  
RevisionNo.  
History  
Draft Date  
Remark  
0.0  
Initial  
December 19, 2006  
Preliminary  
- Design target  
Revision 0.0  
December 2006  
- 2 -  
Preliminary  
K1S3216B9E  
UtRAM  
Table of Contents  
GENERAL DESCRIPTION...............................................................................................................................1  
FEATURES & FUNCTION BLOCK DIAGRAM ................................................................................................1  
PIN DESCRIPTIONS........................................................................................................................................1  
PRODUCT FAMILY..........................................................................................................................................1  
POWER UP SEQUENCE.................................................................................................................................2  
FUNCTIONAL DESCRIPTION.........................................................................................................................2  
ABSOLUTE MAXIMUM RATINGS...................................................................................................................3  
RECOMMENDED DC OPERATING CONDITIONS.........................................................................................3  
CAPACITANCE................................................................................................................................................3  
DC AND OPERATING CHARACTERISTICS...................................................................................................3  
AC OPERATING CONDITIONS.......................................................................................................................4  
TIMING REQUIREMENTS...............................................................................................................................4  
READ Cycle Timing Requirements.............................................................................................................4  
WRITE Cycle Timing Requirements ...........................................................................................................4  
TIMING DIAGRAMS.........................................................................................................................................5  
READ (CS controlled).................................................................................................................................5  
READ (OE controlled).................................................................................................................................6  
READ Followed by WRITE (CS Controlled) ...............................................................................................7  
READ Followed by WRITE (OE, WE Controlled) .......................................................................................8  
READ Followed by WRITE at the Same Address ......................................................................................9  
WRITE (CS Controlled) ..............................................................................................................................10  
WRITE (WE, UB/LB Controlled) ................................................................................................................11  
WRITE Followed by READ (CS Controlled) ..............................................................................................12  
WRITE Followed by READ (OE, WE Controlled) ......................................................................................13  
PACKAGE DIMENSION...................................................................................................................................14  
48 BALL FINE PITCH BGA(0.75mm ball pitch)................................................................................................14  
Revision 0.0  
December 2006  
- 1 -  
Preliminary  
K1S3216B9E  
UtRAM  
2M x 16 bit Multiplexed Asynchronous Uni-Transistor Random Access Memory  
GENERAL DESCRIPTION  
The K1S3216B9E is fabricated by SAMSUNG′s advanced CMOS technology using one transistor memory cell. The device sup-  
ports Industrial temperature range. The device supports internal TCSR(Temperature Compensated Self Refresh) for the standby  
power saving at room temperature range.  
FEATURES & FUNCTION BLOCK DIAGRAM  
• Process technology: CMOS  
Pre-charge circuit  
• Organization: 2M x 16 bit  
• Power supply voltage: 1.7V~1.95V  
• Three state outputs  
• Supports power saving modes  
- Internal TCSR (Temperature Compensated Self Refresh)  
V
CC  
CCQ  
SS  
V
V
Memory  
Array  
V
SSQ  
Row  
select  
Row  
Addresses  
A16~A20  
PIN DESCRIPTIONS  
I/O Circuit  
Data  
cont  
A/DQ0~A/DQ7  
Name  
CS  
Function  
Chip Select Inputs  
Column Select  
Data  
cont  
A/DQ8~A/DQ15  
OE  
Output Enable Input  
Write Enable Input  
Address Valid  
Data  
cont  
WE  
Column Address  
ADV  
A/DQ0~A/DQ15  
A16~A20  
Vcc/VCCQ  
Vss/VssQ  
UB  
Address and Data Inputs/Outputs  
Address Inputs  
ADV  
CS  
Power Supply(core / I/O)  
Ground  
OE  
WE  
UB  
LB  
Control Logic  
Upper Byte(I/O8~15)  
Lower Byte(I/O0~7)  
Do Not Use  
LB  
DNU  
PRODUCT FAMILY  
Product Family  
Current Consumption  
Speed  
(tAA)  
Operating Temp.  
Vcc / Vccq  
Standby  
Operating  
(ISB1, Max.)  
(ICC2, Max.)  
TBD < 85°C  
TBD < 40°C  
K1S3216B9E-I  
Industrial(-40~85°C)  
1.7V~1.95V  
70ns  
TBD  
Revision 0.0  
December 2006  
- 1 -  
Preliminary  
K1S3216B9E  
UtRAM  
POWER UP SEQUENCE  
During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle  
of active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to  
keep the following power up sequence.  
1. Apply power.  
2. Maintain stable power(Vcc min.=1.7V) for a minimum 150µs with CS=high.  
TIMING WAVEFORM OF POWER UP  
Min. 150µs  
VCC(Min)  
VCC  
CS  
FUNCTIONAL DESCRIPTION  
CS  
H
L
OE  
X1)  
H
H
L
WE  
X1)  
H
LB  
X1)  
X1)  
X1)  
L
UB  
X1)  
X1)  
X1)  
H
ADV  
X1)  
A/DQ0~15  
High-Z  
High-Z  
Add. Input  
Dout  
A16 ~ A21  
Mode  
Power  
Standby  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
X1)  
X1)  
Deselected  
H
Output Disabled  
Address Input  
Lower Byte Read  
Upper Byte Read  
Word Read  
L
H
Add. Input  
X1)  
L
H
H
H
H
H
H
H
X1)  
L
L
H
H
L
Dout  
X1)  
L
L
H
L
L
Dout  
X1)  
L
H
H
H
L
L
H
Din  
Lower Byte Write  
Upper Byte Write  
Word Write  
X1)  
L
L
H
L
Din  
X1)  
L
L
L
L
Din  
1) X means don′t care. (Must be VIL or VIH)  
Revision 0.0  
- 2 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
ABSOLUTE MAXIMUM RATINGS  
Item  
Symbol  
VIN, VOUT  
VCC, VCCQ  
PD  
Ratings  
-0.2 to VCCQ+0.3V  
-0.2 to 2.5V  
1.0  
Unit  
V
Voltage on any pin relative to Vss  
Power supply voltage relative to Vss  
Power Dissipation  
V
W
Storage temperature  
TSTG  
-65 to 150  
-40 to 85  
°C  
°C  
Operating Temperature  
TA  
1) Stresses greater than "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be  
used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.  
RECOMMENDED DC OPERATING CONDITIONS  
Item  
Symbol  
VCC, VCCQ  
VSS, VSSQ  
VIH  
Min  
1.7  
Typ  
Max  
1.95  
0
Unit  
V
Power supply voltage(Core, I/O)  
Ground(Core, I/O)  
1.8  
0
0
-
V
VCCQ+0.22)  
0.4  
Input high voltage  
VCCQ-0.4  
V
-0.23)  
Input low voltage  
VIL  
-
V
1. TA=-40 to 85°C, otherwise specified.  
2. Overshoot: VCCQ +1.0V in case of pulse width ≤20ns. Overshoot is sampled, not 100% tested.  
3. Undershoot: -1.0V in case of pulse width ≤20ns. Undershoot is sampled, not 100% tested.  
CAPACITANCE  
Item  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
8
Unit  
pF  
Input capacitance  
-
-
Input/Output capacitance  
CIO  
VIO=0V  
8
pF  
1. Freq.=1MHz, TA=25°C  
2. Capacitance is sampled, not 100% tested.  
DC AND OPERATING CHARACTERISTICS  
Item  
Symbol  
ILI  
Test Conditions  
Min  
Typ  
Max  
Unit  
µA  
Input Leakage Current  
Output Leakage Current  
VIN=VSS to VCCQ  
CS=VIH, OE=VIH or WE=VIL, VIO=VSS to VCCQ  
-1  
-1  
-
-
1
1
ILO  
µA  
Cycle time=70ns, IIO=0mA2), 100% duty, CS=VIL, VIN=VIL or  
VIH  
Average Operating  
Current  
ICC2  
-
-
TBD  
mA  
Output Low Voltage  
Output High Voltage  
VOL  
VOH  
IOL=0.2mA  
IOH=-0.2mA  
-
1.4  
-
-
-
-
-
0.2  
-
V
V
< 40°C  
TBD  
TBD  
µA  
µA  
CS and ADV=VCCQ, Other inputs=0V or  
VCCQ (Toggle is not allowed)  
1)  
Standby Current(CMOS)  
ISB1  
< 85°C  
-
1. Internal TCSR (Temperature Compensated Self Refresh) is used to optimize Refresh cycle below 40°C.  
2. IIO=0mA; This parameter is specified with the outputs disabled to avoid external loading effects.  
Revision 0.0  
- 3 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
AC OPERATING CONDITIONS  
TEST CONDITIONS  
AC Output Load Circuit  
Vtt=0.5 x VCCQ  
(Test Load and Test Input/Output Reference)  
Input pulse level: 0.2 to VCCQ-0.2V  
Input rising and falling time: 3ns  
Input and output reference voltage: 0.5 x VCCQ  
Output load: CL=30pF  
50Ω  
Dout  
Z0=50  
Ω
30pF  
VCC:1.7V~1.95V  
TA: -40°C~85°C  
TIMING REQUIREMENTS  
READ Cycle Timing Requirements  
Parameter  
Symbol  
Min  
Max  
Unit  
Notes  
Address access time  
ADV access time  
tAA  
tAADV  
tAVS  
tAVH  
tBA  
70  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address setup to ADV HIGH  
Address hold from ADV HIGH  
LB/UB access time  
5
2
70  
8
LB/UB disable to DQ High-Z output  
CS HIGH between subsequent Async Operations  
Chip select access time  
tBHZ  
tCPH  
tCO  
1
5
7
70  
CS LOW to ADV HIGH  
tCVS  
tOE  
Output enable to valid output  
Output disable to DQ High-Z output  
Chip disable to DQ High-Z output  
Output ebable to Low-Z output  
READ cycle time  
20  
8
tOHZ  
tHZ  
1
1
2
8
tOLZ  
tRC  
5
80  
5
ADV pulse width LOW  
tVP  
ADV HIGH to OE LOW  
tADVOE  
tOEADV  
5
OE HIGH to ADV LOW  
8
WRITE Cycle Timing Requirements  
Parameter  
Symbol  
Min  
Max  
Unit  
Notes  
Address setup to ADV going HIGH  
Address hold from ADV HIGH  
Address valid to end of WRITE  
LB/UB select to end of WRITE  
CS HIGH between subsequent async operations  
CS LOW to ADV HIGH  
tAVS  
tAVH  
tAW  
5
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
70  
70  
5
tBW  
tCPH  
tCVS  
tCW  
1
2
3
7
Chip enable to end of WRITE  
Data HOLD from WRITE time  
Data WRITE setup time  
70  
0
tDH  
tDW  
20  
5
End WRITE to Low-Z output  
ADV pulse width  
tOW  
tVP  
2
3
5
ADV setup to end of WRITE  
WRITE pulse width  
tVS  
70  
55  
0
tWP  
WRITE recovery time  
tWR  
ADV HIGH to WE LOW  
tADVWE  
5
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.  
2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.  
3. WE LOW time must be limited to 2.5µs.  
Revision 0.0  
- 4 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
TIMING DIAGRAMS  
READ (CS controlled)  
tRC  
VIH  
ADV  
VIL  
tAADV  
tVP  
tVP  
VIH  
Valid Address  
tAVS  
A[20:16]  
Valid Address  
tAVS  
VIL  
tAVH  
tAVH  
tCPH  
tCVS  
tCVS  
VIH  
CS  
VIL  
tCO  
tHZ  
tBA  
VIH  
UB/ LB  
VIL  
tBHZ  
tOHZ  
tOE  
tADVOE  
tADVOE  
VIH  
OE  
VIL  
tOLZ  
tOLZ  
VIH  
WE  
VIL  
tAA  
VOH  
VOL  
VIH  
VOH  
VOL  
Valid Address  
Valid Address  
Valid output  
A/DQ[15:0]  
VIL  
tAVS  
tAVH  
Don’t Care  
tAVS  
tAVH  
Undefined  
1. Don’t care must be in VIL or VIH.  
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.  
3. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.  
4. tOE(max) is met only when OE becomes enabled after tAA(max).  
5. If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to  
sustain standby state for min. tRC at least once in every 2.5us.  
Revision 0.0  
- 5 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
READ (OE controlled)  
tRC  
VIH  
ADV  
VIL  
tAADV  
tOEADV  
tAADV  
tVP  
tVP  
VIH  
Valid Address  
tAVS  
A[20:16]  
Valid Address  
tAVS  
VIL  
tAVH  
tAVH  
tCVS  
VIH  
CS  
VIL  
tCO  
tBA  
VIH  
UB/ LB  
VIL  
tBHZ  
tOE  
tADVOE  
tADVOE  
VIH  
OE  
VIL  
tOLZ  
tOHZ  
tOLZ  
VIH  
WE  
VIL  
tAA  
VOH  
VOL  
VIH  
VOH  
VOL  
Valid Address  
Valid Address  
Valid output  
A/DQ[15:0]  
VIL  
tAVS  
tAVH  
tAVS  
tAVH  
Undefined  
Don’t Care  
1. Don’t care must be in VIL or VIH  
.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.  
3. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.  
4. tOE(max) is met only when OE becomes enabled after tAA(max).  
5. If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to  
sustain standby state for min. tRC at least once in every 2.5us.  
Revision 0.0  
- 6 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
READ Followed by WRITE (CS Controlled)  
tVP  
VIH  
ADV  
VIL  
tAADV  
tAVS  
tAVH  
tVP  
tCVP  
V
IH  
IL  
Valid Address  
tCW  
Valid Address  
tAVS  
A[20:16]  
V
tAVH  
tCPH  
tCVS  
VIH  
CS  
V
IL  
tCO  
tHZ  
tBW  
tBA  
VIH  
UB/ LB  
VIL  
tBHZ  
tOHZ  
tOE  
tADVOE  
V
IH  
OE  
V
IL  
tOLZ  
tWP  
tADVWE  
VIH  
WE  
VIL  
tAW  
tAA  
V
IH  
V
OH  
Valid Address  
Valid Address  
Data Valid  
Valid output  
A/DQ[15:0]  
V
IL  
V
OL  
tAVS  
tDW  
tDH  
tAVH  
tAVS  
tAVH  
Undefined  
Don’t Care  
Revision 0.0  
- 7 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
READ Followed by WRITE (OE, WE Controlled)  
tVP  
VIH  
ADV  
VIL  
tAADV  
tOEADV  
tAVS  
tAVH  
tVP  
V
IH  
IL  
Valid Address  
Valid Address  
tAVS  
A[20:16]  
V
tAVH  
tCVS  
V
IH  
CS  
V
IL  
tCO  
tBW  
tBA  
VIH  
UB/ LB  
VIL  
tBHZ  
tOHZ  
tOE  
tADVOE  
V
IH  
OE  
V
IL  
tOLZ  
tWP  
tADVWE  
VIH  
WE  
VIL  
tAW  
tAA  
V
IH  
V
OH  
Valid Address  
Valid Address  
Data Valid  
Valid output  
A/DQ[15:0]  
V
IL  
V
OL  
tAVS  
tDW  
tDH  
tAVH  
tAVS  
tAVH  
Undefined  
Don’t Care  
Revision 0.0  
- 8 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
READ Followed by WRITE at the Same Address  
VIH  
Valid Address  
A[20:16]  
VIL  
tAVS  
tAADV  
tVP  
VIH  
VIL  
ADV  
tBA  
tBW  
VIH  
VIL  
LB/UB  
tCVS  
tCO  
tBHZ  
tOHZ  
VIH  
VIL  
CS  
OE  
WE  
tADVOE  
tOE  
VIH  
VIL  
tOLZ  
tWP  
VIH  
VIL  
tAA  
tAVH  
tDW  
tAVS  
tDH  
VIH  
VIL  
VOH  
VOL  
A/DQ[15:0]  
IN/OUT  
VIH  
VIL  
Valid Address  
Valid Output  
Valid Input  
Undefined  
Don’t Care  
1. The end of the WRITE cycle is controlled by CS, LB/UB, or WE, whichever de-asserts first.  
2. Don’t care must be in VIL or VIH.  
Revision 0.0  
- 9 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
WRITE (CS Controlled)  
tVS  
tVP  
tVP  
VIH  
ADV  
VIL  
tCVS  
tCVP  
tAVS  
tAVS  
tAVH  
tAVH  
VIH  
A[20:16]  
VIL  
Valid Address  
Valid Address  
tCW  
VIH  
CS  
tCPH  
VIL  
tBW  
tWP  
VIH  
UB/LB  
VIL  
tADVWE  
tAVH  
tADVWE  
VIH  
WE  
VIL  
tAW  
tAVS  
VIH  
A/DQ[15:0]  
Valid Address  
tAVS  
Data Valid  
tDW  
tDH  
Valid Address  
VIL  
tAVH  
Don’t Care  
1. Don’t care must be in VIL or VIH.  
2. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for sin-  
gle byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or  
WE goes high or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.  
3. tCW is measured from the CS going low to the end of write.  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.  
Revision 0.0  
- 10 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
WRITE (WE, UB/LB Controlled)  
tVS  
tVP  
tVP  
VIH  
ADV  
tWR  
VIL  
tCVS  
tAVS  
tAVS  
tAVH  
tAVH  
VIH  
Valid Address  
Valid Address  
A[20:16]  
VIL  
tCW  
VIH  
VIL  
CS  
UB/LB  
WE  
tBW  
tWP  
VIH  
VIL  
tADVWE  
tADVWE  
VIH  
VIL  
tBHZ  
tAW  
tAVS  
tAVH  
VIH  
VIL  
A/DQ[15:0]  
Valid Address  
tAVS  
Data Valid  
Valid Address  
tDW  
tDH  
tAVH  
Don’t Care  
1. Don’t care must be in VIL or VIH.  
2. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for sin-  
gle byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or  
WE goes high or UB/LB goes high. The tWP is measured from the beginning of write to the end of write.  
3. tCW is measured from the CS going low to the end of write.  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.  
Revision 0.0  
- 11 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
WRITE Followed by READ (CS Controlled)  
tVS  
tVP  
tWR  
VIH  
ADV  
VIL  
tAADV  
tAVS  
tAVH  
tVP  
tCVS  
VIH  
A[20:16]  
Valid Address  
Valid Address  
VIL  
tAVS  
tCVS  
tAVH  
tCPH  
tCW  
tBW  
V
IH  
CS  
V
IL  
tCO  
tHZ  
tBA  
VIH  
UB/ LB  
VIL  
tOE  
tBHZ  
tOHZ  
tADVOE  
VIH  
OE  
VIL  
tOLZ  
tWP  
tADVWE  
V
IH  
WE  
V
IL  
tHZ  
tAW  
tAA  
V
IH  
V
OH  
A/DQ[15:0]  
Valid Address  
Valid Address  
Data Valid  
Valid output  
V
IL  
V
OL  
tAVS  
tDW  
tDH  
tAVH  
tAVS  
tAVH  
Undefined  
Don’t Care  
Revision 0.0  
- 12 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
WRITE Followed by READ (OE, WE Controlled)  
tVS  
tVP  
tWR  
VIH  
ADV  
VIL  
tAADV  
tAVS  
tAVH  
tVP  
tCVS  
VIH  
A[20:16]  
Valid Address  
tCW  
Valid Address  
VIL  
tAVS  
tCVS  
tAVH  
V
IH  
CS  
V
IL  
tCO  
tHZ  
tBW  
tBA  
VIH  
UB/ LB  
VIL  
tOE  
tBHZ  
tOHZ  
tADVOE  
VIH  
OE  
VIL  
tOLZ  
tWP  
tADVWE  
V
IH  
WE  
V
IL  
tAW  
tBHZ  
tAA  
V
IH  
V
OH  
A/DQ[15:0]  
Valid Address  
Valid Address  
Data Valid  
tDW  
tDH  
Valid output  
V
IL  
V
OL  
tAVS  
tAVH  
tAVS  
tAVH  
Undefined  
Don’t Care  
Revision 0.0  
- 13 -  
December 2006  
Preliminary  
K1S3216B9E  
UtRAM  
PACKAGE DIMENSION  
Unit: millimeters  
48 BALL FINE PITCH BGA(0.75mm ball pitch)  
Top View  
B
Bottom View  
B
B1  
6
5
4
3
2
1
A
B
#A1  
C
D
E
F
G
H
B/2  
Detail A  
A
Side View  
D
Y
C
Min  
Typ  
0.75  
6.00  
3.75  
7.00  
5.25  
0.45  
0.90  
0.55  
0.35  
-
Max  
-
A
B
-
Notes.  
5.90  
6.10  
-
1. Bump counts: 48(8 row x 6 column)  
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)  
3. All tolerence are ±0.050 unless  
specified beside figures.  
B1  
C
-
6.90  
7.10  
-
C1  
D
-
4. Typ : Typical  
0.40  
0.50  
1.00  
-
5. Y is coplanarity: 0.08(Max)  
E
-
E1  
E2  
Y
-
0.30  
-
0.40  
0.08  
Revision 0.0  
- 14 -  
December 2006  

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