K3N3C3000D-GC120 [SAMSUNG]
MASK ROM, 512KX8, 120ns, CMOS, PDSO32, 0.525 INCH, SOP-32;![K3N3C3000D-GC120](http://pdffile.icpdf.com/pdf2/p00236/img/icpdf/K3N3C3000D-G_1385441_icpdf.jpg)
型号: | K3N3C3000D-GC120 |
厂家: | ![]() |
描述: | MASK ROM, 512KX8, 120ns, CMOS, PDSO32, 0.525 INCH, SOP-32 有原始数据的样本ROM 光电二极管 |
文件: | 总3页 (文件大小:45K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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K3N3C3000D-D(G)C
CMOS MASK ROM
4M-Bit (512Kx8) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· 524,288x8 bit organization
· Access time : 80ns(Max.)
· Supply voltage : single +5V
· Current consumption
Operating : 50mA(Max.)
Standby : 50mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
The K3N3C3000D-D(G)C is a fully static mask programmable
ROM organized 524,288 x 8 bit. It is fabricated using silicon
gate CMOS process technology.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
· Package
The K3N3C3000D-DC is packaged in a 32-DIP and the
K3N3C3000D-GC in a 32-SOP.
-. K3N3C3000D-DC : 32-DIP-600
-. K3N3C3000D-GC : 32-SOP-525
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A18
X
MEMORY CELL
MATRIX
BUFFERS
AND
.
.
.
.
.
.
.
.
N.C
A16
A15
A12
A7
1
2
VCC
32
(524,288x8)
31 A18
DECODER
A17
30
3
A14
29
4
Y
A13
A8
5
28
27
26
25
24
SENSE AMP.
BUFFERS
BUFFERS
AND
A6
6
A5
A9
7
DIP
&
DECODER
A0
A4
8
A11
SOP
A3
9
OE
.
. .
A2
10
23 A10
21 CE
A1
11
12
13
14
CE
OE
Q0
Q7
CONTROL
LOGIC
A0
Q7
Q6
21
20
Q0
Q1
Q2
VSS
19 Q5
Q4
Q3
15
16
18
17
Pin Name
A0 - A18
Q0 - Q7
CE
Pin Function
Address Inputs
Data Outputs
Chip Enable
Output Enable
Power(+5V)
Ground
K3N3C3000D-D(G)C
OE
VCC
VSS
N.C
No Connection
K3N3C3000D-D(G)C
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
Symbol
VIN
Rating
Unit
-0.3 to +7.0
-10 to +85
-55 to +150
V
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Supply Voltage
Symbol
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Test Conditions
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
Unit
Operating Current
ICC
-
50
mA
Standby Current(TTL)
mA
mA
mA
mA
V
ISB1
ISB2
ILI
-
-
1
50
Standby Current(CMOS)
Input Leakage Current
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
V
VOH
VOL
IOH=-400mA
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
X
Mode
Data
High-Z
High-Z
Dout
Power
Standby
Active
H
Standby
Operating
Operating
H
L
L
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
10
Unit
COUT
CIN
-
-
pF
pF
VIN=0V
10
NOTE : Capacitance is periodically sampled and not 100% tested.
K3N3C3000D-D(G)C
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.6V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
0.8V and 2.0V
1 TTL Gate and CL=100pF
READ CYCLE
Item
K3N3C3D-D(G)C08
K3N3C3D-D(G)C10
K3N3C3D-D(G)C12
Symbol
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACE
tAA
80
100
120
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
80
80
40
100
100
50
120
120
60
tOE
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
20
ns
ns
Output Hold from Address Change
0
0
0
TIMING DIAGRAM
READ
ADD1
ADD2
ADD
tRC
tDF(Note)
tACE
CE
tOE
tAA
OE
tOH
DOUT
VALID DATA
VALID DATA
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or
VOL level.
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