K3N3V1000D-TE10 [SAMSUNG]
MASK ROM, 256KX16, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;型号: | K3N3V1000D-TE10 |
厂家: | SAMSUNG |
描述: | MASK ROM, 256KX16, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 有原始数据的样本ROM 输入元件 光电二极管 输出元件 内存集成电路 |
文件: | 总3页 (文件大小:48K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K3N3V(U)1000D-TC(E)
CMOS MASK ROM
4M-Bit (512Kx8 /256x16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
524,288 x 8(byte mode)
The K3N3V(U)1000D-TC(E) is a fully static mask programma-
ble ROM fabricated using silicon gate CMOS process technol-
ogy, and is organized either as 524,288 x 8 bit(byte mode) or as
262,144 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
262,144 x 16(word mode)
· Fast access time
3.3V Operation : 100ns(Max.)
3.0V Operation : 120ns(Max.)
· Supply voltage : single +3.0V/ single +3.3V
· Current consumption
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
Operating : 25mA(Max.)
Standby : 30mA(Max.)
It is suitable for use in program memory of microprocessor, and
data memory, character generator.The K3N3V(U)1000D-TC(E)
is packaged in a 44-TSOP2.
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
· Package
-. K3N3V(U)1000D-TC(E) : 44-TSOP2-400
FUNCTIONAL BLOCK DIAGRAM
PRODUCT INFORMATION
Operating
Temp
Vcc
Range
Speed
(ns)
Product
A17
X
MEMORY CELL
MATRIX
K3N3V(U)1000D-TC
K3N3V(U)1000D-TE
0°C~70°C
BUFFERS
AND
3.3V/3.0V
100/120
.
.
.
.
.
.
.
.
-20°C~85°C
(262,144x16/
524,288x8)
DECODER
Y
SENSE AMP.
BUFFERS
AND
DATA OUT
BUFFERS
PIN CONFIGURATION
DECODER
A0
A-1
N.C
N.C
N.C
N.C
A8
1
2
44
43
42
41
40
39
38
. . .
A17
A7
3
CE
4
A9
Q0/Q8
Q7/Q15
CONTROL
LOGIC
A6
A5
A10
A11
A12
5
OE
6
BHE
A4
7
A3
8
37 A13
A14
36
A2
9
A1
A15
35
10
11
12
13
14
15
16
Pin Name
A0 - A17
Pin Function
A16
34
A0
TSOP2
BHE
CE
VSS
OE
Q0
Q8
Q1
Q9
33
32
31
30
Address Inputs
Data Outputs
VSS
Q0 - Q14
Q15/A-1
Q7
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
29 Q14
28 Q6
17
18
BHE
CE
Word/Byte selection
Chip Enable
Output Enable
Power
Q13
Q5
27
26
Q2 19
Q10 20
25 Q12
OE
Q4
24
Q3
21
VCC
VSS
N.C
Q11
22
VCC
23
Ground
No Connection
K3N3V(U)1000D-TC(E)
K3N3V(U)1000D-TC(E)
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
-0.3 to +4.5
-10 to +85
-55 to +150
0 to +70
Unit
Remark
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
VIN
V
-
TBIAS
TSTG
°C
°C
°C
°C
-
-
K3N3V(U)1000D-TC
K3N3V(U)1000D-TE
Operating Temperature
TA
-20 to +85
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS)
Item
Supply Voltage
Symbol
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Max
25
Unit
mA
mA
mA
mA
mA
mA
V
VCC=3.3±0.3V
VCC=3.0±0.3V
-
Cycle=5MHz, all outputs open, CE=OE=VIL,
VIN=0.45V to 2.4V (AC Test Condition)
Operating Current
ICC
-
20
Standby Current(TTL)
ISB1
ISB2
ILI
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
-
-
500
30
Standby Current(CMOS)
Input Leakage Current
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.0
-0.3
2.4
-
VCC+0.3
0.6
V
IOH=-400mA
VOH
VOL
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
Standby
Active
H
X
X
X
Standby
Operating
Operating
L
H
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
10
Unit
pF
COUT
CIN
-
-
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3N3V(U)1000D-TC(E)
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.45V to 2.4V
10ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
1.5V
1 TTL Gate and CL=100pF
READ CYCLE
Item
VCC=3.3V±0.3V
VCC=3.0V±0.3V
Symbol
Unit
Min
100
Max
Min
120
Max
Read Cycle Time
tRC
tACE
tAA
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
100
100
50
120
120
60
tOE
Output or Chip Disable to
Output High-Z
tDF
20
20
ns
ns
Output Hold from Address Change
tOH
0
0
TIMING DIAGRAM
READ
ADD
ADD2
ADD1
A0~A17
A-1(*1)
tRC
tDF(*3)
tACE
CE/CE
OE/OE
tOE
tOE
tOH
DOUT
VALID DATA
VALID DATA
D0~D7
D8~D15(*2)
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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