K3N6V1000F-GC120 [SAMSUNG]

MASK ROM, 2MX16, 120ns, CMOS, PDSO44, 0.600 INCH, SOP-44;


型号：	K3N6V1000F-GC120
厂家：	SAMSUNG
描述：	MASK ROM, 2MX16, 120ns, CMOS, PDSO44, 0.600 INCH, SOP-44 有原始数据的样本ROM 光电二极管
文件：	总3页 (文件大小：48K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K3N6V(U)1000F-GC

CMOS MASK ROM

32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM

FEATURES

GENERAL DESCRIPTION

· Switchable organization

4,194,304x8(byte mode)

2,097,152x16(word mode)

· Fast access time

3.3V Operation : 100ns(Max.)@CL=50pF,

120ns(Max.)@CL=100pF

3.0V Operation : 120ns(Max.)@CL=100pF

· Supply voltage : single +3.0V/ single +3.3V

· Current consumption

The K3N6V(U)1000F-GC is a fully static mask programmable

ROM fabricated using silicon gate CMOS process technology,

and is organized either as 4,194,304 x 8 bit(byte mode) or as

2,097,152 x 16 bit(word mode) depending on BHE voltage

level.(See mode selection table)

This device operates with 3.0V or 3.3V power supply, and all

inputs and outputs are TTL compatible.

Because of its asynchronous operation, it requires no external

clock assuring extremely easy operation.

Operating : 40mA(Max.)

It is suitable for use in program memory of microprocessor, and

data memory, character generator.

Standby : 30mA(Max.)

· Fully static operation

· All inputs and outputs TTL compatible

· Three state outputs

The K3N6V(U)1000F-GC is packaged in a 44-SOP.

· Package

-. K3N6V(U)1000F-GC : 44-SOP-600

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

A20

MEMORY CELL

MATRIX

(2,097,152x16/

4,194,304x8)

BUFFERS

AND

DECODER

A20

N.C

A18

A17

A19

A10

A11

SENSE AMP.

BUFFERS

38 A12

37 A13

BUFFERS

AND

A14

DECODER

A15

A16

SOP

A-1

BHE

VSS

Q15/A-1

Q0/Q8

Q7/Q15

CONTROL

LOGIC

29 Q14

Q13

BHE

Q2 19

Q10 20

25 Q12

Pin Name

A0 - A20

Pin Function

Address Inputs

Data Outputs

Q11

VCC

Q0 - Q14

Output 15(Word mode)/

LSB Address(Byte mode)

K3N6V(U)1000F-GC

Q15 /A-1

BHE

Word/Byte selection

Chip Enable

Output Enable

Power

VCC

VSS

N.C

Ground

No Connection

K3N6V(U)1000F-GC

CMOS MASK ROM

ABSOLUTE MAXIMUM RATINGS

Item

Voltage on Any Pin Relative to VSS

Temperature Under Bias

Storage Temperature

Symbol

VIN

Rating

Unit

-0.3 to +4.5

-10 to +85

-55 to +150

TBIAS

TStg

°C

NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the

conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)

Item

Symbol

Min

2.7/3.0

Typ

3.0/3.3

Max

3.3/3.6

Unit

Supply Voltage

VCC

Supply Voltage

VSS

DC CHARACTERISTICS

Parameter

Symbol

Test Conditions

Min

Max

Unit

VCC=3.3V±0.3V

VCC=3.0V±0.3V

Cycle=5MHZ, all outputs open, CE=OE=VIL,

VIN=0.45V to 2.4V (AC Test Condition)

Operating Current

ICC

Standby Current(TTL)

ISB1

ISB2

ILI

CE=VIH, all outputs open

CE=VCC, all outputs open

VIN=0 to VCC

500

Standby Current(CMOS)

Input Leakage Current

Output Leakage Current

Input High Voltage, All Inputs

Input Low Voltage, All Inputs

Output High Voltage Level

Output Low Voltage Level

ILO

VOUT=0 to VCC

VIH

VIL

2.0

-0.3

2.4

VCC+0.3

0.6

VOH

VOL

IOH=-400mA

IOL=2.1mA

0.4

NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.

Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

MODE SELECTION

BHE

Q15/A-1

Mode

Data

High-Z

Power

Standby

Operating

Standby

Active

High-Z

Output

Q0~Q15 : Dout

Active

Q0~Q7 : Dout

Q8~Q14 : Hi-Z

Input

Operating

Active

CAPACITANCE(TA=25°C, f=1.0MHz)

Item

Output Capacitance

Input Capacitance

Symbol

Test Conditions

VOUT=0V

Min

Max

Unit

COUT

CIN

VIN=0V

NOTE : Capacitance is periodically sampled and not 100% tested.

K3N6V(U)1000F-GC

CMOS MASK ROM

AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)

TEST CONDITIONS

Item

Value

Input Pulse Levels

0.45V to 2.4V

Input Rise and Fall Times

Input and Output timing Levels

Output Loads

10ns

1.5V

1 TTL Gate and CL=50pF or 100pF

READ CYCLE

K3N6V1000F-GC10

(CL=50pF)

K3N6V1000F-GC12

(CL=100pF)

K3N6U1000F-GC12

(CL=100pF)

Item

Symbol

Unit

Min

Max

Min

Max

Min

120

Max

Read Cycle Time

tRC

tACE

tAA

100

120

Chip Enable Access Time

Address Access Time

Output Enable Access Time

100

120

tOE

Output or Chip Disable to

Output High-Z

tDF

tOH

Output Hold from Address Change

TIMING DIAGRAM

READ

ADD

A0~A20

A-1(*1)

ADD1

ADD2

tRC

tDF(*3)

tACE

tOE

tAA

tOH

DOUT

D0~D7

VALID DATA

D8~D15(*2)

NOTES :

*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)

*2. Word Mode only.(BHE = VIH)

*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.

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