K3N7C1000B-GC100 [SAMSUNG]

MASK ROM, 4MX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44;


型号：	K3N7C1000B-GC100
厂家：	SAMSUNG
描述：	MASK ROM, 4MX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44 有原始数据的样本ROM 光电二极管
文件：	总3页 (文件大小：48K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K3N7C1000B-GC

CMOS MASK ROM

64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM

FEATURES

GENERAL DESCRIPTION

· Switchable organization

8,388,608 x 8(byte mode)

4,194,304 x 16(word mode)

· Fast access time :

100ns(Max.) : CL=50pF

120ns(Max.) : CL=100pF

· Supply voltage : single +5V

· Current consumption

Operating : 70mA(Max.)

Standby : 50mA(Max.)

· Fully static operation

· All inputs and outputs TTL compatible

· Three state outputs

The K3N7C1000B-GC is a fully static mask programmable

ROM fabricated using silicon gate CMOS process technology,

and is organized either as 8,388,608 x 8 bit(byte mode) or as

4,194,304 x 16 bit(word mode) depending on BHE voltage

level.(See mode selection table)

This device operates with a 5V single power supply, and all

inputs and outputs are TTL compatible.

Because of its asynchronous operation, it requires no external

clock assuring extremely easy operation.

It is suitable for use in program memory of microprocessor, and

data memory, character generator.

The K3N7C1000B-GC is packaged in a 44-SOP.

· Package

-. K3N7C1000B-GC : 44-SOP-600

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

A21

MEMORY CELL

MATRIX

(4,194,304x16/

8,388,608x8)

A20

A19

A21

A18

BUFFERS

AND

DECODER

A17

A10

A11

38 A12

37 A13

SENSE AMP.

BUFFERS

AND

DECODER

DATA OUT

BUFFERS

A14

A15

A16

SOP

A-1

CE 12

BHE

VSS

32 VSS

OE 14

Q15/A-1

Q0/Q8

Q7/Q15

CONTROL

LOGIC

Q14

BHE

Q13

Q10 20

Q12

Pin Name

A0 - A21

Pin Function

Address Inputs

Data Outputs

Q11

VCC

Q0 - Q14

Q15 /A-1

Output 15(Word mode)/

LSB Address(Byte mode)

K3N7C1000B-GC

BHE

Word/Byte selection

Chip Enable

Output Enable

Power ( +5V)

Ground

VCC

VSS

K3N7C1000B-GC

CMOS MASK ROM

ABSOLUTE MAXIMUM RATINGS

Item

Symbol

VIN

Rating

Unit

Voltage on Any Pin Relative to VSS

Temperature Under Bias

Storage Temperature

-0.3 to +7.0

-10 to +85

-55 to +150

TBIAS

TStg

°C

NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-

ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)

Item

Min

4.5

Symbol

Typ

5.0

Max

5.5

Unit

Supply Voltage

VCC

Supply Voltage

VSS

DC CHARACTERISTICS

Parameter

Symbol

Test Conditions

Cycle=5MHz, all outputs open

CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)

CE=VIH, all outputs open

CE=VCC, all outputs open

VIN=0 to VCC

Min

Max

Unit

Operating Current

ICC

Standby Current(TTL)

ISB1

ISB2

ILI

Standby Current(CMOS)

Input Leakage Current

Output Leakage Current

Input High Voltage, All Inputs

Input Low Voltage, All Inputs

Output High Voltage Level

Output Low Voltage Level

ILO

VOUT=0 to VCC

VIH

VIL

2.2

-0.3

2.4

VCC+0.3

0.8

IOH=-400mA

VOH

VOL

IOL=2.1mA

0.4

NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.

Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

MODE SELECTION

BHE

Q15/A-1

Mode

Data

High-Z

Power

Standby

Operating

Standby

Active

High-Z

Output

Q0~Q15 : Dout

Active

Q0~Q7 : Dout

Q8~Q14 : Hi-Z

Input

Operating

Active

CAPACITANCE(TA=25°C, f=1.0MHz)

Item

Output Capacitance

Input Capacitance

Symbol

Test Conditions

VOUT=0V

Min

Max

Unit

COUT

CIN

VIN=0V

NOTE : Capacitance is periodically sampled and not 100% tested.

K3N7C1000B-GC

CMOS MASK ROM

AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)

TEST CONDITIONS

Item

Value

0.6V to 2.4V

Input Pulse Levels

Input Rise and Fall Times

Input and Output timing Levels

Output Loads

10ns

0.8V and 2.0V

1 TTL Gate and CL=50pF or 100pF

READ CYCLE

K3N7C1000B-GC10

(CL=50pF)

K3N7C1000B-GC12

(CL=100pF)

K3N7C1000B-GC15

(CL=100pF)

Item

Symbol

Unit

Min

Max

Min

Max

Min

150

Max

Read Cycle Time

tRC

tACE

tAA

100

120

Chip Enable Access Time

Address Access Time

Output Enable Access Time

100

120

150

tOE

Output or Chip Disable to

Output High-Z

tDF

tOH

Output Hold from Address Change

TIMING DIAGRAM

READ

ADD

ADD1

ADD2

A0~A21

A-1(*1)

tRC

tDF(*3)

tACE

tOE

tAA

tOH

DOUT

D0~D7

VALID DATA

D8~D15(*2)

NOTES :

*1. Byte Mode only. A-1 is Least Significant Bit Address. (BHE = VIL)

*2. Word Mode only.(BHE = VIH)

*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.

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