K3N7V1000B-GC10 [SAMSUNG]
MASK ROM, 4MX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44;型号: | K3N7V1000B-GC10 |
厂家: | SAMSUNG |
描述: | MASK ROM, 4MX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44 有原始数据的样本ROM 光电二极管 内存集成电路 |
文件: | 总3页 (文件大小:47K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K3N7V(U)1000B-GC
CMOS MASK ROM
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
The K3N7V(U)1000B-GC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 8,388,608 x 8 bit(byte mode) or as
4,194,304 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
8,388,608 x 8(byte mode)
4,194,304 x 16(word mode)
· Fast access time
3.3V Operation : 100ns(Max.)@CL=50pF,
120ns(Max.)@CL=100pF
3.0V Operation : 120ns(Max.)@CL=100pF
· Supply voltage : single +3.3V/ single +3.0V
· Current consumption
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
Operating : 40mA(Max.)
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
Standby : 50mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
The K3N7V(U)1000B-GC is packaged in a 44-SOP.
· Package
-. K3N7V(U)1000B-GC : 44-SOP-600
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A21
X
MEMORY CELL
MATRIX
(4,194,304x16/
8,388,608x8)
A21
A18
A20
1
2
44
43
42
41
40
39
BUFFERS
AND
DECODER
.
.
.
.
.
.
.
.
A19
A8
A17
A7
3
4
A9
A6
A5
A10
A11
5
6
Y
A4
7
38 A12
37 A13
SENSE AMP.
BUFFERS
BUFFERS
AND
DECODER
A3
8
A14
36
A2
9
A0
A1
A15
35
10
11
12
13
14
15
16
17
18
SOP
A16
34
A0
A-1
BHE
CE
VSS
OE
Q0
Q8
Q1
Q9
33
32
31
30
.
.
.
VSS
Q15/A-1
Q7
CE
Q0/Q8
Q7/Q15
CONTROL
LOGIC
29 Q14
28 Q6
OE
BHE
Q13
Q5
27
26
Q2 19
Q10 20
25 Q12
Q4
24
Q3
21
22
Pin Name
A0 - A21
Pin Function
Address Inputs
Data Outputs
Q11
VCC
23
Q0 - Q14
K3N7V(U)1000B-GC
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
BHE
CE
Word/Byte selection
Chip Enable
Output Enable
Power
OE
VCC
VSS
Ground
K3N7V(U)1000B-GC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
Symbol
VIN
Rating
Unit
-0.3 to +4.5
-10 to +85
-55 to +150
V
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Supply Voltage
Symbol
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Max
Unit
mA
mA
mA
mA
mA
mA
V
VCC=3.3V±0.3V
VCC=3.0V±0.3V
-
40
35
Cycle=5MHZ, all outputs open, CE=OE=VIL,
VIN=0.45V to 2.4V (AC Test Condition)
Operating Current
ICC
Standby Current(TTL)
ISB1
ISB2
ILI
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
500
50
Standby Current(CMOS)
Input Leakage Current
-
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
10
VIH
VIL
2.0
-0.3
2.4
-
VCC+0.3
0.6
V
VOH
VOL
IOH=-400mA
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
H
L
X
H
X
X
Standby
Operating
Operating
Standby
Active
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3N7V(U)1000B-GC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
1.5V
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
K3N7V1000B-GC10
(CL=50pF)
K3N7V1000B-GC12
(CL=100pF)
K3N7U1000B-GC12
(CL=100pF)
Item
Symbol
Unit
Min
Max
Min
Max
Min
120
Max
Read Cycle Time
tRC
tACE
tAA
100
120
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
100
100
50
120
120
60
120
120
60
tOE
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
20
ns
ns
Output Hold from Address Change
0
0
0
TIMING DIAGRAM
READ
ADD
A0~A21
A-1(*1)
ADD1
ADD2
tRC
tDF(*3)
tACE
CE
OE
tOE
tAA
tOH
DOUT
D0~D7
VALID DATA
VALID DATA
D8~D15(*2)
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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