K3P4C1000D-TC120 [SAMSUNG]
MASK ROM, 512KX16, 120ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;型号: | K3P4C1000D-TC120 |
厂家: | SAMSUNG |
描述: | MASK ROM, 512KX16, 120ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 有原始数据的样本ROM 光电二极管 |
文件: | 总4页 (文件大小:63K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K3P4C1000D-TC(E)
CMOS MASK ROM
8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
1,048,576 x 8(byte mode)
524,288 x 16(word mode)
· Fast access time
The K3P4C1000D-TC(E) is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 1,048,576 x 8 bit(byte mode) or as
524,288 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows 4 words (or 8bytes) of data to read fast in the same
page, CE and A2 ~ A18 should not be changed.
Random Access : 100ns(Max.)
Page Access
: 30ns(Max.)
· 4 Words / 8 bytes page access
· Supply voltage : single +5V
· Current consumption
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Operating : 80mA(Max.)
Standby : 50mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
· Package
-. K3P4C1000D-TC(E) : 44-TSOP2-400
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P4C1000D-TC(E) is packaged in a 44-TSOP2.
FUNCTIONAL BLOCK DIAGRAM
PRODUCT INFORMATION
Operating
Temp Range
Vcc Range
(Typical)
Speed
(ns)
Product
A18
X
MEMORY CELL
MATRIX
K3P4C1000D-TC
K3P4C1000D-TE
0°C~70°C
BUFFERS
AND
.
.
.
.
.
.
.
.
5.0V
100
(524,288x16/
1,048,576x8)
-20°C~85°C
DECODER
PIN CONFIGURATION
Y
SENSE AMP.
BUFFERS
AND
DATA OUT
BUFFERS
DECODER
A2
N.C
A18
A17
A7
1
2
44 N.C
N.C
A8
43
42
41
40
39
38
37
36
35
34
33
32
31
30
3
A0~A1
A-1
. . .
4
A9
A6
A10
A11
A12
5
CE
A5
6
Q0/Q8
Q7/Q15
CONTROL
LOGIC
OE
A4
7
A3
8
A13
A14
BHE
A2
9
A1
A15
10
11
12
13
14
15
16
17
18
Pin Name
A0 - A1
Pin Function
A0
A16
TSOP2
BHE
VSS
CE
VSS
OE
Q0
Page Address Inputs
Address Inputs
Data Outputs
A2- A18
Q15/A-1
Q7
Q0 - Q14
Output 15(Word mode)/
LSB Address(Byte mode)
Q8
29 Q14
28 Q6
Q15 /A-1
Q1
BHE
CE
Word/Byte selection
Chip Enable
Q9
Q13
Q5
27
26
25
24
23
Q2 19
Q10 20
Q12
Q4
OE
Output Enable
Power ( +5V)
Ground
Q3
21
22
VCC
VSS
N.C
Q11
VCC
No Connection
K3P4C1000D-TC(E)
K3P4C1000D-TC(E)
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
-0.3 to +7.0
-10 to +85
-55 to +150
0 to +70
Unit
V
Remark
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-
TBIAS
TSTG
°C
°C
°C
°C
-
-
K3P4C1000D-TC
K3P4C1000D-TE
Operating Temperature
TA
-20 to +85
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Min
4.5
0
Symbol
VCC
Typ
5.0
0
Max
5.5
0
Unit
V
Supply Voltage
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
Min
Max
Unit
Operating Current
ICC
-
80
mA
Standby Current(TTL)
ISB1
ISB2
ILI
-
-
1
50
mA
mA
mA
mA
V
Standby Current(CMOS)
Input Leakage Current
-
10
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
-
V
VOH
VOL
IOH=-400mA
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
H
L
X
H
X
X
Standby
Operating
Operating
Standby
Active
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P4C1000D-TC(E)
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.6V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
0.8V and 2.0V
1 TTL Gate and CL=100pF
READ CYCLE
K3P4C1000D-
TC(E)10
K3P4C1000D-
TC(E)12
K3P4C1000D-
TC(E)15
Item
Symbol
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACE
tAA
100
120
150
ns
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
100
100
30
120
120
50
150
150
70
Page Address Access Time
Output Enable Access Time
tPA
tOE
30
50
70
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
NOTE : Page Address is determined as below.
Word mode (BHE = VIH) : A0, A1
Byte mode (BHE = VIL) : A-1, A0, A1
K3P4C1000D-TC(E)
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
ADD2
ADD1
A0~A18
A-1(*1)
tRC
tDF(*3)
tACE
CE
tOE
tAA
OE
tOH
DOUT
VALID DATA
D0~D7
VALID DATA
D8~D15(*2)
PAGE READ
CE
tDF(*3)
OE
ADD
A2~A18
ADD
A0,A1
A-1(*1)
1 st
2 nd
3 rd
tAA
tPA
DOUT
VALID DATA
VALID DATA
VALID DATA
VALID DATA
D0~D7
D8~D15(*2)
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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