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K3P4C1000E-GC100 [SAMSUNG]

MASK ROM, 512KX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44;
K3P4C1000E-GC100
型号： K3P4C1000E-GC100
厂家： SAMSUNG    SAMSUNG
描述：

MASK ROM, 512KX16, 100ns, CMOS, PDSO44, 0.600 INCH, SOP-44

有原始数据的样本ROM 光电二极管 内存集成电路
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K3P4C1000E-D(G)C  
CMOS MASK ROM  
8M-Bit (1Mx8 / 512Kx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
1,048,576 x 8(byte mode)  
524,288 x 16(word mode)  
· Fast access time  
The K3P4C1000E-D(G)C is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 1,048,576 x 8(byte mode) or as  
524,288  
x 16(word mode) depending on BHE voltage  
Random Access : 100ns(Max.)@CL=50pF,  
120ns(Max.)@CL=100pF  
level.(See mode selection table)  
This device includes page read mode function, page read mode  
allows 4 words (or 8 bytes) of data to read fast in the same  
page, CE and A2 ~ A18 should not be changed.  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Page Access  
: 30ns(Max.)@CL=50pF  
40ns(Max.)@CL=100pF  
4 Words / 8 Bytes page access  
· Supply voltage : single +5V  
· Current consumption  
Operating : 80mA(Max.)  
Standby : 50mA(Max.)  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The K3P4C1000E-DC is packaged in  
K3P4C1000E-GC in a 44-SOP.  
a
42-DIP and the  
· Package  
-. K3P4C1000E-DC : 42-DIP-600  
-. K3P4C1000E-GC : 44-SOP-600  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A18  
X
MEMORY CELL  
MATRIX  
(524,288x16/  
1,048,576x8)  
BUFFERS  
AND  
DECODER  
.
.
.
.
.
.
.
.
A18  
1
2
42N.C  
41 A8  
40 A9  
39 A10  
38 A11  
N.C  
A18  
A17  
A7  
N.C  
44  
1
2
A17  
A7  
43 N.C  
3
A8  
42  
3
4
A6  
A5  
4
41 A9  
5
A6  
5
40 A10  
39 A11  
38 A12  
37 A13  
Y
SENSE AMP.  
DATA OUT  
BUFFERS  
6
A4  
A3  
37  
36  
A12  
A13  
A5  
6
BUFFERS  
AND  
DECODER  
7
A4  
7
8
A2  
A1  
35 A14  
34 A15  
33 A16  
32 BHE  
A3  
8
A2  
9
A14  
A15  
A16  
A2  
A1  
9
36  
35  
34  
33  
10  
11  
12  
13  
14  
15  
16  
A0  
CE  
VSS  
OE  
Q0  
10  
11  
A0~A1  
A-1  
. . .  
A0  
DIP  
31  
VSS  
SOP  
CE 12  
BHE  
30  
Q15/A-1  
CE  
VSS  
13  
32 VSS  
29 Q7  
28  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
OE 14  
Q0 15  
31 Q15/A-1  
OE  
Q8  
Q14  
27 Q6  
Q7  
30  
Q1  
BHE  
Q8  
Q1  
Q9  
16  
17  
18  
29 Q14  
28 Q6  
27 Q13  
26 Q5  
25 Q12  
24 Q4  
23 VCC  
Q9 17  
26  
25  
24  
Q13  
Q5  
18  
Q2  
19  
20  
21  
Q10  
Q3  
Pin Name  
A0 - A1  
Pin Function  
Page Address Inputs  
Q12  
Q2 19  
Q10 20  
Q3 21  
23 Q4  
22  
Q11  
VCC  
A2 - A18  
Q0 - Q14  
Address Inputs  
Q11  
22  
Data Outputs  
K3P4C1000E-DC  
Output 15(Word mode)/  
Q15 /A-1  
LSB Address(Byte mode)  
Word/Byte selection  
Chip Enable  
K3P4C1000E-GC  
BHE  
CE  
OE  
Output Enable  
Power ( +5V)  
Ground  
VCC  
VSS  
N.C  
No Connection  
K3P4C1000E-D(G)C  
CMOS MASK ROM  
ABSOLUTE MAXIMUM RATINGS  
Item  
Voltage on Any Pin Relative to VSS  
Temperature Under Bias  
Storage Temperature  
Symbol  
VIN  
Rating  
Unit  
-0.3 to +7.0  
-10 to +85  
-55 to +150  
V
TBIAS  
TStg  
°C  
°C  
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-  
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may  
affect device reliability.  
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)  
Item  
Symbol  
Min  
4.5  
0
Typ  
5.0  
0
Max  
5.5  
0
Unit  
V
Supply Voltage  
VCC  
Supply Voltage  
VSS  
V
DC CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Cycle=5MHz, all outputs open  
CE=OE=VIL, VIN=0V to 3V (AC Test Condition)  
CE=VIH, all outputs open  
CE=VCC, all outputs open  
VIN=0 to VCC  
Min  
Max  
Unit  
Operating Current  
ICC  
-
80  
mA  
Standby Current(TTL)  
ISB1  
ISB2  
ILI  
-
-
1
mA  
mA  
mA  
mA  
V
Standby Current(CMOS)  
Input Leakage Current  
50  
10  
10  
-
Output Leakage Current  
Input High Voltage, All Inputs  
Input Low Voltage, All Inputs  
Output High Voltage Level  
Output Low Voltage Level  
ILO  
VOUT=0 to VCC  
-
VIH  
VIL  
2.2  
-0.3  
2.4  
-
VCC+0.3  
0.8  
-
V
VOH  
VOL  
IOH = -400mA  
V
IOL = 2.1mA  
0.4  
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.  
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.  
MODE SELECTION  
CE  
OE  
BHE  
X
Q15/A-1  
Mode  
Data  
High-Z  
Power  
H
L
X
H
X
X
Standby  
Operating  
Operating  
Standby  
Active  
Active  
X
High-Z  
H
Output  
Q0~Q15 : Dout  
L
L
Q0~Q7 : Dout  
Q8~Q14 : Hi-Z  
L
Input  
Operating  
Active  
CAPACITANCE(TA=25°C, f=1.0MHz)  
Item  
Output Capacitance  
Input Capacitance  
Symbol  
Test Conditions  
VOUT=0V  
Min  
Max  
12  
Unit  
pF  
COUT  
CIN  
-
-
VIN=0V  
12  
pF  
NOTE : Capacitance is periodically sampled and not 100% tested.  
K3P4C1000E-D(G)C  
CMOS MASK ROM  
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)  
TEST CONDITIONS  
Item  
Value  
0V to 3V  
Input Pulse Levels  
Input Rise and Fall Times  
Input and Output timing Levels  
Output Loads  
10ns  
0.8V and 2.0V  
1 TTL Gate and CL=50pF or 100pF  
READ CYCLE  
K3P4C1000E-D(G)C10 K3P4C1000E-D(G)C12 K3P4C1000E-D(G)C15  
(CL=50pF)  
(CL=100pF)  
(CL=100pF)  
Item  
Symbol  
Unit  
Min  
100  
Max  
Min  
120  
Max  
Min  
150  
Max  
Read Cycle Time  
tRC  
tACE  
tAA  
ns  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
Address Access Time  
Page Address Access Time  
Output Enable Access Time  
100  
100  
30  
120  
120  
40  
150  
150  
50  
tPA  
tOE  
30  
40  
50  
Output or Chip Disable to  
Output High-Z  
tDF  
tOH  
20  
20  
30  
ns  
ns  
Output Hold from Address Change  
0
0
0
NOTE : Page Address is determined as below.  
Word mode(BHE=VIH) ; A0, A1  
Byte mode(BHE=VIL) ; A-1, A0, A1  
K3P4C1000E-D(G)C  
CMOS MASK ROM  
TIMING DIAGRAM  
READ  
ADD  
ADD1  
ADD2  
A0~A18  
A-1(*1)  
tRC  
tDF(*3)  
tACE  
CE  
OE  
tOE  
tAA  
tOH  
DOUT  
D0~D7  
VALID DATA  
VALID DATA  
D8~D15(*2)  
PAGE READ  
CE  
tDF(*3)  
OE  
ADD  
A2~A18  
ADD  
A0,A1  
3 rd  
1 st  
2 nd  
A-1(*1)  
tAA  
tPA  
DOUT  
D0~D7  
VALID DATA  
VALID DATA  
VALID DATA  
VALID DATA  
D8~D15(*2)  
NOTES :  
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)  
*2. Word Mode only.(BHE = VIH)  
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VO L level.  

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