K3P5C2000D-SC15 [SAMSUNG]
MASK ROM, 512KX32, 150ns, CMOS, PDSO70, 0.500 INCH, SSOP-70;型号: | K3P5C2000D-SC15 |
厂家: | SAMSUNG |
描述: | MASK ROM, 512KX32, 150ns, CMOS, PDSO70, 0.500 INCH, SSOP-70 有原始数据的样本ROM 光电二极管 内存集成电路 |
文件: | 总4页 (文件大小:63K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K3P5C2000D-SC
CMOS MASK ROM
16M-Bit (1Mx16 /512Kx32) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
1,048,576 x 16(word mode)
524,288 x 32(double word mode)
· Fast access time
The K3P5C2000D-SC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 1,048,576 x 16 bit(word mode) or is
524,288 x 32 bit(double word mode) depending on WORD volt-
age level.(See mode selection table)
This device includes page read mode function, page read mode
allows 4 double words (or 8 words) of data to read fast in the
same page, CE and A2 ~ A18 should not be changed.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Random Access : 100ns(Max.)
Page Access
: 30ns(Max.)
4 double Words / 8 Words page access
· Supply voltage : single +5V
· Current consumption
Operating : 150mA(Max.)
Standby : 50mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
· Package
-. K3P5C2000D-SC : 70-SSOP-500
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator. The K3P5C2000D-SC is
packaged in a 70-SSOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A0
A1
1
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
N.C
N.C
N.C
WORD
OE
A18
X
MEMORY CELL
MATRIX
(524,288x32/
1,048,576x16)
2
BUFFERS
AND
DECODER
.
.
.
.
.
.
.
.
A2
3
A3
4
A4
5
A5
6
CE
VCC
Q0
7
VSS
Q31/A-1
Q15
Q30
Q14
VSS
VCC
Q29
Q13
Q28
Q12
Q27
Q11
Q26
Q10
VSS
VCC
Q25
Q9
8
Y
SENSE AMP.
Q16
Q1
9
BUFFERS
AND
DECODER
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DATA OUT
BUFFERS
Q17
VSS
VCC
Q2
A2
Q18
Q3
A0,A1
A-1
.
.
.
Q19
Q4
CE
SSOP
Q0/Q16
Q15/Q31
CONTROL
LOGIC
Q20
Q5
OE
Q21
VSS
VCC
Q6
WORD
Pin Name
A0 - A1
Pin Function
Page Address Inputs
Q22
Q7
Q24
Q8
Q23
VSS
A6
A2 - A18
Q0 - Q30
Address Inputs
Data Outputs
VCC
N.C
A18
A7
Output 31(Double word mode)/
LSB Address(Word mode)
A8
A17
Q31 /A-1
A9
A16
A10
A11
A12
A15
A14
WORD
CE
Double word/Word mode selection
Chip Enable
A13
OE
Output Enable
K3P5C2000D-SC
VCC
VSS
N.C
Power (+5V)
Ground
No Connection
K3P5C2000D-SC
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
Symbol
VIN
Rating
Unit
-0.3 to +7.0
-10 to +85
-55 to +150
V
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Supply Voltage
Symbol
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition)
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
Min
Max
Unit
Operating Current
ICC
-
150
mA
Standby Current(TTL)
ISB1
ISB2
ILI
-
-
1
50
mA
Standby Current(CMOS)
Input Leakage Current
mA
-
10
mA
mA
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
V
V
V
V
VOH
VOL
IOH=-400mA
-
IOL=2.1mA
0.4
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
WORD
Q31/A-1
Mode
Data
High-Z
Power
H
L
X
H
X
X
H
X
X
Standby
Operating
Operating
Standby
Active
High-Z
Output
Q0~Q31:Dout
Active
L
L
Q0~Q15 : Dout
Q16~Q30 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P5C2000D-SC
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to 70°C, VCC=5V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.6V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
0.8V and 2.0V
1 TTL Gate and CL=100pF
READ CYCLE
K3P5C2000D-SC10
K3P5C2000D-SC12
K3P5C2000D-SC15
Item
Symbol
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACE
tAA
100
120
150
ns
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
100
100
30
120
120
50
150
150
70
tPA
Page Address Access Time
Output Enable Access Time
tOE
30
50
70
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
NOTE : Page Address is determined as below.
Double Word mode (WORD=VIH) : A0, A1
Word mode (WORD=VIL) : A-1, A0, A1
K3P5C2000D-SC
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
ADD1
ADD2
A0~A18
A-1(*1)
tRC
tDF(*3)
tACE
CE
OE
tOE
tAA
tOH
DOUT
D0~D15
D16~D31(*2)
VALID DATA
VALID DATA
PAGE READ
CE
OE
tDF(*3)
ADD
A2~A18
ADD
A0,A1
A-1(*1)
1 st
2 nd
3 rd
tAA
tPA
DOUT
D0~D15
D16~D31(*2)
VALID DATA
VALID DATA
VALID DATA
VALID DATA
NOTES :
*1.Word Mode only. A-1 is Least Significant Bit Address.(WORD = VIL)
*2.Double Word Mode only.(WORD = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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