K4A4G085WE-BCRC_技术文档

Rev. 1.6, Jan. 2017

K4A4G045WE

K4A4G085WE

4Gb E-die DDR4 SDRAM

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

1.2V

datasheet

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- 1 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

Revision History

Revision No.

History

Draft Date

Remark

Editor

J.Y.Lee

1.0

1.01

1.1

- First SPEC release

- Correction of typo

4th Jun, 2015

11th Aug, 2015

27th Oct, 2015

11th Apr, 2016

22th Jun, 2016

3rd Aug, 2016

22th Aug, 2016

4th Nov, 2016

12th Jan, 2017

-

- Added values on page 11 [Table 5]

- Addition of Industrial temp

1.2

1.3

- Addition of DDR4-2666

1.4

- Addition of IDD Current specification of 2666Mbps

- Addition of DDR4-2666 (x4)

1.5

1.51

1.6

- Change of Package pinout on page 5

- Update referring to JEDEC DDR4 datasheet rev.79-4B

- 2 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1. Ordering Information

[ Table 1 ] Samsung 4Gb DDR4 E-die ordering information table

2

Organization

1Gx4

DDR4-2133 (15-15-15)

K4A4G045WE-BCPB

K4A4G085WE-BCPB

K4A4G085WE-BIPB

Package

78 FBGA

DDR4-2400 (17-17-17)

K4A4G045WE-BCRC

K4A4G085WE-BCRC

K4A4G085WE-BIRC

DDR4-2666 (19-19-19)

K4A4G045WE-BCTD

K4A4G085WE-BCTD

K4A4G085WE-BITD

512Mx8

NOTE :

1. Speed bin is in order of CL-tRCD-tRP.

2. Backward compatible to lower frequency

3. 13th digit stands for below.

"C" : Commercial temp/Normal power

"I" : Industrial temp/Normal power

2. Key Features

[ Table 2 ] 4Gb DDR4 E-die Speed bins

DDR4-1600

DDR4-1866

13-13-13

1.071

13

DDR4-2133

15-15-15

0.938

15

DDR4-2400

DDR4-2666

19-19-19

0.75

Speed

Unit

11-11-11

17-17-17

0.833

17

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

1.25

11

ns

nCK

ns

19

13.75

35

13.92

34

14.06

33

14.16

32

14.25

32

ns

tRAS(min)

tRC(min)

ns

48.75

47.92

47.06

46.16

46.25

ns

•

JEDEC standard 1.2V (1.14V~1.26V)

= 1.2V (1.14V~1.26V)

The 4Gb DDR4 SDRAM E-die is organized as a 64Mbit x 4 I/Os x 16banks

or 32Mbit x8 I/Os x 16banks device. This synchronous device achieves

high speed double-data-rate transfer rates of up to 2666Mb/sec/pin (DDR4-

2666) for general applications.

V

DDQ

800 MHz f for 1600Mb/sec/pin,933 MHz f for 1866Mb/sec/pin,

CK

1067MHz f for 2133Mb/sec/pin, 1200MHz f for 2400Mb/sec/pin,

CK

1333MHz f for2666Mb/sec/pin

CK

The chip is designed to comply with the following key DDR4 SDRAM fea-

tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,

On Die Termination using ODT pin and Asynchronous Reset.

•

16 Banks (4 Bank Groups)

Programmable CAS Latency (posted CAS):

10,11,12,13,14,15,16,17,18

•

Programmable Additive Latency: 0, CL-2 or CL-1 clock

All of the control and address inputs are synchronized with a pair of exter-

nally supplied differential clocks. Inputs are latched at the crosspoint of dif-

ferential clocks (CK rising and CK falling). All I/Os are synchronized with a

pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-

ion. The address bus is used to convey row, column, and bank address

information in a RAS/CAS multiplexing style. The DDR4 device operates

with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V).

The 4Gb DDR4 E-die device is available in 78ball FBGAs(x4/x8).

Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12

(DDR4-1866),11,14 (DDR4-2133),12,16 (DDR4-2400) and 14,18

(DDR4-2666)

•

8-bit pre-fetch

Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read

or write [either On the fly using A12 or MRS]

•

Bi-directional Differential Data-Strobe

Internal (self) calibration: Internal self calibration through ZQ pin

(RZQ: 240 ohm ± 1%)

•

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower than T

85C, 3.9us at

CASE

85C < T

< 95 C

CASE

•

Support Industrial Temp (-4095C)

- tREFI 7.8us at -40 °C ≤ TCASE ≤ 85°C

- tREFI 3.9us at 85 °C < TCASE ≤ 95°C

•

Asynchronous Reset

Package: 78 balls FBGA - x4/x8

All of Lead-Free products are compliant for RoHS

All of products are Halogen-free

CRC (Cyclic Redundancy Check) for Read/Write data security

Command address parity check

DBI (Data Bus Inversion)

Gear down mode

POD (Pseudo Open Drain) interface for data input/output

Internal VREF for data inputs

External VPP for DRAM Activating Power

PPR and sPPR is supported

NOTE: 1. This data sheet is an abstract of full DDR4 specification and does not cover the common features which are described in “DDR4 SDRAM Device Operation & Timing

Diagram”.

2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.

- 5 -

Rev. 1.6

K4A4G045WE

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datasheet

DDR4 SDRAM

3. Package pinout/Mechanical Dimension & Addressing

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package

1

2

3

4

5

6

7

8

9

VDD

VPP

VSSQ

VDDQ

DQ0

NC

DQS_c

DQS_t

DQ2

VSSQ

VDDQ

VSS

ZQ

NC

DQ1

VDD

DQ3

NC

A

B

C

D

E

F

A

B

C

D

E

F

VDDQ

VSSQ

VSS

VDDQ

VSSQ

VSS

NC

VDDQ

CK_c

NC

VDDQ

NC

VDD

ODT

CK_t

CS_n

VDD

VSS

NC

CKE

NC

G

WE_n

A14

CAS_n

A15

RAS_n

A16

VDD

ACT_n

VSS

H

J

H

J

A10

AP

A12

BC_n

VREFCA

BG0

BG1

VDD

VSS

RESET_n

VDD

BA0

A6

A4

A0

A3

A1

A9

NC

BA1

A5

VSS

ALERT_n

VPP

K

L

K

L

A8

A2

A7

M

N

M

N

VSS

A11

PAR

A13

VDD

1

2

3

4

5

6

7

8

9

Ball Locations (x4)

A

B

C

D

E

F

Populated ball

Ball not populated

G

H

J

Top view

(See the balls through the package)

K

L

M

N

- 6 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package

1

2

3

4

5

6

7

8

9

DM_n,

DBI_n,

TDQS_t

VDD

VSSQ

VSS

TDQS_c

A

VPP

VDDQ

VSSQ

VSS

VDDQ

DQ0

DQ4

VDDQ

NC

DQS_c

DQS_t

DQ2

DQ1

VDDQ

VSS

ZQ

VDDQ

VSSQ

VSS

B

C

D

E

F

B

C

D

E

F

VDD

DQ3

DQ5

DQ6

DQ7

VDDQ

CK_c

NC

VDD

ODT

CK_t

CS_n

VDD

NC

VSS

NC

CKE

G

WE_n

A14

VDD

ACT_n

CAS_n

RAS_n

BG1

VSS

H

J

H

A10

AP

A12

BC_n

VREFCA

BG0

VDD

VSS

J

VSS

RESET_n

VDD

BA0

A6

A4

A0

A3

A1

A9

NC

BA1

A5

K

L

K

ALERT_n

VPP

L

M

N

A8

A2

A7

M

N

VSS

A11

PAR

A13

VDD

1

2

3

4

5

6

7

8

9

Ball Locations (x8)

A

B

C

D

E

F

Populated ball

Ball not populated

G

H

J

Top view

(See the balls through the package)

K

L

M

N

- 7 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

3.3 FBGA Package Dimension (x4/x8)

Units : Millimeters

7.50 0.10

A

0.80 x 8 6.40

#A1 INDEX MARK

B

0.80

(Datum A)

(Datum B)

1.60

6

3.20

3

9

8

7

5

4

2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

78 - 0.48 Solder ball

(Post Reflow 0.50  0.05)

0.2

M

A B

BOTTOM VIEW

7.50 0.10

#A1

0.37 0.05

1.10 0.10

TOP VIEW

- 8 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

4. Input/Output Functional Description

[ Table 3 ] Input/Output function description

Symbol

Type

Function

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on

the crossing of the positive edge of CK_t and negative edge of CK_c.

CK_t, CK_c

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input

buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation

(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit.

After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence,

they must be maintained during all operations (including Self-Refresh). CKE must be maintained high

throughout read and write accesses. Input buffers, excluding CK_t,CK_cSGODT and CKE are disabled

during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.

CKE, (CKE1)

Input

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank

selection on systems with multiple Ranks. CS_n is considered part of the command code.

CS_n, (CS1_n)

C0,C1,C2

Input

Chip ID : Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked

component. Chip ID is considered part of the command code

On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the

DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/

TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8

conurations. For x16 conuration ODT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c,

DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.

ODT, (ODT1)

ACT_n

Input

Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The

input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14

Input

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being

entered. Those pins have multi function. ForG example, for activation with ACT_n Low, those are

Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command

pins for Read, Write and other command defined in command truth table

RAS_n/A16. CAS_n/

A15. WE_n/A14

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is

masked when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is

sampled on both edges of DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in

MR5. For x8 device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n

is an input/output identifing whether to store/output the true or inverted data. If DBI_n is LOW, the data will

be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only

supported in X8

DM_n/DBI_n/TDQS_t,

(DMU_n/DBIU_n),

(DML_n/DBIL_n)

Input/Output

Bank Group Inputs : BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command

is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. X4/8

have BG0 and BG1 but X16 has only BG0

BG0 - BG1

BA0 - BA1

Input

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is

being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/

Write commands to select one location out of the memory array in the respective bank. (A10/AP, A12/

BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows.The address

inputs also provide the op-code during Mode Register Set commands.A17 is only defined for the x4

conuration.

A0 - A17

A10 / AP

Input

Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge

should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW:

no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge

applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is

selected by bank addresses.

Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-the-

fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

A12 / BC_n

RESET_n

Input

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is

HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC

high and low at 80% and 20% of V

.

DD

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at

the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode

Register Setting MR4 A4=High. During this mode, RTT value should be set to Hi-Z. Refer to vendor

specific datasheets to determine which DQ is used.

DQ

Input / Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write

data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on

DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c,

DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and

writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.

DQS_t, DQS_c,

DQSU_t, DQSU_c,

DQSL_t, DQSL_c

- 9 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

Symbol

Type

Function

Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled via Mode

Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS_t/

TDQS_c that is applied to DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/

TDQS will provide the data mask function or Data Bus Inversion depending on MR5; A11,12,10and

TDQS_c is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.

TDQS_t, TDQS_c

Output

Command and Address Parity Input: DDR4 Supports Even Parity check in DRAM with MR setting. Once

it’s enabled via Register in MR5, then DRAM calculates Parity with ACT_n,RAS_n/A16,CAS_n/A15,WE_n/

A14,BG0-BG1,BA0-BA1,A17-A0, and C0-C2 (3DS devices). Input parity should maintain at the rising edge

of the clock and at the same time with command & address with CS_n LOW

PAR

Input

Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output

signal. If there is error in CRC, then Alert_n goes LOW for the period time interval and goes back HIGH. If

there is error in Command Address Parity Check, then Alert_n goes LOW for relatively long period until on

going DRAM internal recovery transaction to complete. During Connectivity Test mode, this pin works as

input. Using this signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin

must be bounded to VDD on board.

ALERT_n

Input/Output

Connectivity Test Mode Enable: Required on X16 devices and optional input on x4/x8 with densities equal

to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins.

It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is

dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to

VSS.

TEN

Input

NC

VDDQ

VSSQ

VDD

No Connect: No internal electrical connection is present.

DQ Power Supply: 1.2 V +/- 0.06 V

DQ Ground

Supply

Power Supply: 1.2 V +/- 0.06 V

Ground

VSS

DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max)

Reference voltage for CA

VPP

VREFCA

ZQ

Reference Pin for ZQ calibration

NOTE: Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination.

- 10 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

5. DDR4 SDRAM Addressing

2 Gb Addressing Table

Configuration

# of Bank Groups

512 Mb x4

256 Mb x8

4

128 Mb x16

2

4

Bank Address

BG Address

BG0~BG1

BA0~BA1

A0~A14

A0~A9

BG0~BG1

BA0~BA1

A0~A13

A0~A9

1KB

BG0

Bank Address in a BG

BA0~BA1

A0~A13

A0~A9

2KB

Row Address

Column Address

Page size

512B

4 Gb Addressing Table

Configuration

1 Gb x4

4

512 Mb x8

4

256 Mb x16

2

# of Bank Groups

Bank Address

BG Address

BG0~BG1

BA0~BA1

A0~A15

A0~A9

512B

BG0~BG1

BA0~BA1

A0~A14

A0~A9

1KB

BG0

Bank Address in a BG

BA0~BA1

A0~A14

A0~A9

2KB

Row Address

Column Address

Page size

8 Gb Addressing Table

Configuration

2 Gb x4

4

1 Gb x8

4

512 Mb x16

2

# of Bank Groups

Bank Address

BG Address

BG0~BG1

BA0~BA1

A0~A16

A0~A9

512B

BG0~BG1

BA0~BA1

A0~A15

A0~A9

1KB

BG0

Bank Address in a BG

BA0~BA1

A0~A15

A0~A9

2KB

Row Address

Column Address

Page size

16 Gb Addressing Table

Configuration

4 Gb x4

4

2 Gb x8

4

1 Gb x16

2

# of Bank Groups

Bank Address

BG Address

BG0~BG1

BA0~BA1

A0~A17

A0~A9

512B

BG0~BG1

BA0~BA1

A0~A16

A0~A9

1KB

BG0

Bank Address in a BG

BA0~BA1

A0~A16

A0~A9

2KB

Row Address

Column Address

Page size

16 Gb Addressing Table(SR x16 DDP)

Configuration

1 Gb x16

4

# of Bank Groups

Bank Address

BG Address

BG0~BG1

BA0~BA1

A0~A15

A0~A9

2KB

Bank Address in a BG

Row Address

Column Address

Page size

NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.

Page size is per bank, calculated as follows:

page size = 2 ^COLBITS* ORG8

where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

- 11 -

Rev. 1.6

K4A4G045WE

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datasheet

DDR4 SDRAM

6. Absolute Maximum Ratings

6.1 Absolute Maximum DC Ratings

[ Table 4 ] Absolute Maximum DC Ratings

Symbol

Parameter

Voltage on VDD pin relative to Vss

Rating

Units

NOTE

VDD

-0.3 ~ 1.5

V

1,3

VDDQ

VPP

-0.3 ~ 1.5

-0.3 ~ 3.0

-0.3 ~ 1.5

-55 to +100

V

1,3

4

Voltage on VDDQ pin relative to Vss

Voltage on VPP pin relative to Vss

Voltage on any pin except VREFCA relative to Vss

Storage Temperature

V

1,3,5

1,2

IN, OUT

T

°C

STG

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA

may be equal to or less than 300 mV

4. VPP must be equal or greater than VDD/VDDQ at all times.

5. Overshoot area above 1.5 V is specified in section 8.3.4, 8.3.5 and section 8.3.6.

6.2 DRAM Component Operating Temperature Range

[ Table 5 ] Temperature Range

Symbol

Parameter

rating

0 to 95

Unit

C

NOTE

1, 2, 4

1, 3, 4

Normal

T

Operating Temperature Range

OPER

Industrial

-40 to 95

C

NOTE :

1. Operating Temperature T_OPERis the case surface temperature on the center/top side of the DRAM.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

tained between 0-85C under all operating conditions

3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

tained between -40-95C under all operating conditions

4. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the

following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.

b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode with Extended Temperature Range

capability (MR2 A6 = 0_band MR2 A7 = 1_b).

7. AC & DC Operating Conditions

[ Table 6 ] Recommended DC Operating Conditions

Rating

Symbol

Parameter

Unit

NOTE

Min.

1.14

Typ.

1.2

Max.

1.26

2.75

VDD

VDDQ

VPP

Supply Voltage

V

1,2,3

3

Supply Voltage for Output

Peak-to-Peak Voltage

1.14

1.2

2.375

2.5

NOTE :

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. DC bandwidth is limited to 20MHz.

- 12 -

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DDR4 SDRAM

8. AC & DC Input Measurement Levels

8.1 AC & DC Logic Input Levels for Single-ended Signals

[ Table 7 ] Single-ended AC & DC input Levels for Command and Address

DDR4-1600/1866/2133/2400

DDR4-2666

Min.

Symbol

Parameter

Unit

NOTE

Min.

VREFCA+ 0.075

VSS

Max.

VDD

Max.

TBD

VIH.CA(DC75)

VIL.CA(DC75)

VIH.CA(AC100)

VIL.CA(AC100)

VREFCA(DC)

DC input logic high

DC input logic low

TBD

V

VREFCA-0.075

Note 2

AC input logic high

VREF + 0.1

Note 2

1

AC input logic low

VREF - 0.1

0.51*VDD

Reference Voltage for ADD, CMD inputs

0.49*VDD

2,3

NOTE :

1. See “Overshoot and Undershoot Specifications” .

2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)

3. For reference : approx. VDD/2 ± 12mV

8.2 AC and DC Input Measurement Levels: V

Tolerances

REF

The DC-tolerance limits and ac-noise limits for the reference voltages V

is illustrated in Figure 1. It shows a valid reference voltage V

(t) as a

REF

REFCA

function of time. (V

stands for V

and V

likewise).

REFDQ

REF

REFCA

V

(DC) is the linear average of V

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7. Fur-

REF

thermore V

(t) may temporarily deviate from V

(DC) by no more than ± 1% V

.

REF

DD

voltage

V_DD

V_SS

time

Figure 1. Illustration of V

(DC) tolerance and VREF ac-noise limits

REF

The voltage levels for setup and hold time measurements V (AC), V (DC), V (AC) and V (DC) are dependent on V

.

IH

IL

REF

"V

" shall be understood as V

(DC), as defined in Figure 1.

REF

This clarifies, that DC-variations of V

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals.

(DC) deviations from the optimum position within the

REF

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

ac-noise. Timing

REF

and voltage effects due to ac-noise on V

up to the specified limit (+/-1% of V ) are included in DRAM timings and their associated deratings.

DD

REF

- 13 -

Rev. 1.6

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K4A4G085WE

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DDR4 SDRAM

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential Signals Definition

tDVAC

V

.DIFF.AC.MIN

IH

V

.DIFF.MIN

IH

0.0

half cycle

V .DIFF.MAX

IL

V .DIFF.AC.MAX

IL

tDVAC

time

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

NOTE :

1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

8.3.2 Differential Swing Requirement for Clock (CK_t - CK_c)

[ Table 8 ] Differential AC & DC Input Levels

DDR4 -1600/1866/2133

DDR4 -2400/2666

Symbol

Parameter

unit NOTE

min

max

min

TBD

max

NOTE 3

TBD

V

differential input high

differential input low

+0.150

NOTE 3

-0.150

V

1

2

IHdiff

V

NOTE 3

ILdiff

V

(AC)

2 x (V (AC) - V

)

2 x (V (AC) - V

)

differential input high ac

differential input low ac

NOTE 3

IHdiff

IH

REF

IH

REF

V

2 x (V (AC) - V

)

2 x (V (AC) - V

)

REF

NOTE 3

ILdiff

NOTE:

1. Used to define a differential signal slew-rate.

2. for CK_t - CK_c use V_IHCA/V_ILCA(AC) of ADD/CMD and V_REFCA

IL

REF

IL

;

3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V_IHCA(DC) max, V_ILCA(DC)min) for single-ended signals

as well as the limitations for overshoot and undershoot.

- 14 -

Rev. 1.6

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DDR4 SDRAM

[ Table 9 ] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c

tDVAC [ps] @ |V

(AC)| = 200mV

IH/Ldiff

Slew Rate [V/ns]

min

max

> 4.0

4.0

120

115

110

105

100

95

-

3.0

2.0

1.8

1.6

1.4

90

1.2

85

1.0

80

< 1.0

80

8.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.

CK_t and CK _c have to approximately reach V

min / V

max [approximately equal to the ac-levels { V

(AC) / V

(AC)} for ADD/CMD signals]

IL.CA

SEH

SEL

IH.CA

in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g. if Different value than V

ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK _c .

(AC100)/V

(AC100) is used for

IL.CA

IH.CA

V_DDor V_DDQ

V_SEHmin

V_SEH

V_DD/2 or V_DDQ/2

CK

V_SELmax

V_SEL

V_SSor V_SSQ

time

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD signal requirements are with respect to V

, the single-ended components of differential signals have a requirement with

REFCA

respect to V /2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended

DD

components of differential signals the requirement to reach V

characteristics of these signals.

max, V

min has no bearing on timing, but adds a restriction on the common mode

SEL

SEH

- 15 -

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DDR4 SDRAM

[ Table 10 ] Single-ended Levels for CK_t, CK_c

DDR4-1600/1866/2133

DDR4-2400/2666

Symbol

Parameter

Unit NOTE

Min

Max

Min

Max

Single-ended high-level for

CK_t , CK_c

V

(VDD/2)+0.100

NOTE3

TBD

NOTE3

V

1, 2

SEH

Single-ended low-level for

CK_t , CK_c

V

NOTE3

(VDD/2)-0.100

NOTE3

TBD

SEL

NOTE :

1. For CK_t - CK_c use V_IH.CA/V_IL.CA(AC) of ADD/CMD;

2. V_IH(AC)/V_IL(AC) for ADD/CMD is based on V_REFCA

;

3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V_IH.CA(DC) max, V_IL.CA(DC)min) for single-ended sig-

nals as well as the limitations for overshoot and undershoot.

8.3.4 Address, Command and Control Overshoot and Undershoot Specifications

[ Table 11 ] AC Overshoot/Undershoot Specification for Address, Command and Control Pins

Specification

Parameter

Symbol

Unit NOTE

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Maximum peak amplitude above VAOS

Upper boundary of overshoot area AAOS1

VAOSP

VAOS

0.06

TBD

V

VDD + 0.24

V

1

VAUS

0.3

V-ns

Maximum peak amplitude allowed for undershoot

Maximum overshoot area per 1 tCK above VAOS

AAOS2

0.0083

0.0071

0.0062

0.0055

Maximum overshoot area per 1 tCK between VDD and

VAOS

AAOS1

AAUS

0.2550

0.2644

0.2185

0.2265

0.1914

0.1984

0.1699

0.1762

TBD

V-ns

Maximum undershoot area per 1 tCK below VSS

(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)

NOTE: 1.The value of VAOS matches VDD absolute max as defined in Table 4 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended

DC Operating Conditions. If VDD is above the recommended operating conditions, VAOS remains at VDD absolute max as defined in Table 4.

V_AOSP

A_AOS2

V_AOS

A_AOS1

V_DD

Volts

(V)

1 tCK

V_SS

A_AUS

V_AUS

Figure 4. Address, Command and Control Overshoot and Undershoot Definition

- 16 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

8.3.5 Clock Overshoot and Undershoot Specifications

[ Table 12 ] AC Overshoot/Undershoot Specification for Clock

Specification

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Parameter

Symbol

Unit NOTE

Maximum peak amplitude above VCOS

VAOSP

VAOS

VAUS

0.06

TBD

V

Upper boundary of overshoot area ADOS1

Maximum peak amplitude allowed for undershoot

VDD + 0.24

1

0.3

V

AAOS2

AAOS1

AAUS

0.0038

0.1125

0.1144

0.0032

0.0964

0.0980

0.0028

0.0844

0.0858

0.0025

0.0750

0.0762

V-ns

Maximum overshoot area per 1 UI above VCOS

Maximum overshoot area per 1 UI between VDD and VDOS

Maximum undershoot area per 1 UI below VSS

(CK_t, CK_c)

NOTE: The value of VCOS matches VDD absolute max as defined in Table 4 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC

Operating Conditions. If VDD is above the recommended operating conditions, VCOS remains at VDD absolute max as defined in Table 4.

V_COSP

A_COS2

V_COS

A_COS1

V_DD

Volts

(V)

1 UI

V_SS

A_CUS

V_CUS

Figure 5. Clock Overshoot and Undershoot Definition

- 17 -

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DDR4 SDRAM

8.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications

[ Table 13 ] AC Overshoot/Undershoot Specification for Data, Strobe and Mask

Specification

Parameter

Symbol

Unit NOTE

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Maximum peak amplitude above VDOS

Upper boundary of overshoot area ADOS1

Lower boundary of undershoot area ADUS1

Maximum peak amplitude below VDUS

Maximum overshoot area per 1 UI above VDOS

VDOSP

VDOS

0.16

TBD

V

VDDQ + 0.24

1

2

VDUS

0.30

0.10

0.30

0.10

0.30

0.10

0.30

0.10

V

VDUSP

ADOS2

V

0.0150

0.0129

0.0113

0.0100

V-ns

Maximum overshoot area per 1 UI between VDDQ and

VDOS

ADOS1

0.1050

0.0900

0.0788

0.0700

TBD

V-ns

Maximum undershoot area per 1 UI between VSSQ

and VDUS1

ADUS1

ADUS2

0.1050

0.0150

0.0900

0.0129

0.0788

0.0113

0.0700

0.0100

TBD

V-ns

Maximum undershoot area per 1 UI below VDUS

(DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c)

NOTE :

1. The value of VDOS matches (VIN, VOUT) max as defined in Table 4 Absolute Maximum DC Ratings if VDDQ equals VDDQ max as defined in Table 6 Recommended DC

Operating Conditions. If VDDQ is above the recommended operating conditions, VDOS remains at (VIN, VOUT) max as defined in Table 4.

2. The value of VDUS matches (VIN, VOUT) min as defined in Table 4 Absolute Maximum DC Ratings

V_DOSP

A_DOS2

V_DOS

A_DOS1

V_DDQ

Volts

(V)

1 UI

V_SSQ

A_DUS1

V_DUSP

A_DUS2

Figure 6. Data, Strobe and Mask Overshoot and Undershoot Definition

- 18 -

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datasheet

DDR4 SDRAM

8.4 Slew Rate Definitions

8.4.1 Slew Rate Definitions for Differential Input Signals (CK)

Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 14 and Figure 7.

[ Table 14 ] Differential Input Slew Rate Definition

Measured

Description

Defined by

From

To

V

Differential input slew rate for rising edge(CK_t - CK_c)

Differential input slew rate for falling edge(CK_t - CK_c)



DeltaTRdiff

ILdiffmax

IHdiffmin

IHdiffmin - ILdiffmax

V



DeltaTFdiff

IHdiffmin

ILdiffmax

IHdiffmin - ILdiffmax

NOTE :

The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.

Delta TRdiff

V

IHdiffmin

0

V

ILdiffmax

Delta TFdiff

Figure 7. Differential Input Slew Rate definition for CK, CK

- 19 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

8.4.2 Slew Rate Definition for Single-ended Input Signals ( CMD/ADD )

Delta TRsingle

V

IHCA(AC) Min

V

IHCA(DC) Min

VREFCA(DC)

V

ILCA(DC) Max

V

ILCA(AC) Max

Delta TFsingle

NOTE :

1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single

2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single

3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.

4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope.

Figure 8. Single-ended Input Slew Rate definition for CMD and ADD

- 20 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

8.5 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals

(CK_t, CK_c) must meet the requirements in Table 15. The differential input cross point voltage VIX is measured from the actual cross point of true and

complement signals to the midlevel between of VDD and VSS.

VDD

CK_t

Vix

VDD/2

Vix

CK_c

VSEL

VSEH

VSS

Figure 9. Vix Definition (CK)

[ Table 15 ] Cross Point Voltage for Differential Input Signals (CK)

DDR4-1600/1866/2133

Symbol

Parameter

min

VDD/2 - 145mV =<

VSEL =< VDD/2 - =< VSEH =< VDD/

100mV 2 + 145mV

-(VDD/2 - VSEL) + (VSEH - VDD/2) -

max

VDD/2 + 100mV

VSEL =< VDD/2 -

145mV

VDD/2 + 145mV

=< VSEH

-

Area of VSEH, VSEL

Differential Input Cross Point Voltage relative to

VDD/2 for CK_t, CK_c

VlX(CK)

-120mV

120mV

25mV

DDR4-2400/2666

Symbol

Parameter

min

max

-

Area of VSEH, VSEL

TBD

Differential Input Cross Point Voltage relative to

VDD/2 for CK_t, CK_c

VlX(CK)

- 21 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

8.6 CMOS Rail to Rail Input Levels

8.6.1 CMOS Rail to Rail Input Levels for RESET_n

[ Table 16 ] CMOS Rail to Rail Input Levels for RESET_n

Parameter

Symbol

Min

0.8*VDD

0.7*VDD

VSS

Max

VDD

Unit

V

NOTE

AC Input High Voltage

DC Input High Voltage

DC Input Low Voltage

AC Input Low Voltage

Rising time

VIH(AC)_RESET

VIH(DC)_RESET

VIL(DC)_RESET

VIL(AC)_RESET

TR_RESET

6

2

VDD

V

0.3*VDD

0.2*VDD

1.0

V

1

VSS

V

7

-

us

4

RESET pulse width

tPW_RESET

1.0

-

3,5

NOTE :

1.After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, SDRAM may not be reset.

2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM operation will not be guaranteed until it is reset

asserting RESET_n signal LOW.

3. RESET is destructive to data contents.

4. No slope reversal(ringback) requirement during its level transition from Low to High.

5. This definition is applied only “Reset Procedure at Power Stable”.

6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.

7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings

tPW_RESET

0.8*VDD

0.7*VDD

0.3*VDD

0.2*VDD

TR_RESET

Figure 10. RESET_n Input Slew Rate Definition

- 22 -

Rev. 1.6

K4A4G045WE

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datasheet

DDR4 SDRAM

8.7 AC and DC Logic Input Levels for DQS Signals

8.7.1 Differential Signal Definition

Figure 11. Definition of differential DQS Signal AC-swing Level

8.7.2 Differential Swing Requirements for DQS (DQS_t - DQS_c)

[ Table 17 ] Differential AC and DC Input Levels for DQS

DDR4-1600/1866/2133

DDR4-2400

DDR4-2666

Symbol

Parameter

Unit

Note

Min

186

Max

Note2

-186

Min

Max

Note2

-160

Min

TBD

Max

TBD

VIHDiffPeak

VILDiffPeak

VIH.DIFF.Peak Voltage

VIL.DIFF.Peak Voltage

160

mV

1

Note2

NOTE :

1.Used to define a differential signal slew-rate.

2.These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended

signals.

- 23 -

Rev. 1.6

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datasheet

DDR4 SDRAM

8.7.3 Peak Voltage Calculation Method

The peak voltage of Differential DQS signals are calculated in a following equation.

VIH.DIFF.Peak Voltage = Max(f(t))

VIL.DIFF.Peak Voltage = Min(f(t))

f(t) = VDQS_t - VDQS_c

DQS_t

Max(f(t))

Min(f(t))

+50%

+35%

DQS_c

Time

Figure 12. Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling

- 24 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

8.7.4 Differential Input Cross Point Voltage

To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals

(DQS_t, DQS_c) must meet the requirements in Table 18. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) is

measured from the actual cross point of DQS_t, DQS_c relative to the VDQSmid of the DQS_t and DQS_c signals.

VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the

difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of

the transitioning DQS signals.

A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provided the said ledge occurs within +/- 35%

of the midpoint of either VIH.DIFF.Peak Voltage (DQS_t rising) or VIL.DIFF.Peak Voltage (DQS_c rising), refer to Figure 12. A secondary horizontal tan-

gent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is derived

from its negative slope to zero slope transition (point A in Figure 13) and a ring-back’s horizontal tangent derived from its positive slope to zero slope tran-

sition (point B in Figure 13) is not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope to zero slope tran-

sition (point C in Figure 13) and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition (point D in Figure 13) is not a valid

horizontal tangent

Lowest horizontal tangent above VDQSmid of the transitioning signals

C

DQS_t

D

VIX_DQS,RF

VIX_DQS,FR

VIX_DQS,RF

VDQSmid

DQS_c

VIX_DQS,FR

B

A

Highest horizontal tanget below VDQSmid of the transitioning signals

V

SSQ

Figure 13. Vix Definition (DQS)

[ Table 18 ] Cross Point Voltage for DQS differential Input Signals

DDR4-1600/1866/2133/2400

DDR4-2666

Symbol

Parameter

Unit

%

Note

1, 2

Min

Max

Min

Max

DQS_t and DQS_c crossing relative

to the midpoint of the DQS_t and

DQS_c signal swings

Vix_DQS_ratio

-

25

-

25

VDQSmid offset relative to

Vcent_DQ(midpoint)

VDQSmid_to_Vcent

-

min(VIHdiff,50)

-

min(VIHdiff,50)

mV

3, 4, 5

NOTE :

1. Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above

VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the transitioning DQS signals.

2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs drivers and paths are matched.

3. The maximum limit shall not exceed the smaller of VIHdiff minimum limit or 50mV.

4. VIX measurements are only applicable for transitioning DQS_t and DQS_c signals when toggling data, preamble and high-z states are not applicable conditions.

5. The parameter VDQSmid is defined for simulation and ATE testing purposes, it is not expected to be tested in a system.

- 25 -

Rev. 1.6

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datasheet

DDR4 SDRAM

8.7.5 Differential Input Slew Rate Definition

Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in are Figure 13 and Figure 14.

NOTE :

1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.

2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.

Figure 14. Differential Input Slew Rate Definition for DQS_t, DQS_c

[ Table 19 ] Differential Input Slew Rate Definition for DQS_t, DQS_c

Description

Defined by

From

To

Differential input slew rate for rising edge(DQS_t - DQS_c)

Differential input slew rate for falling edge(DQS_t - DQS_c)

VILDiff_DQS

VIHDiff_DQS

|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff

|VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff

VIHDiff_DQS

VILDiff_DQS

[ Table 20 ] Differential Input Level for DQS_t, DQS_c

DDR4-1600/1866/2133

DDR4-2400

DDR4-2666

Symbol

Parameter

Unit NOTE

Min

136

-

Max

-

Min

130

-

Max

-

Min

TBD

Max

TBD

VIHDiff_DQS

VILDiff_DQS

Differntial Input High

Differntial Input Low

mV

-136

-130

[ Table 21 ] Differential Input Slew Rate for DQS_t, DQS_c

DDR4-1600/1866/2133/2400

DDR4-2666

Symbol

Parameter

Unit NOTE

Min

Max

Min

TBD

Max

TBD

SRIdiff

Differential Intput Slew Rate

3

18

V/ns

- 26 -

Rev. 1.6

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datasheet

DDR4 SDRAM

9. AC and DC Output Measurement Levels

9.1 Output Driver DC Electrical Characteristics

The DDR4 driver supports two different Ron values. These Ron values are referred as strong(low Ron) and weak mode(high Ron). A functional

representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:

The individual pull-up and pull-down resistors (RON and RON ) are defined as follows:

Pu

Pd

VDDQ -Vout

I out

under the condition that RONPd is off

under the condition that RONPu is off

RON

=

Pu

Pd

Vout

I out

RON

Chip In Drive Mode

Output Drive

VDDQ

To

I_Pu

other

circuity

like

RON

Pu

Pd

RCV, ...

DQ

RON

I_Pd

I_out

V_out

VSSQ

Figure 15. Output driver

- 27 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohm; entire operating temperature range;

after proper ZQ calibration

RON

Resistor

Vout

Min

0.8

0.9

0.8

0.9

0.8

Nom

1

Max

1.1

Unit

NOTE

1,2

NOM

VOLdc= 0.5*VDDQ

VOMdc= 0.8* VDDQ

VOHdc= 1.1* VDDQ

VOLdc= 0.5* VDDQ

VOMdc= 0.8* VDDQ

VOHdc= 1.1* VDDQ

VOLdc= 0.5*VDDQ

VOMdc= 0.8* VDDQ

VOHdc= 1.1* VDDQ

VOLdc= 0.5* VDDQ

VOMdc= 0.8* VDDQ

VOHdc= 1.1* VDDQ

RZQ/7

RZQ/5

RON34Pd

1

1.1

1

1.25

1.1

34

1

RON34Pu

RON48Pd

RON48Pu

1

1.1

1

1.1

1

1.1

1

1.25

1.1

48

1

1.1

Mismatch between pull-up and

pull-down, MMPuPd

VOMdc= 0.8* VDDQ

-10

-

10

%

1,2,3,4

1,2,4

Mismatch DQ-DQ within byte vari-

ation pull-up, MMPudd

-

Mismatch DQ-DQ within byte vari-

ation pull-dn, MMPddd

1,2,4

NOTE :

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after cal-

ibration, see following section on voltage and temperature sensitivity(TBD).

2. Pull-up and pull-dn output driver impedances are recommended to be calibrated at 0.8 * VDDQ. Other calibration schemes may be used to achieve the linearity spec

shown above, e.g. calibration at 0.5 * VDDQ and 1.1 * VDDQ.

3. Measurement definition for mismatch between pull-up and pull-down, MMPuPd : Measure RONPu and RONPD both at 0.8*VDD separately; Ronnom is the nominal Ron

value

RONPu -RONPd

*100

MMPuPd =

RONNOM

4. RON variance range ratio to RON Nominal value in a given component, including DQS_t and DQS_c.

RONPuMax -RONPuMin

*100

MMPudd =

RONNOM

RONPdMax -RONPdMin

MMPddd =

RONNOM

5. This parameter of x16 device is specified for Upper byte and Lower byte.

- 28 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

9.1.1 Alert_n Output Drive Characteristic

A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:

Vout

RON

=

Pd

l Iout l

under the condition that RON is off

Pu

Alert Driver

DRAM

Alert

RON

Pd

I_out

V_out

I_Pd

VSSQ

Resistor

Vout

VOLdc= 0.1* VDDQ

Min

0.3

0.4

Max

1.2

Unit

34Ω

NOTE

1

V

= 0.8* VDDQ

= 1.1* VDDQ

RON

1.2

OMdc

Pd

V

0.4

1.4

34Ω

1

OHdc

NOTE :

1. VDDQ voltage is at VDDQ DC. VDDQ DC definition is TBD.

9.1.2 Output Driver Characteristic of Connectivity Test ( CT ) Mode

Following Output driver impedance RON will be applied Test Output Pin during Connectivity Test ( CT ) Mode.

The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows:

V

-V

DDQ OUT

RON

=

Pu_CT

Pd_CT

l Iout l

V

OUT

l Iout l

Chip In Driver Mode

Output Driver

V_DDQ

I_{Pu_CT}

RON

To

other

circuity

like

Pu_CT

DQ

RCV,...

Iout

RON

Pd_CT

Vout

I_{Pd_CT}

V_SSQ

Figure 16. Output Driver

- 29 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

RON

Resistor

Vout

Max

1.9

2.0

2.2

2.5

2.2

2.0

1.9

Units

34

NOTE

NOM_CT

VOB = 0.2 x V

1

dc

DDQ

VOL = 0.5 x V

dc

DDQ

RON

Pd_CT

Pu_CT

VOM = 0.8 x V

dc

DDQ

VOH = 1.1 x V

dc

34

VOB = 0.2 x V

dc

VOL = 0.5 x V

dc

DDQ

RON

VOM = 0.8 x V

dc

DDQ

VOH = 1.1 x V

dc

DDQ

NOTE :

^{1. Connectivity test mode uses un-calibrated drivers, showing the full range over PVT. No mismatch between pull up and pull down is defined}.

9.2 Single-ended AC & DC Output Levels

[ Table 23 ] Single-ended AC & DC Output Levels

Symbol

Parameter

DDR4-1600/1866/2133/2400/2666

Units NOTE

V

(DC)

DC output high measurement level (for IV curve linearity)

1.1 x V

0.8 x V

0.5 x V

V

OH

DDQ

V

DC output mid measurement level (for IV curve linearity)

DC output low measurement level (for IV curve linearity)

AC output high measurement level (for output SR)

AC output low measurement level (for output SR)

V

OM

(DC)

OL

(AC)

(0.7 + 0.15) x V

V

1

OH

DDQ

V

(0.7 - 0.15) x V

OL

DDQ

NOTE :

1. The swing of ± 0.15 × V_DDQis based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test

load of 50Ω to V_TT= V_DDQ

.

9.3 Differential AC & DC Output Levels

[ Table 24 ] Differential AC & DC Output Levels

Symbol

(AC)

Parameter

DDR4-1600/1866/2133/2400/2666

Units

NOTE

V

AC differential output high measurement level (for output SR)

+0.3 x V

V

1

OHdiff

DDQ

V

(AC)

AC differential output low measurement level (for output SR)

-0.3 x V

V

1

OLdiff

DDQ

NOTE :

1. The swing of ± 0.3 × V_DDQis based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load

of 50Ω to V_TT= V_DDQat each of the differential outputs.

- 30 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

9.4 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

single ended signals as shown in Table 25 and Figure 17.

and V

for

OL(AC)

OH(AC)

[ Table 25 ] Single-ended Output Slew Rate Definition

Measured

Description

Defined by

[V (AC)-V (AC)] / Delta TRse

From

(AC)

To

(AC)

V

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE :

OL

OH

OL

(AC)

V

(AC)

[V (AC)-V (AC)] / Delta TFse

OH OL

OH

OL

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

V_OH(AC)

V_TT

V_OL(AC)

delta TFse

delta TRse

Figure 17. Single-ended Output Slew Rate Definition

[ Table 26 ] Single-ended Output Slew Rate

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

Parameter

Symbol

Units

V/ns

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Single ended output slew rate

Description: SR: Slew Rate

SRQse

4

9

4

9

4

9

4

9

4

9

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

For Ron = RZQ/7 setting

NOTE :

1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.

-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the

same byte lane are static (i.e. they stay at either high or low).

-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the

same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the

regular maximum limit of 9 V/ns applies

- 31 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

9.5 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and

VOHdiff(AC) for differential signals as shown in Table 27 and Figure 18.

[ Table 27 ] Differential Output Slew Rate Definition

Measured

Description

Defined by

(AC)-V (AC)] / Delta TRdiff

From

(AC)

To

(AC)

V

[V

OHdiff

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE :

OLdiff

OHdiff

OLdiff

(AC)

V

(AC)

[V

(AC)-V (AC)] /Delta TFdiff

OLdiff

OHdiff

OLdiff

OHdiff

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

V_OHdiff(AC)

V_TT

_OLdiff(AC)

V

delta TFdiff

delta TRdiff

Figure 18. Differential Output Slew Rate Definition

[ Table 28 ] Differential Output Slew Rate

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

Parameter

Symbol

SRQdiff

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Differential output slew rate

8

18

8

18

8

18

8

18

8

18

V/ns

Description:

SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

diff: Differential Signals

For Ron = RZQ/7 setting

- 32 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode

Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.

[ Table 29 ] Single-ended AC & DC Output Levels of Connectivity Test Mode

Symbol

Parameter

DDR4-1600/1866/2133/2400/2666

1.1 x VDDQ

Unit

V

Notes

V

DC output high measurement level (for IV curve linearity)

DC output mid measurement level (for IV curve linearity)

DC output low measurement level (for IV curve linearity)

DC output below measurement level (for IV curve linearity)

AC output high measurement level (for output SR)

AC output below measurement level (for output SR)

OH(DC)

0.8 x VDDQ

V

OM(DC)

OL(DC)

OB(DC)

OH(AC)

OL(AC)

0.5 x VDDQ

V

0.2 x VDDQ

V

VTT + (0.1 x VDDQ)

VTT - (0.1 x VDDQ)

V

1

V

NOTE

1. The effective test load is 50Ω terminated by VTT = 0.5 * VDDQ.

VOH(AC)

VTT

0.5 * VDDQ

VOL(AC)

TR_output_CT

Figure 19. Output Slew Rate Definition of Connectivity Test Mode

[ Table 30 ] Single-ended Output Slew Rate of Connectivity Test Mode

DDR4-1600/1866/2133/2400/2666

Parameter

Symbol

Unit

Notes

Min

Max

10

Output signal Falling time

Output signal Rising time

TF_output_CT

TR_output_CT

-

ns/V

10

9.7 Test Load for Connectivity Test Mode Timing

The reference load for ODT timings is defined in Figure 20.

V

DDQ

DQ, DM

DQSL , DQSL

DQSU , DQSU

DQS , DQS

CT_INPUTS

DUT

0.5*VDDQ

Rterm = 50 ohm

V

SSQ

Timing Reference Points

Figure 20. Connectivity Test Mode Timing Reference Load

- 33 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

10. Speed Bin

[ Table 31 ] DDR4-1600 Speed Bins and Operations

Speed Bin

CL-nRCD-nRP

Parameter

DDR4-1600

11-11-11

Unit

NOTE

Symbol

tAA

min

max

13

13.75

Internal read command to first data

Internal read command to first data with read DBI enabled

ACT to internal read or write delay time

18.00

ns

11

5,11

(13.50)

tAA_DBI

tRCD

tAA(min) + 2nCK

tAA(max) +2nCK

-

13

13.75

5,11

(13.50)

13

13.75

PRE command period

ACT to PRE command period

ACT to ACT or REF command period

tRP

tRAS

tRC

-

ns

11

5,11

(13.50)

35

9 x tREFI

-

48.75

5,11

(48.50)

Normal

CL = 9

Read DBI

CL = 11

1.5

tCK(AVG)

1.6

ns

1,2,3,4,10,13

5,11

CWL = 9

(Optional)

CL = 10

CL = 11

CL = 12

CL = 13

CL = 14

tCK(AVG)

Reserved

ns

1,2,3,4,10

1,2,3,4

1,2,3

Reserved

CWL = 9,11

1.25

<1.5

ns

Supported CL Settings

9,11,12

11,13,14

9,11

nCK

12,13

12

Supported CL Settings with read DBI

Supported CWL Settings

- 34 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

[ Table 32 ] DDR4-1866 Speed Bins and Operations

Speed Bin

CL-nRCD-nRP

Parameter

DDR4-1866

13-13-13

Unit

NOTE

Symbol

tAA

min

max

13

13.92

Internal read command to first data

Internal read command to first data with read DBI enabled

ACT to internal read or write delay time

18.00

ns

11

5,11

(13.50)

tAA_DBI

tRCD

tAA(min) + 2nCK

tAA(max) +2nCK

-

13

13.92

5,11

(13.50)

13

13.92

PRE command period

ACT to PRE command period

ACT to ACT or REF command period

tRP

tRAS

tRC

-

ns

11

5,11

(13.50)

34

9 x tREFI

-

47.92

5,11

(47.50)

Normal

CL = 9

Read DBI

CL = 11

1.5

tCK(AVG)

1.6

ns

1,2,3,4,10,13

5,11

CWL = 9

CWL = 9,11

CWL = 10,12

(Optional)

CL = 10

CL = 12

tCK(AVG)

Reserved

ns

1,2,3,4,10

4

1.25

<1.5

CL = 11

CL = 13

tCK(AVG)

ns

1,2,3,4,6

5,11

(Optional)

CL = 12

CL = 13

CL = 14

CL = 15

CL = 16

tCK(AVG)

ns

1,2,3,6

1,2,3,4

1,2,3

Reserved

1.071

<1.25

ns

Supported CL Settings

9,11,12,13,14

11,13,14,15,16

9,10,11,12

nCK

12,13

12

Supported CL Settings with read DBI

Supported CWL Settings

- 35 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

[ Table 33 ] DDR4-2133 Speed Bins and Operations

Speed Bin

CL-nRCD-nRP

Parameter

DDR4-2133

15-15-15

Unit

NOTE

Symbol

min

max

13

14.06

Internal read command to first data

tAA

18.00

ns

11

5,11

(13.75)

Internal read command to first data with read DBI

enabled

tAA_DBI

tRCD

tAA(min) + 3nCK

14.06

tAA(max) + 3nCK

-

ACT to internal read or write delay time

5,11

(13.75)

14.06

PRE command period

ACT to PRE command period

ACT to ACT or REF command period

tRP

tRAS

tRC

-

ns

11

5,11

(13.75)

33

9 x tREFI

-

47.06

5,11

(46.75)

Normal

CL = 9

Read DBI

CL = 11

CL = 12

CL = 13

CL = 14

CL = 15

1.5

1,2,3,4,10,1

3

tCK(AVG)

1.6

ns

5,11

CWL = 9

(Optional)

CL = 10

CL = 11

CL = 12

CL = 13

Reserved

1,2,3,10

1,2,3,4,7

1,2,3,7

1.25

<1.5

5,11

CWL = 9,11

CWL = 10,12

CWL = 11,14

(Optional)

1.25

<1.5

1.071

<1.25

1,2,3,4,7

5,11

(Optional)

CL = 14

CL = 15

CL = 16

CL = 17

CL = 18

CL = 19

tCK(AVG)

1.071

<1.25

ns

1,2,3,7

1,2,3,4

1,2,3

Reserved

0.937

<1.071

ns

Supported CL Settings

Supported CL Settings with read DBI

Supported CWL Settings

9,11.12,13,14,15,16

11,13,14,15,16,18,19

9,10,11,12,14

nCK

12,13

- 36 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

[ Table 34 ] DDR4-2400 Speed Bins and Operations

Speed Bin

CL-nRCD-nRP

Parameter

DDR4-2400

17-17-17

Unit

NOTE

Symbol

min

max

14.16

Internal read command to first data

tAA

18.00

ns

11

5,11

(13.75)

tAA(min) + 3nCK

14.16

Internal read command to first data with read DBI

enabled

tAA_DBI

tRCD

tAA(max) + 3nCK

-

ACT to internal read or write delay time

5,11

(13.75)

14.16

PRE command period

ACT to PRE command period

ACT to ACT or REF command period

tRP

tRAS

tRC

-

ns

11

5,11

(13.75)

32

9 x tREFI

-

46.16

5,11

(45.75)

Normal

CL = 9

Read DBI

CL = 11

CL = 12

tCK(AVG)

Reserved

ns

1,2,3,4,9

4

CWL = 9

CL = 10

1.5

1.6

1.25

<1.5

CWL = 9,11

CL = 11

CL = 13

tCK(AVG)

ns

1,2,3,4,8

5,11

(Optional)

CL = 12

CL = 14

tCK(AVG)

1.25

<1.5

ns

1,2,3,8

4

Reserved

1.071

<1.25

1,2,3,4,8

CWL = 10,12

CWL = 11,14

CWL = 12,16

CL = 13

CL = 15

tCK(AVG)

5,11

(Optional)

CL = 14

CL = 16

CL = 17

tCK(AVG)

1.071

0.937

<1.25

ns

1,2,3,8

4

Reserved

<1.071

1,2,3,4,8

CL = 15

CL = 18

tCK(AVG)

5,11

(Optional)

CL = 16

CL = 15

CL = 16

CL = 17

CL = 18

CL = 19

CL = 18

CL = 19

CL = 20

CL = 21

tCK(AVG)

0.937

<1.071

ns

1,2,3,8

1,2,3,4

Reserved

0.833

<0.937

ns

1,2,3

Supported CL Settings

Supported CL Settings with read DBI

Supported CWL Settings

10,11,12,13,14,15,16,17,18

12,13,14,15,16,18,19,20,21

9,10,11,12,14,16

nCK

12,13

- 37 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

[ Table 35 ] DDR4-2666 Speed Bins and Operations

Speed Bin

CL-nRCD-nRP

Parameter

DDR4-2666

19-19-19

Unit

NOTE

Symbol

min

max

14

14.25

Internal read command to first data

tAA

18.00

ns

11

5,12

(13.75)

Internal read command to first data with read DBI

enabled

tAA_DBI

tRCD

tAA(min) + 3nCK

14.25

tAA(max) + 3nCK

-

ACT to internal read or write delay time

5,12

(13.75)

14

14.25

PRE command period

ACT to PRE command period

ACT to ACT or REF command period

tRP

tRAS

tRC

-

ns

11

5,12

(13.75)

32

9 x tREFI

-

46.25

5,12

(45.75)

Normal

CL = 9

Read DBI

CL = 11

CL = 12

tCK(AVG)

Reserved

ns

1,2,3,4,10

1,2,3,10

4

CWL = 9

CL = 10

1.5

1.6

1.25

<1.5

CWL = 9,11

CL = 11

CL = 13

tCK(AVG)

ns

1,2,3,4,9

5,12

(Optional)

CL = 12

CL = 14

tCK(AVG)

1.25

<1.5

ns

1,2,3,9

4

Reserved

1.071

<1.25

CWL = 10,12

CWL = 11,14

CL = 13

CL = 15

tCK(AVG)

ns

1,2,3,4,9

5,12

(Optional)

CL = 14

CL = 16

CL = 17

tCK(AVG)

1.071

0.937

<1.25

ns

1,2,3,9

4

Reserved

<1.071

CL = 15

CL = 18

tCK(AVG)

ns

1,2,3,4,9

5,12

(Optional)

CL = 16

CL = 15

CL = 16

CL = 19

CL = 18

CL = 19

tCK(AVG)

0.937

<1.071

ns

1,2,3,9

4

Reserved

1,2,3,4S9

1,2,3

0.833

<0.937

CWL = 12,16

CWL = 14.18

CL = 17

CL = 20

tCK(AVG)

ns

5,12

(Optional)

CL = 18

CL = 17

CL = 18

CL = 19

CL = 20

CL = 21

CL = 20

CL = 21

CL = 22

CL = 23

tCK(AVG)

ns

Reserved

1,2,3S4

1,2,3

ns

0.75

<0.833

ns

Supported CL Settings

Supported CL Settings with read DBI

Supported CWL Settings

10,11,12,13,14,15,16,17,18,19,20

12,13,14,15,17,18,19,20,21,22,23

9,10,11,12,14,16,18

nCK

12

- 38 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

10.1 Speed Bin Table Note

Absolute Specification

- VDDQ = VDD = 1.20V +/- 0.06 V

- VPP = 2.5V +0.25/-0.125 V

- The values defined with above-mentioned table are DLL ON case.

- DDR4-1600, 1866, 2133S2400Gand 2666 Speed Bin Tables are valid only when Geardown Mode is disabled.

1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from

CL setting as well as requirements from CWL setting.

2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. CL in clock cycle is calculated from tAA following rounding algorithm defined in Section "Rounding Algorithms"

3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or

0.937 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD

information if and how this setting is supported.

6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

10. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

11. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

12. CL number in parentheses, it means that these numbers are optional.

13. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).

14. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant. JEDEC compliance does not require support for

all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.

- 39 -

Rev. 1.6

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DDR4 SDRAM

11. IDD and IDDQ Specification Parameters and Test Condi-

tions

11.1 IDD, IPP and IDDQ Measurement Conditions

In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined. Figure 21 shows the setup and test load for IDD,

IPP and IDDQ measurements.

l

IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA,

IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E, IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD

balls of the DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.

l

IPP currents have the same definition as IDD except that the current on the VPP supply is measured.

IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR4 SDRAM under test tied

together. Any IDD current is not included in IDDQ currents.

Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can be used to support correlation of simulated IO

power to actual IO power as outlined in Figure 22. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are

using one merged-power layer in Module PCB.

For IDD, IPP and IDDQ measurements, the following definitions apply:

l

“0” and “LOW” is defined as VIN <= VILAC(max).

“1” and “HIGH” is defined as VIN >= VIHAC(min).

“MID-LEVEL” is defined as inputs are VREF = VDD / 2.

Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 36.

Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 37.

Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 38 through Table 46.

IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting

RON = RZQ/7 (34 Ohm in MR1);

RTT_NOM = RZQ/6 (40 Ohm in MR1);

RTT_WR = RZQ/2 (120 Ohm in MR2);

RTT_PARK = Disable;

Qoff = 0 (Output Buffer enabled) in MR1;

B

TDQS_t disabled in MR1;

CRC disabled in MR2;

CA parity feature disabled in MR5;

Gear down mode disabled in MR3

Read/Write DBI disabled in MR5;

DM disabled in MR5

l

Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is

started.

l

Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA changes when directed.

Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} apply invert of BG/BA changes when directed above.

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DDR4 SDRAM

I

DDQ

DD

PP

V

DDQ

DD

PP

RESET

CK_t/CK_c

DDR4 SDRAM

CKE

CS

C

DQS_t/DQS_c

DQ

DM

ACT,RAS,CAS,WE

A,BG,BA

ODT

V

SSQ

SS

ZQ

NOTE:

1. DIMM level Output test load condition may be different from above

Figure 21. Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements

Application specific

IDDQ

TestLad

memory channel

environment

Channel

IO Powe

Simulatin

IDDQ

Simuaion

IDDQ

Measurement

Correlation

X

Channel IO Power

Number

Figure 22. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.

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DDR4 SDRAM

[ Table 36 ] Timings Used for IDD, IPP and IDDQ Measurement-Loop Patterns

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

Unit

Symbol

11-11-11

1.25

11

39

28

11

16

20

28

4

13-13-13

1.071

13

12

13

45

32

13

16

22

28

4

15-15-15

0.937

15

14

15

51

36

15

16

23

32

4

17-17-17

0.833

17

16

17

56

39

17

16

26

36

4

19-19-19

tCK

CL

TBD

ns

nCK

CWL

nRCD

nRC

nRAS

nRP

x4

x8

nFAW

x16

x4

nRRDS

nRRDL

x8

4

x16

x4

5

6

7

5

6

x8

5

6

x16

6

7

8

tCCD_S

4

tCCD_L

tWTR_S

tWTR_L

nRFC 2Gb

nRFC 4Gb

nRFC 8Gb

TBD

5

6

2

3

6

7

8

9

128

208

280

150

243

327

171

278

374

193

313

421

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DDR4 SDRAM

[ Table 37 ] Basic IDD, IPP and IDDQ Measurement Conditions

Symbol

Description

Operating One Bank Active-Precharge Current (AL=0)

1

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: High between ACT and PRE;

Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 38 on page 46; Data IO: VDDQ;

DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 38 on page 46); Output Buffer and

IDD0

2

RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 38 on page 46

Operating One Bank Active-Precharge Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD0

IDD0A

IPP0

Operating One Bank Active-Precharge IPP Current

Same condition with IDD0

Operating One Bank Active-Read-Precharge Current (AL=0)

1

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: High between ACT, RD

IDD1

and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling according to Table 39 on

page 47; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 39 on page 47); Output Buf-

2

fer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 39 on page 47

Operating One Bank Active-Read-Precharge Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD1

IDD1A

IPP1

Operating One Bank Active-Read-Precharge IPP Current

Same condition with IDD1

Precharge Standby Current (AL=0)

1

CKE: High; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: stable at 1; Command, Address, Bank Group

IDD2N

Address, Bank Address Inputs: partially toggling according to Table 40 on page 48; Data IO: VDDQ; DM_n: stable at 1; Bank Activity:

2

all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 40 on

page 48

Precharge Standby Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD2N

IDD2NA

IPP2N

Precharge Standby IPP Current

Same condition with IDD2N

Precharge Standby ODT Current

1

CKE: High; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: stable at 1; Command, Address, Bank Group

IDD2NT Address, Bank Address Inputs: partially toggling according to Table 41 on page 49; Data IO: VSSQ; DM_n: stable at 1; Bank Activity:

2

all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: toggling according to Table 41 on page 49; Pattern

Details: see Table 41 on page 49

IDDQ2NT Precharge Standby ODT IDDQ Current

(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Standby Current with CAL enabled

IDD2NL

3

Same definition like for IDD2N, CAL enabled

Precharge Standby Current with Gear Down mode enabled

IDD2NG

3,5

Same definition like for IDD2N, Gear Down mode enabled

Precharge Standby Current with DLL disabled

IDD2ND

3

Same definition like for IDD2N, DLL disabled

Precharge Standby Current with CA parity enabled

IDD2N_par

3

Same definition like for IDD2N, CA parity enabled

1

Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: stable at 1;

IDD2P

IPP2P

Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all

2

banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0

Precharge Power-Down IPP Current

Same condition with IDD2P

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: stable at 1; Command, Address, Bank Group

1

IDD2Q

IDD3N

Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks closed; Output Buffer and RTT:

Enabled in Mode Registers ; ODT Signal: stable at 0

2

Active Standby Current

1

CKE: High; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: stable at 1; Command, Address, Bank Group

Address, Bank Address Inputs: partially toggling according to Table 40 on page 48; Data IO: VDDQ; DM_n: stable at 1;Bank Activity:

2

all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 40 on page 48

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Rev. 1.6

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DDR4 SDRAM

Symbol

Description

Active Standby Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD3N

IDD3NA

IPP3N

Active Standby IPP Current

Same condition with IDD3N

Active Power-Down Current

1

CKE: Low; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: stable at 1; Command, Address, Bank Group

Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open; Output Buffer and

RTT: Enabled in Mode Registers ; ODT Signal: stable at 0

IDD3P

IPP3P

2

Active Power-Down IPP Current

Same condition with IDD3P

Operating Burst Read Current

2

CKE: High; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: High between RD; Command, Address,

Bank Group Address, Bank Address Inputs: partially toggling according to Table 42 on page 50; Data IO: seamless read data burst

with different data between one burst and the next one according to Table 42 on page 50; DM_n: stable at 1; Bank Activity: all banks

open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 42 on page 50); Output Buffer and RTT: Enabled in Mode

IDD4R

2

Registers ; ODT Signal: stable at 0; Pattern Details: see Table 42 on page 50

Operating Burst Read Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD4R

IDD4RA

IDD4RB

IPP4R

Operating Burst Read Current with Read DBI

3

Read DBI enabled , Other conditions: see IDD4R

Operating Burst Read IPP Current

Same condition with IDD4R

IDDQ4R

Operating Burst Read IDDQ Current

(Optional)

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

IDDQ4RB

(Optional)

Operating Burst Read IDDQ Current with Read DBI

Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current

Operating Burst Write Current

1

CKE: High; External clock: On; tCK, CL: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: High between WR; Command, Address,

Bank Group Address, Bank Address Inputs: partially toggling according to Table 43 on page 51; Data IO: seamless write data burst

with different data between one burst and the next one according to Table 43 on page 51; DM_n: stable at 1; Bank Activity: all banks

open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 43 on page 51); Output Buffer and RTT: Enabled in Mode

IDD4W

2

Registers ; ODT Signal: stable at HIGH; Pattern Details: see Table 43 on page 51

Operating Burst Write Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4W_par

IPP4W

Operating Burst Write Current with Write DBI

3

Write DBI enabled , Other conditions: see IDD4W

Operating Burst Write Current with Write CRC

3

Write CRC enabled , Other conditions: see IDD4W

Operating Burst Write Current with CA Parity

3

CA Parity enabled , Other conditions: see IDD4W

Operating Burst Write IPP Current

Same condition with IDD4W

Burst Refresh Current (1X REF)

CKE: High; External clock: On; tCK, CL, nRFC: see Table 36 on page 42; BL: 8 ; AL: 0; CS_n: High between REF; Command,

1

IDD5B

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 45 on page 53; Data IO: VDDQ; DM_n:

stable at 1; Bank Activity: REF command every nRFC (see Table 45 on page 53); Output Buffer and RTT: Enabled in Mode

Registers ; ODT Signal: stable at 0; Pattern Details: see Table 45 on page 53

2

Burst Refresh Write IPP Current (1X REF)

Same condition with IDD5B

IPP5B

IDD5F2

IPP5F2

IDD5F4

IPP5F4

Burst Refresh Current (2X REF)

tRFC=tRFC_x2, Other conditions: see IDD5B

Burst Refresh Write IPP Current (2X REF)

Same condition with IDD5F2

Burst Refresh Current (4X REF)

tRFC=tRFC_x4, Other conditions: see IDD5B

Burst Refresh Write IPP Current (4X REF)

Same condition with IDD5F4

- 44 -

Rev. 1.6

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datasheet

DDR4 SDRAM

Symbol

Description

Self Refresh Current: Normal Temperature Range

T

: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal⁴; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see

CASE

IDD6N

1

Table 36 on page 42; BL: 8 ; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable

at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: MID-LEVEL

2

Self Refresh IPP Current: Normal Temperature Range

Same condition with IDD6N

IPP6N

IDD6E

IPP6E

IDD6R

)

Self-Refresh Current: Extended Temperature Range

T

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended⁴; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL: see

Table 36 on page 42; BL: 8 ; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at

CASE

1

2

1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: MID-

LEVEL

Self Refresh IPP Current: Extended Temperature Range

Same condition with IDD6E

Self-Refresh Current: Reduced Temperature Range

4

T

: 0 - 45 °C; Low Power Array Self Refresh (LP ASR) : Reduced ; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see

CASE

1

Table 36 on page 42; BL: 8 ; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at

2

1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: MID-

LEVEL

Self Refresh IPP Current: Reduced Temperature Range

Same condition with IDD6R

IPP6R

IDD6A

IPP6A

Auto Self-Refresh Current

4

T

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto ;CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see

CASE

1

Table 36 on page 42; BL: 8 ; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at

2

1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: MID-LEVEL

Auto Self-Refresh IPP Current

Same condition with IDD6A

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 36 on page 42; BL: 8 ; AL: CL-1; CS_n: High

1

between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 46 on

page 54; Data IO: read data bursts with different data between one burst and the next one according to Table 46 on page 54; DM_n: stable

at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 46 on page 54; Output

IDD7

2

Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 46 on page 54

Operating Bank Interleave Read IPP Current

Same condition with IDD7

IPP7

IDD8

IPP8

Maximum Power Down Current

TBD

Maximum Power Down IPP Current

Same condition with IDD8

NOTE :

1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].

2. Output Buffer Enable

- set MR1 [A12 = 0] : Qoff = Output buffer enabled

- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7

RTT Nom enable

- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6

RTT_WR enable

- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2

RTT_PARK disable

- set MR5 [A8:6 = 000]

3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s

010] : 1866MT/s, 2133MT/s

011] : 2400MT/s ,2666MT/s

Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate

DLL disabled : set MR1 [A0 = 0]

CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s

010] : 2400MT/s ,2666MT/s

Read DBI enabled : set MR5 [A12 = 1]

Write DBI enabled : set :MR5 [A11 = 1]

4. Low Power Auto Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal

01] : Reduced Temperature range

10] : Extended Temperature range

11] : Auto Self Refresh

5. IDD2NG should be measured after sync pulse (NOP) input.

- 45 -

Rev. 1.6

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datasheet

DDR4 SDRAM

1

[ Table 38 ] IDD0, IDD0A and IPP0 Measurement-Loop Pattern

4

Data

0

1,2

ACT

D, D

0

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

3,4

D_#, D_#

3

0

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

nRAS

...

0

1

0

1

0

-

repeat pattern 1...4 until nRC - 1, truncate if necessary

2

1

2

1*nRC

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 1 instead

2

2*nRC

3*nRC

4*nRC

5*nRC

6*nRC

7*nRC

8*nRC

9*nRC

10*nRC

11*nRC

12*nRC

13*nRC

14*nRC

15*nRC

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead

2

3

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 3 instead

2

4

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 1 instead

2

5

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 2 instead

2

6

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 3 instead

2

7

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 0 instead

2

8

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 0 instead

2

9

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 1 instead

2

10

11

12

13

14

15

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 3 instead

For x4 and

x8 only

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 0 instead

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

- 46 -

Rev. 1.6

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datasheet

DDR4 SDRAM

1

[ Table 39 ] IDD1, IDD1A and IPP1 Measurement-Loop Pattern

4

Data

0

ACT

0

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

1, 2

3, 4

...

D, D

b

D#, D#

3

repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

0

nRCD -AL

RD

0

1

0

1

0

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

repeat pattern 1...4 until nRC - 1, truncate if necessary

nRAS

0

1

0

1

0

-

...

1*nRC + 0

1*nRC + 1, 2

ACT

0

1

0

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

D, D

0

b

1*nRC + 3, 4

...

D#, D#

3

repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

1

1*nRC + nRCD - AL RD

0

1

0

1

0

1

0

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

1*nRC + nRAS

...

0

1

0

1

0

-

repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary

2

3

4

5

6

8

9

2*nRC

3*nRC

4*nRC

5*nRC

6*nRC

7*nRC

9*nRC

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 0 instead

2

repeat Sub-Loop 1, use BG[1:0] = 2, BA[1:0] = 0 instead

2

10 10*nRC

11 11*nRC

12 12*nRC

13 13*nRC

14 14*nRC

15 15*nRC

16 16*nRC

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 3 instead

For x4 and x8 only

2

repeat Sub-Loop 1, use BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 0 instead

NOTE :

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.

- 47 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1

[ Table 40 ] IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N, IDD3NA and IDD3P Measurement-Loop Pattern

4

Data

0

1

2

D, D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

D, D

0

2

D#, D#

3

2

3

D#, D#

1

0

3

0

7

F

0

2

1

2

3

4

5

6

7

8

9

4-7

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 1 instead

2

8-11

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead

2

12-15

16-19

20-23

24-27

28-31

32-35

36-39

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 1 instead

2

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 1, BA[1:0] = 0 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 0 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 1 instead

2

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 0 instead

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

- 48 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1

[ Table 41 ] IDD2NT and IDDQ2NT Measurement-Loop Pattern

4

Data

0

1

2

D, D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

D, D

0

2

D#, D#

3

2

3

D#, D#

1

0

3

0

7

F

0

-

2

1

2

3

4

5

6

7

8

9

4-7

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 1, BA[1:0] = 1 instead

2

8-11

repeat Sub-Loop 0, but ODT = 0 and BG[1:0] = 0, BA[1:0] = 2 instead

2

12-15

16-19

20-23

24-27

28-31

32-35

36-39

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 1, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, but ODT = 0 and BG[1:0] = 0, BA[1:0] = 1 instead

2

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, but ODT = 0 and BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 1, BA[1:0] = 0 instead

2

repeat Sub-Loop 0, but ODT = 0 and BG[1:0] = 2, BA[1:0] = 0 instead

2

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 3, BA[1:0] = 1 instead

2

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

repeat Sub-Loop 0, but ODT = 0 and BG[1:0] = 2, BA[1:0] = 2 instead

For x4

and x8

only

2

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 3, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, but ODT = 0 and BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, but ODT = 0 and BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 3, BA[1:0] = 0 instead

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

- 49 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1

[ Table 42 ] IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern

4

Data

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

0

RD

0

1

0

1

0

1

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

2,3

D#, D#

3

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

4

RD

0

1

0

1

0

1

0

1

0

7

F

0

5

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

6,7

D#, D#

3

2

3

4

5

6

7

8

9

8-11

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead

2

12-15

16-19

20-23

24-27

28-31

32-35

36-39

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 0 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 0 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 1 instead

2

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 3 instead

For x4 and x8 only

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 0 instead

NOTE :

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Read Command.

- 50 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1

[ Table 43 ] IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern

4

Data

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

0

WR

0

1

0

1

0

1

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

2,3

D#, D#

3

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

4

WR

0

1

0

1

0

1

0

1

0

7

F

0

5

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

6,7

D#, D#

3

2

3

4

5

6

7

8

9

8-11

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead

2

12-15

16-19

20-23

24-27

28-31

32-35

36-39

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 0 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 0 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 1 instead

2

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 3 instead

For x4 and x8 only

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 0 instead

NOTE :

1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Write Command.

- 51 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1

[ Table 44 ] IDD4WC Measurement-Loop Pattern

4

Data

D0=00, D1=FF

D2=FF, D3=00

0

WR

0

1

0

1

0

D4=FF, D5=00

D6=00, D7=FF

D8=CRC

1,2

3,4

D, D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

D#, D#

3

0

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

D8=CRC

5

WR

0

1

0

1

0

1

0

1

0

7

F

0

6,7

D, D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

8,9

D#, D#

3

2

3

4

5

6

7

8

9

10-14

15-19

20-24

25-29

30-34

35-39

40-44

45-49

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 3 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 0 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 0 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 1 instead

2

10 50-54

11 55-59

12 60-64

13 65-69

14 70-74

15 75-79

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 3 instead

For x4 and x8 only

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 0 instead

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Write Command.

- 52 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1

[ Table 45 ] IDD5B Measurement-Loop Pattern

4

Data

0

1

2

0

1

2

3

REF

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

D

2

D#, D#

3

2

4

D#, D#

1

0

3

0

7

F

0

-

2

4-7

repeat pattern 1...4, use BG[1:0] = 1, BA[1:0] = 1 instead

2

8-11

repeat pattern 1...4, use BG[1:0] = 0, BA[1:0] = 2 instead

2

12-15

16-19

20-23

24-27

28-31

32-35

36-39

40-43

44-47

48-51

52-55

56-59

60-63

64 ... nRFC - 1

repeat pattern 1...4, use BG[1:0] = 1, BA[1:0] = 3 instead

2

repeat pattern 1...4, use BG[1:0] = 0, BA[1:0] = 1 instead

2

repeat pattern 1...4, use BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat pattern 1...4, use BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat pattern 1...4, use BG[1:0] = 1, BA[1:0] = 0 instead

2

repeat pattern 1...4, use BG[1:0] = 2, BA[1:0] = 0 instead

2

repeat pattern 1...4, use BG[1:0] = 3, BA[1:0] = 1 instead

2

repeat pattern 1...4, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat pattern 1...4, use BG[1:0] = 3, BA[1:0] = 3 instead

For x4 and x8 only

2

repeat pattern 1...4, use BG[1:0] = 2, BA[1:0] = 1 instead

2

repeat pattern 1...4, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat pattern 1...4, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat pattern 1...4, use BG[1:0] = 3, BA[1:0] = 0 instead

repeat Sub-Loop 1, Truncate, if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. DQ signals are VDDQ.

- 53 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

1

[ Table 46 ] IDD7 Measurement-Loop Pattern

4

Data

0

1

ACT

RDA

0

1

0

1

0

1

0

1

0

-

D0=00, D1=FF

D2=FF, D3=00

D4=FF, D5=00

D6=00, D7=FF

0

2

D

1

0

1

0

1

0

1

0

1

0

3

0

7

0

F

0

-

2

3

D#

3

...

repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary

nRRD

ACT

RDA

0

1

0

1

0

1

0

1

0

1

0

-

D0=FF, D1=00

D2=00, D3=FF

D4=00, D5=FF

D6=FF, D7=00

1

nRRD + 1

...

repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary

2

3

4

2*nRRD

3*nRRD

4*nRRD

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 3 instead

repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary

2

5

6

7

8

9

nFAW

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 1 instead

2

nFAW + nRRD

nFAW + 2*nRRD

nFAW + 3*nRRD

nFAW + 4*nRRD

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 1, BA[1:0] = 0 instead

repeat Sub-Loop 4

2

10 2*nFAW

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 0 instead

2

11 2*nFAW + nRRD

12 2*nFAW + 2*nRRD

13 2*nFAW + 3*nRRD

14 2*nFAW + 4*nRRD

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 1 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 2 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 3 instead

repeat Sub-Loop 4

For x4 and x8

only

2

15 3*nFAW

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 1 instead

2

16 3*nFAW + nRRD

17 3*nFAW + 2*nRRD

18 3*nFAW + 3*nRRD

19 3*nFAW + 4*nRRD

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 2 instead

2

repeat Sub-Loop 0, use BG[1:0] = 2, BA[1:0] = 3 instead

2

repeat Sub-Loop 1, use BG[1:0] = 3, BA[1:0] = 0 instead

repeat Sub-Loop 4

20 4*nFAW

repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.

- 54 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

11.2 4Gb DDR4 SDRAM E-die IDD Specification Table

IDD and IPP values are for typical operating range of voltage and temperature unless otherwise noted.

[ Table 47 ] I and I

Specification

DDQ

DD

1Gx4 (K4A4G045WE)

512Mx8 (K4A4G085WE)

DDR4-2133

15-15-15

1.2V

DDR4-2400

17-17-17

1.2V

DDR4-2666

19-19-19

1.2V

DDR4-2133

DDR4-2400

17-17-17

1.2V

DDR4-2666

Symbol

Unit

NOTE

15-15-15

1.2V

19-19-19

1.2V

IDD Max.

30

32

38

41

15

18

16

11

31

33

40

43

15

19

17

12

16

12

15

10

13

28

29

13

80

83

81

73

77

72

66

81

192

162

122

13

20

10

13

199

6.5

31

33

41

44

16

20

19

13

17

13

16

11

30

32

40

43

15

18

16

11

31

33

42

45

15

19

17

12

16

12

15

10

13

28

29

13

90

95

94

78

81

77

70

85

192

162

122

13

20

10

13

148

6.5

32

34

mA

I

DD0

I

DD0A

43

I

DD1

46

I

DD1A

DD2N

16

I

20

I

DD2NA

18

I

DD2NT

13

I

DD2NL

15

12

15

10

13

27

28

13

72

75

73

65

69

65

59

72

190

160

120

13

20

10

13

181

6.5

15

12

15

10

13

27

28

13

84

87

72

76

72

66

78

190

160

120

13

20

10

13

146

6.5

17

I

DD2NG

13

I

DD2ND

16

I

DD2N_par

10

I

DD2P

DD2Q

14

29

30

14

86

91

88

82

87

82

75

91

192

162

122

14

21

10

13

227

6.5

14

I

29

I

DD3N

30

I

DD3NA

14

I

DD3P

99

I

DD4R

104

101

82

I

DD4RA

DD4RB

I

DD4W

88

I

DD4WA

DD4WB

DD4WC

83

76

I

91

I

DD4W_par

198

162

122

13

I

DD5B

I

DD5F2

DD5F4

I

DD6N

20

I

DD6E

DD6R

10

I

13

I

DD6A

150

6.5

I

DD7

DD8

- 55 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

[ Table 48 ] I Specification

PP

512Mx8 (K4A4G085WE)

1Gx4 (K4A4G045WE)

DDR4-2133

DDR4-2400

17-17-17

2.5V

DDR4-2666

19-19-19

1.2V

DDR4-2133

15-15-15

2.5V

DDR4-2400

17-17-17

2.5V

DDR4-2666

19-19-19

2.5V

Symbol

Unit

NOTE

15-15-15

2.5V

IPP Max.

4

3

4

3

4

3

4

3

4

3

mA

I

PP0

PP1

3

I

PP2N

3

I

PP2P

PP3N

3

I

3

I

PP3P

PP4R

3

I

3

I

PP4W

18

15

11

4

18

15

11

4

19

16

14

4

18

15

11

4

18

15

11

4

18

15

11

4

I

PP5B

I

PP5F2

PP5F4

I

PP6N

4

5

4

I

PP6E

12

2

13

2

14

3

9

I

PP7

2

PP8

[ Table 49 ] I

Specification

DD6

Value

1Gx4 (K4A4G045WE)

512Mx8 (K4A4G085WE)

Symbol

Temperature Range

Unit

NOTE

DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2133 DDR4-2400 DDR4-2666

15-15-15

17-17-17

1.2V

13

19-19-19

15-15-15

17-17-17

1.2V

13

19-19-19

o

0 - 85 C

13

20

14

21

13

20

13

20

mA

3,4

4,5

I

DD6N

o

0 - 95 C

20

I

DD6E

NOTE :

1. Some I_DDcurrents are higher for x16 organization due to larger page-size architecture.

2. Max. values for I_DDcurrents considering worst case conditions of process, temperature and voltage.

3. Applicable for MR2 settings A6=0 and A7=0.

4. Include a max value for I_DD6

.

5. Applicable for MR2 settings A6=0 and A7=1. I_DD6Eis only specified for devices which support the Extended Temperature Range feature.

- 56 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

12. Input/Output Capacitance

[ Table 50 ] Silicon Pad I/O Capacitance

DDR4-1600/1866/2133

DDR4-2400/2666

Symbol

Parameter

Unit

NOTE

min

0.55

-0.1

-

max

1.4

min

0.55

-0.1

-

max

1.15

0.1

C

Input/output capacitance

Input/output capacitance delta

pF

1,2,3

1,2,3,11

1,2,3,5

1,3

IO

C

0.1

DIO

C

Input/output capacitance delta DQS_t and DQS_c

Input capacitance, CK_t and CK_c

0.05

0.8

0.05

0.7

DDQS

C

0.2

-

0.2

-

CK

C

Input capacitance delta CK_t and CK_c

Input capacitance(CTRL, ADD, CMD pins only)

Input capacitance delta(All CTRL pins only)

Input capacitance delta(All ADD/CMD pins only)

Input/output capacitance of ALERT

Input/output capacitance of ZQ

0.05

0.8

0.05

0.7

1,3,4

DCK

C

0.2

-0.1

0.5

-

0.2

-0.1

0.5

-

1,3,6

I

C

0.1

1,3,7,8

1,2,9,10

1,3

DI_ CTRL

C

0.1

DI_ ADD_CMD

C

1.5

ALERT

C

2.3

1,3,12

1,3,13

ZQ

CTEN

Input capacitance of TEN

0.2

2.3

0.2

2.3

NOTE:

1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C

parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd.

2. DQ, DM_n, DQS_T, DQS_C, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value CK_T-CK_C

5. Absolute value of CIO(DQS_T)-CIO(DQS_C)

6. CI applies to ODT, CS_n, CKE, A0-A15, BA0-BA1, BG0-BG1, RAS_n, CAS_n/A15, WE_n/A14, ACT_n and PAR.

7. CDI CTRL applies to ODT, CS_n and CKE

8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))

9. CDI_ADD_ CMD applies to, A0-A15, BA0-BA1, BG0-BG1,RAS_n, CAS_n/A15, WE_n/A14, ACT_n and PAR.

10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))

11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C))

12. Maximum external load capacitance on ZQ pin: tbd pF.

13.TEN pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and system shall verify TEN signal with Vendor

specific information.

- 57 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

[ Table 51 ] DRAM Package Electrical Specifications (x4/x8)

DDR4-1600/1866/2133/2400

DDR4-2666

Symbol

Parameter

Unit

NOTE

min

45

14

-

max

85

min

45

14

-

max

85

Z

Input/output Zpkg

Input/output Pkg Delay

Input/Output Lpkg

W

ps

nH

pF

W

1,2,4,5,10,11

1,3,4,5,11

11,12

IO

T

42

dIO

L

3.3

0.78

85

3.3

0.78

85

io

C

Input/Output Cpkg

-

11,13

io

Z

DQS_t, DQS_c Zpkg

DQS_t, DQS_c Pkg Delay

DQS Lpkg

45

14

-

45

14

-

1,2,5,10,11

1,3,5,10,11

11,12

IO DQS

Td

42

ps

nH

pF

W

IO DQS

L

3.3

0.78

10

3.3

0.78

10

io DQS

C

DQS Cpkg

-

11,13

io DQS

DZ

Delta Zpkg DQS_t, DQS_c

Delta Delay DQS_t, DQS_c

Input- CTRL pins Zpkg

-

1,2,5,7,10

1,3,5,7,10

1,2,5,9,10,11

DIO DQS

D

-

5

-

5

ps

W

TdDIO DQS

Z

50

90

50

90

I CTRL

T

Input- CTRL pins Pkg Delay

Input CTRL Lpkg

14

-

42

3.4

0.7

90

14

-

42

3.4

0.7

90

ps

nH

pF

W

1,3,5,9,10,11

11,12

dI_ CTRL

Li CTRL

Ci CTRL

Input CTRL Cpkg

-

11,13

Z

Input- CMD ADD pins Zpkg

50

1,2,5,8,10,11

IADD CMD

Td

Input- CMD ADD pins Pkg Delay

Input CMD ADD Lpkg

14

-

45

3.6

0.74

90

14

-

45

3.6

0.74

90

ps

nH

pF

W

1,3,5,8,10,11

11,12

IADD_ CMD

Li ADD CMD

Ci ADD CMD

Input CMD ADD Cpkg

-

11,13

Z

CLK_t & CLK_c Zpkg

50

1,2,5,10,11

CK

Td

CLK_t & CLK_c Pkg Delay

Input CLK Lpkg

14

-

42

3.4

0.7

10

14

-

42

3.4

0.7

10

ps

nH

pF

W

1,3,5,10,11

11,12

CK

Li CLK

Ci CLK

Input CLK Cpkg

-

11,13

DZ

Delta Zpkg CLK_t & CLK_c

-

1,2,5,6,10

DCK

D

Delta Delay CLK_t & CLK_c

ZQ Zpkg

-

5

-

5

ps

W

ps

W

ps

1,3,5,6,10

1,2,5,10,11

1,3,5,10,11

1,2,5,10,11

1,3,5,10,11

TdCK

Z

-

100

90

-

100

90

OZQ

Td

ZQ Delay

20

40

20

40

20

O ZQ

Z

ALERT Zpkg

100

55

100

55

O ALERT

Td

ALERT Delay

O ALERT

NOTE :

1. This parameter is not subject to production test. It is verified by design and characterization. The package parasitic( L & C) are validated using package only samples. The

capacitance is measured with VDD, VDDQ, VSS, VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS and VSSQ shorted and

all other signal pins shorted at the die side(not pin). Measurement procedure tbd

2. Package only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where:

Zpkg(total per pin) = GGGGLpkg/Cpkg

3. Package only delay(Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where:

Tdpkg(total per pin) = GGLpkgCpkg

4. Z & Td IO applies to DQ, DM, TDQS_T and TDQS_C

5. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

6. Absolute value of ZCK_t-ZCK_c for impedance(Z) or absolute value of TdCK_t-TdCK_c for delay(Td).

7. Absolute value of ZIO(DQS_t)-ZIO(DQS_c) for impedance(Z) or absolute value of TdIO(DQS_t)-TdIO(DQS_c) for delay(Td)

8. ZI & Td ADD CMD applies to A0-A13,A17, ACT_n, BA0-BA1, BG0-BG1, RAS_n/16, CAS_n/A15, WE_n/A14 and PAR.

9. ZI & Td CTRL applies to ODT, CS_n and CKE

10. This table applies to monolithic X4 and X8 devices.

11. Package implementations shall meet spec if the Zpkg and Pkg Delay fall within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values

shown.

12. It is assumed that Lpkg can be approximated as Lpkg = Zo*Td.

13. It is assumed that Cpkg can be approximated as Cpkg = Td/Zo.

- 58 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

13. Electrical Characteristics & AC Timing

13.1 Reference Load for AC Timing and Output Slew Rate

Figure 23 represents the effective reference load of 50 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate

measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester.

System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to

their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

VDDQ

50 Ohm

DUT

CK_t, CK_c

DQ

DQS_t

DQS_c

VTT = VDDQ

Timing Reference Point

Figure 23. Reference Load for AC Timing and Output Slew Rate

13.2 tREFI

Average periodic Refresh interval (tREFI) of DDR4 SDRAM is defined as shown in the table.

[ Table 52 ] tREFI by Device Density

Parameter

Symbol

2Gb

160

7.8

4Gb

260

7.8

8Gb

350

7.8

16Gb

550

Units

ns

NOTE

All Bank Refresh to active/refresh cmd time

tRFC

0CT

 85C

7.8

s

CASE

-40CT

85CT

Average periodic refresh interval

tREFI

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

s

2

1

CASE

 95C

CASE

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in

this material.

2. Supported only for Industrial Temperature

- 59 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

13.3 Clock Specification

The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR4

SDRAM device.

13.3.1 Definition for tCK(abs)

tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject t o pro-

duction test.

13.3.2 Definition for tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to

rising edge.

N







tCKavg =

tCKabs j  N

N = 200





 _{j = 1}



13.3.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.

N







tCHavg =

tCHj  N  tCKavg

N = 200





 _{j = 1}



tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.

N







tCLavg =

tCLj  N  tCKavg

N = 200





 _{j = 1}



13.3.4 Definition for tERR(nper)

tERR is defined as the cumulative error across n consecutive cycles of n x tCK(avg). tERR is not subject to production test.

- 60 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

13.4 Timing Parameters by Speed Grade

[ Table 53 ] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666

Speed

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

MIN MAX

DDR4-2666

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN MAX

MIN

MAX

MIN

MAX

Clock Timing

tCK

(DLL_OFF)

Minimum Clock Cycle Time (DLL off mode)

8

20

8

20

8

20

8

20

8

20

ns

-

Average Clock Period

Average high pulse width

Average low pulse width

tCK(avg)

tCH(avg)

tCL(avg)

1.25

0.48

<1.5

0.52

1.071

0.48

<1.25

0.52

0.937

0.48

<1.071

0.52

0.833

0.48

<0.937

0.52

0.750

0.48

<0.833

0.52

ns

35,36

tCK(avg)

0.52

tCK(avg)min + tJIT(per)min_tot

tCK(avg)m ax + tJIT(per)max_tot

Absolute Clock Period

tCK(abs)

tCK(avg)

Absolute clock HIGH pulse width

Absolute clock LOW pulse width

Clock Period Jitter- total

tCH(abs)

tCL(abs)

0.45

-63

-31

-50

-

0.45

-54

-27

-43

-

0.45

-47

-23

-38

-

0.45

-42

-21

-33

-

0.45

-38

-19

-30

-

tCK(avg)

23

24

23

26

-

tCK(avg)

JIT(per)_tot

JIT(per)_dj

tJIT(per, lck)

tJIT(cc)

63

31

50

125

54

27

43

107

47

23

38

94

42

21

33

83

38

19

30

75

ps

Clock Period Jitter- deterministic

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL lock-

ing period

tJIT(cc, lck)

-

100

-

86

-

75

-

67

-

60

ps

Duty Cycle Jitter

tJIT(duty)

tERR(2per)

tERR(3per)

tERR(4per)

tERR(5per)

tERR(6per)

tERR(7per)

tERR(8per)

tERR(9per)

tERR(10per)

tERR(11per)

tERR(12per)

tERR(13per)

tERR(14per)

tERR(15per)

tERR(16per)

tERR(17per)

tERR(18per)

TBD

-92

TBD

92

TBD

-79

TBD

79

TBD

-69

TBD

69

TBD

-61

TBD

61

TBD

-55

TBD

55

ps

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

Cumulative error across 13 cycles

Cumulative error across 14 cycles

Cumulative error across 15 cycles

Cumulative error across 16 cycles

Cumulative error across 17 cycles

Cumulative error across 18 cycles

-109

-121

-131

-139

-145

-151

-156

-160

-164

-168

-172

-175

-178

-180

-183

-185

109

121

131

139

145

151

156

160

164

168

172

175

178

189

183

185

-94

94

-82

82

-73

73

-66

66

-104

-112

-119

-124

-129

-134

-137

-141

-144

-147

-150

-152

-155

-157

104

112

119

124

129

134

137

141

144

147

150

152

155

157

159

-91

91

-81

81

-73

73

-98

98

-87

87

-78

78

-104

-109

-113

-117

-120

-123

-126

-129

-131

-133

-135

-137

-139

104

109

113

117

120

123

126

129

131

133

135

137

-92

92

-83

83

-97

97

-87

87

-101

-104

-107

-110

-112

-114

-116

-118

-120

-122

-124

101

104

107

110

112

114

116

118

120

122

124

-91

91

-94

94

-96

96

-99

99

-101

-103

-104

-106

-108

-110

-112

101

103

104

106

108

110

112

-159

t

139

t

Cumulative error across n = 13, 14 . . . 49, 50

cycles

ERR(nper)min = ((1 + 0.68ln(n)) * JIT(per)_total min)

tERR(nper)

tIS(base)

tIS(Vref)

ps

t

ERR(nper)max = ((1 + 0.68ln(n)) * JIT(per)_total max)

Command and Address setup time to

CK_t,CK_c referenced to Vih(ac) / Vil(ac) lev-

els

115

215

140

-

100

200

125

-

80

-

62

162

87

-

TBD

-

Command and Address setup time to

CK_t,CK_c referenced to Vref levels

180

105

Command and Address hold time to

CK_t,CK_c referenced to Vih(dc) / Vil(dc) lev-

els

tIH(base)

Command and Address hold time to

CK_t,CK_c referenced to Vref levels

tIH(Vref)

tIPW

215

600

-

200

525

-

180

460

-

162

410

-

TBD

385

-

ps

Control and Address Input pulse width for

each input

Command and Address Timing

max(5

nCK,

6.250 ns)

max(5

nCK,

5.355 ns)

max(5

nCK,

5.625 ns)

max(5

nCK,

5 ns)

max(5

nCK,

5 ns)

CAS_n to CAS_n command delay for same

bank group

tCCD_L

-

nCK

34

CAS_n to CAS_n command delay for differ-

ent bank group

tCCD_S

4

-

4

-

4

-

4

-

4

-

nCK

34

ACTIVATE to ACTIVATE Command delay to

different bank group for 2KB page size

Max(4nC

K,6ns)

Max(4nC

K,5.3ns)

Max(4nC

K,5.3ns)

Max(4nC

K,5.3ns)

Max(4nC

K,5.3ns)

tRRD_S(2K)

tRRD_S(1K)

tRRD_S(1/2K)

ACTIVATE to ACTIVATE Command delay to

different bank group for 2KB page size

Max(4nC

K,5ns)

Max(4nC

K,4.2ns)

Max(4nC

K,3.7ns)

Max(4nC

K,3.3ns)

Max(4nC

K,3.3ns)

ACTIVATE to ACTIVATE Command delay to

different bank group for 1/2KB page size

Max(4nC

K,5ns)

Max(4nC

K,4.2ns)

Max(4nC

K,3.7ns)

Max(4nC

K,3.3ns)

Max(4nC

K,3.3ns)

- 61 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

Speed

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

ACTIVATE to ACTIVATE Command delay to

same bank group for 2KB page size

Max(4nC

K,7.5ns)

Max(4nC

K,6.4ns)

Max(4nC

K,6.4ns)

Max(4nC

K,6.4ns)

Max(4nC

K,6.4ns)

tRRD_L(2K)

-

nCK

ns

34

ACTIVATE to ACTIVATE Command delay to

same bank group for 1KB page size

Max(4nC

K,6ns)

Max(4nC

K,5.3ns)

Max(4nC

K,5.3ns)

Max(4nC

K,4.9ns)

Max(4nC

K,4.9ns)

tRRD_L(1K)

tRRD_L(1/2K)

tFAW_2K

-

ACTIVATE to ACTIVATE Command delay to

same bank group for 1/2KB page size

Max(4nC

K,6ns)

Max(4nC

K,5.3ns)

Max(4nC

K,5.3ns)

Max(4nC

K,4.9ns)

Max(4nC

K,4.9ns)

Max(28nC

K,35ns)

Max(28nC

K,30ns)

Max(28nC

K,30ns)

Max(28nC

K,30ns)

Max(28n

CK,30ns)

Four activate window for 2KB page size

Four activate window for 1KB page size

Four activate window for 1/2KB page size

Max(20nC

K,25ns)

Max(20nC

K,23ns)

Max(20nC

K,21ns)

Max(20nC

K,21ns)

Max(20n

CK,21ns)

tFAW_1K

ns

Max(16nC

K,20ns)

Max(16nC

K,17ns)

Max(16nC

K,15ns)

Max(16nC

K,13ns)

Max(16n

CK,13ns)

tFAW_1/2K

ns

Delay from start of internal write transaction

to internal read command for different bank

group

max

max(2nC

K,2.5ns)

max(2nC

K,2.5ns)

max(2nC

K,2.5ns)

1,2,e,3

4

tWTR_S

tWTR_L

-

(2nCK,

2.5ns)

-

(2nCK,

2.5ns)

-

ns

Delay from start of internal write transaction

to internal read command for same bank

group

max

(4nCK,7.5

ns)

max

(4nCK,7.

5ns)

max(4nC

K,7.5ns)

max(4nC

K,7.5ns)

max(4nC

K,7.5ns)

1,34

max

(4nCK,7.5

ns)

max

(4nCK,7.

5ns)

Internal READ Command to PRECHARGE

Command delay

max(4nC

K,7.5ns)

max(4nC

K,7.5ns)

max(4nC

K,7.5ns)

tRTP

tWR

-

ns

34

1

WRITE recovery time

15

tWR+ma

x

tWR+max

(4nCK,3.7

5ns)

tWR+max

(5nCK,3.7

5ns)

tWR+max

(5nCK,3.7

5ns)

tWR+max

(5nCK,3.7

5ns)

Write recovery time when CRC and DM are

enabled

tWR_CRC

_DM

-

ns

1, 28

(5nCK,3.

75ns)

tWTR_S+

max

(4nCK,3.7

5ns)

tWTR_S+

max

(5nCK,3.7

5ns)

tWTR_S+

max

(5nCK,3.7

5ns)

tWTR_S+

max

(5nCK,3.7

5ns)

tWTR_S

+max

(5nCK,3.

75ns)

delay from start of internal write transaction

to internal read command for different bank

group with both CRC and DM enabled

tWTR_S_C

RC_DM

2, 29,

34

tWTR_L+

max

(4nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.

75ns)

delay from start of internal write transaction

to internal read command for same bank

group with both CRC and DM enabled

tWTR_L_C

RC_DM

3,30,

34

DLL locking time

tDLLK

tMRD

597

8

-

597

8

-

768

8

-

768

8

-

854

8

-

nCK

Mode Register Set command cycle time

max(24nC

K,15ns)

max(24nC

K,15ns)

max(24nC

K,15ns)

max(24nC

K,15ns)

max(24n

CK,15ns)

Mode Register Set command update delay

Multi-Purpose Register Recovery Time

tMOD

-

nCK

tMPRR

1

33

tMOD

(min)

+ AL +

PL

tMOD

(min)

+ AL + PL

tMOD

(min)

+ AL + PL

tMOD

(min)

+ AL + PL

tMOD

(min)

+ AL + PL

Multi Purpose Register Write Recovery Time

tWR_MPR

-

nCK

Auto precharge write recovery + precharge

time

tDAL(min)

tPDA_S

tPDA_H

Programmed WR + roundup ( tRP / tCK(avg))

nCK

UI

DQ0 or DQL0 driven to 0 set-up time to first

DQS rising edge

0.5

-

0.5

-

0.5

-

0.5

-

0.5

-

45,47

46,47

DQ0 or DQL0 driven to 0 hold time from last

DQS fall-ing edge

UI

CS_n to Command Address Latency

max(3

nCK,

max(3

nCK,

max(3

nCK,

CS_n to Command Address Latency

tCAL

-

5

-

5

-

nCK

3.748 ns)

Mode Register Set command cycle time in

CAL mode

tMOD+

tCAL

tMOD+

tCAL

tMOD+

tCAL

tMOD+

tCAL

tMOD+

tCAL

tMRD_tCAL

tMOD_tCAL

-

nCK

Mode Register Set update delay in CAL

mode

tMOD+

tCAL

tMOD+

tCAL

tMOD+

tCAL

tMOD+

tCAL

tMOD+

tCAL

DRAM Data Timing

DQS_t,DQS_c to DQ skew, per group, per

access

tCK(avg)/ 13,18,3

9,49

tDQSQ

tQH

-

0.16

-

0.16

-

0.16

-

0.16

-

0.18

2

DQ output hold time per group, per access

from DQS_t,DQS_c

tCK(avg)/ 13,17,1

0.76

0.63

0.66

-

0.76

0.63

0.66

-

0.76

0.64

0.69

-

0.74

0.64

0.72

-

0.74

TBD

0.72

-

2

8,39,49

Data Valid Window per device per UI: (tQH -

tDQSQ) of each UI on a given DRAM

17,18,3

9,49

tDVWd

tDVWp

UI

Data Valid Window , per pin per UI : (tQH -

tDQSQ) each UI on a pin of a given DRAM

17,18,3

9,49

UI

DQ low impedance time from CK_t, CK_c

DQ high impedance time from CK_t, CK_c

tLZ(DQ)

tHZ(DQ)

-450

-

225

-390

-

195

-390

-

180

-330

-

175

-310

-

170

ps

39

Data Strobe Timing

DQS_t, DQS_c differential READ Pre-amble

(1 clock preamble)

NOTE

44

NOTE

44

tRPRE

0.9

NOTE44

0.9

NOTE44

0.9

NOTE44

0.9

tCK

40

- 62 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

Speed

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

DQS_t, DQS_c differential READ Pre-amble

(2 clock preamble)

NOTE

44

NOTE

44

tRPRE2

NA

1.8

tCK

41

NOTE

45

NOTE

45

NOTE

45

DQS_t, DQS_c differential READ Postamble

tRPST

0.33

NOTE 45

0.33

NOTE 45

0.33

DQS_t,DQS_c differential output high time

DQS_t,DQS_c differential output low time

tQSH

tQSL

0.4

-

0.4

-

0.4

-

0.4

-

0.4

-

tCK

21

20

DQS_t, DQS_c differential WRITE Pre-amble

(1 clock preamble)

tWPRE

tWPRE2

tWPST

tLZ(DQS)

tHZ(DQS)

tDQSL

0.9

NA

-

0.9

NA

-

0.9

NA

-

0.9

1.8

-

0.9

1.8

-

tCK

ps

42

43

DQS_t, DQS_c differential WRITE Pre-amble

(2 clock preamble)

DQS_t, DQS_c differential WRITE Postam-

ble

0.33

-450

-

0.33

-390

-

0.33

-360

-

0.33

-330

-

0.33

-310

-

DQS_t and DQS_c low-impedance time

(Referenced from RL-1)

225

0.54

0.27

TBD

-

195

0.54

0.27

TBD

-

180

0.54

0.27

TBD

-

175

0.54

0.27

TBD

-

170

0.54

0.27

TBD

-

DQS_t and DQS_c high-impedance time

(Referenced from RL+BL/2)

ps

DQS_t, DQS_c differential input low pulse

width

0.46

-0.27

TBD

0.18

0.46

-0.27

TBD

0.18

0.46

-0.27

TBD

0.18

0.46

-0.27

TBD

0.18

0.46

-0.27

TBD

0.18

tCK

DQS_t, DQS_c differential input high pulse

width

tDQSH

tDQSS

tDQSS2

tDSS

DQS_t, DQS_c rising edge to CK_t, CK_c

rising edge (1 clock preamble)

42

43

DQS_t, DQS_c rising edge to CK_t, CK_c ris-

ing edge (2 clock preamble)

DQS_t, DQS_c falling edge setup time to

CK_t, CK_c rising edge

DQS_t, DQS_c falling edge hold time from

CK_t, CK_c rising edge

tDSH

-

DQS_t, DQS_c rising edge output timing

locatino from rising CK_t, CK_c with DLL On

mode

tDQSCK

(DLL On)

37,38,3

9

-225

225

370

-195

195

330

-180

180

310

-175

175

290

-170

170

270

ps

DQS_t, DQS_c rising edge output variance

window per DRAM

tDQSCKI

(DLL On)

37,38,3

9

MPSM Timing

tMOD(min

) +

tCP-

tMOD(min

) +

tCP-

tMOD(min

) +

tCP-

Command path disable delay upon MPSM

entry

) +

tCP-

tMPED

-

TBD

-

DED(min)

tMOD(min

) +

tCP-

tMOD(min

) +

tCP-

tMOD(min

) +

tCP-

tMOD(min

) + tCP-

Valid clock requirement after MPSM entry

Valid clock requirement before MPSM exit

tCKMPE

-

DED(min)

tCKSRX(

min)

tCKSRX(

min)

tCKSRX(

min)

tCKSRX(

min)

tCKMPX

tXMP

-

TBD

-

Exit MPSM to commands not requiring a

locked DLL

tXS(min)

tXMP(min

) +

tXS-

tXMP(min

) +

tXS-

tXMP(min

) +

tXS-

tXMP(min

) +

tXS-

Exit MPSM to commands requiring a locked

DLL

tXMPDLL

tMPX_S

-

TBD

-

DLL(min)

tIS(min) +

tIHL(min)

tIS(min) +

tIHL(min)

tIS(min) +

tIHL(min)

tIS(min) +

tIHL(min)

CS setup time to CKE

-

Calibration Timing

Power-up and RESET calibration time

Normal operation Full calibration time

Normal operation Short calibration time

tZQinit

tZQoper

tZQCS

1024

512

-

1024

512

-

1024

512

-

1024

512

-

1024

512

-

nCK

128

Reset/Self Refresh Timing

max

Exit Reset from CKE HIGH to a valid com-

mand

(5nCK,tR

FC(min)+

10ns)

(5nCK,tR

FC(min)+

10ns)

(5nCK,tR

FC(min)+

10ns)

(5nCK,tR

FC(min)+

10ns)

(5nCK,tR

FC(min)+

10ns)

tXPR

tXS

-

nCK

Exit Self Refresh to commands not requiring

a locked DLL

tRFC(min)

+10ns

tRFC(min)

+10ns

tRFC(min)

+10ns

tRFC(min)

+10ns

tRFC(min

)+10ns

-

nCK

SRX to commands not requiring a locked

DLL in Self Refresh ABORT

tXS_ABORT(

min)

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

Exit Self Refresh to ZQCL,ZQCS and MRS

(CL,CWL,WR,RTP and Gear Down)

tXS_FAST

(min)

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

Exit Self Refresh to commands requiring a

locked DLL

tDLLK(mi

n)

tDLLK(mi

n)

tDLLK(mi

n)

tDLLK(mi

n)

tDLLK(mi

n)

tXSDLL

tCKESR

Minimum CKE low width for Self refresh entry

to exit timing

tCKE(min)

+1nCK

tCKE(min)

+1nCK

tCKE(min)

+1nCK

tCKE(min)

+1nCK

tCKE(min

)+1nCK

- 63 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

Speed

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

tCKE(min)

+

1nCK+PL

tCKE(min)

+

1nCK+PL

tCKE(min)

+

1nCK+PL

tCKE(min)

+

1nCK+PL

tCKE(min

)+

1nCK+PL

Minimum CKE low width for Self refresh entry

to exit timing with CA Parity enabled

tCKESR_ PAR

-

nCK

max

(5nCK,10

ns)

max

(5nCK,10

ns)

Valid Clock Requirement after Self Refresh

Entry (SRE) or Power-Down Entry (PDE)

max(5nC

K,10ns)

max(5nC

K,10ns)

max(5nC

K,10ns)

tCKSRE

-

nCK

Valid Clock Requirement after Self Refresh

Entry (SRE) or Power-Down when CA Parity tCKSRE_PAR (5nCK,10

max

(5nCK,10

ns)+PL

max

(5nCK,10

ns)+PL

max

(5nCK,10

ns)+PL

max

(5nCK,10

ns)+PL

is enabled

ns)+PL

Valid Clock Requirement before Self Refresh

Exit (SRX) or Power-Down Exit (PDX) or

Reset Exit

max

(5nCK,10

ns)

max

(5nCK,10

ns)

max(5nC

K,10ns)

max(5nC

K,10ns)

max(5nC

K,10ns)

tCKSRX

Power Down Timing

Exit Power Down with DLL on to any valid

command;Exit Precharge Power Down with

DLL frozen to commands not requiring a

locked DLL

max

(4nCK,6n

s)

max

(4nCK,6n

s)

max

(4nCK,6n

s)

max

(4nCK,6n

s)

max

(4nCK,6n

s)

tXP

-

nCK

max

(3nCK,

5ns)

max

(3nCK,

5ns)

max

(3nCK,

5ns)

max

(3nCK,

5ns)

max

(3nCK,

5ns)

CKE minimum pulse width

tCKE

-

31,32

Command pass disable delay

tCPDED

tPD

4

-

nCK

tCKE(min

)

Power Down Entry to Exit Timing

tCKE(min)

9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI

9*tREFI

6

7

Timing of ACT command to Power Down

entry

tACTPDEN

tPRPDEN

tRDPDEN

1

-

1

-

2

-

2

-

2

-

nCK

Timing of PRE or PREA command to Power

Down entry

Timing of RD/RDA command to Power Down

entry

RL+4+1

WL+4+(t

WR/

tCK(avg))

WL+4+(t

WR/

tCK(avg))

WL+4+(t

WR/

tCK(avg))

WL+4+(t

WR/

tCK(avg))

WL+4+(t

WR/

tCK(avg))

Timing of WR command to Power Down

entry (BL8OTF, BL8MRS, BC4OTF)

tWRPDEN

-

nCK

4

5

4

Timing of WRA command to Power Down

entry (BL8OTF, BL8MRS, BC4OTF)

WL+4+W

R+1

WL+4+W

R+1

WL+4+W

R+1

WL+4+W

R+1

WL+4+W

R+1

tWRAPDEN

WL+2+(t

WR/

tCK(avg))

WL+2+(t

WR/

tCK(avg))

WL+2+(t

WR/

tCK(avg))

WL+2+(t

WR/

tCK(avg))

WL+2+(t

WR/

tCK(avg))

Timing of WR command to Power Down

entry (BC4MRS)

tWRP-

BC4DEN

Timing of WRA command to Power Down

entry (BC4MRS)

tWRAP-

BC4DEN

WL+2+W

R+1

WL+2+W

R+1

WL+2+W

R+1

WL+2+W

R+1

WL+2+W

R+1

-

nCK

5

7

Timing of REF command to Power Down

entry

tREFPDEN

tMRSPDEN

1

2

Timing of MRS command to Power Down

entry

tMOD(min

)

tMOD(min

)

tMOD(min

)

tMOD(min

)

tMOD(mi

n)

PDA Timing

Mode Register Set command cycle time in

PDA mode

max(16nC

K,10ns)

max(16nC

K,10ns)

max(16nC

K,10ns)

max(16n

CK,10ns)

tMRD_PDA

tMOD_PDA

-

nCK

K,10ns)

tMOD

Mode Register Set command update delay in

PDA mode

tMOD

ODT Timing

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

tAONAS

1.0

9.0

1.0

9.0

1.0

9.0

1.0

9.0

1.0

9.0

ns

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

tAOFAS

tADC

1.0

0.3

9.0

0.7

1.0

0.3

9.0

0.7

1.0

0.3

9.0

0.7

1.0

0.3

9.0

0.7

1.0

0.3

9.0

0.7

ns

RTT dynamic change skew

tCK(avg)

Write Leveling Timing

First DQS_t/DQS_n rising edge after write

leveling mode is programmed

tWLMRD

40

25

-

40

25

-

40

25

-

40

25

-

40

25

-

nCK

12

DQS_t/DQS_n delay after write leveling

mode is programmed

tWLDQSEN

Write leveling setup time from rising CK_t,

CK_c crossing to rising DQS_t/DQS_n cross-

ing

tWLS

tWLH

0.13

-

0.13

-

0.13

-

0.13

-

0.13

-

tCK(avg)

Write leveling hold time from rising DQS_t/

DQS_n crossing to rising CK_t, CK_ crossing

Write leveling output delay

Write leveling output error

tWLO

0

9.5

2

0

9.5

2

0

9.5

2

0

9.5

2

0

9.5

2

ns

tWLOE

CA Parity Timing

Commands not guaranteed to be executed

during this time

tPAR_UN-

KNOWN

-

PL

-

PL

-

PL

-

PL

-

PL

nCK

Delay from errant command to ALERT_n

assertion

tPAR_ALERT

_ON

PL+6ns

- 64 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

Speed

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

DDR4-2666

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Pulse width of ALERT_n signal when

asserted

tPAR_ALERT

_PW

48

96

56

-

112

64

128

72

-

144

80

160

nCK

Time from when Alert is asserted till control-

ler must start providing DES commands in

Persistent CA parity mode

tPAR_ALERT

_RSP

-

43

50

-

57

64

71

nCK

Parity Latency

PL

4

5

CRC Error Reporting

CRC error to ALERT_n latency

CRC ALERT_n pulse width

tCRC_ALERT

3

6

13

10

3

6

13

10

3

6

13

10

3

6

13

10

3

6

13

10

ns

CRC_ALERT_

PW

nCK

Geardown timing

Exit RESET from CKE HIGH to a valid MRS

geardown (T2/Reset)

tXPR_GEAR

tXS_GEAR

-

TBD

CKE High Assert to Gear Down Enable

time(T2/CKE)

tSYNC_GEA

R

MRS command to Sync pulse time(T3)

TBD

-

27

Sync pulse to First valid command(T4)

Geardown setup time

tCMD_GEAR

tGEAR_setup

tGEAR_hold

-

TBD

2

-

nCK

Geardown hold time

tREFI

2Gb

4Gb

8Gb

16Gb

2Gb

4Gb

8Gb

16Gb

2Gb

4Gb

8Gb

16Gb

160

260

350

550

110

160

260

350

90

-

160

260

350

550

110

160

260

350

90

-

160

260

350

550

110

160

260

350

90

-

160

260

350

550

110

160

260

350

90

-

160

260

350

550

110

160

260

350

90

-

ns

34

tRFC1 (min)

tRFC2 (min)

tRFC4 (min)

110

160

260

110

160

260

110

160

260

110

160

260

110

160

260

- 65 -

Rev. 1.6

K4A4G045WE

K4A4G085WE

datasheet

DDR4 SDRAM

NOTE :

1. Start of internal write transaction is defined as follows :

For BL8 (Fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL.

For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.

2. A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled

3. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

4. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.

5. WR in clock cycles as programmed in MR0.

6. tREFI depends on TOPER.

7. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be

applied until finishing those operations.

8. For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in clock cycles assuming all input clock jitter

specifications are satisfied

9. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.

10. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.

11. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.

12. The max values are system dependent.

13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER. BER spec and measurement method are

tbd.

14. The deterministic component of the total timing. Measurement method tbd.

15. DQ to DQ static offset relative to strobe per group. Measurement method tbd.

16. This parameter will be characterized and guaranteed by design.

17U When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of the input clock. (output deratings are relative to the

SDRAM input clock). Example tbd.

18. DRAM DBI mode is off.

19. DRAM DBI mode is enabled. Applicable to x8 and x16 DRAM only.

20. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge

21. tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge

22. There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI

23. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge

24. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge

25. Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement method are tbd.

26. The deterministic jitter component out of the total jitter. This parameter is characterized and gauranteed by design.

27. This parameter has to be even number of clocks

28. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.

29. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.

30. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.

31. After CKE is registered LOW, CKE signal level shall be maintained below VILDC for tCKE specification ( Low pulse width ).

32. After CKE is registered HIGH, CKE signal level shall be maintained above VIHDC for tCKE specification ( HIGH pulse width ).

33. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

34. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

35. This parameter must keep consistency with Speed-Bin Tables .

36. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

UI=tCK(avg).min/2

37. applied when DRAM is in DLL ON mode.

38. Assume no jitter on input clock signals to the DRAM

39. Value is only valid for RZQ/7 RONNOM = 34 ohms

40. 1tCK toggle mode with setting MR4:A11 to 0

41. 2tCK toggle mode with setting MR4:A11 to 1, which is valid for DDR4-2400/2666/3200 speed grade.

42. 1tCK mode with setting MR4:A12 to 0

43. 2tCK mode with setting MR4:A12 to 1, which is valid for DDR4-2400/2666/3200 speed grade.

44. The maximum read preamble is bounded by tLZ(DQS)min on the left side and tDQSCK(max) on the right side.

45. DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS diff-signal cross-point

46. last falling edge of DQS diff-signal cross-point to DQ rising signal middle-point of transferring from Low to High

47. VrefDQ value must be set to either its midpoint or Vcent_DQ(midpoint) in order to capture DQ0 or DQL0 low level for entering PDA mode.

48. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side.

49. Reference level of DQ output signal is specified with a midpoint as a widest part of Output signal eye which should be approximately 0.7 * VDDQ as a center level of the

static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ .

50. For MR7 commands, the minimum delay to a subsequent non-MRS command is 5nCK. .

- 66 -

Rev. 1.6

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datasheet

DDR4 SDRAM

13.5 Rounding Algorithms

Software algorithms for calculation of timing parameters are subject to rounding errors from many sources. For example, a system may use a memory

clock with a nominal frequency of 933.33... MHz, or a clock period of 1.0714... ns. Similarly, a system with a memory clock frequency of 1066.66... MHz

yields mathematically a clock period of 0.9375... ns. In most cases, it is impossible to express all digits after the decimal point exactly, and rounding must

be done because the DDR4 SDRAM specification establishes a minimum granularity for timing parameters of 1 ps.

Rules for rounding must be defined to allow optimization of device performance without violating device parameters. These algorithms rely on results that

are within correction factors on device testing and specification to avoid losing performance due to rounding errors.

These rules are:

•Clock periods such as tCKAVGmin are defined to 1 ps of accuracy; for example, 0.9375... ns is defined as 937 ps and 1.0714... ns is defined as

1071 ps.

•Using real math, parameters like tAAmin, tRCDmin, etc. which are programmed in systems in numbers of clocks (nCK) but expressed in units of

time (in ns) are divided by the clock period (in ns) yielding a unitless ratio, a correction factor of 2.5% is subtracted, then the result is set to the next

higher integer number of clocks:

nCK = ceiling [ (parameter_in_ns / application_tCK_in_ns) - 0.025 ]

•Alternatively, programmers may prefer to use integer math instead of real math by expressing timing in ps, scaling the desired parameter value by

1000, dividing by the application clock period, adding an inverse correction factor of 97.4%, dividing the result by 1000, then truncating down to the

next lower integer value:

nCK = truncate [ {(parameter_in_ps x 1000) / (application_tCK_in_ps) + 974} / 1000 ]

•Either algorithm yields identical results

- 67 -

Rev. 1.6

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datasheet

DDR4 SDRAM

13.6 The DQ Input Receiver Compliance Mask for Voltage and Timing

The DQ input receiver compliance mask for voltage and timing is shown in the figure below. The receiver mask (Rx Mask) defines area the input signal

must not encroach in order for the DRAM input receiver to be expected to be able to successfully capture a valid input signal with BER of 1e-16; any input

signal encroaching within the Rx Mask is subject to being invalid data. The Rx Mask is the receiver property for each DQ input pin and it is not the valid

data-eye.

Figure 24. DQ Receiver(Rx) compliance mask

DQx

DQz

DQy

(Largest Vref_DQ Level)

(Smallest Vref_DQ Level)

Vcent_DQz

Vcent_DQx

Vcent_DQy

Vcent_DQ(midpoint)

Vref variation

(Component)

Figure 25. Vcent_DQ Variation to Vcent_DQ(midpoint)

The Vref_DQ voltage is an internal reference voltage level that shall be set to the properly trained setting, which is generally Vcent_DQ(midpoint), in order

to have valid Rx Mask values.

Vcent_DQ is defined as the midpoint between the largest Vref_DQ voltage level and the smallest Vref_DQ voltage level across all DQ pins for a given

DDR4 DRAM component Each DQ pin Vref level is defined by the center, i.e. widest opening, of the cumulative data input eye as depicted in

Figure 25.This clarifies that any DDR4 DRAM component level variation must be accounted for within the DDR4 DRAM Rx mask.The component level

Vref will be set by the system to account for Ron and ODT settings.

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Rev. 1.6

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DDR4 SDRAM

DQS, DQs Data-in at DRAM Ball

Rx Mask

Rx Mask - Alternative View

DQS_t

DQS_c

DQS_t

DQS_c

0.5xTdiVW 0.5xTdiVW

DRAMa

Rx Mask

DQx-z

TdiVW

t_DQS2DQ+ 0.5 x TdiVW

t_DQS2DQ

Rx Mask

DRAMb

DQy

DRAMb

DQy

Rx Mask

TdiVW

t_DQ2DQ

Rx Mask

DRAMb

DQz

DRAMb

DQz

Rx Mask

TdiVW

t_DQ2DQ

t_DQS2DQ+ 0.5 x TdiVW

t_DQS2DQ

Rx Mask

DRAMc

DQz

DRAMc

DQz

Rx Mask

TdiVW

t_DQ2DQ

Rx Mask

DRAMc

DQy

DRAMc

DQy

Rx Mask

TdiVW

t_DQ2DQ

NOTE : DQx represents an optimally centered mask.

DQy represents earliest valid mask.

NOTE : DRAMa represents a DRAM without any DQS/DQ skews.

DRAMb represents a DRAM with early skews (negative t_DQS2DQ).

DRAMc represents a DRAM with delayed skews (positive tDQS2DQ).

DQz represents latest valid mask.

.

NOTE : Figures show skew allowed between DRAM to DRAM and DQ to DQ for a DRAM. Signals assume data centered aligned at DRAM Latch.

TdiPW is not shown; composite data-eyes shown would violate TdiPW.

VCENT DQ(midpoint) is not shown but is assummed to be midpoint of VdiVW..

Figure 26. DQS to DQ and DQ to DQ Timings at DRAM Balls

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Rev. 1.6

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datasheet

DDR4 SDRAM

All of the timing terms in Figure 26 are measured at the VdIVW levels centered around Vcent_DQ(midpoint) and are referenced to the DQS_t/DQS_c

center aligned to the DQ per pin.

The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement points for a rising edge are shown in Figure 27 below: A low to high

transition tr1 is measured from 0.5*VdiVW(max) below Vcent_DQ(midpoint) to the last transition through 0.5*VdiVW(max) above Vcent_DQ(midpoint)

while tr2 is measured from the last transition through 0.5*VdiVW(max) above Vcent_DQ(midpoint) to the first transition through the 0.5*VIHL_AC(min)

above Vcent_DQ(midpoint).

Rising edge slew rate equations:

srr1 = VdIVW(max) / tr1

srr2 = (VIHL_AC(min) – VdIVW(max)) / (2*tr2)

t

r2

0.5*VdiVW(max)

Vcent_DQ(midpoint)

0.5*VdiVW(max)

Rx Mask

t

r1

Figure 27. Slew Rate Conditions For Rising Transition

The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement points for a falling edge are shown in Figure 28 B below: A high to

low transition tf1 is measured from 0.5*VdiVW(max) above Vcent_DQ(midpoint) to the last transition through 0.5*VdiVW(max) below Vcent_DQ(midpoint)

while tf2 is measured from the last transition through 0.5*VdiVW(max) below Vcent_DQ(midpoint) to the first transition through the 0.5*VIHL_AC(min)

below Vcent_DQ(pin mid).

Falling edge slew rate equations:

srf1 = VdIVW(max) / tf1

srf2 = (VIHL_AC(min) – VdIVW(max)) / (2*tf2)

t

r1

0.5*VdiVW(max)

Vcent_DQ(midpoint)

0.5*VdiVW(max)

Rx Mask

t

r2

Figure 28. Slew Rate Conditions For Falling Transition

- 70 -

Rev. 1.6

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datasheet

DDR4 SDRAM

[ Table 54 ] DRAM DQs In Receive Mode; * UI=tck(avg)min/2

1600/1866/2133

2400

2666

Symbol Parameter

Unit

NOTE

min

max

min

max

min

max

136

VdIVW

Rx Mask voltage - pk-pk

-

130

-

120

mV

UI*

mV

UI*

1,2,10

0.2

-

TdIVW

Rx timing window

-

186

-

0.2

-

0.22

-

1,2,10

3,4,10

5,10

6, 10

7

VIHL_AC

TdIPW

DQ AC input swing pk-pk

DQ input pulse width

160

150

0.58

-0.17

-

0.58

-0.17

-

0.58

-

tDQS2DQ

tDQ2DQ

Rx Mask DQS to DQ offset

Rx Mask DQ to DQ offset

Input Slew Rate over VdIVW if tCK >= 0.935ns

0.17

tbd

9

-0.19

0.19

tbd

9

1.0

1

V/ns 8,10

V/ns 9,10

srr1, srf1

srr2

Input Slew Rate over

VdIVW if 0.935ns > tCK >= 0.625ns

-

1.25

9

Rising Input Slew Rate

over 1/2 VIHL_AC

0.2*srr1

0.2*srf1

9

0.2*srr1

0.2*srf1

9

0.2*srr1

Falling Input Slew Rate

over 1/2 VIHL_AC

srf2

9

NOTE :

1. Data Rx mask voltage and timing total input valid window where VdIVW is centered around Vcent_DQ( midpoint) after VrefDQ training is completed. The data Rx mask is

applied per bit and should include voltage and temperature drift terms. The input buffer design specification is to achieve at least a BER = e-16 when the RxMask is not vio-

lated. The BER will be characterized and extrapolated if necessary using a dual dirac method from a higher BER(tbd).

2. Defined over the DQ internal Vref range 1.

3. See Overshoot and Undershoot Specification.

4. DQ input pulse signal swing into the receiver must meet or exceed VIHL AC(min). . VIHL_AC(min) is to be achieved on an UI basis when a rising and falling edge occur in

the same UI, i.e. a valid TdiPW.

5. DQ minimum input pulse width defined at the Vcent_DQ( midpoint).

6. DQS to DQ offset is skew between DQS and DQs within a nibble (x4) or word (x8, x16) at the DDR4 SDRAM balls over process, voltage, and temperature.

7. DQ to DQ offset is skew between DQs within a nibble (x4) or word (x8, x16) at the DDR4 SDRAM balls for a given component over process, voltage, and temperature.

8. Input slew rate over VdIVW Mask centered at Vcent_DQ( midpoint). Slowest DQ slew rate to fastest DQ slew rate per transition edge must be within 1.7 V/ns of each other.

9. Input slew rate between VdIVW Mask edge and VIHL_AC(min) points.

10. All Rx Mask specifications must be satisfied for each UI. For example, if the minimum input pulse width is violated when satisfying TdiVW(min), VdiVW(max), and minimum

slew rate limits, then either TdiVW(min) or minimum slew rates would have to be increased to the point where the minimum input pulse width would no longer be violated.

- 71 -

Rev. 1.6

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datasheet

DDR4 SDRAM

13.7 DDR4 Function Matrix

DDR4 SDRAM has several features supported by ORG and also by Speed. The following Table is the summary of the features.

[ Table 55 ] Function Matrix (By ORG. V:Supported, Blank:Not supported)

Functions

x4

x8

x16

NOTE

V

Write Leveling

Temperature controlled Refresh

Low Power Auto Self Refresh

Fine Granularity Refresh

Multi Purpose Register

Data Mask

Data Bus Inversion

TDQS

V

ZQ calibration

DQ Vref Training

Per DRAM Addressability

Mode Register Readout

CAL

WRITE CRC

CA Parity

Control Gear Down Mode

Programmable Preamble

Maximum Power Down Mode

Boundary Scan Mode

Additive Latency

V

3DS

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Rev. 1.6

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DDR4 SDRAM

[ Table 56 ] Function Matrix (By Speed. V:Supported, Blank:Not supported)

DLL Off mode

DLL On mode

2400Mbps

Functions

equal or slower

than

1600/1866/2133

Mbps

2666Mbps

NOTE

250Mbps

V

Write Leveling

Temperature controlled Refresh

Low Power Auto Self Refresh

Fine Granularity Refresh

Multi Purpose Register

Data Mask

Data Bus Inversion

TDQS

V

ZQ calibration

DQ Vref Training

Per DRAM Addressability

Mode Register Readout

CAL

V

WRITE CRC

CA Parity

Control Gear Down Mode

Programmable Preamble ( = 2tCK)

Maximum Power Down Mode

Boundary Scan Mode

3DS

V

- 73 -


型号：	K4A4G085WE-BCRC
厂家：	SAMSUNG
描述：	4Gb E-die DDR4 SDRAM 动态存储器双倍数据速率
文件：	总73页 (文件大小：1689K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4A4G085WE-BCRC [SAMSUNG]

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