K4B2G0446D-HCMA_技术文档

Rev. 1.1, Sep. 2010

K4B2G0446D

K4B2G0846D

2Gb D-die DDR3 SDRAM

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

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- 1 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

Revision History

Revision No.

History

Draft Date

Aug. 2010

Sep. 2010

Remark

Editor

S.H.Kim

1.0

1.1

- First SPEC. Release

-

- Corrected IDD current spec.(IDD7)

- 2 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

1. Ordering Information

[ Table 1 ] Samsung 2Gb DDR3 D-die ordering information table

DDR3-1333 (9-9-9)⁴

K4B2G0446D-HCH9

K4B2G0846D-HCH9

DDR3-1600 (11-11-11)³

K4B2G0446D-HCK0

K4B2G0846D-HCK0

DDR3-1866 (13-13-13)²

K4B2G0446D-HCMA

K4B2G0846D-HCMA

DDR3-1066 (7-7-7)

Package

Organization

512Mx4

K4B2G0446D-HCF8

K4B2G0846D-HCF8

78 FBGA

256Mx8

NOTE :

1. Speed bin is in order of CL-tRCD-tRP.

2. Backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

3. Backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

4. Backward compatible to DDR3-1066(7-7-7)

2. Key Features

[ Table 2 ] 2Gb DDR3 D-die Speed bins

DDR3-800

6-6-6

2.5

DDR3-1066

7-7-7

DDR3-1333

DDR3-1600

11-11-11

1.25

DDR3-1866

13-13-13

1.07

Speed

Unit

9-9-9

1.5

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

1.875

7

ns

nCK

ns

6

9

11

13

15

13.125

37.5

13.5

36

13.75

35

13.91

34

15

ns

tRAS(min)

tRC(min)

37.5

52.5

ns

50.625

49.5

48.75

47.91

ns

•

JEDEC standard 1.5V ± 0.075V Power Supply

V_DDQ= 1.5V ± 0.075V

The 2Gb DDR3 SDRAM D-die is organized as a 64Mbit x 4 I/Os x 8banks

or 32Mbit x 8 I/Os x 8banks device. This synchronous device achieves high

speed double-data-rate transfer rates of up to 1866Mb/sec/pin (DDR3-

1866) for general applications.

•

400 MHz f_CKfor 800Mb/sec/pin, 533MHz f_CKfor 1066Mb/sec/pin,

667MHz f_CKfor 1333Mb/sec/pin, 800MHz f_CKfor 1600Mb/sec/pin,

900MHz f_CKfor 1866Mb/sec/pin,

The chip is designed to comply with the following key DDR3 SDRAM fea-

tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,

On Die Termination using ODT pin and Asynchronous Reset .

•

8 Banks

Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13

Programmable Additive Latency: 0, CL-2 or CL-1 clock

Programmable CAS Write Latency (CWL) = 5(DDR3-800),

6(DDR3-1066), 7(DDR3-1333), 8(DDR3-1600) and 9(DDR3-1866)

All of the control and address inputs are synchronized with a pair of exter-

nally supplied differential clocks. Inputs are latched at the crosspoint of dif-

ferential clocks (CK rising and CK falling). All I/Os are synchronized with a

pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-

ion. The address bus is used to convey row, column, and bank address

information in a RAS/CAS multiplexing style. The DDR3 device operates

•

8-bit pre-fetch

Burst Length: 8 (Interleave without any limit, sequential with starting

address “000” only), 4 with tCCD = 4 which does not allow seamless

read or write [either On the fly using A12 or MRS]

•

Bi-directional Differential Data-Strobe

Internal(self) calibration : Internal self calibration through ZQ pin

(RZQ : 240 ohm ± 1%)

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower than T_CASE85°C, 3.9us at

85°C < T_CASE< 95 °C

with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V_DDQ

The 2Gb DDR3 D-die device is available in 78ball FBGAs(x4/x8).

.

•

Asynchronous Reset

Package : 78 balls FBGA - x4/x8

All of Lead-Free products are compliant for RoHS

All of products are Halogen-free

NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing

Diagram”.

2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.

- 5 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

3. Package pinout/Mechanical Dimension & Addressing

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package

1

2

3

4

5

6

7

8

9

V_SS

V_DD

V_SS

V_DD

V_DDQ

V_SSQ

V_DDQ

NC

A

B

C

D

E

F

NC

DQ0

DQS

NC

DM

A

B

C

D

E

F

V_SSQ

V_DDQ

V_SSQ

V_REFDQ

NC

DQ2

NC

V_DDQ

V_SS

V_DD

CS

DQ1

V_DD

DQ3

V_SS

NC

CK

NC

V_SS

V_DD

RAS

CAS

WE

BA2

A0

G

H

J

ODT

NC

V_SS

CK

A10/AP

NC

CKE

NC

V_SS

G

H

J

ZQ

V_REFCA

BA0

A3

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

K

L

A12/BC

A1

BA1

A4

K

L

A5

A2

M

N

A7

A9

A11

A6

M

N

RESET

A13

A14

A8

1

2

3

4

5

6

7

8

9

Ball Locations (x4)

A

B

C

D

E

F

Populated ball

Ball not populated

G

H

J

Top view

(See the balls through the package)

K

L

M

N

- 6 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package

1

2

3

4

5

6

7

8

9

V_SS

V_DD

V_SS

V_DD

V_DDQ

V_SSQ

V_DDQ

NC

A

B

C

D

E

F

NC

DQ0

DQS

DQ4

RAS

CAS

WE

NU/TDQS

DM/TDQS

DQ1

A

B

C

D

E

F

V_SSQ

V_DDQ

V_SSQ

V_REFDQ

NC

DQ2

DQ6

V_DDQ

V_SS

DQ3

V_SS

V_DD

DQ7

CK

DQ5

V_SS

V_DD

CS

BA0

A3

G

H

J

ODT

NC

V_SS

CK

A10/AP

NC

CKE

NC

V_SS

G

H

J

ZQ

V_REFCA

BA2

A0

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

K

L

A12/BC

A1

BA1

A4

K

L

A5

A2

M

N

A7

A9

A11

A6

M

N

RESET

A13

A14

A8

1

2

3

4

5

6

7

8

9

Ball Locations (x8)

A

B

C

D

E

F

Populated ball

Ball not populated

G

H

J

K

L

Top view

(See the balls through the package)

M

N

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K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

3.3 FBGA Package Dimension (x4/x8)

Units : Millimeters

7.50 ± 0.10

0.80 x 8 = 6.40

A

#A1 INDEX MARK

B

0.80

(Datum A)

(Datum B)

1.60

6

3.20

3

9

8

7

5

4

2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

(0.95)

78 - ∅0.45 Solder ball

(Post Reflow ∅0.50 ± 0.05)

MOLDING AREA

(1.90)

0.2

M

A B

BOTTOM VIEW

7.50 ± 0.10

#A1

0.35 ± 0.05

1.10 ± 0.10

TOP VIEW

- 8 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

4. Input/Output Functional Description

[ Table 3 ] Input/Output function description

Symbol

Type

Function

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of

the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK

CK, CK

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and

output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or

Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After V_REFCAhas become

stable during the power on and initialization sequence, it must be maintained during all operations (including Self-

Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT

and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.

CKE

CS

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on

systems with multiple Ranks. CS is considered part of the command code.

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When

enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode

Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-

grammed to disable ODT.

ODT

RAS, CAS, WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-

dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of

DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.

DM

(DMU), (DML)

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being

applied. Bank address also determines if the mode register or extended mode register is to be accessed during a

MRS cycle.

BA0 - BA2

A0 - A14

Input

Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands

to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,

see below)

The address inputs also provide the op-code during Mode Register Set commands.

Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-

formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)

A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or

all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.

A10 / AP

A12 / BC

Input

Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-

formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details

Input

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.

RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and

20% of V_DD, i.e. 1.20V for DC high and 0.30V for DC low.

RESET

DQ

Input/Output Data Input/ Output: Bi-directional data bus.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the

x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data

Input/Output strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif-

ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and

does not support single-ended.

DQS, (DQS)

Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in

MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When

TDQS, (TDQS)

Output

disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/

x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.

NC

No Connect: No internal electrical connection is present.

V_DDQ

Supply

DQ Power Supply: 1.5V +/- 0.075V

DQ Ground

V_SSQ

V_DD

Power Supply: 1.5V +/- 0.075V

Ground

V_SS

V_REFDQ

V_REFCA

ZQ

Reference voltage for DQ

Reference voltage for CA

Reference Pin for ZQ calibration

NOTE : Input only pins (BA0-BA2, A0-A14, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.

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Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

5. DDR3 SDRAM Addressing

1Gb

Configuration

# of Bank

256Mb x 4

8

128Mb x 8

8

64Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

A0 - A13

A0 - A9,A11

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A13

A0 - A9

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A12

A0 - A9

A12/BC

2 KB

Column Address

BC switch on the fly

Page size ^*1

2Gb

Configuration

# of Bank

512Mb x 4

8

256Mb x 8

8

128Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

A0 - A14

A0 - A9,A11

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A14

A0 - A9

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A13

A0 - A9

A12/BC

2 KB

Column Address

BC switch on the fly

Page size ^*1

4Gb

Configuration

# of Bank

1Gb x 4

8

512Mb x 8

8

256Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

A0 - A15

A0 - A9,A11

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A15

A0 - A9

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A14

A0 - A9

A12/BC

2 KB

Column Address

BC switch on the fly

Page size ^*1

8Gb

Configuration

# of Bank

2Gb x 4

8

1Gb x 8

8

512Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

BA0 - BA2

A10/AP

A0 - A15

A0 - A9,A11

A12/BC

2 KB

BA0 - BA2

A10/AP

A0 - A15

A0 - A9

A12/BC

2 KB

A0 - A15

A0 - A9,A11,A13

A12/BC

Column Address

BC switch on the fly

Page size ^*1

2 KB

NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.

COLBITS

Page size is per bank, calculated as follows:

page size = 2

* ORG÷8

where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

- 10 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

6. Absolute Maximum Ratings

6.1 Absolute Maximum DC Ratings

[ Table 4 ] Absolute Maximum DC Ratings

Symbol

Parameter

Rating

Units

NOTE

V_DD

Voltage on V_DDpin relative to Vss

-0.4 V ~ 1.975 V

-55 to +100

V

1,3

V_DDQ

Voltage on V_DDQpin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

V

1,3

1

V

_IN,V_OUT

T_STG

°C

1, 2

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. V and V

must be within 300mV of each other at all times; and V

must be not greater than 0.6 x V

, When V and V

are less than 500mV; V

may be

DD

DDQ

REF

DDQ

DD

DDQ

REF

equal to or less than 300mV.

6.2 DRAM Component Operating Temperature Range

[ Table 5 ] Temperature Range

Symbol

Parameter

rating

Unit

NOTE

T_OPER

Operating Temperature Range

0 to 95

°C

1, 2, 3

NOTE :

1. Operating Temperature T

JESD51-2.

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

tained between 0-85°C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the

following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI

to 7.8us) in the Extended Temperature Range.

b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0 and MR2 A7 = 1 ), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

b

7. AC & DC Operating Conditions

7.1 Recommended DC operating Conditions (SSTL_1.5)

[ Table 6 ] Recommended DC Operating Conditions

Rating

Typ.

1.5

Symbol

Parameter

Units

NOTE

Min.

1.425

Max.

1.575

V_DD

Supply Voltage

Supply Voltage for Output

V

1,2

V_DDQ

1.5

NOTE :

1. Under all conditions V

must be less than or equal to V

.

DDQ

DD

2. V

tracks with V . AC parameters are measured with V and V

tied together.

DDQ

DD

- 11 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

8. AC & DC Input Measurement Levels

8.1 AC & DC Logic input levels for single-ended signals

[ Table 7 ] Single-ended AC & DC input levels for Command and Address

DDR3-1066/1333/1600

Symbol

Parameter

Unit NOTE

Min.

Max.

V_IH.CA(DC100)

V_REF+ 100

V_DD

DC input logic high

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

mV

1,5

V

_IL.CA(DC100)

_IH.CA(AC175)

_IL.CA(AC175)

_IH.CA(AC150)

_IL.CA(AC150)

V_SS

V_REF- 100

1,6

V

V_REF+ 175

Note 2

1,2,7

1,2,8

1,2,7

1,2,8

V

V_REF- 175

Note 2

V

V_REF+150

Note 2

V

V_REF-150

Note 2

Reference Voltage for ADD,

CMD inputs

V

_REFCA(DC)

0.49*V_DD

0.51*V_DD

V

3,4

NOTE :

1. For input only pins except RESET, V

= V

(DC)

REF

REFCA

2. See ’Overshoot/Undershoot Specification’ on page 19.

3. The AC peak noise on V may not allow V to deviate from V

(DC) by more than ± 1% V (for reference : approx. ± 15mV)

REF

DD

REF

DD

4. For reference : approx. V /2 ± 15mV

5. V (dc) is used as a simplified symbol for V

(DC100)

IH

IH.CA

IL.CA

IH.CA

6. V (dc) is used as a simplified symbol for V

(DC100)

IL

7. V (ac) is used as a simplified symbol for V

IH

(AC175) and V

(AC150); V

(AC175) value is used when V

+ 175mV is referenced and V

(AC150) value is

IH.CA

REF

used when VREF + 150mV is referenced.

8. V (ac) is used as a simplified symbol for V

(AC175) and V

(AC150); V

(AC175) value is used when V

- 175mV is referenced and V (AC150) value is used

IL.CA

IL

IL.CA

REF

when V

- 150mV is referenced.

REF

[ Table 8 ] Single-ended AC & DC input levels for DQ and DM

DDR3-1066

DDR3-1333/1600

DDR3-1866

Symbol

Parameter

Unit NOTE

Min.

Max.

Min.

Max.

Min.

V_REF+ 100

Max.

V_DD

V_IH.DQ(DC100)

V_REF+ 100

V_DD

V_REF+ 100

V_DD

DC input logic high

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

mV

1,5

V

_IL.DQ(DC100)

_IH.DQ(AC175)

_IL.DQ(AC175)

_IH.DQ(AC150)

_IL.DQ(AC150)

_IH.DQ(AC135)

_IL.DQ(AC135)

V_SS

V_REF- 100

V_SS

V_REF- 100

V_SS

V_REF- 100

1,6

V

V_REF+ 175

NOTE 2

-

1,2,7

1,2,8

1,2,7

1,2,8

1,2,7

1,2,8

V

V_REF- 175

NOTE 2

-

V

V_REF+ 150

NOTE 2

V_REF- 150

-

V

V_REF- 150

NOTE 2

-

V

V_REF+ 135

-

NOTE 2

V_REF- 135

V

NOTE 2

Reference Voltage for DQ,

DM inputs

V_REF_DQ(DC)

0.49*V_DD

0.51*V_DD

0.49*V_DD

0.51*V_DD

0.49*V_DD

0.51*V_DD

V

3,4

NOTE :

1. For input only pins except RESET, V

= V

(DC)

REF

REFDQ

2. See ’Overshoot/Undershoot Specification’ on page 19.

3. The AC peak noise on V

may not allow V

to deviate from V

(DC) by more than ± 1% V (for reference : approx. ± 15mV)

REF DD

REF

DD

REF

4. For reference : approx. V /2 ± 15mV

5. V (dc) is used as a simplified symbol for V

(DC100)

IH

IH.DQ

IL.DQ

6. V (dc) is used as a simplified symbol for V

(DC100)

IL

7. V (ac) is used as a simplified symbol for V

(AC175), V

(AC150) ; V

(AC175) value is used when V

+ 175mV is referenced, V

(AC150) value is used

IH.DQ

IH

IH.DQ

REF

when V

+ 150mV is referenced.

REF

8. V (ac) is used as a simplified symbol for V

(AC175), V

(AC150) ; V

(AC175) value is used when V

- 175mV is referenced, V

(AC150) value is used when

IL

IL.DQ

REF

IL.DQ

V

- 150mV is referenced.

REF

- 12 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

8.2 V Tolerances

REF

The dc-tolerance limits and ac-noise limits for the reference voltages V_REFCAand V_REFDQare illustrate in Figure 1. It shows a valid reference voltage

V

_REF(t) as a function of time. (V_REFstands for V_REFCAand V_REFDQlikewise).

_REF(DC) is the linear average of V_REF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on

page 12. Furthermore V_REF(t) may temporarily deviate from V_REF(DC) by no more than ± 1% V_DD

.

voltage

V_DD

V_SS

time

Figure 1. Illustration of V_REF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements V_IH(AC), V_IH(DC), V_IL(AC) and V_IL(DC) are dependent on V_REF

.

"V_REF" shall be understood as V_REF(DC), as defined in Figure 1 .

This clarifies, that dc-variations of V_REFaffect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

which setup and hold is measured. System timing and voltage budgets need to account for V_REF(DC) deviations from the optimum position within the

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V_REFac-noise. Timing

and voltage effects due to ac-noise on V_REFup to the specified limit (+/-1% of V_DD) are included in DRAM timings and their associated deratings.

- 13 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential signals definition

tDVAC

V_IH.DIFF.AC.MIN

V_IH.DIFF.MIN

0.0

half cycle

V_IL.DIFF.MAX

V_IL.DIFF.AC.MAX

tDVAC

time

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

[ Table 9 ] Differential AC & DC Input Levels

DDR3-1066/1333/1600

Symbol

Parameter

unit

NOTE

min

+0.2

max

NOTE 3

V_IHdiff

V_ILdiff

differential input high

differential input low

V

1

2

NOTE 3

-0.2

V_IHdiff(AC)

2 x (V_IH(AC) - V_REF

NOTE 3

)

differential input high ac

differential input low ac

NOTE 3

V

_ILdiff(AC)

2 x (V_IL(AC) - V_REF)

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK - CK use V /V (AC) of ADD/CMD and V

; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use V /V (AC) of DQs and V ; if a reduced ac-high or ac-low

REFDQ

IH IL

REFCA

IH IL

level is used for a signal group, then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (V (DC) max,

IH

V

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"

IL

[ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

tDVAC [ps] @ |V_IH/Ldiff(AC)| = 350mV

Slew Rate [V/ns]

tDVAC [ps] @ |V_IH/Ldiff(AC)| = 300mV

min

75

57

50

38

34

29

22

13

0

max

min

175

170

167

163

162

161

159

155

150

max

> 4.0

4.0

-

3.0

2.0

1.8

1.6

1.4

1.2

1.0

< 1.0

0

- 14 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

8.3.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for

single-ended signals.

CK and CK have to approximately reach V_SEHmin / V_SELmax [approximately equal to the ac-levels { V_IH(AC) / V_IL(AC)} for ADD/CMD signals] in every

half-cycle.

DQS, DQSL, DQSU, DQS, DQSL have to reach V_SEHmin / V_SELmax [approximately the ac-levels { V_IH(AC) / V_IL(AC)} for DQ signals] in every half-cycle

proceeding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V_IH150(AC)/V_IL150(AC) is used for ADD/CMD sig-

nals, then these ac-levels apply also for the single-ended signals CK and CK .

V_DDor V_DDQ

V_SEHmin

V_SEH

V_DD/2 or V_DDQ/2

CK or DQS

V_SELmax

V_SEL

V_SSor V_SSQ

time

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V_REF, the single-ended components of differential signals have a requirement

with respect to V_DD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

ended components of differential signals the requirement to reach V_SELmax, V_SEHmin has no bearing on timing, but adds a restriction on the common

mode characteristics of these signals.

[ Table 11 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU

DDR3-1066/1333/1600

Symbol

Parameter

Unit

NOTE

Min

Max

(V_DD/2)+0.175

NOTE3

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes

Single-ended low-level for CK, CK

NOTE3

(V_DD/2)-0.175

V

1, 2

V_SEH

V_SEL

NOTE3

NOTE :

1. For CK, CK use V /V (AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use V /V (AC) of DQs.

IH IL

2. V (AC)/V (AC) for DQs is based on V

; V (AC)/V (AC) for ADD/CMD is based on V

; if a reduced ac-high or ac-low level is used for a signal group, then the

REFCA

IH

IL

REFDQ

IH

IL

reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective

limits (V (DC) max, V (DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot

IH

IL

Specification"

- 15 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

8.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input

signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V_IXis measured from the actual

cross point of true and complement signal to the mid level between of V_DDand V_SS

.

V_DD

CK, DQS

V_IX

V_DD/2

V_IX

CK, DQS

V_SS

Figure 4. VIX Definition

[ Table 12 ] Cross point voltage for differential input signals (CK, DQS)

DDR3-1066/1333/1600

Symbol

Parameter

Unit

NOTE

Min

Max

150

175

150

-150

-175

-150

mV

V_IX

Differential Input Cross Point Voltage relative to V_DD/2 for CK,CK

Differential Input Cross Point Voltage relative to V_DD/2 for DQS,DQS

1

NOTE :

1. Extended range for V is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing V

/ V

of at least V /2

SEH DD

IX

SEL

±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to Table 11 on page 15 for V

and V

standard values.

SEL

SEH

8.5 Slew rate definition for Differential Input Signals

See 14.3 “Address/Command Setup, Hold and Derating :” on page 48 for single-ended slew rate definitions for address and command signals.

See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 54 for single-ended slew rate definitions for data signals.

8.6 Slew rate definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5.

[ Table 13 ] Differential input slew rate definition

Measured

Description

Defined by

From

To

V_IHdiffmin- V_ILdiffmax

Delta TRdiff

V_ILdiffmax

V_IHdiffmin

Differential input slew rate for rising edge (CK-CK and DQS-DQS)

V_IHdiffmin- V_ILdiffmax

V_IHdiffmin

V_ILdiffmax

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

Delta TFdiff

NOTE :

The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.

V

IHdiffmin

ILdiffmax

0

V

delta TFdiff

delta TRdiff

Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK

- 16 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

9. AC & DC Output Measurement Levels

9.1 Single-ended AC & DC Output Levels

[ Table 14 ] Single-ended AC & DC output levels

Symbol

Parameter

DDR3-1066/1333/1600

Units

NOTE

V_OH(DC)

DC output high measurement level (for IV curve linearity)

0.8 x V_DDQ

V

_OM(DC)

_OL(DC)

V_OH(AC)

_OL(AC)

DC output mid measurement level (for IV curve linearity)

DC output low measurement level (for IV curve linearity)

AC output high measurement level (for output SR)

AC output low measurement level (for output SR)

0.5 x V_DDQ

0.2 x V_DDQ

V

V_TT+ 0.1 x V_DDQ

V_TT- 0.1 x V_DDQ

1

V

NOTE : 1. The swing of +/-0.1 x V

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

load of 25Ω to V =V

/2.

TT

9.2 Differential AC & DC Output Levels

[ Table 15 ] Differential AC & DC output levels

Symbol

Parameter

DDR3-1066/1333/1600

Units

NOTE

V_OHdiff(AC)

AC differential output high measurement level (for output SR)

+0.2 x V_DDQ

V

1

V

_OLdiff(AC)

AC differential output low measurement level (for output SR)

-0.2 x V_DDQ

V

1

NOTE : 1. The swing of +/-0.2xV

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

load of 25Ω to V =V

/2 at each of the differential outputs.

TT

9.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V_OL(AC) and V_OH(AC)

for single ended signals as shown in Table 16 and Figure 6.

[ Table 16 ] Single-ended output slew rate definition

Measured

Description

Defined by

From

To

V_OH(AC)-V_OL(AC)

Delta TRse

V_OL(AC)

V_OH(AC)

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

V_OH(AC)-V_OL(AC)

Delta TFse

V_OH(AC)

V_OL(AC)

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 17 ] Single-ended output slew rate

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Parameter

Symbol

Units

Min

2.5

Max

Min

2.5

Max

Min

2.5

Max

Min

Max

5¹⁾

Single ended output slew rate

Description : SR : Slew Rate

SRQse

5

2.5

V/ns

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals

For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ

signals in the same byte lane are static (i.e they stay at either high or low).

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the

remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

V

OH(AC)

V

TT

OL(AC)

delta TFse

delta TRse

Figure 6. Single-ended Output Slew Rate Definition

- 17 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

9.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V_OLdiff(AC) and V_OH-

_diff(AC) for differential signals as shown in Table 18 and Figure 7.

[ Table 18 ] Differential output slew rate definition

Measured

Description

Defined by

From

To

V_OHdiff(AC)-V_OLdiff(AC)

Delta TRdiff

V_OLdiff(AC)

V_OHdiff(AC)

Differential output slew rate for rising edge

Differential output slew rate for falling edge

V_OHdiff(AC)-V_OLdiff(AC)

Delta TFdiff

V_OHdiff(AC)

V_OLdiff(AC)

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 19 ] Differential output slew rate

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Parameter

Symbol

Units

Min

Max

Min

Max

Min

Max

Min

Max

Differential output slew rate

Description : SR : Slew Rate

SRQdiff

5

10

5

10

5

10

5

12

V/ns

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals

For Ron = RZQ/7 setting

V

(AC)

OHdiff

V

TT

OLdiff

delta TFdiff

delta TRdiff

Figure 7. Differential Output Slew Rate Definition

9.5 Reference Load for AC Timing and Output Slew Rate

Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate

measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. Sys-

tem designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their

production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

V_DDQ

DQ

CK/CK

DQS

DUT

V_TT= V_DDQ/2

DQS

25Ω

Reference

Point

Figure 8. Reference Load for AC Timing and Output Slew Rate

- 18 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

9.6 Overshoot/Undershoot Specification

9.6.1 Address and Control Overshoot and Undershoot specifications

[ Table 20 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT)

Specification

Parameter

Unit

DDR3-1066

0.4V

DDR3-1333

0.4V

DDR3-1600

0.4V

DDR3-1866

0.4V

Maximum peak amplitude allowed for overshoot area (See Figure 9)

Maximum peak amplitude allowed for undershoot area (See Figure 9)

Maximum overshoot area above V_DD(See Figure 9)

V

0.4V

0.5V-ns

0.4V-ns

0.33V-ns

0.28V-ns

V-ns

Maximum undershoot area below V_SS(See Figure 9)

0.5V-ns

0.4V-ns

0.33V-ns

0.28V-ns

V-ns

Maximum Amplitude

Overshoot Area

V_DD

V_SS

Volts

(V)

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 9. Address and Control Overshoot and Undershoot Definition

9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications

[ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK)

Specification

Parameter

Unit

DDR3-1066

0.4V

DDR3-1333

0.4V

DDR3-1600

0.4V

DDR3-1866

0.4V

Maximum peak amplitude allowed for overshoot area (See Figure 10)

Maximum peak amplitude allowed for undershoot area (See Figure 10)

Maximum overshoot area above V_DDQ(See Figure 10)

V

0.4V

0.19V-ns

0.15V-ns

0.13V-ns

0.11V-ns

V-ns

Maximum undershoot area below V_SSQ(See Figure 10)

0.19V-ns

0.15V-ns

0.13V-ns

0.11V-ns

V-ns

Maximum Amplitude

Overshoot Area

V_DDQ

V_SSQ

Volts

(V)

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition

- 19 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

9.7 34ohm Output Driver DC Electrical Characteristics

A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ

as follows:

RON₃₄= RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm)

The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows

V_DDQ-V_OUT

under the condition that RONpd is turned off

RONpu =

l Iout l

V_OUT

l Iout l

under the condition that RONpu is turned off

RONpd =

Output Driver

Ipu

V_DDQ

To

RON

other

Pu

circuity

DQ

Iout

RON

Pd

Vout

Ipd

V_SSQ

Figure 11. Output Driver : Definition of Voltages and Currents

[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ;

entire operating temperature range ; after proper ZQ calibration

RONnom

Resistor

Vout

_OLdc= 0.2 x V_DDQ

Min

0.6

0.9

0.6

0.9

0.6

Nom

1.0

Max

1.1

1.4

1.1

1.4

1.1

Units

NOTE

1,2,3

V

_OMdc= 0.5 x V_DDQ

_OHdc= 0.8 x V_DDQ

V_OLdc= 0.2 x V_DDQ

_OMdc= 0.5 x V_DDQ

_OHdc= 0.8 x V_DDQ

_OLdc= 0.2 x V_DDQ

_OMdc= 0.5 x V_DDQ

_OHdc= 0.8 x V_DDQ

V_OLdc= 0.2 x V_DDQ

_OMdc= 0.5 x V_DDQ

_OHdc= 0.8 x V_DDQ

RON34pd

V

34Ohms

RZQ/7

V

RON34pu

RON40pd

RON40pu

V

40Ohms

RZQ/6

%

V

Mismatch between Pull-up and Pull-down,

MMpupd

V

_OMdc= 0.5 x V_DDQ

-10

10

1,2,4

NOTE :

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-

tion, see following section on voltage and temperature sensitivity

2. The tolerance limits are specified under the condition that V

= V and that V

= V

DDQ

DD

SSQ SS

3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X V

. Other calibration schemes may be used to achieve the linearity spec shown

DDQ

above, e.g. calibration at 0.2 X V

and 0.8 X V

DDQ

4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X V

:

DDQ

RONpu - RONpd

x 100

MMpupd

=

RONnom

- 20 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

9.7.1 Output Drive Temperature and Voltage Sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 23 and Table 24.

∆T = T - T(@calibration); ∆V = V_DDQ- V_DDQ(@calibration); V_DD= V_DDQ

*dR_ONdT and dR_ONdV are not subject to production test but are verified by design and characterization

[ Table 23 ] Output Driver Sensitivity Definition

Min

Max

Units

RONPU@V_OHDC

RON@V_OMDC

0.6 - dR_ONdTH * |∆T| - dR dVH * |∆V|

1.1 + dR_ONdTH * |∆T| + dR dVH * |∆V|

RZQ/7

ON

0.9 - dR_ONdTM * |∆T| - dR dVM * |∆V|

1.1 + dR_ONdTM * |∆T| + dR dVM * |∆V|

ON

RONPD@_VOLDC

0.6 - dR_ONdTL * |∆T| - dR dVL * |∆V|

1.1 + dR_ONdTL * |∆T| + dR dVL * |∆V|

ON

[ Table 24 ] Output Driver Voltage and Temperature Sensitivity

Speed Bin

DDR3-800/1066/1333

DDR3-1600

Units

Min

0

Max

1.5

Min

0

Max

1.5

dR_ONdTM

dR_ONdVM

dR_ONdTL

dR_ONdVL

dR_ONdTH

dR_ONdVH

%/°C

%/mV

%/°C

0

0.15

1.5

0

0.13

1.5

0

0.15

1.5

0

0.13

1.5

%/mV

%/°C

0

0.15

0

0.13

%/mV

9.8 On-Die Termination (ODT) Levels and I-V Characteristics

On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register.

ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins.

A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as

follows :

V_DDQ-V_OUT

under the condition that RTTpd is turned off

under the condition that RTTpu is turned off

RTTpu =

RTTpd =

l Iout l

V_OUT

l Iout l

Chip in Termination Mode

ODT

V_DDQ

Ipu

Iout=Ipd-Ipu

To

RTT_Pu

other

circuitry

like

DQ

RCV,

Iout

RTT_Pd

...

V_OUT

V_SSQ

Ipd

Figure 12. On-Die Termination : Definition of Voltages and Currents

- 21 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

9.8.1 ODT DC Electrical Characteristics

Table 25 provides and overview of the ODT DC electrical characteristics. They values for RTT_60pd120,RTT_60pu120,RTT_120pd240,RTT_120pu240,RTT_40pd80,

RTT_40pu80,RTT_30pd60,RTT_30pu60,RTT_20pd40,RTT_20pu40are not specification requirements, but can be used as design guide lines:

[ Table 25 ] ODT DC Electrical Characteristics, assuming RZQ=240ohm +/- 1% entire operating temperature range; after proper ZQ calibration

MR1 (A9,A6,A2)

RTT

RESISTOR

Vout

Min

Nom

Max

Unit

R_ZQ

NOTE

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

-5

1.0

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

5

1,2,3,4

1,2,5

RTT_120pd240

R_ZQ

V

_OH(DC) 0.8XV_DDQ

R_ZQ

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

R_ZQ

(0,1,0)

120 ohm

RTT_120pu240

R_ZQ

V

_OH(DC) 0.8XV_DDQ

R_ZQ

RTT₁₂₀

V_IL(AC) to V_IH(AC)

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

R_ZQ/2

R_ZQ/4

R_ZQ/3

R_ZQ/6

R_ZQ/4

R_ZQ/8

R_ZQ/6

R_ZQ/12

1,2,3,4

1,2,5

RTT_60pd240

V

_OH(DC) 0.8XV_DDQ

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

(0,0,1)

(0,1,1)

(1,0,1)

(1,0,0)

60 ohm

40 ohm

30 ohm

20 ohm

RTT_60pu240

RTT₆₀

V

_OH(DC) 0.8XV_DDQ

V_IL(AC) to V_IH(AC)

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

1,2,3,4

1,2,5

RTT_40pd240

V

_OH(DC) 0.8XV_DDQ

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

RTT_40pu240

RTT₄₀

V

_OH(DC) 0.8XV_DDQ

V_IL(AC) to V_IH(AC)

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

1,2,3,4

1,2,5

RTT_60pd240

V

_OH(DC) 0.8XV_DDQ

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

RTT60_pu240

RTT₆₀

V

_OH(DC) 0.8XV_DDQ

V_IL(AC) to V_IH(AC)

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

1,2,3,4

1,2,5

RTT_60pd240

V

_OH(DC) 0.8XV_DDQ

V_OL(DC) 0.2XV_DDQ

0.5XV_DDQ

RTT_60pu240

RTT₆₀

V

_OH(DC) 0.8XV_DDQ

V_IL(AC) to V_IH(AC)

Deviation of V_Mw.r.t V_DDQ/2, ∆VM

%

1,2,5,6

- 22 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-

tion, see following section on voltage and temperature sensitivity

2. The tolerance limits are specified under the condition that V

= V and that V

= V

DDQ

DD

SSQ SS

3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XV

. Other calibration schemes may be used to achieve the linearity spec shown above, e.g.

DDQ

calibration at 0.2XV

and 0.8XV

.

DDQ

4. Not a specification requirement, but a design guide line

5. Measurement definition for RTT:

Apply V (AC) to pin under test and measure current I(V (AC)), then apply V (AC) to pin under test and measure current I(V (AC)) respectively

IH

IL

V_IH(AC) - V_IL(AC)

RTT

=

I(V_IH(AC)) - I(V_IL(AC))

6. Measurement definition for V and ∆V : Measure voltage (V ) at test pin (midpoint) with no load

M

2 x V_M

V_DDQ

- 1

x 100

∆ V_M

=

9.8.2 ODT Temperature and Voltage sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to table below

∆T = T - T(@calibration); ∆V = V_DDQ- V_DDQ(@calibration); V_DD= V_DDQ

[ Table 26 ] ODT Sensitivity Definition

Min

Max

Units

0.9 - dR_TTdT * |∆T| - dR dV * |∆V|

1.6 + dR_TTdT * |∆T| + dR dV * |∆V|

RTT

RZQ/2,4,6,8,12

TT

[ Table 27 ] ODT Voltage and Temperature Sensitivity

Min

0

Max

1.5

Units

%/°C

dR_TTdT

dR_TTdV

0

0.15

%/mV

NOTE : These parameters may not be subject to production test. They are verified by design and characterization.

- 23 -

Rev. 1.1

K4B2G0446D

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datasheet

DDR3 SDRAM

9.9 ODT Timing Definitions

9.9.1 Test Load for ODT Timings

Different than for timing measurements, the reference load for ODT timings is defined in Figure 13.

V_DDQ

DUT

DQ, DM

CK,CK

V_TT

=

DQS , DQS

V_SSQ

RTT

=25 ohm

TDQS , TDQS

V_SSQ

Timing Reference Points

Figure 13. ODT Timing Reference Load

9.9.2 ODT Timing Definitions

Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided

in Table 29.

[ Table 28 ] ODT Timing Definitions

Symbol

tAON

Begin Point Definition

End Point Definition

Extrapolated point at V_SSQ

Figure

Rising edge of CK - CK defined by the end point of ODTLon

Rising edge of CK - CK with ODT being first registered high

Rising edge of CK - CK defined by the end point of ODTLoff

Rising edge of CK - CK with ODT being first registered low

Figure 14

Figure 15

Figure 16

Figure 17

tAONPD

tAOF

Extrapolated point at V_SSQ

End point: Extrapolated point at V_{RTT_Nom}

tAOFPD

Rising edge of CK - CK defined by the end point of ODTLcnw,

ODTLcwn4 of ODTLcwn8

End point: Extrapolated point at V_{RTT_Wr}and V_{RTT_Nom}

respectively

tADC

Figure 18

[ Table 29 ] Reference Settings for ODT Timing Measurements

Measured

RTT_Nom Setting

RTT_Wr Setting

V_SW1[V]

V_SW2[V]

NOTE

Parameter

R_ZQ/4

R_ZQ/12

R_ZQ/4

NA

0.05

0.10

0.05

0.10

0.05

0.10

0.05

0.10

0.20

0.10

0.20

0.10

0.20

0.10

0.20

0.10

0.20

0.30

tAON

NA

tAONPD

tAOF

R_ZQ/12

R_ZQ/4

NA

R_ZQ/12

R_ZQ/4

NA

tAOFPD

tADC

R_ZQ/12

NA

R_ZQ/2

- 24 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

Begin point : Rising edge of CK - CK

defined by the end point of ODTLon

CK

V

TT

t

AON

T

SW2

T

SW1

DQ, DM

DQS , DQS

TDQS , TDQS

V

SW2

V

SW1

V_SSQ

End point Extrapolated point at V_SSQ

Figure 14. Definition of tAON

Begin point : Rising edge of CK - CK

with ODT being first registered high

CK

V

TT

t

AONPD

T

SW2

T

SW1

DQ, DM

DQS , DQS

TDQS , TDQS

V

SW2

V

SW1

V_SSQ

End point Extrapolated point at V_SSQ

Figure 15. Definition of tAONPD

Begin point : Rising edge of CK - CK

defined by the end point of ODTLoff

CK

V

TT

t

AOF

End point Extrapolated point at V_{RTT_Nom}

V_{RTT_Nom}

T

SW2

T

DQ, DM

SW1

DQS , DQS

V

SW2

V

TDQS , TDQS

SW1

V_SSQ

TD_TAON_DEF

Figure 16. Definition of tAOF

- 25 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

Begin point : Rising edge of CK - CK

with ODT being first registered low

CK

V

TT

t

AOFPD

End point Extrapolated point at V_{RTT_Nom}

V_{RTT_Nom}

T

SW2

T

DQ, DM

SW1

DQS , DQS

V

SW2

V

TDQS , TDQS

SW1

V_SSQ

Figure 17. Definition of tAOFPD

Begin point : Rising edge of CK - CK

defined by the end point of ODTLcnw

Begin point : Rising edge of CK - CK defined by

the end point of ODTLcwn4 or ODTLcwn8

CK

V

TT

t

ADC

End point Extrapolated point at V_{RTT_Nom}

V_{RTT_Nom}

T

SW21

End point

T

DQ, DM

DQS , DQS

TDQS , TDQS

SW22

Extrapolated point

at V_{RTT_Nom}

V

SW2

T

SW11

T

SW12

V

SW1

End point Extrapolated point at V_{RTT_Wr}

V_{RTT_Wr}

V

SSQ

Figure 18. Definition of tADC

- 26 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

10. IDD Current Measure Method

10.1 IDD Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and

IDDQ measurements.

- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and

IDD7) are measured as time-averaged currents with all V_DDballs of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in

IDD currents.

- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all V_DDQballs of the DDR3 SDRAM under test tied

together. Any IDD current is not included in IDDQ currents.

Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO

power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since V_DDand V_DDQ

are using one merged-power layer in Module PCB.

For IDD and IDDQ measurements, the following definitions apply :

- "0" and "LOW" is defined as V_IN<= V_ILAC(max).

- "1" and "HIGH" is defined as V_IN>= V_IHAC(min).

- "FLOATING" is defined as inputs are V_REF= V_DD/ 2.

- "Timing used for IDD and IDDQ Measured - Loop Patterns for 1066/1333" are provided in Table 30

- "Basic IDD and IDDQ Measurement Conditions" are described in Table 32

- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39.

- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting

RON = RZQ/7 (34 Ohm in MR1);

Qoff = 0B (Output Buffer enabled in MR1);

RTT_Nom = RZQ/6 (40 Ohm in MR1);

RTT_Wr = RZQ/2 (120 Ohm in MR2);

TDQS Feature disabled in MR1

- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.

- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}

- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}

- RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms;

During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC

- 27 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 30 ] Timing used for IDD and IDDQ Measured - Loop Patterns for 1066/1333

DDR3-1066

DDR3-1333

Parameter Bin

Unit

6-6-6

7-7-7

1.875

7

8-8-8

7-7-7

8-8-8

9-9-9

10-10-10

tCKmin(IDD)

CL(IDD)

1.5

ns

6

8

7

8

9

10

34

nCK

tRCDmin(IDD)

tRCmin(IDD)

tRASmin(IDD)

tRPmin(IDD)

7

26

27

20

7

28

31

32

33

24

6

8

7

8

9

10

x4/x8

x16

20

27

4

20

30

4

tFAW(IDD)

tRRD(IDD)

x4/x8

x16

6

5

tRFC(IDD) - 512Mb

tRFC(IDD) - 1Gb

tRFC(IDD) - 2Gb

tRFC(IDD) - 4Gb

tRFC(IDD) - 8Gb

48

59

86

160

187

60

74

107

200

234

[ Table 31 ] Timing used for IDD and IDDQ Measured - Loop Patterns for 1600/1866

DDR3-1600

DDR3-1866

11-11-11 12-12-12

Parameter Bin

Unit

8-8-8

9-9-9

10-10-10

11-11-11

10-10-10

13-13-13

tCKmin(IDD)

CL(IDD)

1.25

1.07

ns

8

9

10

38

11

39

10

42

11

43

12

44

13

45

nCK

tRCDmin(IDD)

tRCmin(IDD)

tRASmin(IDD)

tRPmin(IDD)

36

37

28

32

8

9

10

11

10

11

12

13

x4/x8

x16

24

32

5

26

33

tFAW(IDD)

tRRD(IDD)

x4/x8

x16

5

6

tRFC(IDD) - 512Mb

tRFC(IDD) - 1Gb

tRFC(IDD) - 2Gb

tRFC(IDD) - 4Gb

tRFC(IDD) - 8Gb

72

88

128

240

280

85

103

150

281

328

- 28 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

I

DDQ

DD

V

DDQ

DD

RESET

CK/CK

CKE

CS

RAS, CAS, WE

DQS, DQS

DQ, DM,

TDQS, TDQS

R

= 25 Ohm

V

TT

/2

DDQ

A, BA

ODT

ZQ

V

SSQ

SS

[NOTE : DIMM level Output test load condition may be different from above]

Figure 19. Measurement Setup and Test Load for IDD and IDDQ Measurements

Application specific

memory channel

environment

IDDQ

Test Load

Channel

IO Power

Simulation

IDDQ

Measurement

IDDQ

Simulation

Correlation

Correction

Channel IO Power

Number

Figure 20. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.

- 29 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 32 ] Basic IDD and IDDQ Measurement Conditions

Symbol

Description

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: High between ACT and PRE; Command, Address,

Bank Address Inputs: partially toggling according to Table 32 on page 31 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active

1)

IDD0

IDD1

2)

at a time: 0,0,1,1,2,2,... (see Table 32); Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 32

Operating One Bank Active-Read-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: High between ACT, RD and PRE; Command,

Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 on page 32 ; DM:stable at 0; Bank Activity: Cycling with one bank active at

1)

2)

a time: 0,0,1,1,2,2,... (see Table 33); Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 33

Precharge Standby Current

1)

CKE: High; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-

IDD2N

gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

2)

Registers ; ODT Signal: stable at 0; Pattern Details: see Table 34

Precharge Standby ODT Current

1)

CKE: High; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-

IDD2NT

IDDQ2NT

IDD2P0

gling according to Table 35 on page 33 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

2)

Registers ; ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

1)

2)

Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pre-

3)

charge Power Down Mode: Slow Exi

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: see Table 30 on page 28; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

1)

IDD2P1

IDD2Q

IDD3N

IDD3P

2)

Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pre-

3)

charge Power Down Mode: Fast Exit

Precharge Quiet Standby Current

1)

CKE: High; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0

2)

Active Standby Current

1)

CKE: High; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-

gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

2)

Registers ; ODT Signal: stable at 0; Pattern Details: see Table 34

Active Power-Down Current

1)

CKE: Low; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0

2)

Operating Burst Read Current

1)

CKE: High; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: par-

IDD4R

IDDQ4R

IDD4W

tially toggling according to Table 36 on page 33 ; Data IO: seamless read data burst with different data between one burst and the next one according to

Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 12); Output Buffer and

2)

RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 36

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

Operating Burst Write Current

1)

CKE: High; External clock: On; tCK, CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-

tially toggling according to Table 37 on page 34 ; Data IO: seamless write data burst with different data between one burst and the next one according to

Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT:

2)

Enabled in Mode Registers ; ODT Signal: stable at HIGH; Pattern Details: see Table 37

Burst Refresh Current

1)

CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS: High between REF; Command, Address, Bank Address

Inputs: partially toggling according to Table 38 on page 34 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38);

Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 38

IDD5B

IDD6

2)

Self Refresh Current: Normal Temperature Range

4)

e)

TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:

1)

LOW; CL: see Table 30 on page 28 ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-

2)

Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING

- 30 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 32 ] Basic IDD and IDDQ Measurement Conditions

Symbol

Description

Operating Bank Interleave Read Current

1)

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 on page 28 ; BL: 8 ; AL: CL-1; CS: High between ACT and RDA;

Command, Address, Bank Address Inputs: partially toggling according to Table 39 on page 35 ; Data IO: read data bursts with different data between one

burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing,

IDD7

IDD8

2)

see Table 39 ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: see Table 39

RESET Low Current

RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

FLOATING

NOTE :

1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6) Read Burst type : Nibble Sequential, set MR0 A[3]=0B

- 31 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 33 ] IDD0 Measurement - Loop Pattern¹⁾

0

1,2

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

3,4

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

repeat pattern 1...4 until nRC - 1, truncate if necessary

nRAS

0

1

0

00

0

-

...

1*nRC + 0

1*nRC + 1, 2

1*nRC + 3, 4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary

PRE 00

1*nRC + nRAS

...

0

1

0

F

0

repeat 1...4 until 2*nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

- 32 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 34 ] IDD1 Measurement - Loop Pattern¹⁾

0

1,2

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

3,4

...

repeat pattern 1...4 until nRCD- 1, truncate if necessary

RD

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

repeat pattern 1...4 until nRC - 1, truncate if necessary

nRCD

...

0

1

0

1

0

00

0

00000000

-

nRAS

0

1

0

...

1*nRC+0

1*nRC + 1, 2

1*nRC + 3, 4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary

1*nRC + nRCD

...

RD

repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary

PRE 00

0

1

0

1

0

00

0

F

0

00110011

-

1*nRC + nRAS

...

0

1

0

repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

[ Table 35 ] IDD2 and IDD3N Measurement - Loop Pattern¹⁾

0

D

1

0

1

0

1

0

1

0

00

0

F

0

-

1

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

8-11

12-15

16-19

20-23

24-27

28-31

NOTE :

1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

- 33 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 36 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern¹⁾

0

D

1

0

1

0

1

0

1

0

00

0

F

0

-

1

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

8-11

12-15

16-19

20-23

24-27

28-31

NOTE :

1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

[ Table 37 ] IDD4R and IDDQ4R Measurement - Loop Pattern¹⁾

0

RD

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

1

-

2,3

D,D

RD

D

-

4

00110011

5

-

6,7

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

- 34 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 38 ] IDD4W Measurement - Loop Pattern¹⁾

0

WR

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

1

-

2,3

D,D

WR

D

-

4

00110011

5

-

6,7

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

[ Table 39 ] IDD5B Measurement - Loop Pattern¹⁾

0

1

0

1,2

REF

D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

3,4

D,D

5...8

repeat cycles 1...4, but BA[2:0] = 1

repeat cycles 1...4, but BA[2:0] = 2

repeat cycles 1...4, but BA[2:0] = 3

repeat cycles 1...4, but BA[2:0] = 4

repeat cycles 1...4, but BA[2:0] = 5

repeat cycles 1...4, but BA[2:0] = 6

repeat cycles 1...4, but BA[2:0] = 7

9...12

13...16

17...20

21...24

25...28

29...32

33...nRFC - 1

2

repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

- 35 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 40 ] IDD7 Measurement - Loop Pattern¹⁾

0

1

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

-

00000000

-

0

1

2

...

repeat above D Command until nRRD - 1

nRRD

nRRD + 1

nRRD + 2

...

ACT

RDA

D

0

1

0

1

0

1

0

1

0

1

00

0

1

0

F

0

-

00110011

-

repeat above D Command until 2*nRRD-1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 1, but BA[2:0] = 3

2

3

2 * nRRD

3 * nRRD

D

1

0

3

00

0

F

0

-

4

4 * nRRD

Assert and repeat above D Command until nFAW - 1, if necessary

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 1, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 1, but BA[2:0] = 7

5

6

7

8

nFAW

nFAW+nRRD

nFAW+2*nRRD

nFAW+3*nRRD

D

1

0

7

00

0

9

nFAW+4*nRRD

Assert and repeat above D Command until 2*nFAW - 1, if necessary

2*nFAW+0

2*nFAW+1

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

F

0

-

00110011

-

10

2*nFAW+2

Repeat above D Command until 2*nFAW + nRRD - 1

2*nFAW+nRRD

ACT

RDA

D

0

1

0

1

0

1

0

1

0

1

00

0

1

0

-

2*nFAW+nRRD+1

00000000

-

11

2*nFAW+nRRD+2

Repeat above D Command until 2*nFAW + 2*nRRD - 1

repeat Sub-Loop 10, but BA[2:0] = 2

repeat Sub-Loop 11, but BA[2:0] = 3

12

13

2*nFAW+2*nRRD

2*nFAW+3*nRRD

D

1

0

3

00

0

-

14

2*nFAW+4*nRRD

Assert and repeat above D Command until 3*nFAW - 1, if necessary

repeat Sub-Loop 10, but BA[2:0] = 4

repeat Sub-Loop 11, but BA[2:0] = 5

repeat Sub-Loop 10, but BA[2:0] = 6

repeat Sub-Loop 11, but BA[2:0] = 7

15

16

17

18

3*nFAW

3*nFAW+nRRD

3*nFAW+2*nRRD

3*nFAW+3*nRRD

D

1

0

7

00

0

19

3*nFAW+4*nRRD

Assert and repeat above D Command until 4*nFAW - 1, if necessary

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.

- 36 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

11. 2Gb DDR3 SDRAM D-die IDD Specification Table

[ Table 41 ] IDD Specification for 2Gb DDR3 D-die

512Mx4 (K4B2G0446D)

Symbol

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Unit

NOTE

7-7-7

35

45

12

15

17

20

40

17

30

50

35

60

110

12

105

12

9-9-9

40

50

12

15

20

25

40

20

17

35

60

35

70

115

12

125

12

11-11-11

45

13-13-13

50

IDD0

IDD1

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

mA

55

12

15

20

25

40

20

35

70

35

85

120

12

130

12

60

12

17

20

25

40

20

37

90

35

95

120

12

135

12

IDD2NT

IDDQ2NT

IDD2Q

IDD3P

IDD3N

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

IDD7

IDD8

256Mx8 (K4B2G0846D)

Symbol

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Unit

NOTE

7-7-7

35

45

12

15

17

20

70

17

30

65

50

70

110

12

105

12

9-9-9

40

50

12

15

20

25

70

20

17

35

75

50

80

115

12

135

12

11-11-11

45

13-13-13

50

IDD0

IDD1

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

mA

55

12

15

20

25

70

20

35

90

50

95

120

12

140

12

60

12

17

20

25

70

20

37

100

50

110

120

12

145

12

IDD2NT

IDDQ2NT

IDD2Q

IDD3P

IDD3N

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

IDD7

IDD8

- 37 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

12. Input/Output Capacitance

[ Table 42 ] Input/Output Capacitance

DDR3-1066

Min Max

DDR3-1333

Min Max

DDR3-1600

Min Max

DDR3-1866

Parameter

Symbol

Units NOTE

Min

Max

Input/output capacitance

(DQ, DM, DQS, DQS, TDQS, TDQS)

CIO

CCK

1.5 2.7

1.5 2.5

1.5 2.3

1.4

0.8

0

2.2

pF

1,2,3

2,3

Input capacitance

(CK and CK)

0.8

0

1.6

0.15

1.5

0.2

0.3

0.8

0

1.4

0.15

1.3

0.8

0

1.4

0.15

1.3

0.15

1.2

Input capacitance delta

(CK and CK)

CDCK

2,3,4

2,3,6

2,3,5

2,3,7,8

Input capacitance

(All other input-only pins)

CI

0.75

0

0.75

0

0.75

0

Input capacitance delta

(DQS and DQS)

CDDQS

CDI_CTRL

CDI_ADD_CMD

0.15

0.2

0.15

0.2

0.75

-0.4

Input capacitance delta

(All control input-only pins)

-0.5

-0.4

0.2

Input capacitance delta

(all ADD and CMD input-only pins)

0.5

0.4

pF 2,3,9,10

Input/output capacitance delta

(DQ, DM, DQS, DQS, TDQS, TDQS)

CDIO

CZQ

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

pF

2,3,11

Input/output capacitance of ZQ pin

pF 2, 3, 12

NOTE :

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS

2. This parameter is not subject to production test. It is verified by design and characterization.

The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with

V

, V

, V , V

applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). V =V

=1.5V, V

=V /2 and on-die

BIAS DD

DD

DDQ

SS

SSQ

DD

DDQ

termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK

5. Absolute value of CIO(DQS)-CIO(DQS)

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTRL applies to ODT, CS and CKE

8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance on ZQ pin: 5pF

- 38 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

13. Electrical Characteristics and AC timing for DDR3-1066 to DDR3-1866

13.1 Clock Specification

The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3

SDRAM device.

13.1.1 Definition for tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to

rising edge.

N

tCKj

N=200

N

∑

j=1

13.1.2 Definition for tCK(abs)

tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to produc-

tion test.

13.1.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:

tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:

N

tCHj

tCLj

N x tCK(avg) N=200

∑

N x tCK(avg)

N=200

∑

j=1

13.1.4 Definition for note for tJIT(per), tJIT(per, Ick)

tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}

tJIT(per) defines the single period jitter when the DLL is already locked.

tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.

tJIT(per) and tJIT(per,lck) are not subject to production test.

13.1.5 Definition for tJIT(cc), tJIT(cc, Ick)

tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}

tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.

tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

tJIT(cc) and tJIT(cc,lck) are not subject to production test.

13.1.6 Definition for tERR(nper)

tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.

- 39 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

13.2 Refresh Parameters by Device Density

[ Table 43 ] Refresh parameters by device density

Parameter

All Bank Refresh to active/refresh cmd time

Symbol

tRFC

1Gb

110

7.8

2Gb

160

7.8

4Gb

300

7.8

8Gb

350

7.8

Units

ns

NOTE

0 °C ≤ T_CASE≤ 85°C

µs

Average periodic refresh interval

tREFI

85 °C < T_CASE≤ 95°C

3.9

µs

1

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in

this material.

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

[ Table 44 ] DR3-1066 Speed Bins

Speed

CL-nRCD-nRP

DDR3-1066

7 - 7 - 7

Units

NOTE

Parameter

Symbol

tAA

min

max

20

Internal read command to first data

ACT to internal read or write delay time

PRE command period

13.125

50.625

37.5

ns

tRCD

tRP

-

ACT to ACT or REF command period

ACT to PRE command period

tRC

-

tRAS

9*tREFI

1,2,3,4,5,10,

11

CWL = 5

tCK(AVG)

3.0

3.3

ns

CL = 5

CWL = 6

CWL = 5

CWL = 6

CWL = 5

CWL = 6

CWL = 5

CWL = 6

tCK(AVG)

Reserved

ns

4

1,2,3,5

1,2,3,4

4

2.5

CL = 6

CL = 7

CL = 8

Reserved

ns

1.875

<2.5

ns

1,2,3,4,9

4

Reserved

ns

1,2,3

Supported CL Settings

Supported CWL Settings

5,6,7,8

5,6

nCK

- 40 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 45 ] DDR3-1333 Speed Bins

Speed

DDR3-1333

CL-nRCD-nRP

9 -9 - 9

Units

NOTE

Parameter

Symbol

min

max

13.5

Internal read command to first data

tAA

20

ns

(13.125)⁹

13.5

ACT to internal read or write delay time

PRE command period

tRCD

tRP

-

(13.125)⁹

13.5

(13.125)⁹

49.5

ACT to ACT or REF command period

ACT to PRE command period

tRC

tRAS

-

ns

(49.125)⁹

36

9*tREFI

3.3

1,2,3,4,6,10,

11

CWL = 5

tCK(AVG)

3.0

CL = 5

CL = 6

CWL = 6,7

CWL = 5

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5,6

CWL = 7

CWL = 5,6

CWL = 7

tCK(AVG)

Reserved

ns

4

1,2,3,6

1,2,3,4,6

4

2.5

3.3

Reserved

ns

4

CL = 7

CL = 8

1.875

<2.5

ns

1,2,3,4,6

1,2,3,4

4

Reserved

ns

1,2,3,6

1,2,3,4

4

Reserved

ns

CL = 9

1.5

<1.875

ns

1,2,3,4,9

4

Reserved

ns

CL = 10

ns

1,2,3

Supported CL Settings

Supported CWL Settings

5,6,7,8,9

5,6,7

nCK

- 41 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 46 ] DDR3-1600 Speed Bins

Speed

DDR3-1600

CL-nRCD-nRP

11-11-11

Units

NOTE

Parameter

Symbol

min

max

13.75

Internal read command to first data

tAA

20

ns

(13.125)⁹

13.75

ACT to internal read or write delay time

PRE command period

tRCD

tRP

-

(13.125)⁹

13.75

(13.125)⁹

48.75

ACT to ACT or REF command period

ACT to PRE command period

tRC

tRAS

-

ns

(48.125)⁹

35

9*tREFI

3.3

1,2,3,4,7,10,

11

CWL = 5

tCK(AVG)

3.0

CL = 5

CL = 6

CWL = 6,7,8

CWL = 5

CWL = 6

CWL = 7, 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5,6

CWL = 7

CWL = 8

CWL = 5,6

CWL = 7

CWL = 8

CWL = 5,6,7

CWL = 8

tCK(AVG)

Reserved

ns

nCK

4

1,2,3,7

1,2,3,4,7

4

2.5

3.3

Reserved

4

1.875

<2.5

1,2,3,4,7

4

CL = 7

Reserved

4

1,2,3,7

1,2,3,4,7

1,2,3,4

4

CL = 8

CL = 9

Reserved

1.5

<1.875

<1.5

1,2,3,4,7

1,2,3,4

4

Reserved

CL = 10

CL = 11

1,2,3,7

1,2,3,4

4

Reserved

1.25

1,2,3,9

Supported CL Settings

Supported CWL Settings

5,6,7,8,9,10,11

5,6,7,8

- 42 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 47 ] DDR3-1866 Speed Bins

Speed

DDR3-1866

CL-nRCD-nRP

13-13-13

Units

NOTE

Parameter

Internal read command to first data

ACT to internal read or write delay time

PRE command period

Symbol

tAA

min

13.91

47.91

34

max

20

ns

tRCD

-

tRP

-

ACT to ACT or REF command period

ACT to PRE command period

tRC

-

tRAS

9*tREFI

CWL = 5

tCK(AVG)

Reserved

1,2,3,4,8

CL = 5

CWL = 6,7,8,9

CWL = 5

4

2.5

1.875

1.5

3.3

1,2,3,8

CL = 6

CWL = 6

Reserved

1,2,3,4,8

CWL = 7,8,9

CWL = 5

4

CL = 7

CL = 8

CWL = 6

1,2,3,4,8

CWL = 7,8,9

CWL = 5

4

CWL = 6

<2.5

1,2,3,8

CWL = 7

Reserved

1,2,3,4,8

CWL = 8,9

CWL = 5,6

CWL = 7,8

CWL = 9

4

1,2,3,4,8

4

CL = 9

CWL = 5,6

CWL = 7

ns

4

CL = 10

CL = 11

<1.875

1,2,3,8

1,2,3,4,8

4

CWL = 8

Reserved

ns

CWL = 5,6,7

CWL = 8

ns

1,2,3,4,8

1,2,3,4

4

CWL = 9

ns

CWL = 5,6,7,8

CWL = 9

ns

CL = 12

CL = 13

ns

1,2,3,4

4

CWL = 5,6,7,8

CWL = 9

ns

1.07

<1.25

ns

1,2,3,9

Supported CL Settings

Supported CWL Settings

6,8,10,13

5,6,7,8,9

nCK

- 43 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

13.3.1 Speed Bin Table Notes

Absolute Specification (T_OPER; V_DDQ= V_DD= 1.5V +/- 0.075 V);

NOTE :

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],

rounding up to the next "Supported CL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.

5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte

20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte

18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in

SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be pro-

grammed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-

1600(CL11).

10. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.

11. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.

- 44 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

14. Timing Parameters by Speed Grade

[ Table 48 ] Timing Parameters by Speed Bins for DDR3-1066, DDR3-1333

Speed

DDR3-1066

DDR3-1333

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period

tCK(DLL_OFF)

tCK(avg)

8

-

8

-

ns

ps

6

See Speed Bins Table

tCK(avg)max +

tJIT(per)max

tCK(avg)max +

tJIT(per)max

tCK(avg)min + tJIT(per)min

Clock Period

tCK(abs)

ps

Average high pulse width

tCH(avg)

tCL(avg)

0.47

-90

0.53

90

0.47

-80

0.53

80

tCK(avg)

Average low pulse width

tCK(avg)

ps

Clock Period Jitter

tJIT(per)

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

tJIT(per, lck)

tJIT(cc)

-80

80

-70

70

ps

180

160

140

ps

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

tJIT(cc, lck)

tERR(2per)

tERR(3per)

tERR(4per)

tERR(5per)

tERR(6per)

tERR(7per)

tERR(8per)

tERR(9per)

tERR(10per)

tERR(11per)

tERR(12per)

ps

- 132

- 157

- 175

- 188

- 200

- 209

- 217

- 224

- 231

- 237

- 242

132

157

175

188

200

209

217

224

231

237

242

- 118

- 140

- 155

- 168

- 177

- 186

- 193

- 200

- 205

- 210

- 215

118

140

155

168

177

186

193

200

205

210

215

ps

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

Cumulative error across n = 13, 14 ... 49, 50 cycles

tERR(nper)

ps

24

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

tCH(abs)

tCL(abs)

0.43

-

0.43

-

tCK(avg)

25

26

DQS,DQS to DQ skew, per group, per access

DQ output hold time from DQS, DQS

DQ low-impedance time from CK, CK

DQ high-impedance time from CK, CK

tDQSQ

tQH

-

150

-

125

-

ps

tCK(avg)

ps

13

0.38

-600

-

0.38

-500

-

13, g

tLZ(DQ)

tHZ(DQ)

300

250

13,14, f

ps

tDS(base)

AC175

25

75

-

ps

d, 17

-

Data setup time to DQS, DQS referenced

to V (AC)V (AC) levels

IH

IL

tDS(base)

AC150

30

Data hold time to DQS, DQS referenced

to V (AC)V (AC) levels

tDH(base)

DC100

100

490

65

-

ps

d, 17

28

-

IH

IL

DQ and DM Input pulse width for each input

Data Strobe Timing

tDIPW

400

-

DQS, DQS differential READ Preamble

tRPRE

tRPST

tQSH

0.9

0.3

NOTE 19

0.9

0.3

NOTE 19

tCK

13, 19, g

11, 13, b

13, g

DQS, DQS differential READ Postamble

NOTE 11

DQS, DQS differential output high time

0.38

0.9

-

0.4

-

tCK(avg)

tCK

DQS, DQS differential output low time

tQSL

0.4

13, g

DQS, DQS differential WRITE Preamble

tWPRE

tWPST

tDQSCK

tLZ(DQS)

tHZ(DQS)

tDQSL

tDQSH

tDQSS

tDSS

-

0.9

-

DQS, DQS differential WRITE Postamble

DQS, DQS rising edge output access time from rising CK, CK

DQS, DQS low-impedance time (Referenced from RL-1)

DQS, DQS high-impedance time (Referenced from RL+BL/2)

DQS, DQS differential input low pulse width

DQS, DQS differential input high pulse width

DQS, DQS rising edge to CK, CK rising edge

DQS,DQS falling edge setup time to CK, CK rising edge

DQS,DQS falling edge hold time to CK, CK rising edge

0.3

-

0.3

-

tCK

-300

-600

-

300

0.55

0.25

-

-255

-500

-

255

250

0.55

0.25

-

ps

13,f

13,14,f

12,13,14

29, 31

30, 31

c

ps

0.45

-0.25

0.2

0.45

-0.25

0.2

tCK

tCK(avg)

c, 32

tDSH

0.2

-

0.2

-

c, 32

- 45 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 48 ] Timing Parameters by Speed Bins for DDR3-1066, DDR3-1333 (Cont.)

Speed

Parameter

Command and Address Timing

DLL locking time

DDR3-1066

DDR3-1333

Units

NOTE

Symbol

MIN

MAX

MIN

MAX

tDLLK

tRTP

512

-

512

-

nCK

max

internal READ Command to PRECHARGE Command delay

e

(4nCK,7.5ns)

Delay from start of internal write transaction to internal read com-

mand

max

tWTR

-

e,18

e

(4nCK,7.5ns)

WRITE recovery time

tWR

15

4

-

15

4

-

ns

Mode Register Set command cycle time

tMRD

nCK

max

Mode Register Set command update delay

CAS# to CAS# command delay

tMOD

tCCD

-

(12nCK,15ns)

4

nCK

WR + roundup (tRP /

tCK(AVG))

Auto precharge write recovery + precharge time

tDAL(min)

Multi-Purpose Register Recovery Time

tMPRR

tRAS

1

-

1

-

nCK

ns

22

e

ACTIVE to PRECHARGE command period

See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42

max

ACTIVE to ACTIVE command period for 1KB page size

ACTIVE to ACTIVE command period for 2KB page size

tRRD

-

e

(4nCK,7.5ns)

(4nCK,6ns)

max

(4nCK,10ns)

(4nCK,7.5ns)

Four activate window for 1KB page size

Four activate window for 2KB page size

tFAW

37.5

50

-

30

45

-

ns

e

tIS(base)

AC175

125

65

-

ps

b,16

-

Command and Address setup time to CK, CK referenced to

IH

V

(AC) / V (AC) levels

IL

tIS(base)

AC150

125 + 150

65+125

b,16,27

Command and Address hold time from CK, CK referenced to

(AC) / V (AC) levels

tIH(base)

DC100

200

780

140

620

-

ps

b,16

28

-

V

IH

IL

Control & Address Input pulse width for each input

Calibration Timing

tIPW

Power-up and RESET calibration time

Normal operation Full calibration time

Normal operation short calibration time

Reset Timing

tZQinitI

tZQoper

tZQCS

512

256

64

-

512

256

64

-

nCK

23

max(5nCK, tRFC +

10ns)

max(5nCK, tRFC +

10ns)

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

tXPR

-

max(5nCK,tRFC +

10ns)

max(5nCK,tRFC +

10ns)

Exit Self Refresh to commands not requiring a locked DLL

tXS

-

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

tXSDLL

tCKESR

tDLLK(min)

-

tDLLK(min)

-

nCK

tCKE(min) + 1tCK

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-

Down Entry (PDE)

max(5nCK,

10ns)

max(5nCK,

10ns)

tCKSRE

tCKSRX

-

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-

Down Exit (PDX) or Reset Exit

max(5nCK,

10ns)

max(5nCK,

10ns)

- 46 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 48 ] Timing Parameters by Speed Bins for DDR3-1066, DDR3-1333 (Cont.)

Speed

DDR3-1066

DDR3-1333

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre-

charge Power Down with DLL

max

tXP

tXPDLL

tCKE

(3nCK,

7.5ns)

-

(3nCK,6ns)

frozen to commands not requiring a locked DLL

max

(10nCK,

24ns)

max

(10nCK,

24ns)

Exit Precharge Power Down with DLL frozen to commands re-

quiring a locked DLL

2

max

CKE minimum pulse width

(3nCK,

5.625ns)

(3nCK,

5.625ns)

Command pass disable delay

tCPDED

tPD

1

-

1

-

nCK

tCK

Power Down Entry to Exit Timing

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

15

20

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power Down entry

tACTPDEN

tPRPDEN

tRDPDEN

1

-

1

-

nCK

RL + 4 +1

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BL4OTF)

WL + 4 +(tWR/

tCK(avg))

WL + 4 +(tWR/

tCK(avg))

tWRPDEN

tWRAPDEN

tWRPDEN

tWRAPDEN

-

nCK

9

10

9

Timing of WRA command to Power Down entry

(BL8OTF, BL8MRS, BL4OTF)

WL + 4 +WR +1

Timing of WR command to Power Down entry

(BL4MRS)

WL + 2 +(tWR/

tCK(avg))

WL + 2 +(tWR/

tCK(avg))

Timing of WRA command to Power Down entry

(BL4MRS)

WL +2 +WR +1

10

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

ODT Timing

tREFPDEN

tMRSPDEN

1

-

1

-

20,21

tMOD(min)

ODT high time without write command or with write command

and BC4

ODTH4

ODTH8

tAONPD

4

6

2

-

4

6

2

-

nCK

ns

ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-Down with DLL fro-

zen)

8.5

Asynchronous RTT turn-off delay (Power-Down with DLL fro-

zen)

tAOFPD

2

8.5

2

8.5

ns

RTT turn-on

tAON

tAOF

tADC

-300

0.3

300

0.7

-250

0.3

250

0.7

ps

7,f

8,f

f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference

RTT dynamic change skew

tCK(avg)

0.3

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is pro-

grammed

tWLMRD

tWLDQSEN

tWLS

40

25

-

40

25

-

tCK

ps

3

DQS/DQS delay after tDQS margining mode is programmed

Write leveling setup time from rising CK, CK crossing to rising

DQS, DQS crossing

245

195

Write leveling hold time from rising DQS, DQS crossing to rising

CK, CK crossing

tWLH

245

-

195

-

ps

Write leveling output delay

Write leveling output error

tWLO

0

9

2

0

9

2

ns

tWLOE

- 47 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 49 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866

Speed

DDR3-1600

DDR3-1866

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period

tCK(DLL_OFF)

tCK(avg)

8

-

8

-

ns

ps

6

See Speed Bins Table

tCK(avg)max +

tJIT(per)max

tCK(avg)min +

tJIT(per)min

tCK(avg)max +

tJIT(per)max

tCK(avg)min + tJIT(per)min

Clock Period

tCK(abs)

ps

Average high pulse width

tCH(avg)

tCL(avg)

0.47

-70

0.53

70

0.47

-60

0.53

60

tCK(avg)

Average low pulse width

tCK(avg)

ps

Clock Period Jitter

tJIT(per)

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

tJIT(per, lck)

tJIT(cc)

-60

60

-50

50

ps

140

120

100

ps

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

tJIT(cc, lck)

tERR(2per)

tERR(3per)

tERR(4per)

tERR(5per)

tERR(6per)

tERR(7per)

tERR(8per)

tERR(9per)

tERR(10per)

tERR(11per)

tERR(12per)

ps

-103

-122

-136

-147

-155

-163

-169

-175

-180

-184

-188

103

122

136

147

155

163

169

175

180

184

188

-88

88

ps

-105

-117

-126

-133

-139

-145

-150

-154

-158

-161

105

117

126

133

139

145

150

154

158

161

ps

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

Cumulative error across n = 13, 14 ... 49, 50 cycles

tERR(nper)

ps

24

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

tCH(abs)

tCL(abs)

0.43

-

0.43

-

tCK(avg)

25

26

DQS,DQS to DQ skew, per group, per access

DQ output hold time from DQS, DQS

DQ low-impedance time from CK, CK

DQ high-impedance time from CK, CK

tDQSQ

tQH

-

100

-

85

-

ps

tCK(avg)

ps

13

0.38

-450

-

0.38

-390

-

13, g

tLZ(DQ)

tHZ(DQ)

225

195

13,14, f

ps

tDS(base)

AC150

-

TBD

ps

d, 17

-

Data setup time to DQS, DQS referenced to V (AC)V (AC) lev-

IH

IL

els

tDS(base)

AC125

10

tDH(base)

DC100

Data hold time to DQS, DQS referenced to V (AC)V (AC) levels

45

-

TBD

320

ps

d, 17

28

-

IH

IL

DQ and DM Input pulse width for each input

Data Strobe Timing

tDIPW

360

-

DQS, DQS differential READ Preamble

DQS, DQS differential READ Postamble

DQS, DQS differential output high time

DQS, DQS differential output low time

DQS, DQS differential WRITE Preamble

DQS, DQS differential WRITE Postamble

tRPRE

tRPST

tQSH

0.9

0.3

NOTE 19

0.9

0.3

NOTE 19

tCK

13, 19, g

11, 13, b

13, g

NOTE 11

0.4

-

0.4

-

tCK(avg)

tCK

tQSL

0.4

-

0.4

13, g

tWPRE

tWPST

tDQSCK

tLZ(DQS)

tHZ(DQS)

tDQSL

tDQSH

tDQSS

tDSS

0.9

-

0.3

-

0.3

-

tCK

DQS, DQS rising edge output access time from rising CK, CK

DQS, DQS low-impedance time (Referenced from RL-1)

DQS, DQS high-impedance time (Referenced from RL+BL/2)

DQS, DQS differential input low pulse width

-225

-450

-

225

-195

-390

-

195

0.55

0.27

-

ps

13,f

13,14,f

12,13,14

29, 31

30, 31

c

225

ps

225

ps

0.45

-0.27

0.9

0.55

0.27

NOTE 19

NOTE 11

0.45

-0.27

0.18

tCK

DQS, DQS differential input high pulse width

tCK

DQS, DQS rising edge to CK, CK rising edge

tCK(avg)

DQS,DQS falling edge setup time to CK, CK rising edge

DQS,DQS falling edge hold time to CK, CK rising edge

c, 32

tDSH

0.3

-

c, 32

- 48 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 49 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)

Speed

Parameter

Command and Address Timing

DLL locking time

DDR3-1600

DDR3-1866

Units

NOTE

Symbol

MIN

MAX

MIN

MAX

tDLLK

tRTP

512

-

512

-

nCK

max

internal READ Command to PRECHARGE Command delay

e

(4nCK,7.5ns)

Delay from start of internal write transaction to internal read com-

mand

max

tWTR

-

e,18

e

(4nCK,7.5ns)

WRITE recovery time

tWR

15

4

-

15

4

-

ns

Mode Register Set command cycle time

tMRD

nCK

max

Mode Register Set command update delay

CAS# to CAS# command delay

tMOD

tCCD

-

(12nCK,15ns)

4

nCK

WR + roundup (tRP /

tCK(AVG))

Auto precharge write recovery + precharge time

tDAL(min)

Multi-Purpose Register Recovery Time

tMPRR

tRAS

1

-

1

-

nCK

ns

22

e

ACTIVE to PRECHARGE command period

See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42

max

ACTIVE to ACTIVE command period for 1KB page size

ACTIVE to ACTIVE command period for 2KB page size

tRRD

-

e

(4nCK,6ns)

(4nCK, 5ns)

max

(4nCK,7.5ns)

(4nCK, 6ns)

Four activate window for 1KB page size

Four activate window for 2KB page size

tFAW

30

40

-

27

35

-

ns

e

tIS(base)

AC150

45

-

TBD

ps

b,16

-

Command and Address setup time to CK, CK referenced to

IH

V

(AC) / V (AC) levels

IL

tIS(base)

AC125

45+125

b,16,27

Command and Address hold time from CK, CK referenced to

(AC) / V (AC) levels

tIH(base)

DC100

120

560

-

TBD

535

ps

b,16

28

-

V

IH

IL

Control & Address Input pulse width for each input

Calibration Timing

tIPW

Power-up and RESET calibration time

Normal operation Full calibration time

Normal operation short calibration time

Reset Timing

tZQinitI

tZQoper

tZQCS

512

256

64

-

max(512nCK,640ns)

max(256nCK,320ns)

max(64nCK,80ns)

-

nCK

23

max(5nCK, tRFC +

10ns)

max(5nCK, tRFC +

10ns)

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

tXPR

-

max(5nCK,tRFC +

10ns)

max(5nCK,tRFC +

10ns)

Exit Self Refresh to commands not requiring a locked DLL

tXS

-

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

tXSDLL

tCKESR

tDLLK(min)

-

tDLLK(min)

-

nCK

tCKE(min) + 1tCK

tCKE(min) + 1nCK

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-

Down Entry (PDE)

max(5nCK,

10ns)

max(5nCK,

10ns)

tCKSRE

tCKSRX

-

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-

Down Exit (PDX) or Reset Exit

max(5nCK,

10ns)

max(5nCK,

10ns)

- 49 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 49 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)

Speed

DDR3-1600

DDR3-1866

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre-

charge Power Down with DLL

max

tXP

-

max(3nCK,6ns)

-

(3nCK,6ns)

frozen to commands not requiring a locked DLL

max

(10nCK,

24ns)

Exit Precharge Power Down with DLL frozen to commands re-

quiring a locked DLL

tXPDLL

tCKE

-

max(10nCK,24ns)

max(3nCK,5ns)

-

2

max

CKE minimum pulse width

(3nCK,5ns)

Command pass disable delay

tCPDED

tPD

1

-

2

-

nCK

tCK

Power Down Entry to Exit Timing

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

15

20

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power Down entry

tACTPDEN

tPRPDEN

tRDPDEN

1

-

1

-

nCK

RL + 4 +1

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BL4OTF)

WL + 4 +(tWR/

tCK(avg))

WL + 4 +(tWR/

tCK(avg))

tWRPDEN

tWRAPDEN

tWRPDEN

tWRAPDEN

-

nCK

9

10

9

Timing of WRA command to Power Down entry

(BL8OTF, BL8MRS, BL4OTF)

WL + 4 +WR +1

Timing of WR command to Power Down entry

(BL4MRS)

WL + 2 +(tWR/

tCK(avg))

WL + 2 +(tWR/

tCK(avg))

Timing of WRA command to Power Down entry

(BL4MRS)

WL +2 +WR +1

10

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

ODT Timing

tREFPDEN

tMRSPDEN

1

-

1

-

20,21

tMOD(min)

ODT high time without write command or with write command

and BC4

ODTH4

ODTH8

tAONPD

4

6

2

-

4

6

2

-

nCK

ns

ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-Down with DLL fro-

zen)

8.5

Asynchronous RTT turn-off delay (Power-Down with DLL fro-

zen)

tAOFPD

2

8.5

2

8.5

ns

RTT turn-on

tAON

tAOF

tADC

-225

0.3

225

0.7

-195

0.3

195

0.7

ps

7,f

8,f

f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference

RTT dynamic change skew

tCK(avg)

0.3

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is pro-

grammed

tWLMRD

tWLDQSEN

tWLS

40

25

-

40

25

-

tCK

ps

3

DQS/DQS delay after tDQS margining mode is programmed

Write leveling setup time from rising CK, CK crossing to rising

DQS, DQS crossing

165

140

Write leveling hold time from rising DQS, DQS crossing to rising

CK, CK crossing

tWLH

165

-

140

-

ps

Write leveling output delay

Write leveling output error

tWLO

0

7.5

2

0

7.5

2

ns

tWLOE

- 50 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

14.1 Jitter Notes

Specific Note a

Specific Note b

Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the

input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,

another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.

These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition

edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,

these parameters should be met whether clock jitter is present or not.

Specific Note c

These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK)

crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative

to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note d

Specific Note e

These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data

strobe signal (DQS(L/U), DQS(L/U)) crossing.

For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},

which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the

device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-

mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

Specific Note f

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input

clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +

193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(der-

ated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to

tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the

min/max usage!)

Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=

12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input

clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has

tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +

tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =

tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/

max usage!)

- 51 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

14.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions which are TBD.

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing

Diagram Datasheet.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by TBD

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15. tREFI depends on T

OPER

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

V

(DC) = V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).

REF

See "Address/Command Setup, Hold and Derating :" on page 53. .

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,

(DC)= V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).

V

REF

See "Data Setup, Hold and Slew Rate Derating :" on page 60.

18. Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL

For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram

Datasheet"

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The

appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-

ject to in the application, is illustrated. The interval could be defined by the following formula:

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-

lated as:

0.5

~

= 0.133

128ms

(1.5 x 1) + (0.15 x 15)

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-

nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of V

(DC) and the consecutive crossing of V

(DC)

REF

29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.

30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.

31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

- 52 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

14.3 Address/Command Setup, Hold and Derating :

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see

Table 50) to the ∆tIS and ∆tIH derating value (see Table 51) respectively.

Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

V

_REF(DC) and the first crossing of V_IH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

V_REF(DC) and the first crossing of V_IL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’V_REF(DC) to ac

region’, use nominal slew rate for derating value (see Figure 21). If the actual signal is later than the nominal slew rate line anywhere between shaded

’V_REF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 23).

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_IL(DC)max and the first crossing of V_REF(DC).

Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V_IH(DC)min and the first crossing of V_REF(DC). If

the actual signal is always later than the nominal slew rate line between shaded ’dc to V_REF(DC) region’, use nominal slew rate for derating value (see

Figure 22). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V_REF(DC) region’, the slew rate of a tangent line

to the actual signal from the dc level to V_REF(DC) level is used for derating value (see Figure 24).

For a valid transition the input signal has to remain above/below V_IH/IL(AC) for some time tVAC (see Table 55).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V_IH/IL(AC) at the time of the rising clock

transition) a valid input signal is still required to complete the transition and reach V_IH/IL(AC).

For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

[ Table 50 ] ADD/CMD Setup and Hold Base-Values for 1V/ns

[ps]

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

reference

V_IH/L(AC)

V_IH/L(DC)

tIS(base) AC175

tIS(base) AC150

tIS(base)-AC135

tIS(base)-AC125

tIH(base)-DC100

125

275

-

65

190

-

45

170

-

65

150

100

-

200

140

120

NOTE :

1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-Ck slew rate

2. The tIS(base)-AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125ps for DDR3-800/1066 or 100ps for

DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point

[(175mV-150mV)/1 V/ns]

3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 and 65ps for DDR3-2133 to accommo-

date for the lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mV-125mV)/1V/ns].

[ Table 51 ] Derating values DDR3-1066/1333/1600 tIS/tIH-AC/DC based AC175 Threshold

∆tIS, ∆tIH Derating [ps] AC/DC based

Alternate AC175 Threshold -> V_IH(AC) = V_REF(DC) + 175mV, V_IL(AC) = V_REF(DC) - 175mV

CLK,CLK Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

∆tIS

1.0V/ns

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

58

42

8

∆tIS

∆tIH

66

50

16

12

6

∆tIS

∆tIH

74

58

24

20

14

8

∆tIH

84

68

34

30

24

18

8

∆tIS

∆tIH

100

84

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

88

59

0

88

59

0

88

59

0

96

67

8

104

75

16

14

10

5

112

83

24

22

18

13

7

120

91

32

30

26

21

15

-2

128

99

40

38

34

29

23

5

34

0

50

CMD/

ADD

Slew

rate

-2

-4

-2

-4

-2

-4

6

4

46

-6

-10

-16

-26

-40

-60

-6

-10

-16

-26

-40

-60

-6

-10

-16

-26

-40

-60

2

-2

40

-11

-17

-35

-62

-11

-17

-35

-62

-11

-17

-35

-62

-3

-9

-27

-54

-8

0

34

V/ns

-18

-32

-52

-1

-10

-24

-44

-2

24

-19

-46

-11

-38

-16

-36

-6

10

-30

-26

-22

-10

- 53 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 52 ] Derating values DDR3-1066/1333/1600 tIS/tIH-AC/DC based - Alternate AC150 Threshold

∆tIS, ∆tIH Derating [ps] AC/DC based

Alternate AC150 Threshold -> V_IH(AC) = V_REF(DC) + 150mV, V_IL(AC) = V_REF(DC) - 150mV

CLK,CLK Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

∆tIS

1.0V/ns

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

58

42

8

∆tIS

∆tIH

66

50

16

12

6

∆tIS

∆tIH

74

58

24

20

14

8

∆tIH

84

68

34

30

24

18

8

∆tIS

∆tIH

100

84

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

75

50

0

75

50

0

75

50

0

83

58

8

91

66

16

15

6

99

74

24

23

14

-1

107

82

32

31

22

7

115

90

40

39

30

15

34

0

50

CMD/

ADD

Slew

rate

0

-4

0

-4

0

-4

8

4

46

0

-10

-16

-26

-40

-60

0

-10

-16

-26

-40

-60

0

-10

-16

-26

-40

-60

8

-2

40

0

8

-8

0

34

V/ns

-1

-10

-25

-1

-10

-25

-1

-10

-25

7

-18

-32

-52

-10

-24

-44

-2

24

-2

-17

-16

-36

-6

10

-9

-26

-10

[ Table 53 ] Derating values DDR3-1866/2133 tIS/tIH-AC/DC based Alternate AC135 Threshold

∆tIS, ∆tIH Derating [ps] AC/DC based

Alternate AC125 Threshold -> V_IH(AC) = V_REF(DC) + 135mV, V_IL(AC) = V_REF(DC) - 135mV

CLK,CLK Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

58

42

8

∆tIS

∆tIH

66

50

16

12

6

∆tIS

∆tIH

74

58

24

20

14

8

∆tIS

100

77

∆tIH

84

68

34

30

24

18

8

∆tIS

108

85

∆tIH

100

84

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

68

45

0

68

45

0

68

45

0

76

53

8

84

61

16

18

19

22

25

21

14

92

69

24

26

27

30

33

29

22

34

0

32

40

50

CMD/

ADD

Slew

rate

2

-4

2

-4

2

-4

10

11

14

17

13

6

4

34

42

46

3

-10

-16

-26

-40

-60

3

-10

-16

-26

-40

-60

3

-10

-16

-26

-40

-60

-2

35

43

40

6

-8

0

38

46

34

V/ns

9

-18

-32

-52

-10

-24

-44

-2

41

49

24

5

-16

-36

37

-6

45

10

-3

30

-26

38

-10

- 54 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 54 ] Derating values DDR3-1866/2133 tIS/tIH-AC/DC based - Alternate AC125 Threshold

∆tIS, ∆tIH Derating [ps] AC/DC based

Alternate AC125 Threshold -> V_IH(AC) = V_REF(DC) + 125mV, V_IL(AC) = V_REF(DC) - 125mV

CLK,CLK Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

∆tIS

1.0V/ns

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

50

∆tIS

∆tIH

58

42

8

∆tIS

∆tIH

66

50

16

12

6

∆tIS

∆tIH

74

58

24

20

14

8

∆tIH

84

68

34

30

24

18

8

∆tIS

∆tIH

100

84

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

63

42

0

63

42

0

63

42

0

71

50

8

79

58

16

20

22

27

32

31

29

87

66

24

28

30

35

40

39

37

95

74

32

36

38

43

48

47

45

103

82

40

44

46

51

56

55

53

34

0

50

CMD/

ADD

Slew

rate

4

-4

4

-4

4

-4

12

14

19

24

23

21

4

46

6

-10

-16

-26

-40

-60

6

-10

-16

-26

-40

-60

6

-10

-16

-26

-40

-60

-2

40

11

16

15

13

11

16

15

13

11

16

15

13

-8

0

34

V/ns

-18

-32

-52

-10

-24

-44

-2

24

-16

-36

-6

10

-26

-10

[ Table 55 ] Required time t_VACabove V_IH(AC) {blow V_IL(AC)} for valid transition

t_VAC@175mV [ps]

t_VAC@150mV [ps]

t_VAC@135mV [ps]

t_VAC@125mV [ps]

Slew Rate[V/ns]

min

75

57

50

38

34

29

22

13

0

max

min

175

170

167

163

162

161

159

155

150

max

min

TBD

max

min

TBD

max

>2.0

2.0

-

1.5

1.0

0.9

0.8

0.7

0.6

0.5

< 0.5

0

- 55 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

tVAC

V_IH(AC) min

V_REFto ac

region

V

_IH(DC) min

nominal

slew rate

V_REF(DC)

nominal slew

rate

V_IL(DC) max

V_REFto ac

region

V_IL(AC) max

V_SS

tVAC

∆ TF

∆ TR

V

_REF(DC) - V_IL(AC)max

Setup Slew Rate

Rising Signal

V_IH(AC)min - V_REF(DC)

Setup Slew Rate

Falling Signal

=

∆ TF

∆ TR

Figure 21. Illustration of nominal slew rate and t_VACfor setup time t_DS(for DQ with respect to strobe) and t_IS

(for ADD/CMD with respect to clock).

- 56 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

V_IH(AC) min

V

_IH(DC) min

dc to V_REF

region

nominal

slew rate

V_REF(DC)

nominal

dc to V_REF

region

slew rate

V_IL(DC) max

V_IL(AC) max

V_SS

∆ TR

∆ TF

Hold Slew Rate

Rising Signal

V

_REF(DC) - V_IL(DC)max

Hold Slew Rate

Falling Signal

V

_IH(DC)min - V_REF(DC)

=

∆ TR

∆ TF

Figure 22. Illustration of nominal slew rate for hold time t_DH(for DQ with respect to strobe) and t_IH

(for ADD/CMD with respect to clock).

- 57 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

tVAC

nominal

line

V_IH(AC) min

V

_REFto ac

region

V

_IH(DC) min

tangent

line

V_REF(DC)

tangent

line

V_IL(DC) max

V_IL(AC) max

V_REFto ac

region

nominal

line

∆ TR

tVAC

V_SS

tangent line[V_IH(AC)min - V_REF(DC)]

Setup Slew Rate

Rising Signal

=

∆ TR

∆ TF

Setup Slew Rate tangent line[V_REF(DC) - V_IL(AC)max]

=

Falling Signal

∆ TF

Figure 23. Illustration of tangent line for setup time t_DS(for DQ with respect to strobe) and t_IS

(for ADD/CMD with respect to clock)

- 58 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

V_IH(AC) min

nominal

line

V

_IH(DC) min

dc to V_REF

region

tangent

line

V_REF(DC)

tangent

line

dc to V_REF

region

nominal

line

V_IL(DC) max

V_IL(AC) max

V_SS

∆ TF

∆ TR

tangent line [ V_REF(DC) - V_IL(DC)max ]

Hold Slew Rate

Rising Signal

=

∆ TR

tangent line [ V_IH(DC)min - V_REF(DC) ]

Hold Slew Rate

=

Falling Signal

∆ TF

Figure 24. Illustration of tangent line for hold time t_DH(for DQ with respect to strobe) and t_IH

(for ADD/CMD with respect to clock)

- 59 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

14.4 Data Setup, Hold and Slew Rate Derating :

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see

Table 56) to the ∆ tDS and ∆tDH (see Table 55) derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_REF(DC) and the first crossing of V_IH(AC)min.

Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V_REF(DC) and the first crossing of V_IL(AC)max

(see Figure 25). If the actual signal is always earlier than the nominal slew rate line between shaded ’V_REF(DC) to ac region’, use nominal slew rate for

derating value. If the actual signal is later than the nominal slew rate line anywhere

between shaded ’V_REF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see

Figure 27).

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_IL(DC)max and the first crossing of V_REF(DC).

Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V_IH(DC)min and the first crossing of V_REF(DC)

(see Figure ). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to V_REF(DC) region’, use nominal slew rate for

derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V_REF(DC) region’, the slew rate of a tangent

line to the actual signal from the dc level to V_REF(DC) level is used for derating value (see Figure 28).

For a valid transition the input signal has to remain above/below V_IH/IL(AC) for some time tVAC (see Table 56).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V_IH/IL(AC) at the time of the rising clock

transition) a valid input signal is still required to complete the transition and reach V_IH/IL(AC).

For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

[ Table 56 ] Data Setup and Hold Base-Values

[ps]

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

reference

V_IH/L(AC)

V_IH/L(DC)

tDS(base) AC175

tDS(base) AC150

tDS(base) AC135

tDH(base) DC100

25

75

-

0

30

-

65

10

-

45

100

20

NOTE : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)

[ Table 57 ] Derating values DDR3-800/1066 tDS/tDH - (AC175)

∆tDS, ∆tDH Derating in [ps] AC/DC based¹

DQS,DQS Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

88

59

0

-

50

34

0

-

88

59

0

-2

-

50

34

0

-4

-

88

59

0

-2

-6

-

50

34

0

-4

-10

-

67

8

6

2

-3

-

42

8

-

16

14

10

5

-1

-

16

12

6

-

DDR3 DQ

4

22

18

13

7

-11

-

20

14

8

-2

-16

-

Slew

-

-2

-8

-

26

21

15

-2

-30

24

18

8

-6

-26

800/ rate

1066 V/ns

-

0

29

23

6

34

24

10

-10

-

-10

-

-22

NOTE : 1. Cell contents shaded in red are defined as ’not supported’.

[ Table 58 ] Derating values for DDR3-1066/1333/1600 tDS/tDH - (AC150)

∆tDS, ∆tDH Derating in [ps] AC/DC based¹

DQS,DQS Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

75

50

0

-

50

34

0

-

75

50

0

-

50

34

0

-4

-

75

50

0

-

50

34

0

-4

-10

-

58

8

-

42

8

-

16

15

-

16

12

6

-

DQ

Slew

rate

4

24

23

14

-

20

14

8

-2

-16

-

-2

-8

-

32

31

22

7

24

18

8

-6

-26

-

0

40

39

30

15

34

24

10

-10

V/ns

-

-10

-

NOTE : 1. Cell contents shaded in red are defined as ’not supported’.

- 60 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

[ Table 59 ] Derating values for DDR3-1866 tDS/tDH - (AC135)

∆tDS, ∆tDH Derating in [ps] AC/DC based¹

DQS,DQS Differential Slew Rate

1.8 V/ns 1.6 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

68

45

0

-

50

34

0

-

68

45

0

2

-

50

34

0

-4

-

68

45

0

2

3

-

50

34

0

-

53

8

10

11

14

-

42

8

-

16

18

19

22

25

-

16

12

6

-

DQ

Slew

rate

-4

-10

-

4

26

27

30

33

29

-

20

14

8

-2

-16

-

-2

-8

-

35

38

41

37

30

24

18

8

-6

-26

-

0

46

49

45

38

34

24

10

-10

V/ns

-

-10

-

NOTE : 1. Cell contents shaded in red are defined as ’not supported’.

[ Table 60 ] Required time t_VACabove V_IH(AC) {blow V_IL(AC)} for valid transition

t_VAC[ps] DDR3-1066

(AC175)

t_VAC[ps] DDR3-1066/1333/1600

(AC150)

t_VAC[ps] DDR3-1866

(AC135)

Slew Rate[V/ns]

min

max

min

175

170

167

163

162

161

159

155

150

max

min

max

>2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

75

57

50

38

34

29

22

13

0

-

TBD

-

0

- 61 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

tVAC

V_IH(AC) min

V_REFto ac

region

V

_IH(DC) min

nominal

slew rate

V_REF(DC)

nominal slew

rate

V_IL(DC) max

V_REFto ac

region

V_IL(AC) max

V_SS

tVAC

∆ TF

∆ TR

V

_REF(DC) - V_IL(AC)max

Setup Slew Rate

Rising Signal

V_IH(AC)min - V_REF(DC)

Setup Slew Rate

Falling Signal

=

∆ TF

∆ TR

Figure 25. Illustration of nominal slew rate and t_VACfor setup time t_DS(for DQ with respect to strobe) and t_IS

(for ADD/CMD with respect to clock).

- 62 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

V_IH(AC) min

V

_IH(DC) min

dc to V_REF

region

nominal

slew rate

V_REF(DC)

nominal

dc to V_REF

region

slew rate

V_IL(DC) max

V_IL(AC) max

V_SS

∆ TR

∆ TF

Hold Slew Rate

Rising Signal

V

_REF(DC) - V_IL(DC)max

Hold Slew Rate

Falling Signal

V

_IH(DC)min - V_REF(DC)

=

∆ TR

∆ TF

Figure 26. Illustration of nominal slew rate for hold time t_DH(for DQ with respect to strobe) and t_IH

(for ADD/CMD with respect to clock).

- 63 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

tVAC

nominal

line

V_IH(AC) min

V

_REFto ac

region

V

_IH(DC) min

tangent

line

V_REF(DC)

tangent

line

V_IL(DC) max

V_IL(AC) max

V_REFto ac

region

nominal

line

∆ TR

tVAC

V_SS

tangent line[V_IH(AC)min - V_REF(DC)]

Setup Slew Rate

Rising Signal

=

∆ TR

∆ TF

Setup Slew Rate

Falling Signal

tangent line[V_REF(DC) - V_IL(AC)max]

=

∆ TF

Figure 27. Illustration of tangent line for setup time t_DS(for DQ with respect to strobe) and t_IS

(for ADD/CMD with respect to clock)

- 64 -

Rev. 1.1

K4B2G0446D

K4B2G0846D

datasheet

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V_DDQ

V_IH(AC) min

nominal

line

V

_IH(DC) min

dc to V_REF

region

tangent

line

V_REF(DC)

tangent

line

dc to V_REF

region

nominal

line

V_IL(DC) max

V_IL(AC) max

V_SS

∆ TF

∆ TR

tangent line [ V_REF(DC) - V_IL(DC)max ]

Hold Slew Rate

Rising Signal

=

∆ TR

tangent line [ V_IH(DC)min - V_REF(DC) ]

Hold Slew Rate

=

Falling Signal

∆ TF

Figure 28. Illustration of tangent line for hold time t_DH(for DQ with respect to strobe) and t_IH

(for ADD/CMD with respect to clock)

- 65 -


型号：	K4B2G0446D-HCMA
厂家：	SAMSUNG
描述：	DDR DRAM, 512MX4, 0.195ns, CMOS, PBGA78, 动态存储器双倍数据速率
文件：	总65页 (文件大小：1818K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4B2G0446D-HCMA [SAMSUNG]

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