K4B4G1646Q_技术文档

Rev. 0.5, Apr. 2013

K4B4G1646Q

Preliminary

1.35V

4Gb Q-die DDR3L SDRAMOlny x16

96FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

CAUTION :

This document includes some items still under discussion in JEDEC

Therefore, those may be changed without pre-notice based on JEDEC progress.

In addition, it is highly recommended that you not send specs without Samsung’s permission.

datasheet

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- 1 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

Revision History

Revision No.

History

Draft Date

Remark

Editor

0.5

- Preliminary SPEC. Release

Apr. 2013

-

J.Y.Lee

- 2 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

1. Ordering Information

[ Table 1 ] Samsung 4Gb DDR3L Q-die ordering information table

3

2

DDR3L-1066 (7-7-7)

Package

Organization

DDR3L-1333 (9-9-9)

K4B4G1646Q-HYH9

DDR3L-1600 (11-11-11)

256Mx16

K4B4G1646Q-HYF8

K4B4G1646Q-HYK0

96 FBGA

NOTE :

1. Speed bin is in order of CL-tRCD-tRP.

2. Backward compatible to DDR3L-1333(9-9-9), DDR3L-1066(7-7-7)

3. Backward compatible to DDR3L-1066(7-7-7)

2. Key Features

[ Table 2 ] 4Gb DDR3 Q-die Speed bins

DDR3-800

6-6-6

2.5

DDR3-1066

DDR3-1333

DDR3-1600

11-11-11

1.25

Speed

Unit

7-7-7

1.875

7

9-9-9

1.5

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

ns

nCK

ns

6

9

11

15

13.125

37.5

13.5

36

13.75

35

15

ns

tRAS(min)

tRC(min)

37.5

52.5

ns

50.625

49.5

48.75

ns

•

JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

The 4Gb DDR3 SDRAM Q-die is organized as a 32Mbit x 16 I/Os x 8banks,

device. This synchronous device achieves high speed double-data-rate

transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applica-

tions.

V

DDQ

•

400 MHz f for 800Mb/sec/pin, 533MHz f for 1066Mb/sec/pin,

CK CK

667MHz f for 1333Mb/sec/pin, 800MHz f for 1600Mb/sec/pin

CK

The chip is designed to comply with the following key DDR3 SDRAM fea-

tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,

On Die Termination using ODT pin and Asynchronous Reset .

All of the control and address inputs are synchronized with a pair of exter-

nally supplied differential clocks. Inputs are latched at the crosspoint of dif-

ferential clocks (CK rising and CK falling). All I/Os are synchronized with a

pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-

ion. The address bus is used to convey row, column, and bank address

information in a RAS/CAS multiplexing style. The DDR3 device operates

with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply

and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V).

•

8 Banks

Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11

Programmable Additive Latency: 0, CL-2 or CL-1 clock

Programmable CAS Write Latency (CWL) = 5 (DDR3-800),

(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)

6

•

8-bit pre-fetch

Burst Length: 8 (Interleave without any limit, sequential with starting

address “000” only), 4 with tCCD = 4 which does not allow seamless

read or write [either On the fly using A12 or MRS]

•

Bi-directional Differential Data-Strobe

Internal(self) calibration : Internal self calibration through ZQ pin

(RZQ : 240 ohm ± 1%)

The 4Gb DDR3 Q-die device is available in 96ball FBGAs(x16).

•

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower than T

85C, 3.9us at

CASE

85C < T

< 95 C

CASE

•

Asynchronous Reset

Package : 96 balls FBGA - x16

All of Lead-Free products are compliant for RoHS

All of products are Halogen-free

NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing

Diagram”.

2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.

- 5 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

3. Package pinout/Mechanical Dimension & Addressing

3.1 x16 Package Pinout (Top view) : 96ball FBGA Package

1

2

3

4

5

6

7

8

9

VDDQ

VSSQ

VDDQ

VSSQ

VSS

DQU5

VDD

VDDQ

VSS

VSSQ

VDDQ

A

B

C

D

E

F

DQU7

VSS

DQU4

DQSU

DQU0

A

B

C

D

E

F

DQU6

DQU3

VDDQ

VSSQ

DQL2

DQL6

VDDQ

VSS

DQU1

DMU

DQL0

DQSL

DQL4

RAS

DQU2

VSSQ

VDD

VDDQ

DML

DQL1

VDD

VSSQ

DQL3

VSS

VDDQ

VSSQ

G

H

J

VSSQ

VREFDQ

NC

VSSQ

VDDQ

NC

G

H

J

DQL7

CK

DQL5

VSS

ODT

NC

CKE

NC

K

L

VDD

CAS

CK

VDD

ZQ

K

L

CS

WE

A10/AP

NC

VSS

VDD

M

BA0

BA2

VREFCA

VSS

M

N

P

R

T

A3

A5

A0

A2

A12/BC

A1

BA1

A4

VDD

VSS

VDD

VSS

N

P

R

T

VSS

VDD

VSS

A7

A9

A11

A6

RESET

A13

A14

A8

1

2

3

4

5

6

7

8

9

Ball Locations (x16)

A

B

C

D

E

F

Populated ball

Ball not populated

G

H

J

Top view

(See the balls through the package)

K

L

M

N

P

R

T

- 6 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

3.2 FBGA Package Dimension (x16)

Units : Millimeters

10.00  0.10

0.80 x 8 = 6.40

A

#A1 INDEX MARK

B

(Datum A)

0.80

1.60

6

3.20

3

9

8

7

5

4

2 1

A

B

C

D

E

F

(Datum B)

G

H

J

K

L

M

N

P

R

T

(0.95)

MOLDING AREA

96 - 0.45 Solder ball

(Post Reflow 0.50  0.05)

0.2 A B

(1.90)

M

BOTTOM VIEW

10.00 0.10

#A1

0.35 0.05

1.10 0.10

TOP VIEW

- 7 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

4. Input/Output Functional Description

[ Table 3 ] Input/Output function description

Symbol

Type

Function

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of

CK, CK

Input

the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and

output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or

Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After V

has become

REFCA

CKE

CS

Input

stable during the power on and initialization sequence, it must be maintained during all operations (including Self-

Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT

and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on

Input

systems with multiple Ranks. CS is considered part of the command code.

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When

enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode

Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-

grammed to disable ODT.

ODT

RAS, CAS, WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-

dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of

DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.

DM

(DMU), (DML)

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being

applied. Bank address also determines if the mode register or extended mode register is to be accessed during a

MRS cycle.

BA0 - BA2

A0 - A14

Input

Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands

to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,

see below)

The address inputs also provide the op-code during Mode Register Set commands.

Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-

formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)

A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or

all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.

A10 / AP

A12 / BC

Input

Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-

Input

formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.

RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and

RESET

DQ

20% of V , i.e. 1.20V for DC high and 0.30V for DC low.

DD

Input/Output Data Input/ Output: Bi-directional data bus.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the

x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data

Input/Output strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif-

ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and

does not support single-ended.

DQS, (DQS)

Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in

MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When

disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/

x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.

TDQS, (TDQS)

NC

Output

No Connect: No internal electrical connection is present.

V

Supply

DQ Power Supply: 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

DQ Ground

DDQ

V

SSQ

V

Power Supply: 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

Ground

DD

V

SS

V

Reference voltage for DQ

REFDQ

V

Reference voltage for CA

REFCA

ZQ

Reference Pin for ZQ calibration

NOTE : Input only pins (BA0-BA2, A0-A14, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.

- 8 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

5. DDR3 SDRAM Addressing

1Gb

Configuration

# of Bank

256Mb x 4

8

128Mb x 8

8

64Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

A0 - A13

A0 - A9,A11

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A13

A0 - A9

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A12

A0 - A9

A12/BC

2 KB

Column Address

BC switch on the fly

*1

Page size

2Gb

Configuration

# of Bank

512Mb x 4

8

256Mb x 8

8

128Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

A0 - A14

A0 - A9,A11

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A14

A0 - A9

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A13

A0 - A9

A12/BC

2 KB

Column Address

BC switch on the fly

*1

Page size

4Gb

Configuration

# of Bank

1Gb x 4

8

512Mb x 8

8

256Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

A0 - A15

A0 - A9,A11

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A15

A0 - A9

A12/BC

1 KB

BA0 - BA2

A10/AP

A0 - A14

A0 - A9

A12/BC

2 KB

Column Address

BC switch on the fly

*1

Page size

8Gb

Configuration

# of Bank

2Gb x 4

8

1Gb x 8

8

512Mb x 16

8

Bank Address

Auto precharge

Row Address

BA0 - BA2

A10/AP

BA0 - BA2

A10/AP

A0 - A15

A0 - A9,A11

A12/BC

2 KB

BA0 - BA2

A10/AP

A0 - A15

A0 - A9

A12/BC

2 KB

A0 - A15

A0 - A9,A11,A13

A12/BC

Column Address

BC switch on the fly

*1

2 KB

Page size

NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.

Page size is per bank, calculated as follows:

page size = 2 ^COLBITS* ORG8

where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

- 9 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

6. Absolute Maximum Ratings

6.1 Absolute Maximum DC Ratings

[ Table 4 ] Absolute Maximum DC Ratings

Symbol

Parameter

Voltage on V pin relative to Vss

Rating

Units

NOTE

V

-0.4 V ~ 1.975 V

-55 to +100

V

1,3

DD

V

Voltage on V

pin relative to Vss

DDQ

V

1,3

1

DDQ

V

Voltage on any pin relative to Vss

Storage Temperature

IN, OUT

T

C

1, 2

STG

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. V_DDand V_DDQmust be within 300mV of each other at all times;and V_REFmust be not greater than 0.6 x V_DDQ, When V_DDand V_DDQare less than 500mV; V_REFmay be

equal to or less than 300mV.

6.2 DRAM Component Operating Temperature Range

[ Table 5 ] Temperature Range

Symbol

Parameter

rating

Unit

NOTE

T

Operating Temperature Range

0 to 95

C

1, 2, 3

OPER

NOTE :

1. Operating Temperature T_OPERis the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

tained between 0-85C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the

following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.

b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode with Extended Temperature Range

capability (MR2 A6 = 0_band MR2 A7 = 1_b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

7. AC & DC Operating Conditions

7.1 Recommended DC operating Conditions

[ Table 6 ] Recommended DC Operating Conditions

Rating

Symbol

Parameter

Operation Voltage

Units

NOTE

Min.

1.283

1.425

1.283

1.425

Typ.

1.35

1.5

Max.

1.45

1.35V

1.5V

V

1, 2, 3

V

Supply Voltage

DD

1.575

1.45

1.35V

1.5V

1.35

1.5

V

Supply Voltage for Output

DDQ

1.575

NOTE :

1. Under all conditions V_DDQmust be less than or equal to V_DD

2. V_DDQtracks with V_DD. AC parameters are measured with V_DDand V_DDQtied together.

.

3. V & V

rating are determined by operation voltage.

DDQ

DD

- 10 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

8. AC & DC Input Measurement Levels

8.1 AC & DC Logic input levels for single-ended signals

[ Table 7 ] Single-ended AC & DC input levels for Command and Address(1.35V)

DDR3L-800/1066/1333/1600

Min. Max.

Symbol

Parameter

Unit

NOTE

1.35V

V

(DC90)

V

+ 90

V

DD

DC input logic high

mV

V

1

IH.CA

REF

V

(DC90)

V

- 90

REF

DC input logic low

1

IL.CA

SS

V

(AC160)

(AC135)

(DC)

V

+ 160

REF

AC input logic high

Note 2

1,2,5

3,4

IH.CA

V

- 160

AC input logic low

Note 2

IL.CA

REF

V

+135

AC input logic high

Note 2

IH.CA

REF

V

-135

REF

AC input logic lowM

Note 2

IL.CA

V

0.49*V

0.51*V

DD

Reference Voltage for ADD, CMD inputs

REFCA

DD

NOTE :

1. For input only pins except RESET, V_REF= V_REFCA(DC)

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).

4. For reference: approx. VDD/2 +/- 13.5 mV

5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),

VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do not

apply when the device is operated in the 1.35 voltage range.

[ Table 8 ] Single-ended AC & DC input levels for Command and Address(1.5V)

DDR3-800/1066/1333/1600

Symbol

Parameter

Unit

NOTE

Min.

Max.

1.5V

V

(DC100)

V

+ 100

V

DC input logic high

mV

V

1,5

IH.CA

REF

DD

V

(DC100)

(AC175)

(AC150)

(DC)

V

- 100

REF

DC input logic low

1,6

IL.CA

IH.CA

SS

V

+ 175

AC input logic high

Note 2

1,2,7

1,2,8

1,2,7

1,2,8

3,4,9

REF

V

- 175

AC input logic low

Note 2

IL.CA

IH.CA

REF

V

+150

AC input logic high

Note 2

REF

V

-150

REF

AC input logic low

Note 2

IL.CA

V

0.49*V

0.51*V

DD

Reference Voltage for ADD, CMD inputs

REFCA

DD

NOTE :

1. For input only pins except RESET, V_REF= V_REFCA(DC)

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)

6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)

7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is

referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is

used when Vref + 0.125V is referenced.

8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is

referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is

used when Vref - 0.125V is referenced.

9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device

- 11 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 9 ] Single-ended AC & DC input levels for DQ and DM (1.35V)

DDR3L-800/1066

Min. Max.

DDR3L-1333/1600

Min. Max.

Symbol

Parameter

Unit

NOTE

1.35V

V

(DC90)

V

+ 90

V

+ 90

V

DD

DC input logic high

mV

1

IH.DQ

REF

DD

REF

V

(DC90)

V

- 90

V

- 90

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

1

IL.DQ

SS

REF

SS

REF

V

(AC160)

(AC135)

V + 160

REF

Note 2

-

1,2,5

IH.DQ

V

- 160

REF

Note 2

-

IL.DQ

V

+ 135

V + 135

REF

Note 2

IH.DQ

REF

V

- 135

V

- 135

REF

Note 2

0.49*V

IL.DQ

REF

Reference Voltage for DQ, DM

inputs

V_REF(DC)

0.49*V

0.51*V

DD

V

3,4

DQ

DD

NOTE :

1. For input only pins except RESET, V_REF= V_REFDQ(DC)

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).

4. For reference: approx. VDD/2 +/- 13.5 mV.

5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/

L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the

device is operated in the 1.35 voltage range.

[ Table 10 ] Single-ended AC & DC input levels for DQ and DM (1.5V)

DDR3-800/1066

Min. Max.

DDR3-1333/1600

Min. Max.

Symbol

Parameter

Unit

NOTE

1.5V

V

(DC100)

V

+ 100

V

+ 100

V

DD

DC input logic high

mV

1,5

1,6

IH.DQ

REF

DD

REF

V

(DC100)

(AC175)

(AC150)

(AC135)

V

- 100

V

- 100

REF

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

IL.DQ

IH.DQ

SS

REF

SS

V

+ 175

NOTE 2

-

1,2,7

REF

V

- 175

REF

NOTE 2

-

1,2,8

IL.DQ

V

+ 150

V

+ 150

NOTE 2

1,2,7

IH.DQ

REF

V

- 150

V

- 150

REF

NOTE 2

1,2,8

IL.DQ

REF

+ 135

NOTE 2

1,2,7,10

1,2,8,10

IH.DQ

REF

V

- 135

V

- 135

REF

NOTE 2

IL.DQ

REF

Reference Voltage for DQ, DM

inputs

V_REF(DC)

0.49*V

0.51*V

0.49*V

0.51*V

DD

V

3,4,9

DQ

DD

NOTE :

1. For input only pins except RESET, V_REF= V_REFDQ(DC)

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)

6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)

7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,

VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.

8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,

VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.

9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device

10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices

support this option.

- 12 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

8.2 V_REFTolerances

The dc-tolerance limits and ac-noise limits for the reference voltages V

and V

are illustrate in Figure 1. It shows a valid reference voltage

REFCA

REFDQ

V

(t) as a function of time. (V

stands for V

and V

likewise).

REFDQ

REF

REFCA

(DC) is the linear average of V

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on

REF

page 11. Furthermore V

(t) may temporarily deviate from V

(DC) by no more than ± 1% V

.

REF

DD

voltage

V_DD

V_SS

time

Figure 1. Illustration of V

(DC) tolerance and VREF ac-noise limits

REF

The voltage levels for setup and hold time measurements V (AC), V (DC), V (AC) and V (DC) are dependent on V

.

IH

IL

REF

"V

" shall be understood as V

(DC), as defined in Figure 1 .

REF

This clarifies, that dc-variations of V

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals.

(DC) deviations from the optimum position within the

REF

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

ac-noise. Timing

REF

and voltage effects due to ac-noise on V

up to the specified limit (+/-1% of V ) are included in DRAM timings and their associated deratings.

DD

REF

- 13 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential signals definition

tDVAC

V

.DIFF.AC.MIN

IH

V

.DIFF.MIN

0.0

IH

half cycle

V .DIFF.MAX

IL

V .DIFF.AC.MAX

IL

tDVAC

time

Figure 1. Definition of differential ac-swing and "time above ac level" tDVAC

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

[ Table 11 ] Differential AC & DC Input Levels

DDR3-800/1066/1333/1600

Symbol

Parameter

1.35V

1.5V

unit

NOTE

min

+0.18

max

NOTE 3

-0.18

min

+0.20

max

NOTE 3

-0.20

V

differential input high

differential input low

V

1

2

IHdiff

V

NOTE 3

ILdiff

V

(AC)

2 x (V (AC) - V

)

2 x (V (AC) - V

)

differential input high ac

differential input low ac

NOTE 3

IHdiff

IH

REF

IH

REF

V

2 x (V (AC) - V

)

2 x (V (AC) - V

)

REF

NOTE 3

ILdiff

NOTE :

1. Used to define a differential signal slew-rate.

IL

REF

IL

2. for CK - CK use V_IH/V_IL(AC) of ADD/CMD and V_REFCA; for DQS - DQS use V_IH/V_IL(AC) of DQs and V_REFDQ; if a reduced ac-high or ac-low level is used for a signal group,

then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V_IH(DC) max, V_IL(DC)min) for single-ended sig-

nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

- 14 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 12 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)

DDR3L-800/1066/1333/1600

(AC)| = 320mV tDVAC [ps] @ |V

tDVAC [ps] @ |V

(AC)| = 270mV

IH/Ldiff

Slew Rate [V/ns]

IH/Ldiff

min

189

162

109

91

max

min

201

179

134

119

100

76

max

> 4.0

4.0

-

3.0

2.0

1.8

1.6

69

1.4

40

1.2

note

44

1.0

note

< 1.0

NOTE: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.

[ Table 13 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)

DDR3-800/1066/1333/1600

tDVAC [ps] @ |V

(AC)| =

tDVAC [ps] @ |V

(AC)| = tDVAC [ps] @ |V

(AC)| =270mV

IH/Ldiff

Slew Rate [V/ns]

350mV

300mV

(DQS-DQS#)only(Optional)

min

75

max

min

175

170

167

119

102

81

max

min

214

191

146

131

113

88

max

> 4.0

4.0

-

57

3.0

50

2.0

38

1.8

34

1.6

29

1.4

22

54

1.2

note

19

56

1.0

note

11

< 1.0

note

NOTE: Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac)

level.

- 15 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

8.3.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for

single-ended signals.

CK and CK have to approximately reach V

min / V

max [approximately equal to the ac-levels { V (AC) / V (AC)} for ADD/CMD signals] in every

SEH

SEL IH IL

half-cycle.

DQS, DQSL, DQSU, DQS, DQSL have to reach V

proceeding and following a valid transition.

min / V

max [approximately the ac-levels { V (AC) / V (AC)} for DQ signals] in every half-cycle

SEL IH IL

SEH

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V 150(AC)/V 150(AC) is used for ADD/CMD sig-

IH

IL

nals, then these ac-levels apply also for the single-ended signals CK and CK .

V_DDor V_DDQ

V_SEHmin

V_SEH

V_DD/2 or V_DDQ/2

CK or DQS

V_SELmax

V_SEL

V_SSor V_SSQ

time

Figure 2. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V

, the single-ended components of differential signals have a requirement

REF

with respect to V /2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

DD

ended components of differential signals the requirement to reach V

mode characteristics of these signals.

max, V

min has no bearing on timing, but adds a restriction on the common

SEH

SEL

[ Table 14 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU

DDR3-800/1066/1333/1600

Symbol

Parameter

Unit

NOTE

Min

Max

(V /2)+0.175

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes

Single-ended low-level for CK, CK

NOTE3

V

1, 2

DD

V

SEH

(V /2)+0.175

DD

(V /2)-0.175

NOTE3

DD

V

SEL

(V /2)-0.175

DD

NOTE :

1. For CK, CK use V_IH/V_IL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use V_IH/V_IL(AC) of DQs.

2. V_IH(AC)/V_IL(AC) for DQs is based on V_REFDQ; V_IH(AC)/V_IL(AC) for ADD/CMD is based on V_REFCA; if a reduced ac-high or ac-low level is used for a signal group, then the

reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective

limits (V_IH(DC) max, V_IL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot

Specification"

- 16 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

8.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input

signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V is measured from the actual

IX

cross point of true and complement signal to the mid level between of V and V

.

SS

DD

V

DD

CK, DQS

V

IX

V

/2

DD

V

IX

CK, DQS

V

SS

Figure 3. VIX Definition

[ Table 15 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V

DDR3L-800/1066/1333/1600

Symbol

Parameter

Unit

NOTE

Min

-150

Max

150

V

Differential Input Cross Point Voltage relative to V /2 for CK,CK

mV

1

IX

DD

V

Differential Input Cross Point Voltage relative to V /2 for DQS,DQS

IX

DD

NOTE :

1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.

(VDD/2) + Vix(Min) - VSEL 25mV

VSEH - ((VDD/2) + Vix(Max)) 25mV

[ Table 16 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V

DDR3-800/1066/1333/1600

Symbol

Parameter

Unit

NOTE

Min

-150

-175

-150

Max

150

175

150

mV

V

Differential Input Cross Point Voltage relative to V /2 for CK,CK

IX

DD

1

Differential Input Cross Point Voltage relative to V /2 for DQS,DQS

IX

DD

NOTE :

1. Extended range for V_IXis only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V_SEL/ V_SEHof at least V_DD/2

±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.

- 17 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

8.5 Slew rate definition for Differential Input Signals

See 14.3 “Address/Command Setup, Hold and Derating :” on page 50 for single-ended slew rate definitions for address and command signals.

See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 56 for single-ended slew rate definitions for data signals.

8.6 Slew rate definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 17 and Figure 4.

[ Table 17 ] Differential input slew rate definition

Measured

Description

Defined by

From

To

V

[V

- V

Delta TRdiff

Differential input slew rate for rising edge (CK-CK and DQS-DQS)

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

NOTE :

ILdiffmax

IHdiffmin

ILdiffmax] /

Delta TFdiff

ILdiffmax] /

V

[V - V

IHdiffmin

ILdiffmax

The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.

V_IHdiffmin

0

V_ILdiffmax

delta TFdiff

delta TRdiff

Figure 4. Differential Input Slew Rate definition for DQS, DQS, and CK, CK

9. AC & DC Output Measurement Levels

9.1 Single-ended AC & DC Output Levels

[ Table 18 ] Single-ended AC & DC output levels

Symbol

Parameter

DDR3-800/1066/1333/1600

Units

NOTE

V

(DC)

DC output high measurement level (for IV curve linearity)

0.8 x V

0.5 x V

0.2 x V

V

OH

DDQ

V

DC output mid measurement level (for IV curve linearity)

DC output low measurement level (for IV curve linearity)

AC output high measurement level (for output SR)

AC output low measurement level (for output SR)

OM

(DC)

OL

V

(AC)

V

+ 0.1 x V

1

OH

TT

DDQ

V

- 0.1 x V

TT

OL

NOTE : 1. The swing of +/-0.1 x V_DDQis based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test

load of 25 to V_TT=V_DDQ/2.

9.2 Differential AC & DC Output Levels

[ Table 19 ] Differential AC & DC output levels

Symbol

(AC)

Parameter

DDR3-800/1066/1333/1600

Units

NOTE

V

AC differential output high measurement level (for output SR)

+0.2 x V

V

1

OHdiff

DDQ

V

(AC)

AC differential output low measurement level (for output SR)

-0.2 x V

V

1

OLdiff

DDQ

NOTE : 1. The swing of +/-0.2xV_DDQis based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test

load of 25 to V_TT=V_DDQ/2 at each of the differential outputs.

- 18 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) and V (AC)

OL

OH

for single ended signals as shown in Table 20 and Figure 5.

[ Table 20 ] Single-ended output slew rate definition

Description

Measured

Defined by

[V (AC)-V (AC)] / Delta TRse

From

(AC)

To

(AC)

V

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

OL

OH

OL

(AC)

V

(AC)

[V (AC)-V (AC)] / Delta TFse

OH OL

OH

OL

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 21 ] Single-ended output slew rate

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Operation

Voltage

Parameter

Symbol

Units

Min

1.75

2.5

Max

Min

1.75

2.5

Max

Min

1.75

2.5

Max

Min

1.75

2.5

Max

1)

1.35V

1.5V

V/ns

5

Single ended output slew rate

Description : SR : Slew Rate

SRQse

5

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals

For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in

the same byte lane are static (i.e they stay at either high or low).

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining

DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

V_OH(AC)

V_TT

V_OL(AC)

delta TFse

delta TRse

Figure 5. Single-ended Output Slew Rate Definition

- 19 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

(AC) and V

OH-

OLdiff

(AC) for differential signals as shown in Table 22 and Figure 6.

diff

[ Table 22 ] Differential output slew rate definition

Description

Measured

Defined by

From

To

(AC)

V

(AC)

V

[V

(AC)-V

OLdiff

(AC)] / Delta TRdiff

(AC)]/ Delta TFdiff

Differential output slew rate for rising edge

Differential output slew rate for falling edge

OLdiff

OHdiff

(AC)

V

(AC)

[V

(AC)-V

OHdiff OLdiff

OHdiff

OLdiff

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 23 ] Differential output slew rate

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Operation

Voltage

Parameter

Symbol

Units

Min

Max

12

Min

3.5

5

Max

Min

3.5

5

Max

12

Min

3.5

5

Max

12

1.35V

1.5V

3.5

5

12

10

V/ns

Differential output slew rate

Description : SR : Slew Rate

SRQdiff

10

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals

For Ron = RZQ/7 setting

V_OHdiff(AC)

V_TT

_OLdiff(AC)

V

delta TFdiff

delta TRdiff

Figure 6. Differential Output Slew Rate Definition

9.5 Reference Load for AC Timing and Output Slew Rate

Figure 7 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate

measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. Sys-

tem designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their

production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

V

DDQ

DQ

DQS

CK/CK

DUT

V

= V

/2

DDQ

TT

25

Reference

Point

Figure 7. Reference Load for AC Timing and Output Slew Rate

- 20 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.6 Overshoot/Undershoot Specification

9.6.1 Address and Control Overshoot and Undershoot specifications

[ Table 24 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT)

Specification

Parameter

Unit

DDR3-800

1.35V

DDR3-1066

DDR3-1333

DDR3-1600

Maximum peak amplitude allowed for overshoot area (See Figure 8)

Maximum peak amplitude allowed for undershoot area (See Figure 8)

0.4

0.5

0.4

V

Maximum overshoot area above V (See Figure 8)

0.67

0.33

V-ns

DD

Maximum undershoot area below V (See Figure 8)

0.67

0.5

0.4

0.33

V-ns

SS

1.5V

Maximum peak amplitude allowed for overshoot area (See Figure 8)

Maximum peak amplitude allowed for undershoot area (See Figure 8)

0.4

0.5

0.4

V

Maximum overshoot area above V (See Figure 8)

0.67

0.33

V-ns

DD

Maximum undershoot area below V (See Figure 8)

0.67

0.5

0.4

0.33

V-ns

SS

(A0-A15, BA0-BA3, CS#, RAS#, CAS#, WE#, CKE, ODT)

NOTE :

1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings

2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings

Maximum Amplitude

Overshoot Area

V_DD

V_SS

Volts

(V)

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 8. Address and Control Overshoot and Undershoot Definition

- 21 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications

[ Table 25 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK)

Specification

Parameter

Unit

DDR3-800

1.35V

DDR3-1066

DDR3-1333

DDR3-1600

Maximum peak amplitude allowed for overshoot area (See Figure 9)

Maximum peak amplitude allowed for undershoot area (See Figure 9)

0.4

V

Maximum overshoot area above V

(See Figure 9)

0.25

0.19

0.15

0.13

V-ns

DDQ

Maximum undershoot area below V

0.25

0.19

0.15

0.13

V-ns

SSQ

1.5V

Maximum peak amplitude allowed for overshoot area (See Figure 9)

Maximum peak amplitude allowed for undershoot area (See Figure 9)

0.4

V

Maximum overshoot area above V

(See Figure 9)

0.25

0.19

0.15

0.13

V-ns

DDQ

Maximum undershoot area below V

0.25

0.19

0.15

0.13

V-ns

SSQ

(A0-A15, BA0-BA3, CS#, RAS#, CAS#, WE#, CKE, ODT)

NOTE :

1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings

2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings

Maximum Amplitude

Overshoot Area

V_DDQ

V_SSQ

Volts

(V)

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 9. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition

- 22 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.7 34ohm Output Driver DC Electrical Characteristics

A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ

as follows:

RON = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm)

34

The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows

V

-V

DDQ OUT

under the condition that RONpd is turned off

RONpu =

RONpd =

l Iout l

V

OUT

under the condition that RONpu is turned off

Output Driver

l Iout l

V_DDQ

Ipu

To

other

circuity

RON

Pu

DQ

Iout

RON

Pd

Vout

Ipd

V_SSQ

Figure 10. Output Driver : Definition of Voltages and Currents

- 23 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 26 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ;

entire operating temperature range ; after proper ZQ calibration

RONnom

Resistor

Vout

Min

Nom

Max

Units

Notes

1.35V

V

= 0.2 x V

0.6

0.9

0.6

0.9

0.6

1.0

1.15

1.45

1.15

1.45

1.15

1,2,3

OLdc

DDQ

= 0.5 x V

= 0.8 x V

= 0.2 x V

RON34pd

OMdc

DDQ

V

OHdc

DDQ

34Ohms

RZQ/7

V

OLdc

DDQ

V

= 0.5 x V

RON34pu

RON40pd

RON40pu

OMdc

DDQ

V

= 0.8 x V

= 0.2 x V

OHdc

V

OLdc

= 0.5 x V

= 0.8 x V

= 0.2 x V

OMdc

DDQ

V

OHdc

40Ohms

RZQ/6

V

OLdc

DDQ

V

= 0.5 x V

OMdc

DDQ

V

= 0.8 x V

= 0.5 x V

OHdc

Mismatch between Pull-up and Pull-down,

MMpupd

-10

10

%

1,2,4

OMdc

DDQ

1.5V

V

= 0.2 x V

0.6

0.9

0.6

0.9

0.6

1.0

1.1

1.4

1.1

1.4

1.1

1,2,3

OLdc

DDQ

V

= 0.5 x V

RON34pd

OMdc

DDQ

V

= 0.8 x V

= 0.2 x V

OHdc

34Ohms

RZQ/7

V

OLdc

= 0.5 x V

= 0.8 x V

= 0.2 x V

RON34pu

OMdc

DDQ

V

OHdc

V

OLdc

DDQ

V

= 0.5 x V

RON40pd

OMdc

DDQ

V

= 0.8 x V

= 0.2 x V

OHdc

40Ohms

RZQ/6

V

OLdc

= 0.5 x V

= 0.8 x V

RON40pu

OMdc

DDQ

V

OHdc

Mismatch between Pull-up and Pull-down,

MMpupd

V

= 0.5 x V

-10

10

%

1,2,4

OMdc

DDQ

NOTE :

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-

tion, see following section on voltage and temperature sensitivity

2. The tolerance limits are specified under the condition that V_DDQ= V_DDand that V_SSQ= V_SS

3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X V_DDQ. Other calibration schemes may be used to achieve the linearity spec shown

above, e.g. calibration at 0.2 X V_DDQand 0.8 X V_DDQ

4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X V_DDQ

:

RONpu - RONpd

x 100

MMpupd =

RONnom

- 24 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.7.1 Output Drive Temperature and Voltage Sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 27 and Table 28.

T = T - T(@calibration); V = V

- V

(@calibration); V = V

DDQ

DDQ DD DDQ

*dR dT and dR dV are not subject to production test but are verified by design and characterization

ON

[ Table 27 ] Output Driver Sensitivity Definition

Min

Max

Units

RONPU@V

RON@V

0.6 - dR dTH * |T| - dR_ONdVH * |V|

1.1 + dR dTH * |T| + dR_ONdVH * |V|

RZQ/7

OHDC

ON

0.9 - dR dTM * |T| - dR_ONdVM * |V|

1.1 + dR dTM * |T| + dR_ONdVM * |V|

OMDC

ON

RONPD@

0.6 - dR dTL * |T| - dR_ONdVL * |V|

1.1 + dR dTL * |T| + dR_ONdVL * |V|

VOLDC

ON

[ Table 28 ] Output Driver Voltage and Temperature Sensitivity

Speed Bin

800/1066/1333

1600

Units

Min

0

Max

1.5

Min

0

Max

1.5

dR dTM

%/C

%/mV

%/C

ON

dR dVM

0

0.15

1.5

0

0.13

1.5

ON

dR dTL

0

ON

dR dVL

0

0.15

1.5

0

0.13

1.5

%/mV

%/C

ON

dR dTH

0

ON

dR dVH

0

0.15

0

0.13

%/mV

ON

9.8 On-Die Termination (ODT) Levels and I-V Characteristics

On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register.

ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins.

A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as

follows :

V

-V

DDQ OUT

under the condition that RTTpd is turned off

under the condition that RTTpu is turned off

RTTpu =

RTTpd =

l Iout l

V

OUT

l Iout l

Chip in Termination Mode

ODT

V_DDQ

Ipu

Iout=Ipd-Ipu

To

RTT_Pu

other

circuitry

like

DQ

RCV,

...

Iout

RTT_Pd

V_OUT

V_SSQ

Ipd

Figure 11. On-Die Termination : Definition of Voltages and Currents

- 25 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.8.1 ODT DC Electrical Characteristics

Table 29 provides and overview of the ODT DC electrical characteristics. They values for RTT

RTT

120pu240, 40pd80,

60pd120,

60pu120,

120pd240,

RTT

are not specification requirements, but can be used as design guide lines:

40pu80,

30pd60,

30pu60,

20pd40,

20pu40

[ Table 29 ] ODT DC Electrical Characteristics, assuming RZQ=240ohm +/- 1% entire operating temperature range; after proper ZQ calibration

1.35V

MR1 (A9,A6,A2)

RTT

RESISTOR

Vout

Min

Nom

Max

Unit

Notes

V

(DC) 0.2XV

R

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

-5

1.0

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

5

1,2,3,4

1,2,5

OL

DDQ

ZQ

RTT

0.5XV

R

120pd240

DDQ

ZQ

(DC) 0.8XV

R

OH

DDQ

ZQ

V

(DC) 0.2XV

R

(0,1,0)

120 ohm

OL

DDQ

ZQ

RTT

0.5XV

R

120pu240

DDQ

ZQ

V

(DC) 0.8XV

R

OH

DDQ

ZQ

RTT

V (AC) to V (AC)

R

/2

120

IL

IH

ZQ

V

(DC) 0.2XV

R

/2

/4

/3

/6

/4

/8

/6

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

60pd120

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

(0,0,1)

(0,1,1)

(1,0,1)

(1,0,0)

60 ohm

40 ohm

30 ohm

20 ohm

OL

DDQ

RTT

0.5XV

DDQ

60pu120

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

60

IL

IH

V

(DC) 0.2XV

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

40pd80

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

OL

DDQ

RTT

0.5XV

DDQ

40pu80

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

40

IL

IH

V

(DC) 0.2XV

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

30pd60

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

OL

DDQ

RTT

0.5XV

DDQ

30pu60

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

30

IL

IH

V

(DC) 0.2XV

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

20pd40

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

OL

DDQ

RTT

0.5XV

DDQ

20pu40

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

R

/12

20

IL

IH

ZQ

Deviation of V_Mw.r.t V_DDQ/2, VM

%

1,2,5,6

- 26 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

1.5V

Vout

MR1 (A9,A6,A2)

RTT

RESISTOR

Min

Nom

Max

Unit

Notes

V

(DC) 0.2XV

R

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

-5

1.0

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

5

1,2,3,4

1,2,5

OL

DDQ

ZQ

RTT

0.5XV

R

120pd240

DDQ

ZQ

(DC) 0.8XV

R

OH

DDQ

ZQ

V

(DC) 0.2XV

R

(0,1,0)

120 ohm

OL

DDQ

ZQ

RTT

0.5XV

R

120pu240

DDQ

ZQ

V

(DC) 0.8XV

R

OH

DDQ

ZQ

RTT

V (AC) to V (AC)

R

/2

120

IL

IH

ZQ

V

(DC) 0.2XV

R

/2

/4

/3

/6

/4

/8

/6

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

60pd240

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

(0,0,1)

(0,1,1)

(1,0,1)

(1,0,0)

60 ohm

40 ohm

30 ohm

20 ohm

OL

DDQ

RTT

0.5XV

DDQ

60pu240

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

60

IL

IH

V

(DC) 0.2XV

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

40pd240

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

OL

DDQ

RTT

0.5XV

DDQ

40pu240

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

40

IL

IH

V

(DC) 0.2XV

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

60pd240

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

OL

DDQ

RTT

0.5XV

DDQ

60pu240

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

60

IL

IH

V

(DC) 0.2XV

1,2,3,4

1,2,5

OL

DDQ

RTT

0.5XV

60pd240

DDQ

V

(DC) 0.8XV

OH

DDQ

V

(DC) 0.2XV

OL

DDQ

RTT

0.5XV

DDQ

60pu240

V

(DC) 0.8XV

DDQ

OH

RTT

V (AC) to V (AC)

R

/12

60

IL

IH

ZQ

Deviation of V_Mw.r.t V_DDQ/2, VM

%

1,2,5,6

- 27 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-

tion, see following section on voltage and temperature sensitivity

2. The tolerance limits are specified under the condition that V_DDQ= V_DDand that V_SSQ= V_SS

3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XV_DDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g.

calibration at 0.2XV_DDQand 0.8XV_DDQ

.

4. Not a specification requirement, but a design guide line

5. Measurement definition for RTT:

Apply V_IH(AC) to pin under test and measure current I(V_IH(AC)), then apply V_IL(AC) to pin under test and measure current I(V_IL(AC)) respectively

V

(AC) - V (AC)

IL

IH

RTT

=

I(V (AC)) - I(V (AC))

IH

IL

6. Measurement definition for V_Mand V_M: Measure voltage (V_M) at test pin (midpoint) with no load

2 x V_M

- 1

x 100

 V_M

=

V

DDQ

9.8.2 ODT Temperature and Voltage sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to table below

T = T - T(@calibration); V = V

- V

(@calibration); V = V

DDQ

DD

[ Table 30 ] ODT Sensitivity Definition

Min

Max

Units

0.9 - dR dT * |T| - dR_TTdV * |V|

1.6 + dR dT * |T| + dR_TTdV * |V|

RTT

RZQ/2,4,6,8,12

TT

[ Table 31 ] ODT Voltage and Temperature Sensitivity

Min

0

Max

1.5

Units

%/C

dR dT

TT

dR dV

0

0.15

%/mV

TT

NOTE : These parameters may not be subject to production test. They are verified by design and characterization.

- 28 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

9.9 ODT Timing Definitions

9.9.1 Test Load for ODT Timings

Different than for timing measurements, the reference load for ODT timings is defined in Figure 12.

V_DDQ

DUT

DQ, DM

CK,CK

V

=

TT

SSQ

DQS , DQS

TDQS , TDQS

RTT

=25 ohm

V_SSQ

Timing Reference Points

Figure 12. ODT Timing Reference Load

9.9.2 ODT Timing Definitions

Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 32 and subsequent figures. Measurement reference settings are provided

in Table 33 .

[ Table 32 ] ODT Timing Definitions

Symbol

tAON

Begin Point Definition

End Point Definition

Figure

Rising edge of CK - CK defined by the end point of ODTLon

Rising edge of CK - CK with ODT being first registered high

Rising edge of CK - CK defined by the end point of ODTLoff

Rising edge of CK - CK with ODT being first registered low

Extrapolated point at V

Figure 13

Figure 14

Figure 15

Figure 16

SSQ

tAONPD

tAOF

Extrapolated point at V

End point: Extrapolated point at V

RTT_Nom

tAOFPD

Rising edge of CK - CK defined by the end point of ODTLcnw,

ODTLcwn4 of ODTLcwn8

End point: Extrapolated point at V

respectively

and V

RTT_Wr RTT_Nom

tADC

Figure 17

[ Table 33 ] Reference Settings for ODT Timing Measurements

Measured

RTT_Nom Setting

RTT_Wr Setting

V

[V]

V

[V]

SW2

NOTE

SW1

Parameter

R

/4

NA

0.05

0.10

0.05

0.10

0.05

0.10

0.05

0.10

0.20

0.10

0.20

0.10

0.20

0.10

0.20

0.10

0.20

0.25

ZQ

tAON

R

/12

ZQ

R

/4

ZQ

tAONPD

tAOF

R

/12

ZQ

R

/4

ZQ

R

/12

ZQ

R

/4

ZQ

tAOFPD

tADC

R

/12

ZQ

R

/2

ZQ

- 29 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

Begin point : Rising edge of CK - CK

defined by the end point of ODTLon

CK

V

TT

t_AON

T_SW2

T_SW1

DQ, DM

DQS , DQS

TDQS , TDQS

V_SW2

V_SW1

V

SSQ

End point Extrapolated point at V

SSQ

Figure 13. Definition of tAON

Begin point : Rising edge of CK - CK

with ODT being first registered high

CK

V

TT

t_AONPD

T_SW2

T_SW1

DQ, DM

DQS , DQS

TDQS , TDQS

V_SW2

V_SW1

V

SSQ

End point Extrapolated point at V

SSQ

Figure 14. Definition of tAONPD

Begin point : Rising edge of CK - CK

defined by the end point of ODTLoff

CK

V

TT

t_AOF

End point Extrapolated point at V

RTT_Nom

V

RTT_Nom

T_SW2

T_SW1

DQ, DM

DQS , DQS

TDQS , TDQS

V_SW2

V_SW1

SSQ

TD_TAON_DEF

Figure 15. Definition of tAOF

- 30 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

Begin point : Rising edge of CK - CK

with ODT being first registered low

CK

V

TT

t

AOFPD

End point Extrapolated point at V

RTT_Nom

V

RTT_Nom

T

SW2

DQ, DM

DQS , DQS

T

SW1

V

SW2

V

TDQS , TDQS

SW1

V

SSQ

Figure 16. Definition of tAOFPD

Begin point : Rising edge of CK - CK

defined by the end point of ODTLcnw

Begin point : Rising edge of CK - CK defined by

the end point of ODTLcwn4 or ODTLcwn8

CK

V

TT

t

ADC

End point Extrapolated point at V

RTT_Nom

V

RTT_Nom

V

RTT_Nom

T

SW21

End point

Extrapolated point

at V

T

DQ, DM

DQS , DQS

TDQS , TDQS

SW22

V

SW2

T

SW11

RTT_Nom

T

SW12

V

SW1

End point Extrapolated point at V

V

RTT_Wr

V

SSQ

Figure 17. Definition of tADC

- 31 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

10. IDD Current Measure Method

10.1 IDD Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and

IDDQ measurements.

- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and

IDD7) are measured as time-averaged currents with all V balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in

DD

IDD currents.

- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all V

balls of the DDR3 SDRAM under test tied

DDQ

together. Any IDD current is not included in IDDQ currents.

Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO

power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since V and V

DD

DDQ

are using one merged-power layer in Module PCB.

For IDD and IDDQ measurements, the following definitions apply :

- "0" and "LOW" is defined as V <= V AC(max).

IN

IL

- "1" and "HIGH" is defined as V >= V AC(min).

IN

IH

- "FLOATING" is defined as inputs are V

= V / 2.

DD

REF

- "Timing used for IDD and IDDQ Measured - Loop Patterns" are provided in Table 34

- "Basic IDD and IDDQ Measurement Conditions" are described in Table 35

- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39.

- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting

RON = RZQ/7 (34 Ohm in MR1);

Qoff = 0B (Output Buffer enabled in MR1);

RTT_Nom = RZQ/6 (40 Ohm in MR1);

RTT_Wr = RZQ/2 (120 Ohm in MR2);

TDQS Feature disabled in MR1

- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.

- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}

- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}

- RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms;

During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC

[ Table 34 ] Timing used for IDD and IDDQ Measured - Loop Patterns

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Parameter Bin

tCKmin(IDD)

Unit

6-6-6

2.5

6

7-7-7

1.875

7

9-9-9

1.5

9

11-11-11

1.25

11

ns

CL(IDD)

nCK

tRCDmin(IDD)

tRCmin(IDD)

tRASmin(IDD)

tRPmin(IDD)

6

7

9

11

21

15

6

27

20

7

33

24

9

39

28

11

x4/x8

x16

16

20

4

20

27

4

20

30

4

24

tFAW(IDD)

tRRD(IDD)

32

x4/x8

x16

5

4

6

5

6

tRFC(IDD) - 512Mb

tRFC(IDD) - 1Gb

tRFC(IDD) - 2Gb

tRFC(IDD) - 4Gb

tRFC(IDD) - 8Gb

36

44

64

104

140

48

59

86

139

187

60

74

107

174

234

72

88

128

208

280

- 32 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

I_DD

I_DDQ

V_DD

V_DDQ

RESET

CK/CK

CKE

CS

DQS, DQS

DQ, DM,

R

_TT= 25 Ohm

V_DDQ/2

RAS, CAS, WE

TDQS, TDQS

A, BA

ODT

ZQ

V_SS

V_SSQ

[NOTE : DIMM level Output test load condition may be different from above]

Figure 18. Measurement Setup and Test Load for IDD and IDDQ Measurements

Application specific

IDDQ

Test Load

memory channel

environment

Channel

IO Power

Simulation

IDDQ

Measurement

IDDQ

Simulation

Correlation

Correction

Channel IO Power

Number

Figure 19. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.

- 33 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 35 ] Basic IDD and IDDQ Measurement Conditions

Symbol

Description

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: High between ACT and PRE; Command, Address,

Bank Address Inputs: partially toggling according to Table 32 on page 31 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active

at a time: 0,0,1,1,2,2,... (see Table 32); Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0; Pattern Details: see Table 32

IDD0

IDD1

Operating One Bank Active-Read-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: High between ACT, RD and PRE; Command,

Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 on page 32 ; DM:stable at 0; Bank Activity: Cycling with one bank active at

a time: 0,0,1,1,2,2,... (see Table 33); Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0; Pattern Details: see Table 33

Precharge Standby Current

CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-

gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

IDD2N

Registers²⁾; ODT Signal: stable at 0; Pattern Details: see Table 34

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-

gling according to Table 35 on page 33 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

Registers²⁾; ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35

IDD2NT

IDDQ2NT

IDD2P0

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0; Pre-

charge Power Down Mode: Slow Exi³⁾

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32; BL: 8¹⁾; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0; Pre-

charge Power Down Mode: Fast Exit³⁾

IDD2P1

IDD2Q

IDD3N

IDD3P

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0

Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-

gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

Registers²⁾; ODT Signal: stable at 0; Pattern Details: see Table 34

Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;

Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0

Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: par-

tially toggling according to Table 36 on page 33 ; Data IO: seamless read data burst with different data between one burst and the next one according to

Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 11); Output Buffer and

IDD4R

IDDQ4R

IDD4W

RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0; Pattern Details: see Table 36

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-

tially toggling according to Table 37 on page 34 ; Data IO: seamless write data burst with different data between one burst and the next one according to

Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT:

Enabled in Mode Registers²⁾; ODT Signal: stable at HIGH; Pattern Details: see Table 37

Burst Refresh Current

CKE: High; External clock: On; tCK, CL, nRFC: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS: High between REF; Command, Address, Bank Address

Inputs: partially toggling according to Table 38 on page 34 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38);

Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0; Pattern Details: see Table 38

IDD5B

IDD6

Self Refresh Current: Normal Temperature Range

TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled⁴⁾; Self-Refresh Temperature Range (SRT): Normal⁵⁾; CKE: Low; External clock: Off; CK and CK:

LOW; CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-

Refresh operation; Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: FLOATING

- 34 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 33 ] Basic IDD and IDDQ Measurement Conditions

Symbol

Description

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 34 on page 32 ; BL: 8¹⁾; AL: CL-1; CS: High between ACT and RDA;

Command, Address, Bank Address Inputs: partially toggling according to Table 39 on page 35 ; Data IO: read data bursts with different data between one

burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing,

IDD7

IDD8

see Table 39 ; Output Buffer and RTT: Enabled in Mode Registers²⁾; ODT Signal: stable at 0; Pattern Details: see Table 39

RESET Low Current

RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

FLOATING

NOTE :

1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6) Read Burst type : Nibble Sequential, set MR0 A[3]=0B

- 35 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

1)

[ Table 36 ] IDD0 Measurement - Loop Pattern

0

1,2

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

3,4

...

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

repeat pattern 1...4 until nRC - 1, truncate if necessary

nRAS

0

1

0

00

0

-

...

1*nRC + 0

1*nRC + 1, 2

1*nRC + 3, 4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary

PRE 00

1*nRC + nRAS

...

0

1

0

F

0

repeat 1...4 until 2*nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

- 36 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

1)

[ Table 37 ] IDD1 Measurement - Loop Pattern

0

1,2

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

-

3,4

...

repeat pattern 1...4 until nRCD- 1, truncate if necessary

RD

repeat pattern 1...4 until nRAS - 1, truncate if necessary

PRE

repeat pattern 1...4 until nRC - 1, truncate if necessary

nRCD

...

0

1

0

1

0

00

0

00000000

-

nRAS

0

1

0

...

1*nRC+0

1*nRC + 1, 2

1*nRC + 3, 4

...

ACT

D, D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary

RD 00

repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary

1*nRC + nRCD

...

0

1

0

1

0

F

0

00110011

-

1*nRC + nRAS

...

PRE

0

1

0

00

0

repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

1

2

3

4

5

6

7

2*nRC

4*nRC

6*nRC

8*nRC

10*nRC

12*nRC

14*nRC

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

1)

[ Table 38 ] IDD2 and IDD3N Measurement - Loop Pattern

0

D

1

0

1

0

1

0

1

0

00

0

F

0

-

1

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, use BA[2:0] = 1 instead

repeat Sub-Loop 0, use BA[2:0] = 2 instead

repeat Sub-Loop 0, use BA[2:0] = 3 instead

repeat Sub-Loop 0, use BA[2:0] = 4 instead

repeat Sub-Loop 0, use BA[2:0] = 5 instead

repeat Sub-Loop 0, use BA[2:0] = 6 instead

repeat Sub-Loop 0, use BA[2:0] = 7 instead

8-11

12-15

16-19

20-23

24-27

28-31

NOTE :

1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

- 37 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

1)

[ Table 39 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern

0

D

1

0

1

0

1

0

1

0

00

0

F

0

-

1

2

3

1

2

3

4

5

6

7

4-7

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

8-11

12-15

16-19

20-23

24-27

28-31

NOTE :

1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

1)

[ Table 40 ] IDD4R and IDDQ4R Measurement - Loop Pattern

0

RD

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

1

-

2,3

D,D

RD

D

-

4

00110011

5

-

6,7

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

- 38 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

1)

[ Table 41 ] IDD4W Measurement - Loop Pattern

0

WR

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

0

F

0

00000000

1

-

2,3

D,D

WR

D

-

4

00110011

5

-

6,7

D,D

1

2

3

4

5

6

7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

repeat Sub-Loop 0, but BA[2:0] = 1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 0, but BA[2:0] = 3

repeat Sub-Loop 0, but BA[2:0] = 4

repeat Sub-Loop 0, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 0, but BA[2:0] = 7

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

1)

[ Table 42 ] IDD5B Measurement - Loop Pattern

0

1

0

1,2

REF

D

0

1

0

1

0

1

0

1

0

00

0

F

0

-

3,4

D,D

5...8

repeat cycles 1...4, but BA[2:0] = 1

repeat cycles 1...4, but BA[2:0] = 2

repeat cycles 1...4, but BA[2:0] = 3

repeat cycles 1...4, but BA[2:0] = 4

repeat cycles 1...4, but BA[2:0] = 5

repeat cycles 1...4, but BA[2:0] = 6

repeat cycles 1...4, but BA[2:0] = 7

9...12

13...16

17...20

21...24

25...28

29...32

33...nRFC - 1

2

repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

2. DQ signals are MID-LEVEL.

- 39 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

1)

[ Table 43 ] IDD7 Measurement - Loop Pattern

0

1

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

-

00000000

-

0

1

2

...

repeat above D Command until nRRD - 1

nRRD

nRRD + 1

nRRD + 2

...

ACT

RDA

D

0

1

0

1

0

1

0

1

0

1

00

0

1

0

F

0

-

00110011

-

repeat above D Command until 2*nRRD-1

repeat Sub-Loop 0, but BA[2:0] = 2

repeat Sub-Loop 1, but BA[2:0] = 3

2

3

2 * nRRD

3 * nRRD

D

1

0

3

00

0

F

0

-

4

4 * nRRD

Assert and repeat above D Command until nFAW - 1, if necessary

repeat Sub-Loop 0, but BA[2:0] = 4

5

6

7

8

nFAW

nFAW+nRRD

nFAW+2*nRRD

nFAW+3*nRRD

repeat Sub-Loop 1, but BA[2:0] = 5

repeat Sub-Loop 0, but BA[2:0] = 6

repeat Sub-Loop 1, but BA[2:0] = 7

D

1

0

7

00

0

F

0

-

9

nFAW+4*nRRD

Assert and repeat above D Command until 2*nFAW - 1, if necessary

2*nFAW+0

2*nFAW+1

ACT

RDA

D

0

1

0

1

0

1

0

1

0

00

0

1

0

F

0

-

00110011

-

10

2*nFAW+2

Repeat above D Command until 2*nFAW + nRRD - 1

2*nFAW+nRRD

ACT

RDA

D

0

1

0

1

0

1

0

1

0

1

00

0

1

0

-

2*nFAW+nRRD+1

00000000

-

11

2*nFAW+nRRD+2

Repeat above D Command until 2*nFAW + 2*nRRD - 1

repeat Sub-Loop 10, but BA[2:0] = 2

12

13

2*nFAW+2*nRRD

2*nFAW+3*nRRD

repeat Sub-Loop 11, but BA[2:0] = 3

D

1

0

3

00

0

-

14

2*nFAW+4*nRRD

Assert and repeat above D Command until 3*nFAW - 1, if necessary

repeat Sub-Loop 10, but BA[2:0] = 4

15

16

17

18

3*nFAW

3*nFAW+nRRD

3*nFAW+2*nRRD

3*nFAW+3*nRRD

repeat Sub-Loop 11, but BA[2:0] = 5

repeat Sub-Loop 10, but BA[2:0] = 6

repeat Sub-Loop 11, but BA[2:0] = 7

D

1

0

7

00

0

-

19

3*nFAW+4*nRRD

Assert and repeat above D Command until 4*nFAW - 1, if necessary

NOTE :

1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.

- 40 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

11. 4Gb DDR3 SDRAM Q-die IDD Specification Table

[ Table 44 ] IDD Specification for 4Gb DDR3 Q-die

256Mx16 (K4B4G1646Q)

DDR3-1066

7-7-7

DDR3-1333

9-9-9

DDR3-1600

11-11-11

Symbol

Unit

NOTE

1.35V

TBD

1.5V

TBD

1.35V

TBD

1.5V

TBD

1.35V

TBD

1.5V

TBD

IDD0

IDD1

mA

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

IDD2NT

IDDQ2NT

IDD2Q

IDD3P

IDD3N

IDD4R

IDDQ4R

IDD4W

IDD5B

IDD6

IDD7

IDD8

NOTE : V_DDcondition : 1.45V for 1.35V operation, 1.575V for 1.5V operation

- 41 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

12. Input/Output Capacitance

[ Table 45 ] Input/Output Capacitance

DDR3-800

Min Max

1.35V

DDR3-1066

DDR3-1333

DDR3-1600

Parameter

Symbol

Units NOTE

Min

Max

Min

Max

Min

Max

Input/output capacitance

CIO

CCK

1.4

0.8

0

2.5

1.6

0.15

1.3

0.2

0.3

0.5

1.4

0.8

0

2.5

1.6

0.15

1.3

0.2

0.3

0.5

1.4

0.8

0

2.3

1.4

0.8

0

2.2

1.4

pF

1,2,3

2,3

(DQ, DM, DQS, DQS, TDQS, TDQS)

Input capacitance

(CK and CK)

Input capacitance delta

(CK and CK)

CDCK

0.15

1.3

0.15

1.2

2,3,4

Input capacitance

CI

0.75

0

0.75

0

0.75

0

0.75

0

2,3,6

(All other input-only pins)

Input/Output capacitance delta

(DQS and DQS)

CDDQS

CDI_CTRL

CDI_ADD_CMD

0.15

0.2

0.15

0.2

2,3,5

Input capacitance delta

-0.5

-0.4

2,3,7,8

2,3,9,10

(All control input-only pins)

Input capacitance delta

0.4

(all ADD and CMD input-only pins)

Input/output capacitance delta

CDIO

CZQ

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

pF

2,3,11

(DQ, DM, DQS, DQS, TDQS, TDQS)

Input/output capacitance of ZQ pin

2, 3, 12

1.5V

Input/output capacitance

CIO

CCK

1.4

0.8

0

3.0

1.6

0.15

1.4

0.2

0.3

0.5

1.4

0.8

0

2.7

1.6

1.4

0.8

0

2.5

1.4

0.8

0

2.3

1.4

pF

1,2,3

2,3

(DQ, DM, DQS, DQS, TDQS, TDQS)

Input capacitance

(CK and CK)

Input capacitance delta

(CK and CK)

CDCK

0.15

1.35

0.2

0.15

1.3

0.15

1.3

2,3,4

Input capacitance

CI

0.75

0

0.75

0

0.75

0

0.75

0

2,3,6

(All other input-only pins)

Input capacitance delta

(DQS and DQS)

CDDQS

CDI_CTRL

CDI_ADD_CMD

0.15

0.2

0.15

0.2

2,3,5

Input capacitance delta

-0.5

0.3

-0.4

2,3,7,8

2,3,9,10

(All control input-only pins)

Input capacitance delta

0.5

0.4

(all ADD and CMD input-only pins)

Input/output capacitance delta

CDIO

CZQ

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

pF

2,3,11

(DQ, DM, DQS, DQS, TDQS, TDQS)

Input/output capacitance of ZQ pin

2, 3, 12

NOTE :

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS

2. This parameter is not subject to production test. It is verified by design and characterization.

The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with

_DD, V_DDQ, V_SS, V_SSQapplied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). V_DD=V_DDQ=1.5V or 1.35V, V_BIAS=V_DD/2 and on-

V

die termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK

5. Absolute value of CIO(DQS)-CIO(DQS)

6. CI applies to ODT, CS, CKE, A0-A14, BA0-BA2, RAS, CAS, WE.

7. CDI_CTRL applies to ODT, CS and CKE

8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))

9. CDI_ADD_CMD applies to A0-A14, BA0-BA2, RAS, CAS and WE

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance on ZQ pin: 5pF

- 42 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600

13.1 Clock Specification

The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3

SDRAM device.

13.1.1 Definition for tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to

rising edge.

N

tCKj

N=200

N



j=1

13.1.2 Definition for tCK(abs)

tCK(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to produc-

tion test.

13.1.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:

tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:

N

tCHj

tCLj

N x tCK(avg) N=200



N x tCK(avg)

N=200



j=1

13.1.4 Definition for note for tJIT(per), tJIT(per, Ick)

tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}

tJIT(per) defines the single period jitter when the DLL is already locked.

tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.

tJIT(per) and tJIT(per,lck) are not subject to production test.

13.1.5 Definition for tJIT(cc), tJIT(cc, Ick)

tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}

tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.

tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

tJIT(cc) and tJIT(cc,lck) are not subject to production test.

13.1.6 Definition for tERR(nper)

tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.

- 43 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

13.2 Refresh Parameters by Device Density

[ Table 46 ] Refresh parameters by device density

Parameter

Symbol

1Gb

110

7.8

2Gb

160

7.8

4Gb

260

7.8

8Gb

350

7.8

Units

ns

NOTE

All Bank Refresh to active/refresh cmd time

tRFC

0CT

 85C

 95C

s

CASE

Average periodic refresh interval

tREFI

85CT

3.9

s

1

CASE

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in

this material.

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

[ Table 47 ] DDR3-800 Speed Bins

Speed

DDR3-800

6 - 6 - 6

CL-nRCD-nRP

Units

NOTE

Parameter

Symbol

tAA

min

15

max

Internal read command to first data

ACT to internal read or write delay time

PRE command period

20

ns

tRCD

15

-

tRP

15

-

ns

ACT to ACT or REF command period

ACT to PRE command period

tRC

52.5

37.5

3.0

2.5

ns

tRAS

9*tREFI

3.3

ns

CL = 5

CWL = 5

tCK(AVG)

ns

1,2,3,4,9,10

1,2,3

CL = 6

3.3

ns

Supported CL Settings

Supported CWL Settings

5,6

5

nCK

[ Table 48 ] DDR3-1066 Speed Bins

Speed

DDR3-1066

7 - 7 - 7

CL-nRCD-nRP

Units

NOTE

Parameter

Internal read command to first data

ACT to internal read or write delay time

PRE command period

Symbol

tAA

min

13.125

50.625

37.5

max

20

ns

tRCD

-

tRP

-

ns

ACT to ACT or REF command period

ACT to PRE command period

tRC

ns

tRAS

9*tREFI

3.3

ns

CWL = 5

CWL = 6

CWL = 5

CWL = 6

CWL = 5

CWL = 6

CWL = 5

CWL = 6

tCK(AVG)

3.0

ns

1,2,3,4,5,9,10

CL = 5

CL = 6

CL = 7

CL = 8

Reserved

ns

4

1,2,3,5

1,2,3,4

4

2.5

3.3

ns

Reserved

ns

1.875

<2.5

ns

1,2,3,4,8

4

Reserved

ns

1,2,3

Supported CL Settings

Supported CWL Settings

5,6,7,8

5,6

nCK

- 44 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 49 ] DDR3-1333 Speed Bins

Speed

DDR3-1333

CL-nRCD-nRP

9 -9 - 9

Units

NOTE

Parameter

Symbol

min

max

13.5

(13.125)

Internal read command to first data

tAA

20

ns

8

13.5

(13.125)

ACT to internal read or write delay time

PRE command period

tRCD

tRP

-

13.5

(13.125)

49.5

(49.125)

ACT to ACT or REF command period

ACT to PRE command period

tRC

tRAS

36

9*tREFI

3.3

ns

CWL = 5

tCK(AVG)

3.0

1,2,3,4,6,9,10

CL = 5

CWL = 6,7

CWL = 5

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5,6

CWL = 7

CWL = 5,6

CWL = 7

Reserved

ns

4

1,2,3,6

1,2,3,4,6

4

2.5

3.3

ns

CL = 6

Reserved

ns

4

CL = 7

CL = 8

1.875

<2.5

ns

1,2,3,4,6

1,2,3,4

4

Reserved

ns

1,2,3,6

1,2,3,4

4

Reserved

ns

CL = 9

1.5

<1.875

ns

1,2,3,4,8

4

Reserved

ns

CL = 10

ns

1,2,3

Supported CL Settings

Supported CWL Settings

5,6,7,8,9,10

5,6,7

nCK

- 45 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 50 ] DDR3-1600 Speed Bins

Speed

DDR3-1600

CL-nRCD-nRP

11-11-11

Units

NOTE

Parameter

Symbol

min

max

13.75

(13.125)

Internal read command to first data

tAA

20

ns

8

13.75

(13.125)

ACT to internal read or write delay time

PRE command period

tRCD

tRP

-

13.75

(13.125)

48.75

(48.125)

ACT to ACT or REF command period

ACT to PRE command period

tRC

tRAS

35

9*tREFI

3.3

ns

nCK

CWL = 5

tCK(AVG)

3.0

1,2,3,4,7,9,10

CL = 5

CWL = 6,7,8

CWL = 5

CWL = 6

CWL = 7, 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5,6

CWL = 7

CWL = 8

CWL = 5,6

CWL = 7

CWL = 8

CWL = 5,6,7

CWL = 8

Reserved

4

1,2,3,7

1,2,3,4,7

4

2.5

3.3

CL = 6

Reserved

4

1.875

<2.5

1,2,3,4,7

4

CL = 7

Reserved

4

1,2,3,7

1,2,3,4,7

1,2,3,4

4

CL = 8

CL = 9

Reserved

1.5

<1.875

<1.5

1,2,3,4,7

1,2,3,4

4

Reserved

CL = 10

CL = 11

1,2,3,7

1,2,3,4

4

Reserved

1.25

1,2,3,8

Supported CL Settings

Supported CWL Settings

5,6,7,8,9,10,11

5,6,7,8

- 46 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

13.3.1 Speed Bin Table Notes

Absolute Specification {T

; V

= V = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)};

OPER

DDQ DD

NOTE :

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],

rounding up to the next "SupportedCL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.

5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte

20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte

18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin

+ tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).

9. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.

10. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.

- 47 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

14. Timing Parameters by Speed Grade

[ Table 51 ] Timing Parameters by Speed Bin(Cont.)

Speed

Parameter

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

NOTE

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock Timing

tCK(DLL_OF

F)

Minimum Clock Cycle Time (DLL off mode)

8

-

8

-

8

-

8

-

ns

6

Average Clock Period

Clock Period

tCK(avg)

tCK(abs)

See Speed Bins Table

ps

tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +

tJIT(per)min

tJIT(per)max

tJIT(per)min

tJIT(per)max

tJIT(per)min

tJIT(per)max

tJIT(per)min

tJIT(per)max

Average high pulse width

tCH(avg)

tCL(avg)

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

tCK(avg)

Average low pulse width

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

tCK(avg)

ps

Clock Period Jitter

tJIT(per)

-100

100

-90

90

-80

80

-70

70

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

tJIT(per, lck)

tJIT(cc)

-90

90

-80

80

-70

70

-60

60

ps

200

180

160

140

120

ps

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

tJIT(cc, lck)

tERR(2per)

tERR(3per)

tERR(4per)

tERR(5per)

tERR(6per)

tERR(7per)

tERR(8per)

tERR(9per)

tERR(10per)

tERR(11per)

tERR(12per)

ps

- 147

- 175

- 194

- 209

- 222

- 232

- 241

- 249

- 257

- 263

- 269

147

175

194

209

222

232

241

249

257

263

269

- 132

- 157

- 175

- 188

- 200

- 209

- 217

- 224

- 231

- 237

- 242

132

157

175

188

200

209

217

224

231

237

242

- 118

- 140

- 155

- 168

- 177

- 186

- 193

- 200

- 205

- 210

- 215

118

140

155

168

177

186

193

200

205

210

215

-103

-122

-136

-147

-155

-163

-169

-175

-180

-184

-188

103

122

136

147

155

163

169

175

180

184

188

ps

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max

Cumulative error across n = 13, 14 ... 49, 50 cycles

tERR(nper)

ps

24

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

tCH(abs)

tCL(abs)

0.43

-

0.43

-

0.43

-

0.43

-

tCK(avg)

25

26

DQS,DQS to DQ skew, per group, per access

DQ output hold time from DQS, DQS

DQ low-impedance time from CK, CK

DQ high-impedance time from CK, CK

tDQSQ

tQH

-

200

-

150

-

125

-

100

-

ps

tCK(avg)

ps

13

0.38

-800

-

0.38

-600

-

0.38

-500

-

0.38

-450

-

13, g

tLZ(DQ)

tHZ(DQ)

400

300

250

225

13,14, f

ps

1.35V

tDS(base)

AC160

90

40

90

-

ps

d, 17

-

tDS(base)

AC135

140

45

25

Data setup time to DQS, DQS referenced to

V

(AC)V (AC) levels

IH

IL

1.5V

tDS(base)

AC175

75

25

75

-

ps

-

tDS(base)

AC150

125

30

10

1.35V

75

1.5V

65

400

tDH(base)

DC90

160

110

-

55

-

ps

-

Data hold time from DQS, DQS referenced to

(DC)V (DC) levels

V

IH

IL

tDH(base)

DC100

150

600

100

490

-

45

-

ps

d, 17

28

-

DQ and DM Input pulse width for each input

tDIPW

360

-

- 48 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 51 ] Timing Parameters by Speed Bin (Cont.)

Speed

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Data Strobe Timing

DQS, DQS differential READ Preamble

DQS, DQS differential READ Postamble

DQS, DQS differential output high time

DQS, DQS differential output low time

DQS, DQS differential WRITE Preamble

DQS, DQS differential WRITE Postamble

tRPRE

tRPST

tQSH

0.9

0.3

Note 19

0.9

0.3

Note 19

0.9

0.3

0.4

0.9

0.3

Note 19

0.9

0.3

0.4

0.9

0.3

Note 19

tCK(avg) 13, 19, g

tCK(avg) 11, 13, b

Note 11

0.38

0.9

-

0.38

0.9

-

tCK(avg)

13, g

tQSL

tWPRE

tWPST

0.3

DQS, DQS rising edge output access time from rising

CK, CK

tDQSCK

tLZ(DQS)

tHZ(DQS)

-400

-800

-

400

-300

-600

-

300

-255

-500

-

255

250

-225

-450

-

225

ps

13,f

DQS, DQS low-impedance time (Referenced from RL-

1)

13,14,f

12,13,14

DQS, DQS high-impedance time (Referenced from

RL+BL/2)

DQS, DQS differential input low pulse width

DQS, DQS differential input high pulse width

DQS, DQS rising edge to CK, CK rising edge

DQS,DQS falling edge setup time to CK, CK rising edge

DQS,DQS falling edge hold time to CK, CK rising edge

Command and Address Timing

tDQSL

tDQSH

tDQSS

tDSS

0.45

-0.25

0.2

0.55

0.25

-

0.45

-0.25

0.2

0.55

0.25

-

0.45

-0.25

0.2

0.55

0.25

-

0.45

-0.27

0.18

0.55

0.27

-

tCK(avg) 29, 31

tCK(avg) 30, 31

tCK(avg)

c

c, 32

tDSH

0.2

-

0.2

-

0.2

-

DLL locking time

tDLLK

tRTP

512

-

512

-

512

-

512

-

nCK

internal READ Command to PRECHARGE Command

delay

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

e

Delay from start of internal write transaction to internal

read command

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

tWTR

-

e,18

e

WRITE recovery time

tWR

15

4

-

15

4

-

15

4

-

15

4

-

ns

Mode Register Set command cycle time

tMRD

nCK

max

(12nCK,15ns)

max

(12nCK,15ns)

max

(12nCK,15ns)

max

(12nCK,15ns)

Mode Register Set command update delay

tMOD

-

CAS to CAS command delay

tCCD

tDAL(min)

tMPRR

tRAS

4

1

4

nCK

ns

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

WR + roundup (tRP / tCK(AVG))

-

1

-

1

-

1

-

22

e

See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin”

max

(4nCK,10ns)

max

(4nCK,7.5ns)

max

(4nCK,6ns)

max

(4nCK,6ns)

ACTIVE to ACTIVE command period for 1KB page size

ACTIVE to ACTIVE command period for 2KB page size

tRRD

-

e

max

(4nCK,10ns)

max

(4nCK,10ns)

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

Four activate window for 1KB page size

Four activate window for 2KB page size

tFAW

40

50

-

37.5

50

-

30

45

-

30

40

-

ns

e

1.35V

tIS(base)

AC160

215

365

140

290

80

-

60

-

ps

b,16

-

tIS(base)

AC135

205

1.5V

65

185

b,16,27

Command and Address setup time to CK, CK refer-

enced to V (AC) / V (AC) levels

IH

IL

tIS(base)

AC175

200

350

125

275

-

45

-

ps

b,16

-

tIS(base)

AC150

190

1.35V

150

170

b,16,27

tIH(base)

DC90

285

210

-

130

-

ps

b,16

-

Command and Address hold time from CK, CK refer-

enced to V (DC) / V (DC) levels

IH

IL

1.5V

140

tIH(base)

DC100

275

900

200

780

120

560

-

ps

b,16

28

Control & Address Input pulse width for each input

Calibration Timing

tIPW

620

-

Power-up and RESET calibration time

Normal operation Full calibration time

Normal operation short calibration time

tZQinitI

tZQoper

tZQCS

512

256

64

-

512

256

64

-

512

256

64

-

512

256

64

-

nCK

23

- 49 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 51 ] Timing Parameters by Speed Bin

Speed

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Reset Timing

max(5nCK,

tRFC +

max(5nCK,

tRFC +

max(5nCK,

tRFC +

max(5nCK,

tRFC +

Exit Reset from CKE HIGH to a valid command

tXPR

-

10ns)

Self Refresh Timing

max(5nCK,t

RFC +

10ns)

max(5nCK,t

RFC +

10ns)

max(5nCK,t

RFC +

10ns)

Exit Self Refresh to commands not requiring a locked

DLL

max(5nCK,t

RFC + 10ns)

tXS

-

Exit Self Refresh to commands requiring a locked DLL

tXSDLL

tCKESR

tDLLK(min)

-

tDLLK(min)

-

tDLLK(min)

-

tDLLK(min)

-

nCK

Minimum CKE low width for Self refresh entry to exit

timing

tCKE(min)+

1tCK

tCKE(min)+

1tCK

tCKE(min)+

1tCK

tCKE(min) +

1tCK

Valid Clock Requirement after Self Refresh Entry

(SRE) or Power-Down Entry (PDE)

max(5nCK,

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

tCKSRE

tCKSRX

-

Valid Clock Requirement before Self Refresh Exit

(SRX) or Power-Down Exit (PDX) or Reset Exit

max(5nCK,

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

Power Down Timing

Exit Power Down with DLL on to any valid com-

mand;Exit Precharge Power Down with DLL

frozen to commands not requiring a locked DLL

max

(3nCK,

7.5ns)

max

(3nCK,

7.5ns)

max

(3nCK,6ns)

max

(3nCK,6ns)

tXP

tXPDLL

tCKE

-

max

(10nCK,

24ns)

max

(10nCK,

24ns)

max

(10nCK,

24ns)

max

(10nCK,

24ns)

Exit Precharge Power Down with DLL frozen to com-

mands requiring a locked DLL

2

max

(3nCK,

7.5ns)

max

(3nCK,

5.625ns)

max

(3nCK,

5.625ns)

max

(3nCK,5ns)

CKE minimum pulse width

Command pass disable delay

tCPDED

tPD

1

-

1

-

1

-

1

-

nCK

tCK(avg)

nCK

Power Down Entry to Exit Timing

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

15

20

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power Down entry

tACTPDEN

tPRPDEN

tRDPDEN

1

-

1

-

1

-

1

-

nCK

RL + 4 +1

WL + 4

+(tWR/

tCK(avg))

WL + 4

+(tWR/

tCK(avg))

WL + 4

+(tWR/

tCK(avg))

WL + 4

+(tWR/

tCK(avg))

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

tWRPDEN

tWRAPDEN

tWRPDEN

-

nCK

9

10

9

Timing of WRA command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

WL + 4

+WR +1

WL + 4

+WR +1

WL + 4

+WR +1

WL + 4 +WR

+1

WL + 2

+(tWR/

tCK(avg))

WL + 2

+(tWR/

tCK(avg))

WL + 2

+(tWR/

tCK(avg))

WL + 2

+(tWR/

tCK(avg))

Timing of WR command to Power Down entry

(BC4MRS)

Timing of WRA command to Power Down entry

(BC4MRS)

WL +2 +WR

+1

WL +2 +WR

+1

WL +2 +WR

+1

WL +2 +WR

+1

tWRAPDEN

tREFPDEN

10

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

ODT Timing

1

-

1

-

1

-

1

-

20,21

tMRSPDEN tMOD(min)

tMOD(min)

ODT high time without write command or with write

command and BC4

ODTH4

ODTH8

tAONPD

4

6

2

-

4

6

2

-

4

6

2

-

4

6

2

-

nCK

ns

ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-Down with

DLL frozen)

8.5

Asynchronous RTT turn-off delay (Power-Down with

DLL frozen)

tAOFPD

tAON

2

8.5

400

0.7

2

8.5

300

0.7

2

8.5

250

0.7

2

8.5

225

0.7

ns

RTT turn-on

-400

0.3

-300

0.3

-250

0.3

-225

0.3

ps

7,f

8,f

f

RTT_NOM and RTT_WR turn-off time from ODTLoff

reference

tAOF

tCK(avg)

RTT dynamic change skew

tADC

Write Leveling Timing

First DQS/DQS rising edge after write

leveling mode is programmed

tWLMRD

tWLDQSEN

tWLS

40

25

-

40

25

-

40

25

-

40

25

-

tCK(avg)

ps

3

DQS/DQS delay after write leveling

mode is programmed

Write leveling setup time from rising CK, CK crossing

to rising DQS, DQS crossing

325

245

195

165

Write leveling hold time from rising DQS, DQS cross-

ing to rising CK, CK crossing

tWLH

ps

Write leveling output delay

Write leveling output error

tWLO

0

9

2

0

9

2

0

9

2

0

7.5

2

ns

tWLOE

- 50 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

14.1 Jitter Notes

Specific Note a

Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the

input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,

another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.

Specific Note b

These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition

edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,

these parameters should be met whether clock jitter is present or not.

Specific Note c

These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK)

crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative

to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note d

Specific Note e

These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data

strobe signal (DQS(L/U), DQS(L/U)) crossing.

For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},

which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the

device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-

mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

Specific Note f

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input

clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +

193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and

tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800

derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution

on the min/max usage!)

Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=

12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input

clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has

tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +

tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =

tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/

max usage!)

- 51 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

14.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions See "Device Operation & Timing Diagram Datasheet".

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing

Diagram Datasheet.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by 14.1-Jitter Notes on page 51

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15. tREFI depends on T

OPER

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

(DC) = V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).

V

REF

See Address/Command Setup, Hold and Derating : on page 56. .

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,

(DC)= V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).

V

REF

See Data Setup, Hold and Slew Rate Derating : on page 63.

18. Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL

For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Data-

sheet"

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The

appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-

ject to in the application, is illustrated. The interval could be defined by the following formula:

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-

lated as:

0.5

~

128ms

= 0.133

(1.5 x 1) + (0.15 x 15)

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-

nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of V

(DC) and the consecutive crossing of V

(DC)

REF

29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.

30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.

31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

- 52 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

14.3 Address/Command Setup, Hold and Derating :

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see

Table 52) to the tIS and tIH derating value (see Table 54) respectively.

Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

V

(DC) and the first crossing of V (AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

REF

IH

V

(DC) and the first crossing of V (AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’V

(DC) to ac

REF

IL

region’, use nominal slew rate for derating value (see 20-Fegure Title on page Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with

respect to strobe) and tIS). If the actual signal is later than the nominal slew rate line anywhere between shaded ’V (DC) to ac region’, the slew rate of

REF

a tangent line to the actual signal from the ac level to dc level is used for derating value (see 22-Fegure Title on page Illustration of tangent line for setup

time tDS (for DQ with respect to strobe) and tIS).

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V (DC)max and the first crossing of V

(DC).

REF

IL

Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V (DC)min and the first crossing of V

(DC). If

REF

IH

the actual signal is always later than the nominal slew rate line between shaded ’dc to V

(DC) region’, use nominal slew rate for derating value (see 21-

REF

Fegure Title on page Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH). If the actual signal is earlier than the nom-

inal slew rate line anywhere between shaded ’dc to V (DC) region’, the slew rate of a tangent line to the actual signal from the dc level to V (DC)

REF

level is used for derating value (see 23-Fegure Title on page Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH).

For a valid transition the input signal has to remain above/below V (AC) for some time tVAC (see Table 51).

IH/IL

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V

(AC) at the time of the rising clock

IH/IL

transition) a valid input signal is still required to complete the transition and reach V

(AC).

IH/IL

For slew rates in between the values listed in Table 54, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

[ Table 52 ] ADD/CMD Setup and Hold Base-Values for 1V/ns (1.35V)

[ps]

DDR3L-800

215

DDR3L-1066

DDR3L-1333

DDR3L-1600

reference

Note

1

tIS(base) AC160

tIS(base) AC135

tIH(base)-DC90

140

290

210

80

60

V

IH/L(AC)

IH/L(DC)

DDR3L

365

205

150

185

130

1,2

1

285

NOTE :

1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate

2. The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125 ps for DDR3L-800/1066 or 100ps for DDR3L-1333/1600

of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the earlier reference point [(160mv - 135 mV) / 1 V/ns].

[ Table 53 ] ADD/CMD Setup and Hold Base-Values for 1V/ns (1.5V)

[ps]

DDR3-800

200

DDR3-1066

125

DDR3-1333

DDR3-1600

reference

tIS(base) AC175

tIS(base) AC150

tIS(base) AC100

65

45

V

IH/L(AC)

IH/L(DC)

DDR3

350

275

190

140

170

120

275

200

NOTE:

1.AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate

2.The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-1333/1600 of

derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].

- 53 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 54 ] Derating values DDR3L-800/1066/1333/1600 tIS/tIH-AC/DC based AC160 Threshold(1.35V)

tIS, tIH Derating [ps] AC/DC based

AC160 Threshold -> V (AC) = V

(DC) + 160mV, V (AC) = V

(DC) - 160mV

IH

REF

IL

REF

CLK,CLK Differential Slew Rate

1.8 V/ns 1.6 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.4V/ns

1.2V/ns

tIS

1.0V/ns

tIS

tIH

45

tIS

tIH

45

tIS

tIH

45

tIS

tIH

53

38

8

tIS

tIH

61

46

16

13

9

tIS

104

77

24

23

21

19

16

4

tIH

69

54

24

21

17

11

4

tIH

79

64

32

31

27

21

14

4

tIH

95

80

50

47

43

37

30

20

5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

80

53

0

80

53

0

80

53

0

88

61

8

96

69

16

15

13

11

8

112

85

32

31

29

27

24

12

-8

120

93

40

39

37

35

32

20

0

30

0

CMD/

ADD

Slew

rate

-1

-3

-1

-3

-1

-3

7

5

-3

-8

-3

-8

-3

-8

5

1

-5

-13

-20

-30

-45

-5

-13

-20

-30

-45

-5

-13

-20

-30

-45

3

-5

3

V/ns

-8

0

-12

-22

-37

-4

-20

-40

-20

-40

-20

-40

-12

-32

-4

-14

-29

-6

-24

-16

-21

-11

[ Table 55 ] Derating values DDR3L-800/1066/1333/1600 tIS/tIH-AC/DC based - Alternate AC135 Threshold (1.35V)

tIS, tIH Derating [ps] AC/DC based

Alternate AC135 Threshold -> V (AC) = V

(DC) + 135mV, V (AC) = V

(DC) - 135mV

REF

IH

REF

IL

CLK,CLK Differential Slew Rate

1.8 V/ns 1.6 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.4V/ns

tIS

1.2V/ns

1.0V/ns

tIS

tIH

45

tIS

tIH

45

tIS

tIH

45

tIS

tIH

53

38

8

tIS

tIH

61

46

16

13

9

tIH

69

54

24

21

17

11

4

tIS

100

77

tIH

79

64

32

31

27

21

14

4

tIS

108

85

tIH

95

80

50

47

43

37

30

20

5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

68

45

0

68

45

0

68

45

0

76

53

8

84

61

16

18

19

22

25

21

14

92

69

24

26

27

30

33

29

22

30

0

32

40

CMD/

ADD

Slew

rate

2

-3

2

-3

2

-3

10

11

14

17

13

6

5

34

42

3

-8

3

-8

3

-8

1

35

43

6

-13

-20

-30

-45

6

-13

-20

-30

-45

6

-13

-20

-30

-45

-5

3

38

46

V/ns

9

-12

-22

-37

-4

41

49

5

-14

-29

-6

37

45

-3

-21

30

-11

38

[ Table 56 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC175 Threshold(1.5V)

tIS, tIH Derating [ps] AC/DC based

Alternate AC175 Threshold -> V (AC) = V

(DC) + 175mV, V (AC) = V

(DC) - 175mV

REF

IH

REF

IL

CLK,CLK Differential Slew Rate

1.8 V/ns 1.6 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.4V/ns

tIS

1.2V/ns

1.0V/ns

tIS

tIH

50

tIS

tIH

50

tIS

tIH

50

tIS

tIH

58

42

8

tIS

tIH

66

50

16

12

6

tIH

74

58

24

20

14

8

tIS

120

91

tIH

84

68

34

30

24

18

8

tIS

128

99

40

38

34

29

tIH

100

84

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

88

59

0

88

59

0

88

59

0

96

67

8

104

75

16

14

10

5

112

83

24

22

18

13

7

34

0

32

50

CMD/

ADD

Slew

rate

-2

-4

-2

-4

-2

-4

6

4

30

46

-6

-10

-16

-26

-40

-60

-6

-10

-16

-26

-40

-60

-6

-10

-16

-26

-40

-60

2

-2

26

40

-11

-17

-35

-62

-11

-17

-35

-62

-11

-17

-35

-62

-3

-9

-27

-54

-8

0

21

34

V/ns

-18

-32

-52

-1

-10

-24

-44

-2

15

23

5

24

-19

-46

-11

-38

-16

-36

-2

-6

10

-30

-26

-22

-10

- 54 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 57 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC150 Threshold (1.5V)

tIS, tIH Derating [ps] AC/DC based

Alternate AC150 Threshold -> V (AC) = V

(DC) + 150mV, V (AC) = V

(DC) - 150mV

REF

IH

REF

IL

CK,CK Differential Slew Rate

1.8 V/ns 1.6 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.4V/ns

tIS

1.2V/ns

tIS

1.0V/ns

tIS

tIH

50

tIS

tIH

50

tIS

tIH

50

tIS

tIH

58

42

8

tIS

tIH

66

50

16

12

6

tIH

74

58

24

20

14

8

tIH

84

68

34

30

24

18

8

tIS

tIH

100

84

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

75

50

0

75

50

0

75

50

0

83

58

8

91

66

16

15

6

99

74

24

23

14

-1

107

82

32

31

22

7

115

90

40

39

30

15

34

0

50

CMD/

ADD

Slew

rate

0

-4

0

-4

0

-4

8

4

46

0

-10

-16

-26

-40

-60

0

-10

-16

-26

-40

-60

0

-10

-16

-26

-40

-60

8

-2

40

0

8

-8

0

34

V/ns

-1

-10

-25

-1

-10

-25

-1

-10

-25

7

-18

-32

-52

-10

-24

-44

-2

24

-2

-17

-16

-36

-6

10

-9

-26

-10

[ Table 58 ] Required time t

Slew Rate[V/ns]

above V (AC) {blow V (AC)} for valid ADD/CMD transition

IH IL

VAC

1.35V

DDR3L-800/1066/1333/1600

1.5V

DDR3-800/1066/1333/1600

t

@160mV [ps]

t

@135mV [ps]

t

@175mV [ps]

t

@150mV [ps]

VAC

min

200

173

120

102

80

VAC

min

213

190

145

130

111

87

VAC

min

75

VAC

min

175

170

167

130

113

93

max

>2.0

2.0

-

57

1.5

50

1.0

38

0.9

34

0.8

29

0.7

51

22

66

0.6

13

55

Note

30

0.5

Note

10

Note

< 0.5

Note

10

Note

NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.

- 55 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

tVAC

(AC) min

IH

V

to ac

REF

region

V

(DC) min

IH

nominal

slew rate

V

(DC)

REF

nominal slew

rate

V (DC) max

IL

V

to ac

REF

region

V (AC) max

IL

tVAC

V

SS

 TF

 TR

Setup Slew Rate

Rising Signal

V

(AC)min - V

(DC)

REF

V

(DC) - V (AC)max

Setup Slew Rate

Falling Signal

REF

IL

IH

=

 TF

 TR

Figure 20. Illustration of nominal slew rate and t

(for ADD/CMD with respect to clock).

for setup time t (for DQ with respect to strobe) and t

IS

VAC

DS

- 56 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

(AC) min

(DC) min

IH

dc to V

region

REF

nominal

slew rate

V

(DC)

REF

nominal

slew rate

dc to V

region

REF

V (DC) max

IL

V (AC) max

IL

V

SS

 TR

 TF

Hold Slew Rate

Rising Signal

V

(DC) - V (DC)max

REF

IL

Hold Slew Rate

Falling Signal

V

(DC)min - V

(DC)

IH

REF

=

 TR

 TF

Figure 21. Illustration of nominal slew rate for hold time t (for DQ with respect to strobe) and t

DH

IH

(for ADD/CMD with respect to clock).

- 57 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

tVAC

nominal

line

(AC) min

(DC) min

IH

V

to ac

REF

region

tangent

line

V

(DC)

REF

tangent

line

V (DC) max

IL

V

to ac

REF

region

V (AC) max

IL

nominal

line

 TR

tVAC

V

SS

tangent line[V (AC)min - V

(DC)]

REF

Setup Slew Rate

Rising Signal

IH

=

 TR

 TF

Setup Slew Rate tangent line[V

Falling Signal

(DC) - V (AC)max]

IL

REF

=

 TF

Figure 22. Illustration of tangent line for setup time t (for DQ with respect to strobe) and t

DS

IS

(for ADD/CMD with respect to clock)

- 58 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

(AC) min

(DC) min

IH

nominal

line

dc to V

region

REF

tangent

line

V

(DC)

REF

tangent

line

dc to V

region

REF

nominal

line

V (DC) max

IL

V (AC) max

IL

V

SS

 TF

 TR

(DC) - V (DC)max ]

tangent line [ V

Hold Slew Rate

Rising Signal

REF

IL

=

 TR

tangent line [ V (DC)min - V

(DC) ]

Hold Slew Rate

Falling Signal

IH

REF

=

 TF

Figure 23. Illustration of tangent line for hold time t (for DQ with respect to strobe) and t

DH

IH

(for ADD/CMD with respect to clock)

- 59 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

14.4 Data Setup, Hold and Slew Rate Derating :

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see

Table 59) to the  tDS and tDH (see Table 55) derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V

(DC) and the first crossing of V (AC)min.

REF

IH

Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V

(DC) and the first crossing of V (AC)max

IL

REF

(see 24-Fegure Title on page Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS). If the actual signal is

always earlier than the nominal slew rate line between shaded ’V

(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is

REF

later than the nominal slew rate line anywhere

between shaded ’V

(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see 26-

REF

Fegure Title on page Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS).

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V (DC)max and the first crossing of V

(DC).

REF

IL

Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V (DC)min and the first crossing of V

(DC)

IH

REF

(see -Body on page ). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to V

rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V

(DC) region’, use nominal slew

(DC) region’, the slew rate of a

REF

tangent line to the actual signal from the dc level to V

(DC) level is used for derating value (see 27-Fegure Title on page Illustration of tangent line for

REF

hold time tDH (for DQ with respect to strobe) and tIH).

For a valid transition the input signal has to remain above/below V

(AC) for some time tVAC (see Table 56).

IH/IL

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V

(AC) at the time of the rising clock

IH/IL

transition) a valid input signal is still required to complete the transition and reach V

(AC).

IH/IL

For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

[ Table 59 ] Data Setup and Hold Base-Values

[ps]

DDR3-800

75

DDR3-1066

DDR3-1333

DDR3-1600

reference

tDS(base) AC175

tDS(base) AC150

tDH(base) DC100

tDS(base) AC160

tDS(base) AC135

tDH(base) DC90

25

75

-

V

(AC)

(DC)

(AC)

(DC)

IH/L

DDR3

125

30

65

-

10

45

-

150

100

40

90

DDR3L

140

90

45

75

25

55

160

110

NOTE : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate

[ Table 60 ] Derating values DDR3L-800/1066 tDS/tDH-AC/DC based - AC160(1.35V)

1

tDS, tDH Derating in [ps] AC/DC based

DQS,DQS Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

80

53

0

-

45

30

0

-

80

53

0

-1

-

45

30

0

-3

-

80

53

0

-1

-3

-

45

30

0

-3

-8

-

61

8

7

5

3

-

38

8

5

1

-5

-

16

13

9

3

-4

-

23

21

19

16

4

-

21

17

11

4

-6

-

35

32

20

0

-

37

30

20

5

16

15

13

11

8

DQ

Slew

rate

-

29

27

24

12

-8

27

21

14

4

V/ns

-

-11

NOTE : 1. Cell contents shaded in red are defined as ’not supported’.

[ Table 61 ] Derating values for DDR3L-800/1066/1333/1600 tDS/tDH - AC135 (1.35V)

tDS, tDH Derating in [ps] AC/DC based

DQS,DQS Differential Slew Rate

1.8 V/ns 1.6 V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

1

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

68

45

0

-

45

30

0

-

68

45

0

2

-

45

30

0

-3

-

68

45

0

2

3

-

45

30

0

-3

-8

-

53

8

10

11

14

-

38

8

5

1

-5

-

16

13

9

3

-4

-

26

27

30

33

29

-

21

17

11

4

-6

-

35

38

41

37

30

-

27

21

14

4

-

16

18

19

22

25

-

DQ

Slew

rate

-

46

49

45

38

37

30

20

5

V/ns

-

-11

NOTE : 1. Cell contents shaded in red are defined as ’not supported’.

- 60 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

[ Table 62 ] Derating values DDR3-800/1066 tDS/tDH - AC175 (1.5V)

tDS, tDH Derating in [ps] AC/DC based

DQS,DQS Differential Slew Rate

1.8 V/ns 1.6 V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

1

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

88

59

0

-

50

34

0

-

88

59

0

-2

-

50

34

0

-4

-

88

59

0

-2

-6

-

50

34

0

-4

-10

-

67

8

6

2

-3

-

42

8

-

16

12

6

0

-10

-

16

14

10

5

-1

-

DDR3 DQ

Slew

800/ rate

1066 V/ns

4

22

18

13

7

-11

-

20

14

8

-2

-16

-

-2

-8

-

26

21

15

-2

-30

24

18

8

-6

-26

-

29

23

6

34

24

10

-10

-

-22

NOTE : 1. Cell contents shaded in red are defined as ’not supported’.

[ Table 63 ] Derating values for DDR3-800/1066/1333/1600 tDS/tDH - AC150 (1.5V)

1

tDS, tDH Derating in [ps] AC/DC based

DQS,DQS Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4V/ns

1.2V/ns

1.0V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

75

50

0

-

50

34

0

-

75

50

0

-

50

34

0

-4

-

75

50

0

-

50

34

0

-4

-10

-

58

8

-

42

8

-

16

12

6

0

-10

-

24

23

14

-

32

31

22

7

-

16

15

-

DQ

Slew

rate

4

20

14

8

-2

-16

-

-2

-8

-

24

18

8

-6

-26

-

40

39

30

15

34

24

10

-10

V/ns

-

NOTE : 1. Cell contents shaded in red are defined as ’not supported’.

[ Table 64 ] Required time t

Slew Rate[V/ns]

above V (AC) {blow V (AC)} for valid DQ transition

VAC

IH

IL

1.35V

1.5V

DDR3L-800/1066

(AC160)

DDR3L-800/1066/

1333/1600 (AC135)

DDR3-800/1066

(AC175)

DDR3-800/1066/

1333/1600 (AC150)

DDR3-800/1066/

1333/1600 (AC135)

t

[ps]

t

[ps]

t

[ps]

t

[ps]

t

[ps]

VAC

min

165

138

85

max

min

113

90

max

min

75

57

50

38

34

29

max

min

105

80

max

min

113

90

max

>2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

-

45

30

45

67

30

13

30

45

11

Note

11

16

Note

NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.

- 61 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

tVAC

(AC) min

IH

V

to ac

REF

region

V

(DC) min

IH

nominal

slew rate

V

(DC)

REF

nominal slew

rate

V (DC) max

IL

V

to ac

REF

region

V (AC) max

IL

tVAC

V

SS

 TF

 TR

Setup Slew Rate

Rising Signal

V

(AC)min - V

(DC)

REF

V

(DC) - V (AC)max

Setup Slew Rate

Falling Signal

REF

IL

IH

=

 TF

 TR

Figure 24. Illustration of nominal slew rate and t

(for ADD/CMD with respect to clock).

for setup time t (for DQ with respect to strobe) and t

IS

VAC

DS

- 62 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

(AC) min

(DC) min

IH

dc to V

region

REF

nominal

slew rate

V

(DC)

REF

nominal

slew rate

dc to V

region

REF

V (DC) max

IL

V (AC) max

IL

V

SS

 TR

 TF

Hold Slew Rate

Rising Signal

V

(DC) - V (DC)max

REF

IL

Hold Slew Rate

Falling Signal

V

(DC)min - V

(DC)

IH

REF

=

 TR

 TF

Figure 25. Illustration of nominal slew rate for hold time t (for DQ with respect to strobe) and t

DH

IH

(for ADD/CMD with respect to clock).

- 63 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

tVAC

nominal

line

(AC) min

(DC) min

IH

V

to ac

REF

region

tangent

line

V

(DC)

REF

tangent

line

V (DC) max

IL

V

to ac

REF

region

V (AC) max

IL

nominal

line

 TR

tVAC

V

SS

tangent line[V (AC)min - V

(DC)]

REF

Setup Slew Rate

Rising Signal

IH

=

 TR

 TF

Setup Slew Rate tangent line[V

Falling Signal

(DC) - V (AC)max]

IL

REF

=

 TF

Figure 26. Illustration of tangent line for setup time t (for DQ with respect to strobe) and t

DS

IS

(for ADD/CMD with respect to clock)

- 64 -

Preliminary

Rev. 0.5

K4B4G1646Q

datasheet

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIH

tIS

CK

DQS

tDH

tDS

V

DDQ

(AC) min

(DC) min

IH

nominal

line

dc to V

region

REF

tangent

line

V

(DC)

REF

tangent

line

dc to V

region

REF

nominal

line

V (DC) max

IL

V (AC) max

IL

V

SS

 TF

 TR

(DC) - V (DC)max ]

tangent line [ V

Hold Slew Rate

Rising Signal

REF

IL

=

 TR

tangent line [ V (DC)min - V

(DC) ]

Hold Slew Rate

Falling Signal

IH

REF

=

 TF

Figure 27. Illustration of tangent line for hold time t (for DQ with respect to strobe) and t

DH

IH

(for ADD/CMD with respect to clock)

- 65 -


型号：	K4B4G1646Q
厂家：	SAMSUNG
描述：	4Gb Q-die DDR3L SDRAM Olny x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant) 1.35V 动态存储器双倍数据速率
文件：	总65页 (文件大小：522K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4B4G1646Q [SAMSUNG]

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