K4D261638F-TC36T [SAMSUNG]
DDR DRAM, 8MX16, 0.6ns, CMOS, PDSO66;
| 型号： | K4D261638F-TC36T |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 8MX16, 0.6ns, CMOS, PDSO66 动态存储器 双倍数据速率 光电二极管 |
| 文件： | 总18页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128M GDDR SDRAM
K4D261638F
128Mbit GDDR SDRAM
Revision 1.5
March 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
Revision History
Revision 1. 5(March 17, 2005)
• Added Full output driver impedance in the EMRS spec.
Revision 1. 4 (February 2, 2005)
• Added -TC5A speed in the spec
Revision 1.3 (November 2, 2004)
• Added ns scale based AC spec table.
• Removed -TC25 from the spec
Revision 1.2 (January 30, 2004)
• Changed tWR & tWR_A of K4D261638F-TC25/2A/33/36 from 3tCK to 4tCK
• Changed tRC of K4D261638F-TC25 from 17tCK to 18tCK
• Changed tRC of K4D261638F-TC2A/33/36 from 15tCK to 16tCK
• Changed tRAS of K4D261638F-TC25 from 12tCK to 13tCK.
• Changed tRAS of K4D261638F-TC2A/33/36 from 10tCK to 11tCK.
• Changed tDAL of K4D261638F-TC25/2A/33/36 from 8tCK to 9tCK
Revision 1.1 (January 7, 2004)
• Added K4D261638F-TC25 in the spec.
Revision 1.0 (December 5, 2003)
Revision 0.9 (October 14, 2003) - Preliminary Spec
• Defined DC spec
Revision 0.1 (October 2, 2003) - Target Spec
• Added Lead free package part number in the datasheet
Revision 0.0 (August 6, 2003) - Target Spec
• Defined Target Specification
- 2 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• MRS cycle with address key programs
-. Read latency 3, 4 and 5(clock)
-. Burst length (2, 4 and 8)
• Auto & Self refresh
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• 32ms refresh period (4K cycle)
• 66pin TSOP-II
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin
• Differential clock input
• No Wrtie-Interrupted by Read Function
ORDERING INFORMATION
Part NO.
Max Freq.
350MHz
300MHz
275MHz
250MHz
200MHz
200MHz
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
400Mbps/pin
400Mbps/pin
Interface
Package
K4D261638F-TC2A
K4D261638F-TC33
K4D261638F-TC36
K4D261638F-TC40
K4D261638F-TC50
K4D261638F-TC5A
SSTL_2
66pin TSOP-II
K4D261638F-LC is the Lead Free package part number.
For the K4D261638F-TC2A, VDD & VDDQ = 2.8V+0.1V
For the K4D261638F-TC5A, VDD & VDDQ = 2.4V to 2.7V
GENERAL DESCRIPTION
FOR 2M x 16Bit x 4 Bank DDR SDRAM
The K4D261638F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
PIN CONFIGURATION (Top View)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
1
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
VSSQ
UDQS
NC
VDDQ
LDQS
NC
VREF
VSS
VDD
NC
UDM
CK
LDM
WE
CK
CAS
RAS
CS
22
23
CKE
NC
24
25
26
27
28
29
30
31
32
33
NC
NC
A11
BA0
BA1
AP/A10
A0
A9
A8
A7
A6
A1
A5
A2
A4
A3
VSS
VDD
PIN DESCRIPTION
CK,CK
CKE
Differential Clock Input
Clock Enable
BA0, BA1
A0 ~A11
DQ0 ~ DQ15
VDD
Bank Select Address
Address Input
Data Input/Output
Power
CS
Chip Select
RAS
Row Address Strobe
Column Address Strobe
Write Enable
CAS
VSS
Ground
WE
VDDQ
Power for DQ’s
Ground for DQ’s
No Connection
L(U)DQS
L(U)DM
RFU
Data Strobe
VSSQ
Data Mask
NC
Reserved for Future Use
- 4 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
The differential system clock Input.
CK, CK*1
Input
Input
Input
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CKE
CS
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
RAS
CAS
WE
Input
Input
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
LDQS,UDQS
LDM,UDM
Input/Output
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
DQ0 ~ DQ15
BA0, BA1
Input/Output
Input
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8.
A0 ~ A11
VDD/VSS
Input
Power Supply
Power Supply
Power Supply
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ/VSSQ
VREF
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
This pin is recommended to be left "No connection" on the device
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank)
16
Intput Buffer
LWE
CK, CK
Data Input Register
Serial to parallel
LDMi
Bank Select
2Mx16
2Mx16
2Mx16
2Mx16
32
16
x16
DQi
CK,CK
ADDR
Column Decoder
Latency & Burst Length
Data Strobe
Programming Register
LWCBR
DLL
LCKE
LRAS LCBR
LWE
LCAS
CK,CK
LDMi
Timing Register
UDM
CK,CK
CKE
CS
RAS
CAS
WE
LDM
- 6 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10 11
12 13
14
15 16 17
18
19
CK,CK
tRP
2 Clock min.
tRFC
tRFC
2 Clock min.
tRP
2 Clock min.
Command
precharge
ALL Banks
2nd Auto
Refresh
precharge
ALL Banks
MRS
DLL Reset
1st Auto
Refresh
Mode
Register Set
Any
Command
EMRS
200 Clock min.
Inputs must be
stable for 200us
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
- 7 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
Address Bus
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Burst Type
A3
DLL
Test Mode
A7
Type
A8
0
DLL Reset
No
mode
0
1
Sequential
Interleave
0
1
Normal
Test
1
Yes
Burst Length
Burst Type
CAS Latency
A2
A1
A0
Sequential Interleave
BA0
0
An ~ A0
MRS
A6 A5 A4 Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserve
2
Reserve
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
1
EMRS
4
4
8
8
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
4
5
Reserved
Reserved
MRS Cycle
0
1
2
3
4
5
6
7
8
CK, CK
Precharge
All Banks
Any
Command
Command
NOP
NOP
NOP
MRS
NOP
NOP
NOP
tMRD=2 tCK
tRP
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
- 8 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
BA1
BA0
1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
Extended
Mode Register
*1
RFU
D.I.C
RFU
D.I.C DLL
RFU
BA0
0
An ~ A0
MRS
Output Driver Impedence Control*2
A0
0
DLL Enable
Enable
A6 A1
Full
0
0
1
0
1
1
1
EMRS
1
Disable
Weak
Matched
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
*2 : Samsung would like to recommend "Weak" output driver impedance in point-to-point application.
but it’s possible to use by "Full", if user system can support "Full" output driver impedance.
- 9 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
Unit
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
2.0
V
V
VDDQ
TSTG
V
°C
W
mA
Power dissipation
PD
Short circuit current
IOS
50
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Device Supply voltage
Output Supply voltage
Reference voltage
Symbol
VDD
Min
2.375
Typ
Max
2.625
Unit
V
Note
2.50
1, 7
VDDQ
VREF
Vtt
2.375
2.50
2.625
V
1, 7
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.30
-
0.51*VDDQ
VREF+0.04
VDDQ+0.30
VREF-0.15
-
V
2
Termination voltage
VREF
V
3
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
VIH(DC)
VIL(DC)
VOH
-
-
-
-
-
-
V
4
V
5
Vtt+0.76
-
V
IOH=-15.2mA
VOL
Vtt-0.76
5
V
IOL=+15.2mA
IIL
-5
uA
uA
6
6
IOL
-5
5
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
7. For the K4D261638F-TC2A, VDD & VDDQ = 2.8V+0.1V
For the K4D261638F-TC5A, VDD & VDDQ = 2.4V to 2.7V
- 10 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-2A
-33
-36
-40
-50
-5A
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
Operating Current
(One Bank Active)
ICC1
210
190
180
170
150
TBD mA
TBD mA
TBD mA
TBD mA
TBD mA
TBD mA
1
Precharge Standby Current
in Power-down mode
ICC2P
ICC2N
ICC3P
ICC3N
ICC4
60
90
45
CKE ≤ VIL(max), tCC= tCC(min)
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Precharge Standby Current
in Non Power-down mode
75
65
70
60
65
55
95
60
50
90
Active Standby Current
power-down mode
75
CKE ≤ VIL(max), tCC= tCC(min)
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Active Standby Current in
in Non Power-down mode
135
100
100
275
Operating Current
( Burst Mode)
tRC ≥ tRFC(min)tRC ≥ tRFC(min)
Page Burst, All Banks activated.
400
245
290
210
260
195
245
190
Refresh Current
ICC5
ICC6
200
4
TBD mA
TBD mA
2
tRC ≥ tRFC(min)
CKE ≤ 0.2V
Self Refresh Current
Note : 1. Measured with outputs open.
2. Refresh period is 32ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)
Parameter
Symbol
VIH
Min
VREF+0.35
-
Typ
Max
-
Unit
V
Note
Input High (Logic 1) Voltage; DQ
-
-
-
-
Input Low (Logic 0) Voltage; DQ
VIL
VREF-0.35
VDDQ+0.6
0.5*VDDQ+0.2
V
Clock Input Differential Voltage; CK and CK
Clock Input Crossing Point Voltage; CK and CK
VID
0.7
V
1
2
VIX
0.5*VDDQ-0.2
V
Note :
1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
3. For the K4D261638F-TC2A, VDD & VDDQ = 2.8V+0.1V.
For the K4D261638F-TC5A, VDD & VDDQ = 2.4V to 2.7V
- 11 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
AC OPERATING TEST CONDITIONS (VDD=2.5V±5%, TA= 0 to 65°C)
Parameter
Value
Unit
V
Note
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
0.50*VDDQ
1.5
V
1.0
V/ns
V
Input Levels(VIH/VIL)
VREF+0.35/VREF-0.35
Input timing measurement reference level
Output timing measurement reference level
Output load condition
VREF
Vtt
V
V
See Fig.1
1.For the K4D261638F-TC2A, VDD & VDDQ = 2.8V+0.1V.
For the K4D261638F-TC5A, VDD & VDDQ = 2.4V to 2.7V
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz)
Parameter
Input capacitance( CK, CK )
Symbol
CIN1
Min
1.0
Max
5.0
Unit
pF
pF
Input capacitance(A0~A11, BA0~BA1)
CIN2
1.0
4.0
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ0~DQ15)
Input capacitance(DM0 ~ DM3)
COUT
CIN4
1.0
1.0
6.5
6.5
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
CDC1
Value
Unit
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
0.1 + 0.01
0.1 + 0.01
uF
uF
CDC2
Note :
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
AC CHARACTERISTICS(I)
-2A
-33
-36
Parameter
Symbol
Unit
Note
Min
-
2.86
Max
Min
-
3.3
Max
Min
-
3.6
Max
CL=3
CL=4
CL=5
ns
ns
ns
CK cycle time
tCK
10
10
10
-
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
tCH
tCL
tDQSCK
tAC
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.40
0.40
tCLmin
or
tCHmin
tHP-0.4
0.55
0.55
0.6
0.6
0.40
1.1
0.6
1.15
-
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
1
-
-
-
DQS write postamble
0.6
0.6
0.6
-
-
-
0.6
0.6
0.6
-
-
-
0.6
0.6
0.6
-
-
-
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
0.4
0.4
0.9
0.9
0.4
0.4
0.9
0.9
tIH
tDS
tDH
ns
ns
ns
0.35
0.35
tCLmin
or
tCHmin
tHP-0.35
0.35
0.35
tCLmin
or
tCHmin
tHP-0.35
-
-
-
1
1
Clock half period
tHP
tQH
-
-
-
-
-
-
ns
ns
Data output hold time from DQS
- 13 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
AC CHARACTERISTICS(I) _Continued
-40
-50
-5A
Parameter
Symbol
Unit
Note
Min
4.0
-
Max
Min
5.0
-
Max
Min
5.0
-
Max
CL=3
CL=4
CL=5
ns
ns
ns
CK cycle time
tCK
10
10
10
-
-
-
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
tCH
tCL
tDQSCK
tAC
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
1
-
-
-
DQS write postamble
0.6
0.6
0.6
-
-
-
0.6
0.6
0.6
-
-
-
0.6
0.6
0.6
-
-
-
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
tIH
tDS
tDH
ns
ns
ns
-
-
-
Clock half period
tHP
tQH
-
-
-
-
-
-
ns
ns
1
1
tCHmin
tHP-0.4
tCHmin
tHP-0.45
tCHmin
tHP-0.45
Data output hold time from DQS
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
- 14 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
AC CHARACTERISTICS (II)
-2A
-33
-36
Parameter
Symbol
tRC
tRFC
Unit
Note
Min
45.8
48.6
31.5
14.3
8.6
Max
-
-
Min
52.8
56.1
36.3
16.5
9.9
Max
-
-
Min
57.6
61.2
39.6
14.4
7.2
Max
-
-
Row cycle time
ns
ns
ns
ns
ns
ns
ns
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge @Normal
Precharge
Last data in to Row precharge @Auto
Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery + Pre-
charge
tRAS
100K
100K
100K
tRCDRD
tRCDWR
tRP
-
-
-
-
-
-
-
-
-
-
-
-
2
1
14.3
8.6
16.5
9.9
18
10.8
tRRD
tWR
4
4
-
-
4
4
-
-
4
4
-
-
tCK
tCK
tWR_A
1
1
tCDLR
tCCD
tMRD
3
1
2
-
-
-
3
1
2
-
-
-
2
1
2
-
-
-
tCK
tCK
tCK
tDAL
9
-
-
-
-
9
-
-
-
-
9
-
-
-
-
tCK
tCK
ns
Exit self refresh to read command
tXSR
tPDEX
tREF
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
Power down exit time
Refresh interval time
us
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
2. tRCDWR should be always greater or equal to 2tCK
AC CHARACTERISTICS (III)
(Unit : Number of Clock)
K4D261638F-TC2A
Unit
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD tRCDWR
tRP
tRRD
tDAL
350MHz ( 2.86ns )
4
16
17
11
5
3
5
3
9
tCK
K4D261638F-TC33
Frequency
300MHz ( 3.3ns )
275MHz ( 3.6ns )
250MHz ( 4.0ns )
200MHz ( 5.0ns )
Unit
tCK
tCK
tCK
tCK
Cas Latency
tRC
16
16
13
12
tRFC
17
17
15
14
tRAS
11
11
9
tRCDRD tRCDWR
tRP
5
5
4
4
tRRD
tDAL
4
4
3
3
5
4
4
4
3
2
2
2
3
3
3
3
9
9
7
7
8
K4D261638F-TC36
Frequency
275MHz ( 3.6ns )
250MHz ( 4.0ns )
200MHz ( 5.0ns )
Unit
tCK
tCK
tCK
Cas Latency
tRC
16
13
tRFC
17
15
tRAS
11
9
tRCDRD tRCDWR
tRP
5
4
tRRD
tDAL
4
3
3
4
4
4
2
2
2
3
3
3
9
7
7
12
14
8
4
- 15 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
AC CHARACTERISTICS (II)_Continued
-40
-50
-5A
Parameter
Symbol
Unit
Note
Min
52
60
36
16
8
Max
-
-
Min
60
70
40
20
10
20
15
Max
-
-
Min
55
70
40
15
10
15
10
Max
-
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge @Normal
Precharge
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
ns
ns
ns
ns
ns
ns
ns
100K
100K
100K
-
-
-
-
-
-
-
-
-
-
-
2
1
16
12
tRRD
tWR
3
3
-
-
3
3
-
-
3
3
-
-
tCK
tCK
Last data in to Row precharge @Auto
Precharge
tWR_A
1
1
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery + Pre-
charge
tCDLR
tCCD
tMRD
2
1
2
-
-
-
2
1
2
-
-
-
2
1
2
-
-
-
tCK
tCK
tCK
tDAL
7
-
-
-
-
7
-
-
-
-
6
-
-
-
-
tCK
tCK
ns
Exit self refresh to read command
tXSR
tPDEX
tREF
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
200
3tCK
+tIS
7.8
Power down exit time
Refresh interval time
us
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
2. tRCDWR should be always greater or equal to 2tCK
AC CHARACTERISTICS (III)_Continued
(Unit : Number of Clock)
K4D261638F-TC40
Frequency
250MHz ( 4.0ns )
200MHz ( 5.0ns )
Cas Latency
tRC
13
12
tRFC
15
14
tRAS
9
8
tRCDRD tRCDWR
tRP
4
4
tRRD
3
3
tDAL
7
7
Unit
tCK
tCK
3
3
4
4
2
2
K4D261638F-TC50
Frequency
Cas Latency
tRC
tRFC
tRAS
tRCDRD tRCDWR
tRP
tRRD
tDAL
Unit
200MHz ( 5.0ns )
3
12
14
8
4
2
4
3
7
tCK
K4D261638F-TC5A
Frequency
200MHz ( 5.0ns )
166MHz ( 6.0ns )
133MHz ( 7.5ns )
Cas Latency
tRC
11
10
8
tRFC
14
12
tRAS
tRCDRD tRCDWR
tRP
3
3
tRRD
tDAL
Unit
tCK
tCK
tCK
3
3
3
8
7
6
3
3
2
2
2
2
2
2
2
6
5
4
10
2
* 166/133MHz were supported in K4D261638F-TC5A
- 16 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
Simplified Timing @ BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CK, CK
BA[1:0]
A8/AP
BAa
BAa
BAb
BAa
BAa
BAa
BAb
Rb
Rb
Ra
Ra
Ra
Ra
ADDR
(A0~A7
,A9~A11)
Cb
Ca
Ca
WE
DQS
Da0 Da1 Da2 Da3
Da0 Da1 Da2 Da3
Db0 Db1 Db2 Db3
DQ
DM
ACT_A
WR_A
PRECH
ACT_A
WR_A
ACT_B
WR_B
COM
t
t
RCD
RP
t
RAS
t
t
RRD
RC
Multi Bank Interleaving Write Burst
(@ BL=4)
Normal Write Burst
(@ BL=4)
- 17 -
Rev 1.5 (Mar. 2005)
128M GDDR SDRAM
K4D261638F
PACKAGE DIMENSIONS (66pin TSOP-II)
Units : Millimeters
#66
#34
(10×)
(10×)
#1
#33
+0.075
-0.035
0.125
(1.50)
22.22±0.10
(10×)
(10×)
0.10 MAX
0.25TYP
(0.71)
0.65TYP
0.65±0.08
0.30±0.08
[
]
0.075 MAX
NOTE
1. (
0×~8×
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
- 18 -
Rev 1.5 (Mar. 2005)
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