K4D551638F-LC60_技术文档

256M GDDR SDRAM

K4D551638F-TC

256Mbit GDDR SDRAM

Revision 2.1

April 2005

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

Revision History

Revision 2.1(April 29, 2005)

• Mofidied CKE input functional description on page 5.

• Added K4D551638F-TC60 from the data sheet.

Revision 2.0(March 24, 2005)

• Removed K4D551638F-TC60 from the data sheet.

• Typo corrected.

Revision 1.9(February 24, 2005)

• Typo corrected.

Revision 1.8 (August 30, 2004)

• DC Spec defined for -TC33/36/40

Revision 1.7 (June 15, 2004)

• Changed VDD/VDDQ of K4D551638F-TC33 from 2.8V + 0.1V to 2.8V(min)/2.95V(max)

• Spec for -TC33/36/40 still in target

Revision 1.6 (March 31, 2004)

• AC Changes : Refer to the AC characteristics of page 13 and 14.

Revision 1.5 (March 18, 2004)

• Added K4D551638F-TC33 in the data sheet.

• Target spec defined for -TC33

Revision 1.4 (February 27, 2004)

• Added K4D551638F-TC36/40 in the data sheet.

• Target spec defined for -TC36/40

Revision 1.3 (December 5, 2003)

• Changed VDD/VDDQ of K4D551638F-TC50 from 2.5V + 5% to 2.6V + 0.1V

Revision 1.2 (November 11, 2003)

• "Wrtie-Interrupted by Read Function" is supported

Revision 1.1 (October 13, 2003)

• Defined ICC7 value

Revision 1.0 (October 10, 2003)

• Defined DC spec

• Changed part number of 16Mx16 GDDR F-die from K4D561638F-TC to K4D551638F-TC.

Revision 0.1 (October 2, 2003) - Target Spec

• Added Lead free package part number in the data sheet.

• Removed K4D561638F-TC40 from the data sheet.

- 2 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM

with Bi-directional Data Strobe and DLL

FEATURES

• 2.6V + 0.1V power supply for device operation

• 2.6V + 0.1V power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• 2 DQS’s ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• MRS cycle with address key programs

-. Read latency 3 (clock)

-. Burst length (2, 4 and 8)

• Auto & Self refresh

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive

going edge of the system clock

• 64ms refresh period (8K cycle)

• 66pin TSOP-II

• Maximum clock frequency up to 300MHz

• Maximum data rate up to 600Mbps/pin

• Differential clock input

• No Write-Interrupted by Read Function

ORDERING INFORMATION

Part NO.

Max Freq.

300MHz

275MHz

250MHz

200MHz

166MHz

Max Data Rate

600Mbps/pin

550Mbps/pin

500Mbps/pin

400Mbps/pin

333Mbps/pin

Interface

VDD & VDDQ

2.8V ~ 2.95V

2.8V+0.1V

Package

K4D551638F-TC33

K4D551638F-TC36

K4D551638F-TC40

K4D551638F-TC50

K4D551638F-TC60*

SSTL_2

66pin TSOP-II

2.6V+0.1V

2.5V+0.125V

1. K4D551638F-LC is the Lead Free package part number.

2. For the K4D551638F-TC60, VDD & VDDQ = 2.5V + 5%

3. For the K4D551638F-TC36, VDD & VDDQ = 2.8V + 0.1V

4. For the K4D551638F-TC33, VDD & VDDQ = 2.8V ~ 2.95V

GENERAL DESCRIPTION

FOR 4M x 16Bit x 4 Bank GDDR SDRAM

The K4D551638F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by

16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

- 3 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

PIN CONFIGURATION (Top View)

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

VSS

1

V^DD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ⁸

NC

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm Pin Pitch)

VSSQ

UDQS

NC

V^DDQ

LDQS

NC

V^REF

V^SS

VDD

NC

UDM

CK

LDM

WE

CK

CAS

RAS

CS

22

23

CKE

NC

24

25

26

27

28

29

30

31

32

33

A¹²

NC

A11

BA0

BA1

AP/A10

A0

A9

A8

A7

A6

A1

A5

A2

A4

A3

VSS

V^DD

PIN DESCRIPTION

CK,CK

CKE

Differential Clock Input

Clock Enable

BA0, BA1

A0 ~A12

DQ0 ~ DQ15

VDD

Bank Select Address

Address Input

Data Input/Output

Power

CS

Chip Select

RAS

Row Address Strobe

Column Address Strobe

Write Enable

CAS

VSS

Ground

WE

VDDQ

Power for DQ’s

Ground for DQ’s

No Connection

Reference voltage

L(U)DQS

L(U)DM

RFU

Data Strobe

VSSQ

Data Mask

NC

Reserved for Future Use

VREF

- 4 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Sym-

Type

Function

The differential system clock Input.

CK, CK*1

Input

All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s

that are sampled on both edges of the DQS.

Activates the CK signal when high and deactivates the CK signal when low. By

deactivating the clock, CKE low indicates the Power down mode or Self refresh

mode.CKE is synchronous for Power down entry and exit, and for Self refresh

entry. CKE is asynchronous for Self refresh exit, and for output disable. CKE must

be maintained high through Read and Write accesses. Input buffers, excluding CK,

CK and CKE are disbled during Power down. Input buffers, excluding CKE are dis-

abled during Self refresh. CKE is an SSTL_2 input, but will detect a LVCMOS low

level after Vdd is applied upon 1st power up. After Vref has become stable during

the power on and intialization sequence, it must be maintained for proper opera-

tion of the CKE receiver. For proper Self refresh entry and exit, Vref must be main-

tained to this input.

CKE

CS enables the command decoder when low and disabled the command decoder

when high. When the command decoder is disabled, new commands are ignored

but previous operations continue.

CS

Latches row addresses on the positive going edge of the CK with RAS low.

Enables row access & precharge.

RAS

CAS

WE

Input

Latches column addresses on the positive going edge of the CK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Data input and output are synchronized with both edge of DQS.

For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to

the data on DQ8-DQ15.

LDQS,UDQS

LDM,UDM

Input/Output

Input

Data in Mask. Data In is masked by DM Latency=0 when DM is

high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM

correspons to the data on DQ8-DQ15.

DQ0 ~ DQ15

BA0, BA1

Input/Output

Input

Data inputs/Outputs are multiplexed on the same pins.

Selects which bank is to be active.

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.

A0 ~ A12

VDD/VSS

Input

Power Supply

Power and ground for the input buffers and core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VDDQ/VSSQ

VREF

Reference voltage for inputs, used for SSTL interface.

NC/RFU

No connection/

This pin is recommended to be left "No connection" on the device

Reserved for future use

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply VREF to CK pin.

- 5 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

BLOCK DIAGRAM (4Mbit x 16I/O x 4 Bank)

16

Intput Buffer

LWE

CK, CK

Data Input Register

Serial to parallel

LDMi

Bank Select

4Mx16

32

16

x16

DQi

CK,CK

ADDR

Column Decoder

Latency & Burst Length

Data Strobe

Programming Register

LWCBR

DLL

LCKE

LRAS LCBR

LWE

LCAS

CK,CK

LDMi

Timing Register

UDM

CK,CK

CKE

CS

RAS

CAS

WE

LDM

- 6 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

FUNCTIONAL DESCRIPTION

• Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before VDDQ .

- Apply VDDQ before VREF & VTT

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

*1

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order.

Power up & Initialization Sequence

0

1

2

3

4

5

6

7

8

9

10

11

12 13

14

15 16 17

18

19

CK,CK

tRP

2 Clock min.

tRFC

2 Clock min.

tRP

2 Clock min.

Command

precharge

ALL Banks

MRS

DLL Reset

precharge

ALL Banks

1st Auto

Refresh

2nd Auto

Refresh

Mode

Register Set

Any

Command

EMRS

200 Clock min.

Inputs must be

stable for 200us

* When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.

- 7 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

MODE REGISTER SET(MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the mode register is not defined, therefore the mode register must be

written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and

WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of

address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the

idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,

addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

Address Bus

BA1 BA0

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

RFU

0

RFU

DLL

TM

CAS Latency

BT

Burst Length

Mode Register

Burst Type

DLL

Test Mode

A7

A3

0

Type

A8

0

DLL Reset

No

mode

Sequential

Interleave

0

1

Normal

Test

1

Yes

0

Burst Length

Burst Type

Sequential Interleave

CAS Latency

A2

A1

A0

BA0

0

An ~ A0

MRS

A6 A5 A4 Latency

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserve

2

Reserve

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

3

1

EMRS

4

8

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

Reserve

Reserved

MRS Cycle

0

1

2

3

4

5

6

7

8

CK, CK

Precharge

All Banks

Any

Command

NOP

MRS

NOP

tMRD=2 tCK

tRP

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

- 8 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

EXTENDED MODE REGISTER SET(EMRS)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register

must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-

ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A12

and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1

and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are

required to complete the write operation in the extended mode register. The mode register contents can be

changed using the same command and clock cycle requirements during operation as long as all banks are in

the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address

pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific

codes.

BA1

BA0

1

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address Bus

Extended

Mode Register

RFU

D.I.C

RFU

D.I.C DLL

A0

0

DLL Enable

Enable

Disable

BA0

An ~ A0

MRS

Output Driver Impedence Control

A6 A1

0

1

Full

Weak

Matched

N/A

100%

60%

0

1

0

1

0

1

EMRS

30%

Do not use

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

- 9 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Voltage on VDDQ supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD

Value

Unit

-0.5 ~ 3.6

-1.0 ~ 3.6

-0.5 ~ 3.6

-55 ~ +150

2.0

V

VDDQ

TSTG

V

°C

W

mA

Power dissipation

PD

Short circuit current

IOS

50

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter

Device Supply voltage

Output Supply voltage

Reference voltage

Symbol

VDD

Min

2.5

Typ

Max

Unit

V

Note

2.6

2.7

1, 7

VDDQ

VREF

Vtt

2.5

2.6

V

1

0.49*VDDQ

VREF-0.04

VREF+0.15

-0.30

-

0.51*VDDQ

VREF+0.04

VDDQ+0.30

VREF-0.15

-

V

2

Termination voltage

VREF

V

3

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Output leakage current

VIH(DC)

VIL(DC)

VOH

-

V

4

V

5

Vtt+0.76

-

V

IOH=-15.2mA

VOL

Vtt-0.76

5

V

IOL=+15.2mA

IIL

-5

uA

6

IOL

-5

5

Note :

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error

and an additional + 25mV for AC noise.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.

7. For the K4D551638F-TC60 , VDD & VDDQ =2.5V + 5%,

For the K4D551638F-TC36 , VDD & VDDQ =2.8V + 0.1V

and For the K4D551638F-TC33 , VDD & VDDQ = 2.8V ~ 2.95V

- 10 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

DC CHARACTERISTICS

Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)

Version

-40

Parameter

Symbol

Test Condition

Unit

Note

-33

-36

-50

-60

Burst Lenth=2 tRC ≥ tRC(min)

IOL=0mA, tCC= tCC(min)

Operating Current

(One Bank Active)

ICC1

210

205

165

5

150

125

mA

1

Precharge Standby Current

in Power-down mode

ICC2P

ICC2N

ICC3P

ICC3N

ICC4

6

45

4

25

55

75

250

3

20

CKE ≤ VIL(max), tCC= tCC(min)

CKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min)

Precharge Standby Current

in Non Power-down mode

50

37

60

80

320

Active Standby Current

power-down mode

70

65

35

CKE ≤ VIL(max), tCC= tCC(min)

CKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min)

Active Standby Current in

in Non Power-down mode

100

405

95

56

Operating Current

(Burst Mode)

tRC ≥ tRFC(min)tRC ≥ tRFC(min)

Page Burst, All Banks activated.

400

200

Refresh Current

ICC5

ICC6

275

4

270

4

220

4

200

3

180

3

mA

2

tRC ≥ tRFC(min)

CKE ≤ 0.2V

Self Refresh Current

Operating Current

(4Bank Interleaving)

Burst Length=4, tRC ≥ tRFC(min)

IOL=0mA, tCC = tCC(min)

ICC7

520

515

410

380

350

mA

Note : 1. Measured with outputs open.

2. Refresh period is 64ms

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.6V+ 0.1V, VDDQ=2.6V+ 0.1V ,TA=0 to 65°C)

Parameter

Symbol

VIH

Min

VREF+0.35

-

Typ

Max

-

Unit

Note

Input High (Logic 1) Voltage; DQ

-

V

Input Low (Logic 0) Voltage; DQ

VIL

VREF-0.35

VDDQ+0.6

0.5*VDDQ+0.2

Clock Input Differential Voltage; CK and CK

Clock Input Crossing Point Voltage; CK and CK

VID

0.7

1

2

VIX

0.5*VDDQ-0.2

Note :

1. VID is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same

- 11 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

AC OPERATING TEST CONDITIONS (VDD=2.6V ± 0.1V, TA= 0 to 65°C)

Parameter

Value

Unit

V

Note

Input reference voltage for CK(for single ended)

CK and CK signal maximum peak swing

CK signal minimum slew rate

0.50*VDDQ

1.5

V

1.0

VREF+0.35/VREF-0.35

VREF

V/ns

V

Input Levels(VIH/VIL)

Input timing measurement reference level

Output timing measurement reference level

Output load condition

V

Vtt

V

See Fig.1

Vtt=0.5*VDDQ

RT=50Ω

Output

Z0=50Ω

VREF

=0.5*VDDQ

CLOAD=30pF

(Fig. 1) Output Load Circuit

CAPACITANCE (VDD=2.6V, TA= 25°C, f=1MHz)

Parameter

Input capacitance( CK, CK )

Symbol

CIN1

Min

1.0

Max

5.0

Unit

pF

Input capacitance(A0~A12, BA0~BA1)

CIN2

1.0

4.0

Input capacitance

( CKE, CS, RAS,CAS, WE )

CIN3

1.0

4.0

pF

Data & DQS input/output capacitance(DQ0~DQ15)

Input capacitance(DM0 ~ DM3)

COUT

CIN4

1.0

6.5

pF

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

CDC1

Value

Unit

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

0.1 + 0.01

uF

CDC2

Note :

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

- 12 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

AC CHARACTERISTICS

-33

-36

-40

-50

-60

Parameter

Symbol

Unit Note

Min

3.3

0.45

-0.6

-

Max

10

0.55

0.6

0.35

1.1

0.6

1.15

-

Min

3.6

0.45

-0.6

-

Max

10

0.55

0.6

0.4

1.1

0.6

1.15

-

Min

4.0

0.45

-0.6

-

Max

10

0.55

0.6

0.4

1.1

0.6

1.15

-

Min

5.0

Max

10

0.55

0.65

0.4

1.1

0.6

1.28

-

Min

6.0

Max

12

0.55

0.6

0.7

0.45

1.1

0.6

1.25

-

CK cycle time

CL=3 tCK

ns

tCK

ns

CK high level width

tCH

0.45

-0.55

-0.65

-

0.45

-0.6

-0.7

-

CK low level width

tCL

DQS out access time from CK

Output access time from CK

tDQSCK

tAC

ns

Data strobe edge to Dout edge tDQSQ

ns

tCK

ns

1

Read preamble

tRPRE

tRPST

0.9

0.4

0.85

0

0.9

0.4

0.85

0

0.9

Read postamble

0.4

CK to valid DQS-in

DQS-In setup time

DQS-in hold time

tDQSS

tWPRES

tWPREH

tWPST

tDQSH

tDQSL

0.85

0

0.72

0

0.75

0

0.35

0.4

-

0.35

0.4

0.9

0.4

-

0.35

0.4

0.9

0.4

-

0.25

0.4

-

0.25

0.4

-

tCK

ns

DQS write postamble

DQS-In high level width

DQS-In low level width

0.6

-

0.6

-

0.6

-

0.6

-

0.6

-

0.4

0.9

0.35

0.6

0.35

0.8

-

Address and Control input setup tIS

Address and Control input hold tIH

DQ and DM setup time to DQS tDS

-

0.6

-

0.8

-

ns

-

0.4

-

0.45

-

ns

DQ and DM hold time to DQS

tDH

-

0.4

-

ns

tCLmin

or

tCHmin

tHP-

tCLmin

or

tCHmin

tCLmin

or

tCHmin

tCLmin

or

tCHmin

tCLmin

or

tCHmin

tHP-

Clock half period

tHP

-

ns

1

Data output hold time from DQS tQH

tHP-0.4

tHP-0.5

0.35

0.55

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming

the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

- 13 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

AC CHARACTERISTICS (I)

-33

-36

-40

-50

-60

Parameter

Symbol

Unit Note

Min

15

17

10

5

Max

-

Min

15

17

10

5

Max

-

Min

13

15

9

Max

-

Min

12

14

8

Max

-

Min

10

12

7

Max

-

Row cycle time

tRC

tCK

Refresh row cycle time

tRFC

-

Row active time

tRAS

100K

RAS to CAS delay for Read

RAS to CAS delay for Write

Row precharge time

tRCDRD

tRCDWR

tRP

-

4

-

4

-

3

-

3

2

5

4

3

Row active to Row active

Last data in to Row precharge @Nor-

mal Precharge

tRRD

3

2

tWR

3

-

3

-

3

-

3

-

3

-

tCK

1

Last data in to Row precharge @Auto

Precharge

tWR_A

1

Last data in to Read command

Col. address to Col. address

Mode register set cycle time

Auto precharge write recovery + Pre-

charge

tCDLR

tCCD

tMRD

3

1

2

-

2

1

2

-

2

1

2

-

2

1

2

-

1

2

-

tCK

tDAL

8

-

8

-

7

-

7

-

6

-

tCK

ns

Exit self refresh to read command

tXSR

tPDEX

tREF

200

3tCK

+tIS

7.8

200

3tCK

+tIS

7.8

200

3tCK

+tIS

7.8

200

1tCK

+tIS

7.8

200

1tCK

+tIS

7.8

Power down exit time

Refresh interval time

us

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

AC CHARACTERISTICS (II)

(Unit : Number of Clock)

K4D551638F-TC33

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

300MHz ( 3.3ns )

3

15

17

10

5

3

5

3

8

tCK

K4D551638F-TC36

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

275MHz ( 3.6ns )

3

15

17

10

5

3

5

3

8

tCK

K4D551638F-TC40

Frequency

250MHz ( 4.0ns )

200MHz ( 5.0ns )

Unit

tCK

Cas Latency

tRC

13

12

tRFC

15

14

tRAS

9

8

tRCDRD tRCDWR

tRP

4

tRRD

3

tDAL

7

3

4

2

K4D551638F-TC50

Frequency

Unit

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

200MHz ( 5.0ns )

3

12

14

8

4

2

4

3

7

tCK

K4D551638F-TC60

Frequency

Unit

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

166MHz ( 6.0ns )

3

10

12

7

3

2

3

2

6

tCK

- 14 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

Write Interrupted by a Read & DM

A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at

least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read

command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data

to read command (tCDLR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins

before the read command is initiated will actually be written to the memory. Read command interrupting write can not be

issued at the next clock edge of that of write command.

< Burst Length=8, CAS Latency=3 >

0

1

2

3

4

5

6

7

8

CK

Command

NOP

WRITE

NOP

DQSSmax

NOP

CDLR

READ

NOP

t

DQS

5

t_WPRES*

CAS Latency=3

Din 7

Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6

CDLR

Dout 0 Dout 1

DQ

′

s

tDQSSmin

t

DQS

5

CAS Latency=3

t_WPRES*

Din 6

Din 0 Din 1 Din 2 Din 3 Din 4 Din 5

Din 7

DQ

′

s

Dout 0 Dout 1

DM

The following function established how a Read command may interrupt a Write burst and which input data is not written

into the memory.

1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The

case where the Write to Read delay is 1 clock cycle is disallowed

2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich imme-

diately precede the interrupting Read operation and the input data word which immediately follows the interrupting

Read operation

3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the

memory controller) in time to allow the buses to turn around before the GDDR drives them during a read operation.

4. If input Write data is masked by the Read command, the DQS input is ignored by the GDDR.

* This function is only supported in 200/166MHz.

- 15 -

Rev 2.1 (Apr. 2005)

256M GDDR SDRAM

K4D551638F-TC

PACKAGE DIMENSIONS (66pin TSOP-II)

Units : Millimeters

#66

#34

(10×)

#1

#33

+0.075

-0.035

0.125

(1.50)

22.22±0.10

(10×)

0.10 MAX

0.25TYP

(0.71)

0.65TYP

0.65±0.08

0.30±0.08

[

]

0.075 MAX

NOTE

1. (

0×~8×

) IS REFERENCE

2. [

] IS ASS’Y OUT QUALITY

- 16 -

Rev 2.1 (Apr. 2005)


型号：	K4D551638F-LC60
厂家：	SAMSUNG
描述：	DDR DRAM, 16MX16, CMOS, PDSO66, 动态存储器双倍数据速率光电二极管
文件：	总16页 (文件大小：206K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4D551638F-LC60 [SAMSUNG]

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